Commit | Line | Data |
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80c4445e | 1 | // SPDX-License-Identifier: GPL-2.0+ |
96286b57 FM |
2 | /* |
3 | * BCM2835 DMA engine support | |
4 | * | |
5 | * This driver only supports cyclic DMA transfers | |
6 | * as needed for the I2S module. | |
7 | * | |
8 | * Author: Florian Meier <florian.meier@koalo.de> | |
9 | * Copyright 2013 | |
10 | * | |
11 | * Based on | |
12 | * OMAP DMAengine support by Russell King | |
13 | * | |
14 | * BCM2708 DMA Driver | |
15 | * Copyright (C) 2010 Broadcom | |
16 | * | |
17 | * Raspberry Pi PCM I2S ALSA Driver | |
18 | * Copyright (c) by Phil Poole 2013 | |
19 | * | |
20 | * MARVELL MMP Peripheral DMA Driver | |
21 | * Copyright 2012 Marvell International Ltd. | |
96286b57 FM |
22 | */ |
23 | #include <linux/dmaengine.h> | |
24 | #include <linux/dma-mapping.h> | |
27bc944c | 25 | #include <linux/dmapool.h> |
96286b57 FM |
26 | #include <linux/err.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/list.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/spinlock.h> | |
35 | #include <linux/of.h> | |
36 | #include <linux/of_dma.h> | |
37 | ||
38 | #include "virt-dma.h" | |
39 | ||
e2eca638 MS |
40 | #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14 |
41 | #define BCM2835_DMA_CHAN_NAME_SIZE 8 | |
42 | ||
96286b57 FM |
43 | struct bcm2835_dmadev { |
44 | struct dma_device ddev; | |
45 | spinlock_t lock; | |
46 | void __iomem *base; | |
47 | struct device_dma_parameters dma_parms; | |
48 | }; | |
49 | ||
50 | struct bcm2835_dma_cb { | |
51 | uint32_t info; | |
52 | uint32_t src; | |
53 | uint32_t dst; | |
54 | uint32_t length; | |
55 | uint32_t stride; | |
56 | uint32_t next; | |
57 | uint32_t pad[2]; | |
58 | }; | |
59 | ||
27bc944c PU |
60 | struct bcm2835_cb_entry { |
61 | struct bcm2835_dma_cb *cb; | |
62 | dma_addr_t paddr; | |
63 | }; | |
64 | ||
96286b57 FM |
65 | struct bcm2835_chan { |
66 | struct virt_dma_chan vc; | |
67 | struct list_head node; | |
68 | ||
69 | struct dma_slave_config cfg; | |
96286b57 FM |
70 | unsigned int dreq; |
71 | ||
72 | int ch; | |
73 | struct bcm2835_desc *desc; | |
27bc944c | 74 | struct dma_pool *cb_pool; |
96286b57 FM |
75 | |
76 | void __iomem *chan_base; | |
77 | int irq_number; | |
e2eca638 | 78 | unsigned int irq_flags; |
40874122 MS |
79 | |
80 | bool is_lite_channel; | |
96286b57 FM |
81 | }; |
82 | ||
83 | struct bcm2835_desc { | |
27bc944c | 84 | struct bcm2835_chan *c; |
96286b57 FM |
85 | struct virt_dma_desc vd; |
86 | enum dma_transfer_direction dir; | |
87 | ||
96286b57 FM |
88 | unsigned int frames; |
89 | size_t size; | |
a4dcdd84 MS |
90 | |
91 | bool cyclic; | |
92153bb5 MS |
92 | |
93 | struct bcm2835_cb_entry cb_list[]; | |
96286b57 FM |
94 | }; |
95 | ||
96 | #define BCM2835_DMA_CS 0x00 | |
97 | #define BCM2835_DMA_ADDR 0x04 | |
e42685d7 | 98 | #define BCM2835_DMA_TI 0x08 |
96286b57 FM |
99 | #define BCM2835_DMA_SOURCE_AD 0x0c |
100 | #define BCM2835_DMA_DEST_AD 0x10 | |
e42685d7 MS |
101 | #define BCM2835_DMA_LEN 0x14 |
102 | #define BCM2835_DMA_STRIDE 0x18 | |
103 | #define BCM2835_DMA_NEXTCB 0x1c | |
104 | #define BCM2835_DMA_DEBUG 0x20 | |
96286b57 FM |
105 | |
106 | /* DMA CS Control and Status bits */ | |
e42685d7 MS |
107 | #define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */ |
108 | #define BCM2835_DMA_END BIT(1) /* current CB has ended */ | |
109 | #define BCM2835_DMA_INT BIT(2) /* interrupt status */ | |
110 | #define BCM2835_DMA_DREQ BIT(3) /* DREQ state */ | |
96286b57 FM |
111 | #define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ |
112 | #define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ | |
e42685d7 MS |
113 | #define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last |
114 | * AXI-write to ack | |
115 | */ | |
116 | #define BCM2835_DMA_ERR BIT(8) | |
117 | #define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */ | |
118 | #define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */ | |
119 | /* current value of TI.BCM2835_DMA_WAIT_RESP */ | |
120 | #define BCM2835_DMA_WAIT_FOR_WRITES BIT(28) | |
121 | #define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */ | |
96286b57 FM |
122 | #define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ |
123 | #define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ | |
124 | ||
e42685d7 | 125 | /* Transfer information bits - also bcm2835_cb.info field */ |
96286b57 | 126 | #define BCM2835_DMA_INT_EN BIT(0) |
e42685d7 MS |
127 | #define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */ |
128 | #define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */ | |
96286b57 | 129 | #define BCM2835_DMA_D_INC BIT(4) |
e42685d7 MS |
130 | #define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */ |
131 | #define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */ | |
132 | #define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */ | |
96286b57 | 133 | #define BCM2835_DMA_S_INC BIT(8) |
e42685d7 MS |
134 | #define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */ |
135 | #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ | |
136 | #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */ | |
137 | #define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12) | |
138 | #define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */ | |
139 | #define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */ | |
140 | #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */ | |
141 | ||
142 | /* debug register bits */ | |
143 | #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0) | |
144 | #define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1) | |
145 | #define BCM2835_DMA_DEBUG_READ_ERR BIT(2) | |
146 | #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4 | |
147 | #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4 | |
148 | #define BCM2835_DMA_DEBUG_ID_SHIFT 16 | |
149 | #define BCM2835_DMA_DEBUG_ID_BITS 9 | |
150 | #define BCM2835_DMA_DEBUG_STATE_SHIFT 16 | |
151 | #define BCM2835_DMA_DEBUG_STATE_BITS 9 | |
152 | #define BCM2835_DMA_DEBUG_VERSION_SHIFT 25 | |
153 | #define BCM2835_DMA_DEBUG_VERSION_BITS 3 | |
154 | #define BCM2835_DMA_DEBUG_LITE BIT(28) | |
155 | ||
156 | /* shared registers for all dma channels */ | |
157 | #define BCM2835_DMA_INT_STATUS 0xfe0 | |
158 | #define BCM2835_DMA_ENABLE 0xff0 | |
96286b57 FM |
159 | |
160 | #define BCM2835_DMA_DATA_TYPE_S8 1 | |
161 | #define BCM2835_DMA_DATA_TYPE_S16 2 | |
162 | #define BCM2835_DMA_DATA_TYPE_S32 4 | |
163 | #define BCM2835_DMA_DATA_TYPE_S128 16 | |
164 | ||
96286b57 FM |
165 | /* Valid only for channels 0 - 14, 15 has its own base address */ |
166 | #define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ | |
167 | #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) | |
168 | ||
40874122 MS |
169 | /* the max dma length for different channels */ |
170 | #define MAX_DMA_LEN SZ_1G | |
171 | #define MAX_LITE_DMA_LEN (SZ_64K - 4) | |
172 | ||
173 | static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c) | |
174 | { | |
175 | /* lite and normal channels have different max frame length */ | |
176 | return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN; | |
177 | } | |
178 | ||
92153bb5 MS |
179 | /* how many frames of max_len size do we need to transfer len bytes */ |
180 | static inline size_t bcm2835_dma_frames_for_length(size_t len, | |
181 | size_t max_len) | |
182 | { | |
183 | return DIV_ROUND_UP(len, max_len); | |
184 | } | |
185 | ||
96286b57 FM |
186 | static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) |
187 | { | |
188 | return container_of(d, struct bcm2835_dmadev, ddev); | |
189 | } | |
190 | ||
191 | static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) | |
192 | { | |
193 | return container_of(c, struct bcm2835_chan, vc.chan); | |
194 | } | |
195 | ||
196 | static inline struct bcm2835_desc *to_bcm2835_dma_desc( | |
197 | struct dma_async_tx_descriptor *t) | |
198 | { | |
199 | return container_of(t, struct bcm2835_desc, vd.tx); | |
200 | } | |
201 | ||
92153bb5 | 202 | static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc) |
96286b57 | 203 | { |
92153bb5 | 204 | size_t i; |
27bc944c PU |
205 | |
206 | for (i = 0; i < desc->frames; i++) | |
207 | dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb, | |
208 | desc->cb_list[i].paddr); | |
209 | ||
96286b57 FM |
210 | kfree(desc); |
211 | } | |
212 | ||
92153bb5 MS |
213 | static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) |
214 | { | |
215 | bcm2835_dma_free_cb_chain( | |
216 | container_of(vd, struct bcm2835_desc, vd)); | |
217 | } | |
218 | ||
219 | static void bcm2835_dma_create_cb_set_length( | |
220 | struct bcm2835_chan *chan, | |
221 | struct bcm2835_dma_cb *control_block, | |
222 | size_t len, | |
223 | size_t period_len, | |
224 | size_t *total_len, | |
225 | u32 finalextrainfo) | |
226 | { | |
40874122 MS |
227 | size_t max_len = bcm2835_dma_max_frame_length(chan); |
228 | ||
229 | /* set the length taking lite-channel limitations into account */ | |
230 | control_block->length = min_t(u32, len, max_len); | |
92153bb5 MS |
231 | |
232 | /* finished if we have no period_length */ | |
233 | if (!period_len) | |
234 | return; | |
235 | ||
236 | /* | |
237 | * period_len means: that we need to generate | |
238 | * transfers that are terminating at every | |
239 | * multiple of period_len - this is typically | |
240 | * used to set the interrupt flag in info | |
241 | * which is required during cyclic transfers | |
242 | */ | |
243 | ||
244 | /* have we filled in period_length yet? */ | |
2201ac61 MR |
245 | if (*total_len + control_block->length < period_len) { |
246 | /* update number of bytes in this period so far */ | |
247 | *total_len += control_block->length; | |
92153bb5 | 248 | return; |
2201ac61 | 249 | } |
92153bb5 MS |
250 | |
251 | /* calculate the length that remains to reach period_length */ | |
252 | control_block->length = period_len - *total_len; | |
253 | ||
254 | /* reset total_length for next period */ | |
255 | *total_len = 0; | |
256 | ||
257 | /* add extrainfo bits in info */ | |
258 | control_block->info |= finalextrainfo; | |
259 | } | |
260 | ||
388cc7a2 MS |
261 | static inline size_t bcm2835_dma_count_frames_for_sg( |
262 | struct bcm2835_chan *c, | |
263 | struct scatterlist *sgl, | |
264 | unsigned int sg_len) | |
265 | { | |
266 | size_t frames = 0; | |
267 | struct scatterlist *sgent; | |
268 | unsigned int i; | |
269 | size_t plength = bcm2835_dma_max_frame_length(c); | |
270 | ||
271 | for_each_sg(sgl, sgent, sg_len, i) | |
272 | frames += bcm2835_dma_frames_for_length( | |
273 | sg_dma_len(sgent), plength); | |
274 | ||
275 | return frames; | |
276 | } | |
277 | ||
92153bb5 MS |
278 | /** |
279 | * bcm2835_dma_create_cb_chain - create a control block and fills data in | |
280 | * | |
281 | * @chan: the @dma_chan for which we run this | |
282 | * @direction: the direction in which we transfer | |
283 | * @cyclic: it is a cyclic transfer | |
284 | * @info: the default info bits to apply per controlblock | |
285 | * @frames: number of controlblocks to allocate | |
286 | * @src: the src address to assign (if the S_INC bit is set | |
287 | * in @info, then it gets incremented) | |
288 | * @dst: the dst address to assign (if the D_INC bit is set | |
289 | * in @info, then it gets incremented) | |
290 | * @buf_len: the full buffer length (may also be 0) | |
291 | * @period_len: the period length when to apply @finalextrainfo | |
292 | * in addition to the last transfer | |
293 | * this will also break some control-blocks early | |
294 | * @finalextrainfo: additional bits in last controlblock | |
295 | * (or when period_len is reached in case of cyclic) | |
296 | * @gfp: the GFP flag to use for allocation | |
297 | */ | |
298 | static struct bcm2835_desc *bcm2835_dma_create_cb_chain( | |
299 | struct dma_chan *chan, enum dma_transfer_direction direction, | |
300 | bool cyclic, u32 info, u32 finalextrainfo, size_t frames, | |
301 | dma_addr_t src, dma_addr_t dst, size_t buf_len, | |
302 | size_t period_len, gfp_t gfp) | |
303 | { | |
304 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
305 | size_t len = buf_len, total_len; | |
306 | size_t frame; | |
307 | struct bcm2835_desc *d; | |
308 | struct bcm2835_cb_entry *cb_entry; | |
309 | struct bcm2835_dma_cb *control_block; | |
310 | ||
d9f094a0 MS |
311 | if (!frames) |
312 | return NULL; | |
313 | ||
92153bb5 MS |
314 | /* allocate and setup the descriptor. */ |
315 | d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry), | |
316 | gfp); | |
317 | if (!d) | |
318 | return NULL; | |
319 | ||
320 | d->c = c; | |
321 | d->dir = direction; | |
322 | d->cyclic = cyclic; | |
323 | ||
324 | /* | |
325 | * Iterate over all frames, create a control block | |
326 | * for each frame and link them together. | |
327 | */ | |
328 | for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) { | |
329 | cb_entry = &d->cb_list[frame]; | |
330 | cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp, | |
331 | &cb_entry->paddr); | |
332 | if (!cb_entry->cb) | |
333 | goto error_cb; | |
334 | ||
335 | /* fill in the control block */ | |
336 | control_block = cb_entry->cb; | |
337 | control_block->info = info; | |
338 | control_block->src = src; | |
339 | control_block->dst = dst; | |
340 | control_block->stride = 0; | |
341 | control_block->next = 0; | |
342 | /* set up length in control_block if requested */ | |
343 | if (buf_len) { | |
344 | /* calculate length honoring period_length */ | |
345 | bcm2835_dma_create_cb_set_length( | |
346 | c, control_block, | |
347 | len, period_len, &total_len, | |
348 | cyclic ? finalextrainfo : 0); | |
349 | ||
350 | /* calculate new remaining length */ | |
351 | len -= control_block->length; | |
352 | } | |
353 | ||
354 | /* link this the last controlblock */ | |
355 | if (frame) | |
356 | d->cb_list[frame - 1].cb->next = cb_entry->paddr; | |
357 | ||
358 | /* update src and dst and length */ | |
359 | if (src && (info & BCM2835_DMA_S_INC)) | |
360 | src += control_block->length; | |
361 | if (dst && (info & BCM2835_DMA_D_INC)) | |
362 | dst += control_block->length; | |
363 | ||
364 | /* Length of total transfer */ | |
365 | d->size += control_block->length; | |
366 | } | |
367 | ||
368 | /* the last frame requires extra flags */ | |
369 | d->cb_list[d->frames - 1].cb->info |= finalextrainfo; | |
370 | ||
371 | /* detect a size missmatch */ | |
372 | if (buf_len && (d->size != buf_len)) | |
373 | goto error_cb; | |
374 | ||
375 | return d; | |
376 | error_cb: | |
377 | bcm2835_dma_free_cb_chain(d); | |
378 | ||
379 | return NULL; | |
380 | } | |
381 | ||
388cc7a2 MS |
382 | static void bcm2835_dma_fill_cb_chain_with_sg( |
383 | struct dma_chan *chan, | |
384 | enum dma_transfer_direction direction, | |
385 | struct bcm2835_cb_entry *cb, | |
386 | struct scatterlist *sgl, | |
387 | unsigned int sg_len) | |
388 | { | |
389 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
4aa819c7 AB |
390 | size_t len, max_len; |
391 | unsigned int i; | |
388cc7a2 MS |
392 | dma_addr_t addr; |
393 | struct scatterlist *sgent; | |
394 | ||
4aa819c7 | 395 | max_len = bcm2835_dma_max_frame_length(c); |
388cc7a2 MS |
396 | for_each_sg(sgl, sgent, sg_len, i) { |
397 | for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent); | |
398 | len > 0; | |
399 | addr += cb->cb->length, len -= cb->cb->length, cb++) { | |
400 | if (direction == DMA_DEV_TO_MEM) | |
401 | cb->cb->dst = addr; | |
402 | else | |
403 | cb->cb->src = addr; | |
404 | cb->cb->length = min(len, max_len); | |
405 | } | |
406 | } | |
407 | } | |
408 | ||
3e05ada0 | 409 | static void bcm2835_dma_abort(struct bcm2835_chan *c) |
96286b57 | 410 | { |
9e528c79 | 411 | void __iomem *chan_base = c->chan_base; |
96286b57 FM |
412 | long int timeout = 10000; |
413 | ||
f7da7782 LW |
414 | /* |
415 | * A zero control block address means the channel is idle. | |
416 | * (The ACTIVE flag in the CS register is not a reliable indicator.) | |
417 | */ | |
418 | if (!readl(chan_base + BCM2835_DMA_ADDR)) | |
3e05ada0 | 419 | return; |
96286b57 FM |
420 | |
421 | /* Write 0 to the active bit - Pause the DMA */ | |
422 | writel(0, chan_base + BCM2835_DMA_CS); | |
423 | ||
424 | /* Wait for any current AXI transfer to complete */ | |
9e528c79 LW |
425 | while ((readl(chan_base + BCM2835_DMA_CS) & |
426 | BCM2835_DMA_WAITING_FOR_WRITES) && --timeout) | |
96286b57 | 427 | cpu_relax(); |
96286b57 | 428 | |
9e528c79 | 429 | /* Peripheral might be stuck and fail to signal AXI write responses */ |
96286b57 | 430 | if (!timeout) |
9e528c79 LW |
431 | dev_err(c->vc.chan.device->dev, |
432 | "failed to complete outstanding writes\n"); | |
96286b57 | 433 | |
9e528c79 | 434 | writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS); |
96286b57 FM |
435 | } |
436 | ||
437 | static void bcm2835_dma_start_desc(struct bcm2835_chan *c) | |
438 | { | |
439 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
440 | struct bcm2835_desc *d; | |
441 | ||
442 | if (!vd) { | |
443 | c->desc = NULL; | |
444 | return; | |
445 | } | |
446 | ||
447 | list_del(&vd->node); | |
448 | ||
449 | c->desc = d = to_bcm2835_dma_desc(&vd->tx); | |
450 | ||
27bc944c | 451 | writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); |
96286b57 FM |
452 | writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); |
453 | } | |
454 | ||
455 | static irqreturn_t bcm2835_dma_callback(int irq, void *data) | |
456 | { | |
457 | struct bcm2835_chan *c = data; | |
458 | struct bcm2835_desc *d; | |
459 | unsigned long flags; | |
460 | ||
e2eca638 MS |
461 | /* check the shared interrupt */ |
462 | if (c->irq_flags & IRQF_SHARED) { | |
463 | /* check if the interrupt is enabled */ | |
464 | flags = readl(c->chan_base + BCM2835_DMA_CS); | |
465 | /* if not set then we are not the reason for the irq */ | |
466 | if (!(flags & BCM2835_DMA_INT)) | |
467 | return IRQ_NONE; | |
468 | } | |
469 | ||
96286b57 FM |
470 | spin_lock_irqsave(&c->vc.lock, flags); |
471 | ||
f7da7782 LW |
472 | /* |
473 | * Clear the INT flag to receive further interrupts. Keep the channel | |
474 | * active in case the descriptor is cyclic or in case the client has | |
475 | * already terminated the descriptor and issued a new one. (May happen | |
476 | * if this IRQ handler is threaded.) If the channel is finished, it | |
477 | * will remain idle despite the ACTIVE flag being set. | |
478 | */ | |
479 | writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE, | |
480 | c->chan_base + BCM2835_DMA_CS); | |
96286b57 FM |
481 | |
482 | d = c->desc; | |
483 | ||
484 | if (d) { | |
388cc7a2 MS |
485 | if (d->cyclic) { |
486 | /* call the cyclic callback */ | |
487 | vchan_cyclic_callback(&d->vd); | |
f7da7782 | 488 | } else if (!readl(c->chan_base + BCM2835_DMA_ADDR)) { |
388cc7a2 MS |
489 | vchan_cookie_complete(&c->desc->vd); |
490 | bcm2835_dma_start_desc(c); | |
491 | } | |
96286b57 FM |
492 | } |
493 | ||
96286b57 FM |
494 | spin_unlock_irqrestore(&c->vc.lock, flags); |
495 | ||
496 | return IRQ_HANDLED; | |
497 | } | |
498 | ||
499 | static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) | |
500 | { | |
501 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
27bc944c | 502 | struct device *dev = c->vc.chan.device->dev; |
96286b57 | 503 | |
27bc944c PU |
504 | dev_dbg(dev, "Allocating DMA channel %d\n", c->ch); |
505 | ||
506 | c->cb_pool = dma_pool_create(dev_name(dev), dev, | |
507 | sizeof(struct bcm2835_dma_cb), 0, 0); | |
508 | if (!c->cb_pool) { | |
509 | dev_err(dev, "unable to allocate descriptor pool\n"); | |
510 | return -ENOMEM; | |
511 | } | |
96286b57 | 512 | |
e2eca638 MS |
513 | return request_irq(c->irq_number, bcm2835_dma_callback, |
514 | c->irq_flags, "DMA IRQ", c); | |
96286b57 FM |
515 | } |
516 | ||
517 | static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) | |
518 | { | |
519 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
520 | ||
521 | vchan_free_chan_resources(&c->vc); | |
522 | free_irq(c->irq_number, c); | |
27bc944c | 523 | dma_pool_destroy(c->cb_pool); |
96286b57 FM |
524 | |
525 | dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); | |
526 | } | |
527 | ||
528 | static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) | |
529 | { | |
530 | return d->size; | |
531 | } | |
532 | ||
533 | static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) | |
534 | { | |
535 | unsigned int i; | |
536 | size_t size; | |
537 | ||
538 | for (size = i = 0; i < d->frames; i++) { | |
27bc944c | 539 | struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; |
96286b57 FM |
540 | size_t this_size = control_block->length; |
541 | dma_addr_t dma; | |
542 | ||
543 | if (d->dir == DMA_DEV_TO_MEM) | |
544 | dma = control_block->dst; | |
545 | else | |
546 | dma = control_block->src; | |
547 | ||
548 | if (size) | |
549 | size += this_size; | |
550 | else if (addr >= dma && addr < dma + this_size) | |
551 | size += dma + this_size - addr; | |
552 | } | |
553 | ||
554 | return size; | |
555 | } | |
556 | ||
557 | static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, | |
558 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
559 | { | |
560 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
561 | struct virt_dma_desc *vd; | |
562 | enum dma_status ret; | |
563 | unsigned long flags; | |
564 | ||
565 | ret = dma_cookie_status(chan, cookie, txstate); | |
566 | if (ret == DMA_COMPLETE || !txstate) | |
567 | return ret; | |
568 | ||
569 | spin_lock_irqsave(&c->vc.lock, flags); | |
570 | vd = vchan_find_desc(&c->vc, cookie); | |
571 | if (vd) { | |
572 | txstate->residue = | |
573 | bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); | |
574 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { | |
575 | struct bcm2835_desc *d = c->desc; | |
576 | dma_addr_t pos; | |
577 | ||
578 | if (d->dir == DMA_MEM_TO_DEV) | |
579 | pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); | |
580 | else if (d->dir == DMA_DEV_TO_MEM) | |
581 | pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); | |
582 | else | |
583 | pos = 0; | |
584 | ||
585 | txstate->residue = bcm2835_dma_desc_size_pos(d, pos); | |
586 | } else { | |
587 | txstate->residue = 0; | |
588 | } | |
589 | ||
590 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
595 | static void bcm2835_dma_issue_pending(struct dma_chan *chan) | |
596 | { | |
597 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
598 | unsigned long flags; | |
599 | ||
96286b57 FM |
600 | spin_lock_irqsave(&c->vc.lock, flags); |
601 | if (vchan_issue_pending(&c->vc) && !c->desc) | |
602 | bcm2835_dma_start_desc(c); | |
603 | ||
604 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
605 | } | |
606 | ||
63637228 | 607 | static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy( |
d9f094a0 MS |
608 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, |
609 | size_t len, unsigned long flags) | |
610 | { | |
611 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
612 | struct bcm2835_desc *d; | |
613 | u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC; | |
614 | u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP; | |
615 | size_t max_len = bcm2835_dma_max_frame_length(c); | |
616 | size_t frames; | |
617 | ||
618 | /* if src, dst or len is not given return with an error */ | |
619 | if (!src || !dst || !len) | |
620 | return NULL; | |
621 | ||
622 | /* calculate number of frames */ | |
623 | frames = bcm2835_dma_frames_for_length(len, max_len); | |
624 | ||
625 | /* allocate the CB chain - this also fills in the pointers */ | |
626 | d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false, | |
627 | info, extra, frames, | |
628 | src, dst, len, 0, GFP_KERNEL); | |
629 | if (!d) | |
630 | return NULL; | |
631 | ||
632 | return vchan_tx_prep(&c->vc, &d->vd, flags); | |
633 | } | |
634 | ||
388cc7a2 MS |
635 | static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( |
636 | struct dma_chan *chan, | |
637 | struct scatterlist *sgl, unsigned int sg_len, | |
638 | enum dma_transfer_direction direction, | |
639 | unsigned long flags, void *context) | |
640 | { | |
641 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
642 | struct bcm2835_desc *d; | |
643 | dma_addr_t src = 0, dst = 0; | |
644 | u32 info = BCM2835_DMA_WAIT_RESP; | |
645 | u32 extra = BCM2835_DMA_INT_EN; | |
646 | size_t frames; | |
647 | ||
648 | if (!is_slave_direction(direction)) { | |
649 | dev_err(chan->device->dev, | |
650 | "%s: bad direction?\n", __func__); | |
651 | return NULL; | |
652 | } | |
653 | ||
654 | if (c->dreq != 0) | |
655 | info |= BCM2835_DMA_PER_MAP(c->dreq); | |
656 | ||
657 | if (direction == DMA_DEV_TO_MEM) { | |
658 | if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) | |
659 | return NULL; | |
660 | src = c->cfg.src_addr; | |
661 | info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; | |
662 | } else { | |
663 | if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) | |
664 | return NULL; | |
665 | dst = c->cfg.dst_addr; | |
666 | info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; | |
667 | } | |
668 | ||
669 | /* count frames in sg list */ | |
670 | frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len); | |
671 | ||
672 | /* allocate the CB chain */ | |
673 | d = bcm2835_dma_create_cb_chain(chan, direction, false, | |
674 | info, extra, | |
675 | frames, src, dst, 0, 0, | |
676 | GFP_KERNEL); | |
677 | if (!d) | |
678 | return NULL; | |
679 | ||
680 | /* fill in frames with scatterlist pointers */ | |
681 | bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list, | |
682 | sgl, sg_len); | |
683 | ||
684 | return vchan_tx_prep(&c->vc, &d->vd, flags); | |
685 | } | |
686 | ||
96286b57 FM |
687 | static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( |
688 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
689 | size_t period_len, enum dma_transfer_direction direction, | |
31c1e5a1 | 690 | unsigned long flags) |
96286b57 FM |
691 | { |
692 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
96286b57 | 693 | struct bcm2835_desc *d; |
92153bb5 MS |
694 | dma_addr_t src, dst; |
695 | u32 info = BCM2835_DMA_WAIT_RESP; | |
696 | u32 extra = BCM2835_DMA_INT_EN; | |
40874122 | 697 | size_t max_len = bcm2835_dma_max_frame_length(c); |
92153bb5 | 698 | size_t frames; |
96286b57 FM |
699 | |
700 | /* Grab configuration */ | |
701 | if (!is_slave_direction(direction)) { | |
702 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
703 | return NULL; | |
704 | } | |
705 | ||
92153bb5 MS |
706 | if (!buf_len) { |
707 | dev_err(chan->device->dev, | |
708 | "%s: bad buffer length (= 0)\n", __func__); | |
96286b57 FM |
709 | return NULL; |
710 | } | |
711 | ||
92153bb5 MS |
712 | /* |
713 | * warn if buf_len is not a multiple of period_len - this may leed | |
714 | * to unexpected latencies for interrupts and thus audiable clicks | |
715 | */ | |
716 | if (buf_len % period_len) | |
717 | dev_warn_once(chan->device->dev, | |
718 | "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n", | |
719 | __func__, buf_len, period_len); | |
96286b57 | 720 | |
92153bb5 MS |
721 | /* Setup DREQ channel */ |
722 | if (c->dreq != 0) | |
723 | info |= BCM2835_DMA_PER_MAP(c->dreq); | |
96286b57 | 724 | |
92153bb5 MS |
725 | if (direction == DMA_DEV_TO_MEM) { |
726 | if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) | |
727 | return NULL; | |
728 | src = c->cfg.src_addr; | |
729 | dst = buf_addr; | |
730 | info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; | |
731 | } else { | |
732 | if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) | |
733 | return NULL; | |
734 | dst = c->cfg.dst_addr; | |
735 | src = buf_addr; | |
736 | info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; | |
96286b57 | 737 | } |
27bc944c | 738 | |
92153bb5 | 739 | /* calculate number of frames */ |
40874122 MS |
740 | frames = /* number of periods */ |
741 | DIV_ROUND_UP(buf_len, period_len) * | |
742 | /* number of frames per period */ | |
743 | bcm2835_dma_frames_for_length(period_len, max_len); | |
96286b57 FM |
744 | |
745 | /* | |
92153bb5 MS |
746 | * allocate the CB chain |
747 | * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine | |
748 | * implementation calls prep_dma_cyclic with interrupts disabled. | |
96286b57 | 749 | */ |
92153bb5 MS |
750 | d = bcm2835_dma_create_cb_chain(chan, direction, true, |
751 | info, extra, | |
752 | frames, src, dst, buf_len, | |
753 | period_len, GFP_NOWAIT); | |
754 | if (!d) | |
755 | return NULL; | |
96286b57 | 756 | |
92153bb5 MS |
757 | /* wrap around into a loop */ |
758 | d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr; | |
96286b57 FM |
759 | |
760 | return vchan_tx_prep(&c->vc, &d->vd, flags); | |
761 | } | |
762 | ||
39159bea MR |
763 | static int bcm2835_dma_slave_config(struct dma_chan *chan, |
764 | struct dma_slave_config *cfg) | |
96286b57 | 765 | { |
39159bea MR |
766 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); |
767 | ||
96286b57 FM |
768 | c->cfg = *cfg; |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
39159bea | 773 | static int bcm2835_dma_terminate_all(struct dma_chan *chan) |
96286b57 | 774 | { |
39159bea | 775 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); |
96286b57 FM |
776 | struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); |
777 | unsigned long flags; | |
96286b57 FM |
778 | LIST_HEAD(head); |
779 | ||
780 | spin_lock_irqsave(&c->vc.lock, flags); | |
781 | ||
782 | /* Prevent this channel being scheduled */ | |
783 | spin_lock(&d->lock); | |
784 | list_del_init(&c->node); | |
785 | spin_unlock(&d->lock); | |
786 | ||
f7da7782 | 787 | /* stop DMA activity */ |
96286b57 | 788 | if (c->desc) { |
de92436a | 789 | vchan_terminate_vdesc(&c->desc->vd); |
96286b57 | 790 | c->desc = NULL; |
9e528c79 | 791 | bcm2835_dma_abort(c); |
96286b57 FM |
792 | } |
793 | ||
794 | vchan_get_all_descriptors(&c->vc, &head); | |
795 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
796 | vchan_dma_desc_free_list(&c->vc, &head); | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
de92436a PU |
801 | static void bcm2835_dma_synchronize(struct dma_chan *chan) |
802 | { | |
803 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
804 | ||
805 | vchan_synchronize(&c->vc); | |
806 | } | |
807 | ||
e2eca638 MS |
808 | static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, |
809 | int irq, unsigned int irq_flags) | |
96286b57 FM |
810 | { |
811 | struct bcm2835_chan *c; | |
812 | ||
813 | c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); | |
814 | if (!c) | |
815 | return -ENOMEM; | |
816 | ||
817 | c->vc.desc_free = bcm2835_dma_desc_free; | |
818 | vchan_init(&c->vc, &d->ddev); | |
819 | INIT_LIST_HEAD(&c->node); | |
820 | ||
96286b57 FM |
821 | c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); |
822 | c->ch = chan_id; | |
823 | c->irq_number = irq; | |
e2eca638 | 824 | c->irq_flags = irq_flags; |
96286b57 | 825 | |
40874122 MS |
826 | /* check in DEBUG register if this is a LITE channel */ |
827 | if (readl(c->chan_base + BCM2835_DMA_DEBUG) & | |
828 | BCM2835_DMA_DEBUG_LITE) | |
829 | c->is_lite_channel = true; | |
830 | ||
96286b57 FM |
831 | return 0; |
832 | } | |
833 | ||
834 | static void bcm2835_dma_free(struct bcm2835_dmadev *od) | |
835 | { | |
836 | struct bcm2835_chan *c, *next; | |
837 | ||
838 | list_for_each_entry_safe(c, next, &od->ddev.channels, | |
839 | vc.chan.device_node) { | |
840 | list_del(&c->vc.chan.device_node); | |
841 | tasklet_kill(&c->vc.task); | |
842 | } | |
843 | } | |
844 | ||
845 | static const struct of_device_id bcm2835_dma_of_match[] = { | |
846 | { .compatible = "brcm,bcm2835-dma", }, | |
847 | {}, | |
848 | }; | |
849 | MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); | |
850 | ||
851 | static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, | |
852 | struct of_dma *ofdma) | |
853 | { | |
854 | struct bcm2835_dmadev *d = ofdma->of_dma_data; | |
855 | struct dma_chan *chan; | |
856 | ||
857 | chan = dma_get_any_slave_channel(&d->ddev); | |
858 | if (!chan) | |
859 | return NULL; | |
860 | ||
861 | /* Set DREQ from param */ | |
862 | to_bcm2835_dma_chan(chan)->dreq = spec->args[0]; | |
863 | ||
864 | return chan; | |
865 | } | |
866 | ||
96286b57 FM |
867 | static int bcm2835_dma_probe(struct platform_device *pdev) |
868 | { | |
869 | struct bcm2835_dmadev *od; | |
870 | struct resource *res; | |
871 | void __iomem *base; | |
872 | int rc; | |
e2eca638 MS |
873 | int i, j; |
874 | int irq[BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1]; | |
875 | int irq_flags; | |
96286b57 | 876 | uint32_t chans_available; |
e2eca638 | 877 | char chan_name[BCM2835_DMA_CHAN_NAME_SIZE]; |
96286b57 FM |
878 | |
879 | if (!pdev->dev.dma_mask) | |
880 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | |
881 | ||
882 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
883 | if (rc) | |
884 | return rc; | |
885 | ||
886 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); | |
887 | if (!od) | |
888 | return -ENOMEM; | |
889 | ||
890 | pdev->dev.dma_parms = &od->dma_parms; | |
891 | dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); | |
892 | ||
893 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
894 | base = devm_ioremap_resource(&pdev->dev, res); | |
895 | if (IS_ERR(base)) | |
896 | return PTR_ERR(base); | |
897 | ||
898 | od->base = base; | |
899 | ||
900 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); | |
7f5ae355 | 901 | dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); |
96286b57 | 902 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
388cc7a2 | 903 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
d9f094a0 | 904 | dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask); |
96286b57 FM |
905 | od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; |
906 | od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; | |
907 | od->ddev.device_tx_status = bcm2835_dma_tx_status; | |
908 | od->ddev.device_issue_pending = bcm2835_dma_issue_pending; | |
96286b57 | 909 | od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; |
388cc7a2 | 910 | od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; |
d9f094a0 | 911 | od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy; |
39159bea MR |
912 | od->ddev.device_config = bcm2835_dma_slave_config; |
913 | od->ddev.device_terminate_all = bcm2835_dma_terminate_all; | |
de92436a | 914 | od->ddev.device_synchronize = bcm2835_dma_synchronize; |
b5743680 MR |
915 | od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); |
916 | od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); | |
d9f094a0 MS |
917 | od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | |
918 | BIT(DMA_MEM_TO_MEM); | |
0fa5867e | 919 | od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
96286b57 FM |
920 | od->ddev.dev = &pdev->dev; |
921 | INIT_LIST_HEAD(&od->ddev.channels); | |
922 | spin_lock_init(&od->lock); | |
923 | ||
924 | platform_set_drvdata(pdev, od); | |
925 | ||
926 | /* Request DMA channel mask from device tree */ | |
927 | if (of_property_read_u32(pdev->dev.of_node, | |
928 | "brcm,dma-channel-mask", | |
929 | &chans_available)) { | |
930 | dev_err(&pdev->dev, "Failed to get channel mask\n"); | |
931 | rc = -EINVAL; | |
932 | goto err_no_dma; | |
933 | } | |
934 | ||
e2eca638 MS |
935 | /* get irqs for each channel that we support */ |
936 | for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) { | |
937 | /* skip masked out channels */ | |
938 | if (!(chans_available & (1 << i))) { | |
939 | irq[i] = -1; | |
940 | continue; | |
96286b57 | 941 | } |
e2eca638 MS |
942 | |
943 | /* get the named irq */ | |
944 | snprintf(chan_name, sizeof(chan_name), "dma%i", i); | |
945 | irq[i] = platform_get_irq_byname(pdev, chan_name); | |
946 | if (irq[i] >= 0) | |
947 | continue; | |
948 | ||
949 | /* legacy device tree case handling */ | |
950 | dev_warn_once(&pdev->dev, | |
0eef727a | 951 | "missing interrupt-names property in device tree - legacy interpretation is used\n"); |
e2eca638 MS |
952 | /* |
953 | * in case of channel >= 11 | |
954 | * use the 11th interrupt and that is shared | |
955 | */ | |
956 | irq[i] = platform_get_irq(pdev, i < 11 ? i : 11); | |
957 | } | |
958 | ||
959 | /* get irqs for each channel */ | |
960 | for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) { | |
961 | /* skip channels without irq */ | |
962 | if (irq[i] < 0) | |
963 | continue; | |
964 | ||
965 | /* check if there are other channels that also use this irq */ | |
966 | irq_flags = 0; | |
967 | for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++) | |
968 | if ((i != j) && (irq[j] == irq[i])) { | |
969 | irq_flags = IRQF_SHARED; | |
970 | break; | |
971 | } | |
972 | ||
973 | /* initialize the channel */ | |
974 | rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags); | |
975 | if (rc) | |
976 | goto err_no_dma; | |
96286b57 FM |
977 | } |
978 | ||
979 | dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); | |
980 | ||
981 | /* Device-tree DMA controller registration */ | |
982 | rc = of_dma_controller_register(pdev->dev.of_node, | |
983 | bcm2835_dma_xlate, od); | |
984 | if (rc) { | |
985 | dev_err(&pdev->dev, "Failed to register DMA controller\n"); | |
986 | goto err_no_dma; | |
987 | } | |
988 | ||
989 | rc = dma_async_device_register(&od->ddev); | |
990 | if (rc) { | |
991 | dev_err(&pdev->dev, | |
992 | "Failed to register slave DMA engine device: %d\n", rc); | |
993 | goto err_no_dma; | |
994 | } | |
995 | ||
996 | dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n"); | |
997 | ||
998 | return 0; | |
999 | ||
1000 | err_no_dma: | |
1001 | bcm2835_dma_free(od); | |
1002 | return rc; | |
1003 | } | |
1004 | ||
1005 | static int bcm2835_dma_remove(struct platform_device *pdev) | |
1006 | { | |
1007 | struct bcm2835_dmadev *od = platform_get_drvdata(pdev); | |
1008 | ||
1009 | dma_async_device_unregister(&od->ddev); | |
1010 | bcm2835_dma_free(od); | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
1015 | static struct platform_driver bcm2835_dma_driver = { | |
1016 | .probe = bcm2835_dma_probe, | |
1017 | .remove = bcm2835_dma_remove, | |
1018 | .driver = { | |
1019 | .name = "bcm2835-dma", | |
96286b57 FM |
1020 | .of_match_table = of_match_ptr(bcm2835_dma_of_match), |
1021 | }, | |
1022 | }; | |
1023 | ||
1024 | module_platform_driver(bcm2835_dma_driver); | |
1025 | ||
1026 | MODULE_ALIAS("platform:bcm2835-dma"); | |
1027 | MODULE_DESCRIPTION("BCM2835 DMA engine driver"); | |
1028 | MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>"); | |
ab39e147 | 1029 | MODULE_LICENSE("GPL"); |