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e1f7c9ee LD |
1 | /* |
2 | * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2014 Atmel Corporation | |
5 | * | |
6 | * Author: Ludovic Desroches <ludovic.desroches@atmel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <asm/barrier.h> | |
22 | #include <dt-bindings/dma/at91.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/dmapool.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/irq.h> | |
6d3a7d9e | 28 | #include <linux/kernel.h> |
e1f7c9ee LD |
29 | #include <linux/list.h> |
30 | #include <linux/module.h> | |
31 | #include <linux/of_dma.h> | |
32 | #include <linux/of_platform.h> | |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/pm.h> | |
35 | ||
36 | #include "dmaengine.h" | |
37 | ||
38 | /* Global registers */ | |
39 | #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */ | |
40 | #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */ | |
41 | #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */ | |
42 | #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */ | |
43 | #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */ | |
44 | #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */ | |
45 | #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */ | |
46 | #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */ | |
47 | #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */ | |
48 | #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */ | |
49 | #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */ | |
50 | #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */ | |
51 | #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */ | |
52 | #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */ | |
53 | #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */ | |
54 | #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */ | |
55 | #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */ | |
56 | #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */ | |
57 | #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */ | |
58 | #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */ | |
59 | #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */ | |
60 | ||
61 | /* Channel relative registers offsets */ | |
62 | #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */ | |
63 | #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */ | |
64 | #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */ | |
65 | #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */ | |
66 | #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */ | |
67 | #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */ | |
68 | #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */ | |
69 | #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */ | |
70 | #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */ | |
71 | #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */ | |
72 | #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */ | |
73 | #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */ | |
74 | #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */ | |
75 | #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */ | |
76 | #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */ | |
77 | #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */ | |
78 | #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */ | |
79 | #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */ | |
80 | #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */ | |
81 | #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */ | |
82 | #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */ | |
83 | #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */ | |
84 | #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */ | |
85 | #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */ | |
86 | #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */ | |
87 | #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */ | |
88 | #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */ | |
89 | #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */ | |
90 | #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */ | |
91 | #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */ | |
92 | #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */ | |
93 | #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */ | |
94 | #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */ | |
95 | #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */ | |
96 | #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */ | |
97 | #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */ | |
98 | #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */ | |
99 | #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */ | |
100 | #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */ | |
101 | #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */ | |
102 | #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */ | |
103 | #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */ | |
104 | #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */ | |
105 | #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */ | |
106 | #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */ | |
107 | #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */ | |
108 | #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */ | |
109 | #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */ | |
110 | #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */ | |
111 | #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */ | |
112 | #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */ | |
113 | #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1) | |
114 | #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1) | |
115 | #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1) | |
116 | #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1) | |
117 | #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1) | |
118 | #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */ | |
119 | #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4) | |
120 | #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4) | |
121 | #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */ | |
122 | #define AT_XDMAC_CC_PROT_SEC (0x0 << 5) | |
123 | #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5) | |
124 | #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */ | |
125 | #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6) | |
126 | #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6) | |
127 | #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */ | |
128 | #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7) | |
129 | #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7) | |
130 | #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */ | |
131 | #define AT_XDMAC_CC_DWIDTH_OFFSET 11 | |
132 | #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET) | |
133 | #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */ | |
134 | #define AT_XDMAC_CC_DWIDTH_BYTE 0x0 | |
135 | #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1 | |
136 | #define AT_XDMAC_CC_DWIDTH_WORD 0x2 | |
137 | #define AT_XDMAC_CC_DWIDTH_DWORD 0x3 | |
138 | #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */ | |
139 | #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */ | |
140 | #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */ | |
141 | #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16) | |
142 | #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16) | |
143 | #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16) | |
144 | #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16) | |
145 | #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */ | |
146 | #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18) | |
147 | #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18) | |
148 | #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18) | |
149 | #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18) | |
150 | #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */ | |
151 | #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21) | |
152 | #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21) | |
153 | #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */ | |
154 | #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22) | |
155 | #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22) | |
156 | #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */ | |
157 | #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23) | |
158 | #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23) | |
15a03850 | 159 | #define AT_XDMAC_CC_PERID(i) (0x7f & (i) << 24) /* Channel Peripheral Identifier */ |
e1f7c9ee LD |
160 | #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */ |
161 | #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */ | |
162 | #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */ | |
163 | ||
164 | #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */ | |
165 | ||
166 | /* Microblock control members */ | |
167 | #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */ | |
168 | #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */ | |
169 | #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */ | |
170 | #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */ | |
171 | #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */ | |
172 | #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */ | |
173 | #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */ | |
174 | #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */ | |
175 | ||
176 | #define AT_XDMAC_MAX_CHAN 0x20 | |
765c37d8 LD |
177 | #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */ |
178 | #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */ | |
25c5e962 | 179 | #define AT_XDMAC_RESIDUE_MAX_RETRIES 5 |
e1f7c9ee | 180 | |
8ac82f88 LD |
181 | #define AT_XDMAC_DMA_BUSWIDTHS\ |
182 | (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ | |
183 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ | |
184 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ | |
185 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\ | |
186 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) | |
187 | ||
e1f7c9ee LD |
188 | enum atc_status { |
189 | AT_XDMAC_CHAN_IS_CYCLIC = 0, | |
190 | AT_XDMAC_CHAN_IS_PAUSED, | |
191 | }; | |
192 | ||
193 | /* ----- Channels ----- */ | |
194 | struct at_xdmac_chan { | |
195 | struct dma_chan chan; | |
196 | void __iomem *ch_regs; | |
197 | u32 mask; /* Channel Mask */ | |
765c37d8 | 198 | u32 cfg; /* Channel Configuration Register */ |
e1f7c9ee LD |
199 | u8 perid; /* Peripheral ID */ |
200 | u8 perif; /* Peripheral Interface */ | |
201 | u8 memif; /* Memory Interface */ | |
734bb9a7 | 202 | u32 save_cc; |
e1f7c9ee LD |
203 | u32 save_cim; |
204 | u32 save_cnda; | |
205 | u32 save_cndc; | |
206 | unsigned long status; | |
207 | struct tasklet_struct tasklet; | |
765c37d8 | 208 | struct dma_slave_config sconfig; |
e1f7c9ee LD |
209 | |
210 | spinlock_t lock; | |
211 | ||
212 | struct list_head xfers_list; | |
213 | struct list_head free_descs_list; | |
214 | }; | |
215 | ||
216 | ||
217 | /* ----- Controller ----- */ | |
218 | struct at_xdmac { | |
219 | struct dma_device dma; | |
220 | void __iomem *regs; | |
221 | int irq; | |
222 | struct clk *clk; | |
223 | u32 save_gim; | |
e1f7c9ee LD |
224 | struct dma_pool *at_xdmac_desc_pool; |
225 | struct at_xdmac_chan chan[0]; | |
226 | }; | |
227 | ||
228 | ||
229 | /* ----- Descriptors ----- */ | |
230 | ||
231 | /* Linked List Descriptor */ | |
232 | struct at_xdmac_lld { | |
233 | dma_addr_t mbr_nda; /* Next Descriptor Member */ | |
234 | u32 mbr_ubc; /* Microblock Control Member */ | |
235 | dma_addr_t mbr_sa; /* Source Address Member */ | |
236 | dma_addr_t mbr_da; /* Destination Address Member */ | |
237 | u32 mbr_cfg; /* Configuration Register */ | |
ee0fe35c MR |
238 | u32 mbr_bc; /* Block Control Register */ |
239 | u32 mbr_ds; /* Data Stride Register */ | |
240 | u32 mbr_sus; /* Source Microblock Stride Register */ | |
241 | u32 mbr_dus; /* Destination Microblock Stride Register */ | |
e1f7c9ee LD |
242 | }; |
243 | ||
4a9723e8 | 244 | /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */ |
e1f7c9ee LD |
245 | struct at_xdmac_desc { |
246 | struct at_xdmac_lld lld; | |
247 | enum dma_transfer_direction direction; | |
248 | struct dma_async_tx_descriptor tx_dma_desc; | |
249 | struct list_head desc_node; | |
250 | /* Following members are only used by the first descriptor */ | |
251 | bool active_xfer; | |
252 | unsigned int xfer_size; | |
253 | struct list_head descs_list; | |
254 | struct list_head xfer_node; | |
4a9723e8 | 255 | } __aligned(sizeof(u64)); |
e1f7c9ee LD |
256 | |
257 | static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) | |
258 | { | |
259 | return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40); | |
260 | } | |
261 | ||
6e5ae29b | 262 | #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) |
e1f7c9ee | 263 | #define at_xdmac_write(atxdmac, reg, value) \ |
6e5ae29b | 264 | writel_relaxed((value), (atxdmac)->regs + (reg)) |
e1f7c9ee | 265 | |
6e5ae29b LD |
266 | #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg)) |
267 | #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg)) | |
e1f7c9ee LD |
268 | |
269 | static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan) | |
270 | { | |
271 | return container_of(dchan, struct at_xdmac_chan, chan); | |
272 | } | |
273 | ||
274 | static struct device *chan2dev(struct dma_chan *chan) | |
275 | { | |
276 | return &chan->dev->device; | |
277 | } | |
278 | ||
279 | static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev) | |
280 | { | |
281 | return container_of(ddev, struct at_xdmac, dma); | |
282 | } | |
283 | ||
284 | static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd) | |
285 | { | |
286 | return container_of(txd, struct at_xdmac_desc, tx_dma_desc); | |
287 | } | |
288 | ||
289 | static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan) | |
290 | { | |
291 | return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); | |
292 | } | |
293 | ||
294 | static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan) | |
295 | { | |
296 | return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); | |
297 | } | |
298 | ||
299 | static inline int at_xdmac_csize(u32 maxburst) | |
300 | { | |
301 | int csize; | |
302 | ||
303 | csize = ffs(maxburst) - 1; | |
304 | if (csize > 4) | |
305 | csize = -EINVAL; | |
306 | ||
307 | return csize; | |
308 | }; | |
309 | ||
310 | static inline u8 at_xdmac_get_dwidth(u32 cfg) | |
311 | { | |
312 | return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET; | |
313 | }; | |
314 | ||
315 | static unsigned int init_nr_desc_per_channel = 64; | |
316 | module_param(init_nr_desc_per_channel, uint, 0644); | |
317 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
318 | "initial descriptors per channel (default: 64)"); | |
319 | ||
320 | ||
321 | static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan) | |
322 | { | |
323 | return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask; | |
324 | } | |
325 | ||
326 | static void at_xdmac_off(struct at_xdmac *atxdmac) | |
327 | { | |
328 | at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L); | |
329 | ||
330 | /* Wait that all chans are disabled. */ | |
331 | while (at_xdmac_read(atxdmac, AT_XDMAC_GS)) | |
332 | cpu_relax(); | |
333 | ||
334 | at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L); | |
335 | } | |
336 | ||
337 | /* Call with lock hold. */ | |
338 | static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, | |
339 | struct at_xdmac_desc *first) | |
340 | { | |
341 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
342 | u32 reg; | |
343 | ||
344 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first); | |
345 | ||
346 | if (at_xdmac_chan_is_enabled(atchan)) | |
347 | return; | |
348 | ||
349 | /* Set transfer as active to not try to start it again. */ | |
350 | first->active_xfer = true; | |
351 | ||
352 | /* Tell xdmac where to get the first descriptor. */ | |
353 | reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) | |
354 | | AT_XDMAC_CNDA_NDAIF(atchan->memif); | |
355 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); | |
356 | ||
357 | /* | |
6d3a7d9e | 358 | * When doing non cyclic transfer we need to use the next |
e1f7c9ee LD |
359 | * descriptor view 2 since some fields of the configuration register |
360 | * depend on transfer size and src/dest addresses. | |
361 | */ | |
20cadcb4 | 362 | if (at_xdmac_chan_is_cyclic(atchan)) |
e1f7c9ee | 363 | reg = AT_XDMAC_CNDC_NDVIEW_NDV1; |
20cadcb4 | 364 | else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) |
ee0fe35c | 365 | reg = AT_XDMAC_CNDC_NDVIEW_NDV3; |
20cadcb4 | 366 | else |
e1f7c9ee | 367 | reg = AT_XDMAC_CNDC_NDVIEW_NDV2; |
20cadcb4 LD |
368 | /* |
369 | * Even if the register will be updated from the configuration in the | |
370 | * descriptor when using view 2 or higher, the PROT bit won't be set | |
371 | * properly. This bit can be modified only by using the channel | |
372 | * configuration register. | |
373 | */ | |
374 | at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg); | |
e1f7c9ee LD |
375 | |
376 | reg |= AT_XDMAC_CNDC_NDDUP | |
377 | | AT_XDMAC_CNDC_NDSUP | |
378 | | AT_XDMAC_CNDC_NDE; | |
379 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg); | |
380 | ||
381 | dev_vdbg(chan2dev(&atchan->chan), | |
382 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", | |
383 | __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), | |
384 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), | |
385 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), | |
386 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), | |
387 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), | |
388 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); | |
389 | ||
390 | at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff); | |
391 | reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE; | |
392 | /* | |
393 | * There is no end of list when doing cyclic dma, we need to get | |
394 | * an interrupt after each periods. | |
395 | */ | |
396 | if (at_xdmac_chan_is_cyclic(atchan)) | |
397 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, | |
398 | reg | AT_XDMAC_CIE_BIE); | |
399 | else | |
400 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, | |
401 | reg | AT_XDMAC_CIE_LIE); | |
402 | at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask); | |
403 | dev_vdbg(chan2dev(&atchan->chan), | |
404 | "%s: enable channel (0x%08x)\n", __func__, atchan->mask); | |
405 | wmb(); | |
406 | at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); | |
407 | ||
408 | dev_vdbg(chan2dev(&atchan->chan), | |
409 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", | |
410 | __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), | |
411 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), | |
412 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), | |
413 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), | |
414 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), | |
415 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); | |
416 | ||
417 | } | |
418 | ||
419 | static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx) | |
420 | { | |
421 | struct at_xdmac_desc *desc = txd_to_at_desc(tx); | |
422 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan); | |
423 | dma_cookie_t cookie; | |
4c374fc7 | 424 | unsigned long irqflags; |
e1f7c9ee | 425 | |
4c374fc7 | 426 | spin_lock_irqsave(&atchan->lock, irqflags); |
e1f7c9ee LD |
427 | cookie = dma_cookie_assign(tx); |
428 | ||
429 | dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", | |
430 | __func__, atchan, desc); | |
431 | list_add_tail(&desc->xfer_node, &atchan->xfers_list); | |
432 | if (list_is_singular(&atchan->xfers_list)) | |
433 | at_xdmac_start_xfer(atchan, desc); | |
434 | ||
4c374fc7 | 435 | spin_unlock_irqrestore(&atchan->lock, irqflags); |
e1f7c9ee LD |
436 | return cookie; |
437 | } | |
438 | ||
439 | static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan, | |
440 | gfp_t gfp_flags) | |
441 | { | |
442 | struct at_xdmac_desc *desc; | |
443 | struct at_xdmac *atxdmac = to_at_xdmac(chan->device); | |
444 | dma_addr_t phys; | |
445 | ||
9dcd7408 | 446 | desc = dma_pool_zalloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys); |
e1f7c9ee | 447 | if (desc) { |
e1f7c9ee LD |
448 | INIT_LIST_HEAD(&desc->descs_list); |
449 | dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan); | |
450 | desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit; | |
451 | desc->tx_dma_desc.phys = phys; | |
452 | } | |
453 | ||
454 | return desc; | |
455 | } | |
456 | ||
192dc8c0 | 457 | static void at_xdmac_init_used_desc(struct at_xdmac_desc *desc) |
0be2136b LD |
458 | { |
459 | memset(&desc->lld, 0, sizeof(desc->lld)); | |
460 | INIT_LIST_HEAD(&desc->descs_list); | |
461 | desc->direction = DMA_TRANS_NONE; | |
462 | desc->xfer_size = 0; | |
463 | desc->active_xfer = false; | |
464 | } | |
465 | ||
e1f7c9ee LD |
466 | /* Call must be protected by lock. */ |
467 | static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan) | |
468 | { | |
469 | struct at_xdmac_desc *desc; | |
470 | ||
471 | if (list_empty(&atchan->free_descs_list)) { | |
472 | desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT); | |
473 | } else { | |
474 | desc = list_first_entry(&atchan->free_descs_list, | |
475 | struct at_xdmac_desc, desc_node); | |
476 | list_del(&desc->desc_node); | |
0be2136b | 477 | at_xdmac_init_used_desc(desc); |
e1f7c9ee LD |
478 | } |
479 | ||
480 | return desc; | |
481 | } | |
482 | ||
0d0ee751 MR |
483 | static void at_xdmac_queue_desc(struct dma_chan *chan, |
484 | struct at_xdmac_desc *prev, | |
485 | struct at_xdmac_desc *desc) | |
486 | { | |
487 | if (!prev || !desc) | |
488 | return; | |
489 | ||
490 | prev->lld.mbr_nda = desc->tx_dma_desc.phys; | |
491 | prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE; | |
492 | ||
493 | dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", | |
494 | __func__, prev, &prev->lld.mbr_nda); | |
495 | } | |
496 | ||
6007ccb5 MR |
497 | static inline void at_xdmac_increment_block_count(struct dma_chan *chan, |
498 | struct at_xdmac_desc *desc) | |
499 | { | |
500 | if (!desc) | |
501 | return; | |
502 | ||
503 | desc->lld.mbr_bc++; | |
504 | ||
505 | dev_dbg(chan2dev(chan), | |
506 | "%s: incrementing the block count of the desc 0x%p\n", | |
507 | __func__, desc); | |
508 | } | |
509 | ||
e1f7c9ee LD |
510 | static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec, |
511 | struct of_dma *of_dma) | |
512 | { | |
513 | struct at_xdmac *atxdmac = of_dma->of_dma_data; | |
514 | struct at_xdmac_chan *atchan; | |
515 | struct dma_chan *chan; | |
516 | struct device *dev = atxdmac->dma.dev; | |
517 | ||
518 | if (dma_spec->args_count != 1) { | |
519 | dev_err(dev, "dma phandler args: bad number of args\n"); | |
520 | return NULL; | |
521 | } | |
522 | ||
523 | chan = dma_get_any_slave_channel(&atxdmac->dma); | |
524 | if (!chan) { | |
525 | dev_err(dev, "can't get a dma channel\n"); | |
526 | return NULL; | |
527 | } | |
528 | ||
529 | atchan = to_at_xdmac_chan(chan); | |
530 | atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]); | |
531 | atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]); | |
532 | atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]); | |
533 | dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n", | |
534 | atchan->memif, atchan->perif, atchan->perid); | |
535 | ||
536 | return chan; | |
537 | } | |
538 | ||
765c37d8 LD |
539 | static int at_xdmac_compute_chan_conf(struct dma_chan *chan, |
540 | enum dma_transfer_direction direction) | |
541 | { | |
542 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
543 | int csize, dwidth; | |
544 | ||
545 | if (direction == DMA_DEV_TO_MEM) { | |
546 | atchan->cfg = | |
547 | AT91_XDMAC_DT_PERID(atchan->perid) | |
548 | | AT_XDMAC_CC_DAM_INCREMENTED_AM | |
549 | | AT_XDMAC_CC_SAM_FIXED_AM | |
550 | | AT_XDMAC_CC_DIF(atchan->memif) | |
551 | | AT_XDMAC_CC_SIF(atchan->perif) | |
552 | | AT_XDMAC_CC_SWREQ_HWR_CONNECTED | |
553 | | AT_XDMAC_CC_DSYNC_PER2MEM | |
554 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
555 | | AT_XDMAC_CC_TYPE_PER_TRAN; | |
556 | csize = ffs(atchan->sconfig.src_maxburst) - 1; | |
557 | if (csize < 0) { | |
558 | dev_err(chan2dev(chan), "invalid src maxburst value\n"); | |
559 | return -EINVAL; | |
560 | } | |
561 | atchan->cfg |= AT_XDMAC_CC_CSIZE(csize); | |
562 | dwidth = ffs(atchan->sconfig.src_addr_width) - 1; | |
563 | if (dwidth < 0) { | |
564 | dev_err(chan2dev(chan), "invalid src addr width value\n"); | |
565 | return -EINVAL; | |
566 | } | |
567 | atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth); | |
568 | } else if (direction == DMA_MEM_TO_DEV) { | |
569 | atchan->cfg = | |
570 | AT91_XDMAC_DT_PERID(atchan->perid) | |
571 | | AT_XDMAC_CC_DAM_FIXED_AM | |
572 | | AT_XDMAC_CC_SAM_INCREMENTED_AM | |
573 | | AT_XDMAC_CC_DIF(atchan->perif) | |
574 | | AT_XDMAC_CC_SIF(atchan->memif) | |
575 | | AT_XDMAC_CC_SWREQ_HWR_CONNECTED | |
576 | | AT_XDMAC_CC_DSYNC_MEM2PER | |
577 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
578 | | AT_XDMAC_CC_TYPE_PER_TRAN; | |
579 | csize = ffs(atchan->sconfig.dst_maxburst) - 1; | |
580 | if (csize < 0) { | |
581 | dev_err(chan2dev(chan), "invalid src maxburst value\n"); | |
582 | return -EINVAL; | |
583 | } | |
584 | atchan->cfg |= AT_XDMAC_CC_CSIZE(csize); | |
585 | dwidth = ffs(atchan->sconfig.dst_addr_width) - 1; | |
586 | if (dwidth < 0) { | |
587 | dev_err(chan2dev(chan), "invalid dst addr width value\n"); | |
588 | return -EINVAL; | |
589 | } | |
590 | atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth); | |
591 | } | |
592 | ||
593 | dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg); | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
598 | /* | |
599 | * Only check that maxburst and addr width values are supported by the | |
600 | * the controller but not that the configuration is good to perform the | |
601 | * transfer since we don't know the direction at this stage. | |
602 | */ | |
603 | static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig) | |
604 | { | |
605 | if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE) | |
606 | || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE)) | |
607 | return -EINVAL; | |
608 | ||
609 | if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH) | |
610 | || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH)) | |
611 | return -EINVAL; | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
e1f7c9ee LD |
616 | static int at_xdmac_set_slave_config(struct dma_chan *chan, |
617 | struct dma_slave_config *sconfig) | |
618 | { | |
619 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
e1f7c9ee | 620 | |
765c37d8 LD |
621 | if (at_xdmac_check_slave_config(sconfig)) { |
622 | dev_err(chan2dev(chan), "invalid slave configuration\n"); | |
e1f7c9ee LD |
623 | return -EINVAL; |
624 | } | |
e1f7c9ee | 625 | |
765c37d8 | 626 | memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig)); |
e1f7c9ee LD |
627 | |
628 | return 0; | |
629 | } | |
630 | ||
631 | static struct dma_async_tx_descriptor * | |
632 | at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
633 | unsigned int sg_len, enum dma_transfer_direction direction, | |
634 | unsigned long flags, void *context) | |
635 | { | |
35ca0ee4 LD |
636 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
637 | struct at_xdmac_desc *first = NULL, *prev = NULL; | |
638 | struct scatterlist *sg; | |
639 | int i; | |
640 | unsigned int xfer_size = 0; | |
641 | unsigned long irqflags; | |
4c374fc7 | 642 | struct dma_async_tx_descriptor *ret = NULL; |
e1f7c9ee LD |
643 | |
644 | if (!sgl) | |
645 | return NULL; | |
646 | ||
647 | if (!is_slave_direction(direction)) { | |
648 | dev_err(chan2dev(chan), "invalid DMA direction\n"); | |
649 | return NULL; | |
650 | } | |
651 | ||
652 | dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n", | |
653 | __func__, sg_len, | |
654 | direction == DMA_MEM_TO_DEV ? "to device" : "from device", | |
655 | flags); | |
656 | ||
657 | /* Protect dma_sconfig field that can be modified by set_slave_conf. */ | |
4c374fc7 | 658 | spin_lock_irqsave(&atchan->lock, irqflags); |
e1f7c9ee | 659 | |
765c37d8 LD |
660 | if (at_xdmac_compute_chan_conf(chan, direction)) |
661 | goto spin_unlock; | |
662 | ||
e1f7c9ee LD |
663 | /* Prepare descriptors. */ |
664 | for_each_sg(sgl, sg, sg_len, i) { | |
665 | struct at_xdmac_desc *desc = NULL; | |
6d3a7d9e | 666 | u32 len, mem, dwidth, fixed_dwidth; |
e1f7c9ee LD |
667 | |
668 | len = sg_dma_len(sg); | |
669 | mem = sg_dma_address(sg); | |
670 | if (unlikely(!len)) { | |
671 | dev_err(chan2dev(chan), "sg data length is zero\n"); | |
4c374fc7 | 672 | goto spin_unlock; |
e1f7c9ee LD |
673 | } |
674 | dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n", | |
675 | __func__, i, len, mem); | |
676 | ||
677 | desc = at_xdmac_get_desc(atchan); | |
678 | if (!desc) { | |
679 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
680 | if (first) | |
681 | list_splice_init(&first->descs_list, &atchan->free_descs_list); | |
4c374fc7 | 682 | goto spin_unlock; |
e1f7c9ee LD |
683 | } |
684 | ||
685 | /* Linked list descriptor setup. */ | |
686 | if (direction == DMA_DEV_TO_MEM) { | |
765c37d8 | 687 | desc->lld.mbr_sa = atchan->sconfig.src_addr; |
e1f7c9ee | 688 | desc->lld.mbr_da = mem; |
e1f7c9ee LD |
689 | } else { |
690 | desc->lld.mbr_sa = mem; | |
765c37d8 | 691 | desc->lld.mbr_da = atchan->sconfig.dst_addr; |
e1f7c9ee | 692 | } |
1c8a38b1 | 693 | dwidth = at_xdmac_get_dwidth(atchan->cfg); |
6d3a7d9e | 694 | fixed_dwidth = IS_ALIGNED(len, 1 << dwidth) |
1c8a38b1 | 695 | ? dwidth |
6d3a7d9e LD |
696 | : AT_XDMAC_CC_DWIDTH_BYTE; |
697 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */ | |
be835074 LD |
698 | | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */ |
699 | | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */ | |
6d3a7d9e | 700 | | (len >> fixed_dwidth); /* microblock length */ |
1c8a38b1 CP |
701 | desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) | |
702 | AT_XDMAC_CC_DWIDTH(fixed_dwidth); | |
e1f7c9ee | 703 | dev_dbg(chan2dev(chan), |
82e24246 VK |
704 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", |
705 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); | |
e1f7c9ee LD |
706 | |
707 | /* Chain lld. */ | |
0d0ee751 MR |
708 | if (prev) |
709 | at_xdmac_queue_desc(chan, prev, desc); | |
e1f7c9ee LD |
710 | |
711 | prev = desc; | |
712 | if (!first) | |
713 | first = desc; | |
714 | ||
715 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
716 | __func__, desc, first); | |
717 | list_add_tail(&desc->desc_node, &first->descs_list); | |
57819276 | 718 | xfer_size += len; |
e1f7c9ee LD |
719 | } |
720 | ||
e1f7c9ee LD |
721 | |
722 | first->tx_dma_desc.flags = flags; | |
57819276 | 723 | first->xfer_size = xfer_size; |
e1f7c9ee | 724 | first->direction = direction; |
4c374fc7 | 725 | ret = &first->tx_dma_desc; |
e1f7c9ee | 726 | |
4c374fc7 LD |
727 | spin_unlock: |
728 | spin_unlock_irqrestore(&atchan->lock, irqflags); | |
729 | return ret; | |
e1f7c9ee LD |
730 | } |
731 | ||
732 | static struct dma_async_tx_descriptor * | |
733 | at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, | |
734 | size_t buf_len, size_t period_len, | |
735 | enum dma_transfer_direction direction, | |
736 | unsigned long flags) | |
737 | { | |
738 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
739 | struct at_xdmac_desc *first = NULL, *prev = NULL; | |
740 | unsigned int periods = buf_len / period_len; | |
741 | int i; | |
4c374fc7 | 742 | unsigned long irqflags; |
e1f7c9ee | 743 | |
82e24246 VK |
744 | dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n", |
745 | __func__, &buf_addr, buf_len, period_len, | |
e1f7c9ee LD |
746 | direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags); |
747 | ||
748 | if (!is_slave_direction(direction)) { | |
749 | dev_err(chan2dev(chan), "invalid DMA direction\n"); | |
750 | return NULL; | |
751 | } | |
752 | ||
753 | if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) { | |
754 | dev_err(chan2dev(chan), "channel currently used\n"); | |
755 | return NULL; | |
756 | } | |
757 | ||
765c37d8 LD |
758 | if (at_xdmac_compute_chan_conf(chan, direction)) |
759 | return NULL; | |
760 | ||
e1f7c9ee LD |
761 | for (i = 0; i < periods; i++) { |
762 | struct at_xdmac_desc *desc = NULL; | |
763 | ||
4c374fc7 | 764 | spin_lock_irqsave(&atchan->lock, irqflags); |
e1f7c9ee LD |
765 | desc = at_xdmac_get_desc(atchan); |
766 | if (!desc) { | |
767 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
768 | if (first) | |
769 | list_splice_init(&first->descs_list, &atchan->free_descs_list); | |
4c374fc7 | 770 | spin_unlock_irqrestore(&atchan->lock, irqflags); |
e1f7c9ee LD |
771 | return NULL; |
772 | } | |
4c374fc7 | 773 | spin_unlock_irqrestore(&atchan->lock, irqflags); |
e1f7c9ee | 774 | dev_dbg(chan2dev(chan), |
82e24246 VK |
775 | "%s: desc=0x%p, tx_dma_desc.phys=%pad\n", |
776 | __func__, desc, &desc->tx_dma_desc.phys); | |
e1f7c9ee LD |
777 | |
778 | if (direction == DMA_DEV_TO_MEM) { | |
765c37d8 | 779 | desc->lld.mbr_sa = atchan->sconfig.src_addr; |
e1f7c9ee | 780 | desc->lld.mbr_da = buf_addr + i * period_len; |
e1f7c9ee LD |
781 | } else { |
782 | desc->lld.mbr_sa = buf_addr + i * period_len; | |
765c37d8 | 783 | desc->lld.mbr_da = atchan->sconfig.dst_addr; |
5ac7d582 | 784 | } |
765c37d8 | 785 | desc->lld.mbr_cfg = atchan->cfg; |
e1f7c9ee LD |
786 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1 |
787 | | AT_XDMAC_MBR_UBC_NDEN | |
788 | | AT_XDMAC_MBR_UBC_NSEN | |
6eb9d3c1 | 789 | | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg); |
e1f7c9ee LD |
790 | |
791 | dev_dbg(chan2dev(chan), | |
82e24246 VK |
792 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", |
793 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); | |
e1f7c9ee LD |
794 | |
795 | /* Chain lld. */ | |
0d0ee751 MR |
796 | if (prev) |
797 | at_xdmac_queue_desc(chan, prev, desc); | |
e1f7c9ee LD |
798 | |
799 | prev = desc; | |
800 | if (!first) | |
801 | first = desc; | |
802 | ||
803 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
804 | __func__, desc, first); | |
805 | list_add_tail(&desc->desc_node, &first->descs_list); | |
806 | } | |
807 | ||
e900c30d | 808 | at_xdmac_queue_desc(chan, prev, first); |
e1f7c9ee LD |
809 | first->tx_dma_desc.flags = flags; |
810 | first->xfer_size = buf_len; | |
811 | first->direction = direction; | |
812 | ||
813 | return &first->tx_dma_desc; | |
814 | } | |
815 | ||
f0816a36 MR |
816 | static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr) |
817 | { | |
818 | u32 width; | |
819 | ||
820 | /* | |
821 | * Check address alignment to select the greater data width we | |
822 | * can use. | |
823 | * | |
824 | * Some XDMAC implementations don't provide dword transfer, in | |
825 | * this case selecting dword has the same behavior as | |
826 | * selecting word transfers. | |
827 | */ | |
828 | if (!(addr & 7)) { | |
829 | width = AT_XDMAC_CC_DWIDTH_DWORD; | |
830 | dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__); | |
831 | } else if (!(addr & 3)) { | |
832 | width = AT_XDMAC_CC_DWIDTH_WORD; | |
833 | dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__); | |
834 | } else if (!(addr & 1)) { | |
835 | width = AT_XDMAC_CC_DWIDTH_HALFWORD; | |
836 | dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__); | |
837 | } else { | |
838 | width = AT_XDMAC_CC_DWIDTH_BYTE; | |
839 | dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__); | |
840 | } | |
841 | ||
842 | return width; | |
843 | } | |
844 | ||
6007ccb5 MR |
845 | static struct at_xdmac_desc * |
846 | at_xdmac_interleaved_queue_desc(struct dma_chan *chan, | |
847 | struct at_xdmac_chan *atchan, | |
848 | struct at_xdmac_desc *prev, | |
849 | dma_addr_t src, dma_addr_t dst, | |
850 | struct dma_interleaved_template *xt, | |
851 | struct data_chunk *chunk) | |
852 | { | |
853 | struct at_xdmac_desc *desc; | |
854 | u32 dwidth; | |
855 | unsigned long flags; | |
856 | size_t ublen; | |
857 | /* | |
858 | * WARNING: The channel configuration is set here since there is no | |
859 | * dmaengine_slave_config call in this case. Moreover we don't know the | |
860 | * direction, it involves we can't dynamically set the source and dest | |
861 | * interface so we have to use the same one. Only interface 0 allows EBI | |
862 | * access. Hopefully we can access DDR through both ports (at least on | |
863 | * SAMA5D4x), so we can use the same interface for source and dest, | |
864 | * that solves the fact we don't know the direction. | |
95da0c19 LD |
865 | * ERRATA: Even if useless for memory transfers, the PERID has to not |
866 | * match the one of another channel. If not, it could lead to spurious | |
867 | * flag status. | |
6007ccb5 | 868 | */ |
95da0c19 LD |
869 | u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) |
870 | | AT_XDMAC_CC_DIF(0) | |
6007ccb5 MR |
871 | | AT_XDMAC_CC_SIF(0) |
872 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
873 | | AT_XDMAC_CC_TYPE_MEM_TRAN; | |
874 | ||
875 | dwidth = at_xdmac_align_width(chan, src | dst | chunk->size); | |
876 | if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) { | |
877 | dev_dbg(chan2dev(chan), | |
1edc85dc | 878 | "%s: chunk too big (%zu, max size %lu)...\n", |
6007ccb5 MR |
879 | __func__, chunk->size, |
880 | AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth); | |
881 | return NULL; | |
882 | } | |
883 | ||
884 | if (prev) | |
885 | dev_dbg(chan2dev(chan), | |
886 | "Adding items at the end of desc 0x%p\n", prev); | |
887 | ||
888 | if (xt->src_inc) { | |
889 | if (xt->src_sgl) | |
a1cf0903 | 890 | chan_cc |= AT_XDMAC_CC_SAM_UBS_AM; |
6007ccb5 MR |
891 | else |
892 | chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM; | |
893 | } | |
894 | ||
895 | if (xt->dst_inc) { | |
896 | if (xt->dst_sgl) | |
a1cf0903 | 897 | chan_cc |= AT_XDMAC_CC_DAM_UBS_AM; |
6007ccb5 MR |
898 | else |
899 | chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM; | |
900 | } | |
901 | ||
902 | spin_lock_irqsave(&atchan->lock, flags); | |
903 | desc = at_xdmac_get_desc(atchan); | |
904 | spin_unlock_irqrestore(&atchan->lock, flags); | |
905 | if (!desc) { | |
906 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
907 | return NULL; | |
908 | } | |
909 | ||
910 | chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); | |
911 | ||
912 | ublen = chunk->size >> dwidth; | |
913 | ||
914 | desc->lld.mbr_sa = src; | |
915 | desc->lld.mbr_da = dst; | |
87d001ef MR |
916 | desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk); |
917 | desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk); | |
6007ccb5 MR |
918 | |
919 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3 | |
920 | | AT_XDMAC_MBR_UBC_NDEN | |
921 | | AT_XDMAC_MBR_UBC_NSEN | |
922 | | ublen; | |
923 | desc->lld.mbr_cfg = chan_cc; | |
924 | ||
925 | dev_dbg(chan2dev(chan), | |
268914f4 AB |
926 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", |
927 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, | |
6007ccb5 MR |
928 | desc->lld.mbr_ubc, desc->lld.mbr_cfg); |
929 | ||
930 | /* Chain lld. */ | |
931 | if (prev) | |
932 | at_xdmac_queue_desc(chan, prev, desc); | |
933 | ||
934 | return desc; | |
935 | } | |
936 | ||
6007ccb5 MR |
937 | static struct dma_async_tx_descriptor * |
938 | at_xdmac_prep_interleaved(struct dma_chan *chan, | |
939 | struct dma_interleaved_template *xt, | |
940 | unsigned long flags) | |
941 | { | |
942 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
943 | struct at_xdmac_desc *prev = NULL, *first = NULL; | |
6007ccb5 | 944 | dma_addr_t dst_addr, src_addr; |
4e538578 MR |
945 | size_t src_skip = 0, dst_skip = 0, len = 0; |
946 | struct data_chunk *chunk; | |
6007ccb5 MR |
947 | int i; |
948 | ||
4e538578 MR |
949 | if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM)) |
950 | return NULL; | |
951 | ||
952 | /* | |
953 | * TODO: Handle the case where we have to repeat a chain of | |
954 | * descriptors... | |
955 | */ | |
956 | if ((xt->numf > 1) && (xt->frame_size > 1)) | |
6007ccb5 MR |
957 | return NULL; |
958 | ||
1edc85dc | 959 | dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n", |
268914f4 | 960 | __func__, &xt->src_start, &xt->dst_start, xt->numf, |
6007ccb5 MR |
961 | xt->frame_size, flags); |
962 | ||
963 | src_addr = xt->src_start; | |
964 | dst_addr = xt->dst_start; | |
965 | ||
4e538578 MR |
966 | if (xt->numf > 1) { |
967 | first = at_xdmac_interleaved_queue_desc(chan, atchan, | |
968 | NULL, | |
969 | src_addr, dst_addr, | |
970 | xt, xt->sgl); | |
ef10b0b2 SE |
971 | |
972 | /* Length of the block is (BLEN+1) microblocks. */ | |
973 | for (i = 0; i < xt->numf - 1; i++) | |
4e538578 | 974 | at_xdmac_increment_block_count(chan, first); |
62b5cb75 LD |
975 | |
976 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
977 | __func__, first, first); | |
978 | list_add_tail(&first->desc_node, &first->descs_list); | |
4e538578 MR |
979 | } else { |
980 | for (i = 0; i < xt->frame_size; i++) { | |
981 | size_t src_icg = 0, dst_icg = 0; | |
982 | struct at_xdmac_desc *desc; | |
6007ccb5 | 983 | |
4e538578 | 984 | chunk = xt->sgl + i; |
6007ccb5 | 985 | |
4e538578 MR |
986 | dst_icg = dmaengine_get_dst_icg(xt, chunk); |
987 | src_icg = dmaengine_get_src_icg(xt, chunk); | |
6007ccb5 | 988 | |
4e538578 MR |
989 | src_skip = chunk->size + src_icg; |
990 | dst_skip = chunk->size + dst_icg; | |
6007ccb5 | 991 | |
6007ccb5 | 992 | dev_dbg(chan2dev(chan), |
1edc85dc | 993 | "%s: chunk size=%zu, src icg=%zu, dst icg=%zu\n", |
4e538578 MR |
994 | __func__, chunk->size, src_icg, dst_icg); |
995 | ||
996 | desc = at_xdmac_interleaved_queue_desc(chan, atchan, | |
997 | prev, | |
998 | src_addr, dst_addr, | |
999 | xt, chunk); | |
1000 | if (!desc) { | |
1001 | list_splice_init(&first->descs_list, | |
1002 | &atchan->free_descs_list); | |
1003 | return NULL; | |
1004 | } | |
1005 | ||
1006 | if (!first) | |
1007 | first = desc; | |
1008 | ||
1009 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
1010 | __func__, desc, first); | |
1011 | list_add_tail(&desc->desc_node, &first->descs_list); | |
1012 | ||
1013 | if (xt->src_sgl) | |
1014 | src_addr += src_skip; | |
1015 | ||
1016 | if (xt->dst_sgl) | |
1017 | dst_addr += dst_skip; | |
1018 | ||
1019 | len += chunk->size; | |
1020 | prev = desc; | |
6007ccb5 | 1021 | } |
6007ccb5 MR |
1022 | } |
1023 | ||
1024 | first->tx_dma_desc.cookie = -EBUSY; | |
1025 | first->tx_dma_desc.flags = flags; | |
1026 | first->xfer_size = len; | |
1027 | ||
1028 | return &first->tx_dma_desc; | |
1029 | } | |
1030 | ||
e1f7c9ee LD |
1031 | static struct dma_async_tx_descriptor * |
1032 | at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1033 | size_t len, unsigned long flags) | |
1034 | { | |
1035 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1036 | struct at_xdmac_desc *first = NULL, *prev = NULL; | |
1037 | size_t remaining_size = len, xfer_size = 0, ublen; | |
1038 | dma_addr_t src_addr = src, dst_addr = dest; | |
1039 | u32 dwidth; | |
1040 | /* | |
1041 | * WARNING: We don't know the direction, it involves we can't | |
1042 | * dynamically set the source and dest interface so we have to use the | |
1043 | * same one. Only interface 0 allows EBI access. Hopefully we can | |
1044 | * access DDR through both ports (at least on SAMA5D4x), so we can use | |
1045 | * the same interface for source and dest, that solves the fact we | |
1046 | * don't know the direction. | |
95da0c19 LD |
1047 | * ERRATA: Even if useless for memory transfers, the PERID has to not |
1048 | * match the one of another channel. If not, it could lead to spurious | |
1049 | * flag status. | |
e1f7c9ee | 1050 | */ |
95da0c19 LD |
1051 | u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) |
1052 | | AT_XDMAC_CC_DAM_INCREMENTED_AM | |
e1f7c9ee LD |
1053 | | AT_XDMAC_CC_SAM_INCREMENTED_AM |
1054 | | AT_XDMAC_CC_DIF(0) | |
1055 | | AT_XDMAC_CC_SIF(0) | |
1056 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
1057 | | AT_XDMAC_CC_TYPE_MEM_TRAN; | |
4c374fc7 | 1058 | unsigned long irqflags; |
e1f7c9ee | 1059 | |
82e24246 VK |
1060 | dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n", |
1061 | __func__, &src, &dest, len, flags); | |
e1f7c9ee LD |
1062 | |
1063 | if (unlikely(!len)) | |
1064 | return NULL; | |
1065 | ||
f0816a36 | 1066 | dwidth = at_xdmac_align_width(chan, src_addr | dst_addr); |
e1f7c9ee LD |
1067 | |
1068 | /* Prepare descriptors. */ | |
1069 | while (remaining_size) { | |
1070 | struct at_xdmac_desc *desc = NULL; | |
1071 | ||
c66ec04e | 1072 | dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size); |
e1f7c9ee | 1073 | |
4c374fc7 | 1074 | spin_lock_irqsave(&atchan->lock, irqflags); |
e1f7c9ee | 1075 | desc = at_xdmac_get_desc(atchan); |
4c374fc7 | 1076 | spin_unlock_irqrestore(&atchan->lock, irqflags); |
e1f7c9ee LD |
1077 | if (!desc) { |
1078 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
1079 | if (first) | |
1080 | list_splice_init(&first->descs_list, &atchan->free_descs_list); | |
1081 | return NULL; | |
1082 | } | |
1083 | ||
1084 | /* Update src and dest addresses. */ | |
1085 | src_addr += xfer_size; | |
1086 | dst_addr += xfer_size; | |
1087 | ||
1088 | if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth) | |
1089 | xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth; | |
1090 | else | |
1091 | xfer_size = remaining_size; | |
1092 | ||
c66ec04e | 1093 | dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size); |
e1f7c9ee LD |
1094 | |
1095 | /* Check remaining length and change data width if needed. */ | |
f0816a36 MR |
1096 | dwidth = at_xdmac_align_width(chan, |
1097 | src_addr | dst_addr | xfer_size); | |
aa876cd4 | 1098 | chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK; |
e1f7c9ee LD |
1099 | chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); |
1100 | ||
1101 | ublen = xfer_size >> dwidth; | |
1102 | remaining_size -= xfer_size; | |
1103 | ||
1104 | desc->lld.mbr_sa = src_addr; | |
1105 | desc->lld.mbr_da = dst_addr; | |
1106 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 | |
1107 | | AT_XDMAC_MBR_UBC_NDEN | |
1108 | | AT_XDMAC_MBR_UBC_NSEN | |
e1f7c9ee LD |
1109 | | ublen; |
1110 | desc->lld.mbr_cfg = chan_cc; | |
1111 | ||
1112 | dev_dbg(chan2dev(chan), | |
82e24246 VK |
1113 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", |
1114 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg); | |
e1f7c9ee LD |
1115 | |
1116 | /* Chain lld. */ | |
0d0ee751 MR |
1117 | if (prev) |
1118 | at_xdmac_queue_desc(chan, prev, desc); | |
e1f7c9ee LD |
1119 | |
1120 | prev = desc; | |
1121 | if (!first) | |
1122 | first = desc; | |
1123 | ||
1124 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
1125 | __func__, desc, first); | |
1126 | list_add_tail(&desc->desc_node, &first->descs_list); | |
1127 | } | |
1128 | ||
1129 | first->tx_dma_desc.flags = flags; | |
1130 | first->xfer_size = len; | |
1131 | ||
1132 | return &first->tx_dma_desc; | |
1133 | } | |
1134 | ||
b206d9a2 MR |
1135 | static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan, |
1136 | struct at_xdmac_chan *atchan, | |
1137 | dma_addr_t dst_addr, | |
1138 | size_t len, | |
1139 | int value) | |
1140 | { | |
1141 | struct at_xdmac_desc *desc; | |
1142 | unsigned long flags; | |
1143 | size_t ublen; | |
1144 | u32 dwidth; | |
1145 | /* | |
1146 | * WARNING: The channel configuration is set here since there is no | |
1147 | * dmaengine_slave_config call in this case. Moreover we don't know the | |
1148 | * direction, it involves we can't dynamically set the source and dest | |
1149 | * interface so we have to use the same one. Only interface 0 allows EBI | |
1150 | * access. Hopefully we can access DDR through both ports (at least on | |
1151 | * SAMA5D4x), so we can use the same interface for source and dest, | |
1152 | * that solves the fact we don't know the direction. | |
95da0c19 LD |
1153 | * ERRATA: Even if useless for memory transfers, the PERID has to not |
1154 | * match the one of another channel. If not, it could lead to spurious | |
1155 | * flag status. | |
b206d9a2 | 1156 | */ |
95da0c19 LD |
1157 | u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) |
1158 | | AT_XDMAC_CC_DAM_UBS_AM | |
b206d9a2 MR |
1159 | | AT_XDMAC_CC_SAM_INCREMENTED_AM |
1160 | | AT_XDMAC_CC_DIF(0) | |
1161 | | AT_XDMAC_CC_SIF(0) | |
1162 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
1163 | | AT_XDMAC_CC_MEMSET_HW_MODE | |
1164 | | AT_XDMAC_CC_TYPE_MEM_TRAN; | |
1165 | ||
1166 | dwidth = at_xdmac_align_width(chan, dst_addr); | |
1167 | ||
1168 | if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) { | |
1169 | dev_err(chan2dev(chan), | |
1170 | "%s: Transfer too large, aborting...\n", | |
1171 | __func__); | |
1172 | return NULL; | |
1173 | } | |
1174 | ||
1175 | spin_lock_irqsave(&atchan->lock, flags); | |
1176 | desc = at_xdmac_get_desc(atchan); | |
1177 | spin_unlock_irqrestore(&atchan->lock, flags); | |
1178 | if (!desc) { | |
1179 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
1180 | return NULL; | |
1181 | } | |
1182 | ||
1183 | chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); | |
1184 | ||
1185 | ublen = len >> dwidth; | |
1186 | ||
1187 | desc->lld.mbr_da = dst_addr; | |
1188 | desc->lld.mbr_ds = value; | |
1189 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3 | |
1190 | | AT_XDMAC_MBR_UBC_NDEN | |
1191 | | AT_XDMAC_MBR_UBC_NSEN | |
1192 | | ublen; | |
1193 | desc->lld.mbr_cfg = chan_cc; | |
1194 | ||
1195 | dev_dbg(chan2dev(chan), | |
3935e087 AB |
1196 | "%s: lld: mbr_da=%pad, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", |
1197 | __func__, &desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc, | |
b206d9a2 MR |
1198 | desc->lld.mbr_cfg); |
1199 | ||
1200 | return desc; | |
1201 | } | |
1202 | ||
192dc8c0 | 1203 | static struct dma_async_tx_descriptor * |
b206d9a2 MR |
1204 | at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, |
1205 | size_t len, unsigned long flags) | |
1206 | { | |
1207 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1208 | struct at_xdmac_desc *desc; | |
1209 | ||
1edc85dc | 1210 | dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%zu, pattern=0x%x, flags=0x%lx\n", |
268914f4 | 1211 | __func__, &dest, len, value, flags); |
b206d9a2 MR |
1212 | |
1213 | if (unlikely(!len)) | |
1214 | return NULL; | |
1215 | ||
1216 | desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value); | |
1217 | list_add_tail(&desc->desc_node, &desc->descs_list); | |
1218 | ||
1219 | desc->tx_dma_desc.cookie = -EBUSY; | |
1220 | desc->tx_dma_desc.flags = flags; | |
1221 | desc->xfer_size = len; | |
1222 | ||
1223 | return &desc->tx_dma_desc; | |
1224 | } | |
1225 | ||
67a6eedc MR |
1226 | static struct dma_async_tx_descriptor * |
1227 | at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
1228 | unsigned int sg_len, int value, | |
1229 | unsigned long flags) | |
1230 | { | |
1231 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1232 | struct at_xdmac_desc *desc, *pdesc = NULL, | |
1233 | *ppdesc = NULL, *first = NULL; | |
1234 | struct scatterlist *sg, *psg = NULL, *ppsg = NULL; | |
1235 | size_t stride = 0, pstride = 0, len = 0; | |
1236 | int i; | |
1237 | ||
1238 | if (!sgl) | |
1239 | return NULL; | |
1240 | ||
1241 | dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n", | |
1242 | __func__, sg_len, value, flags); | |
1243 | ||
1244 | /* Prepare descriptors. */ | |
1245 | for_each_sg(sgl, sg, sg_len, i) { | |
268914f4 AB |
1246 | dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n", |
1247 | __func__, &sg_dma_address(sg), sg_dma_len(sg), | |
67a6eedc MR |
1248 | value, flags); |
1249 | desc = at_xdmac_memset_create_desc(chan, atchan, | |
1250 | sg_dma_address(sg), | |
1251 | sg_dma_len(sg), | |
1252 | value); | |
1253 | if (!desc && first) | |
1254 | list_splice_init(&first->descs_list, | |
1255 | &atchan->free_descs_list); | |
1256 | ||
1257 | if (!first) | |
1258 | first = desc; | |
1259 | ||
1260 | /* Update our strides */ | |
1261 | pstride = stride; | |
1262 | if (psg) | |
1263 | stride = sg_dma_address(sg) - | |
1264 | (sg_dma_address(psg) + sg_dma_len(psg)); | |
1265 | ||
1266 | /* | |
1267 | * The scatterlist API gives us only the address and | |
1268 | * length of each elements. | |
1269 | * | |
1270 | * Unfortunately, we don't have the stride, which we | |
1271 | * will need to compute. | |
1272 | * | |
1273 | * That make us end up in a situation like this one: | |
1274 | * len stride len stride len | |
1275 | * +-------+ +-------+ +-------+ | |
1276 | * | N-2 | | N-1 | | N | | |
1277 | * +-------+ +-------+ +-------+ | |
1278 | * | |
1279 | * We need all these three elements (N-2, N-1 and N) | |
1280 | * to actually take the decision on whether we need to | |
1281 | * queue N-1 or reuse N-2. | |
1282 | * | |
1283 | * We will only consider N if it is the last element. | |
1284 | */ | |
1285 | if (ppdesc && pdesc) { | |
1286 | if ((stride == pstride) && | |
1287 | (sg_dma_len(ppsg) == sg_dma_len(psg))) { | |
1288 | dev_dbg(chan2dev(chan), | |
1289 | "%s: desc 0x%p can be merged with desc 0x%p\n", | |
1290 | __func__, pdesc, ppdesc); | |
1291 | ||
1292 | /* | |
1293 | * Increment the block count of the | |
1294 | * N-2 descriptor | |
1295 | */ | |
1296 | at_xdmac_increment_block_count(chan, ppdesc); | |
1297 | ppdesc->lld.mbr_dus = stride; | |
1298 | ||
1299 | /* | |
1300 | * Put back the N-1 descriptor in the | |
1301 | * free descriptor list | |
1302 | */ | |
1303 | list_add_tail(&pdesc->desc_node, | |
1304 | &atchan->free_descs_list); | |
1305 | ||
1306 | /* | |
1307 | * Make our N-1 descriptor pointer | |
1308 | * point to the N-2 since they were | |
1309 | * actually merged. | |
1310 | */ | |
1311 | pdesc = ppdesc; | |
1312 | ||
1313 | /* | |
1314 | * Rule out the case where we don't have | |
1315 | * pstride computed yet (our second sg | |
1316 | * element) | |
1317 | * | |
1318 | * We also want to catch the case where there | |
1319 | * would be a negative stride, | |
1320 | */ | |
1321 | } else if (pstride || | |
1322 | sg_dma_address(sg) < sg_dma_address(psg)) { | |
1323 | /* | |
1324 | * Queue the N-1 descriptor after the | |
1325 | * N-2 | |
1326 | */ | |
1327 | at_xdmac_queue_desc(chan, ppdesc, pdesc); | |
1328 | ||
1329 | /* | |
1330 | * Add the N-1 descriptor to the list | |
1331 | * of the descriptors used for this | |
1332 | * transfer | |
1333 | */ | |
1334 | list_add_tail(&desc->desc_node, | |
1335 | &first->descs_list); | |
1336 | dev_dbg(chan2dev(chan), | |
1337 | "%s: add desc 0x%p to descs_list 0x%p\n", | |
1338 | __func__, desc, first); | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | /* | |
1343 | * If we are the last element, just see if we have the | |
1344 | * same size than the previous element. | |
1345 | * | |
1346 | * If so, we can merge it with the previous descriptor | |
1347 | * since we don't care about the stride anymore. | |
1348 | */ | |
1349 | if ((i == (sg_len - 1)) && | |
f5a00eb7 | 1350 | sg_dma_len(psg) == sg_dma_len(sg)) { |
67a6eedc MR |
1351 | dev_dbg(chan2dev(chan), |
1352 | "%s: desc 0x%p can be merged with desc 0x%p\n", | |
1353 | __func__, desc, pdesc); | |
1354 | ||
1355 | /* | |
1356 | * Increment the block count of the N-1 | |
1357 | * descriptor | |
1358 | */ | |
1359 | at_xdmac_increment_block_count(chan, pdesc); | |
1360 | pdesc->lld.mbr_dus = stride; | |
1361 | ||
1362 | /* | |
1363 | * Put back the N descriptor in the free | |
1364 | * descriptor list | |
1365 | */ | |
1366 | list_add_tail(&desc->desc_node, | |
1367 | &atchan->free_descs_list); | |
1368 | } | |
1369 | ||
1370 | /* Update our descriptors */ | |
1371 | ppdesc = pdesc; | |
1372 | pdesc = desc; | |
1373 | ||
1374 | /* Update our scatter pointers */ | |
1375 | ppsg = psg; | |
1376 | psg = sg; | |
1377 | ||
1378 | len += sg_dma_len(sg); | |
1379 | } | |
1380 | ||
1381 | first->tx_dma_desc.cookie = -EBUSY; | |
1382 | first->tx_dma_desc.flags = flags; | |
1383 | first->xfer_size = len; | |
1384 | ||
1385 | return &first->tx_dma_desc; | |
1386 | } | |
1387 | ||
e1f7c9ee LD |
1388 | static enum dma_status |
1389 | at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
1390 | struct dma_tx_state *txstate) | |
1391 | { | |
1392 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1393 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
1394 | struct at_xdmac_desc *desc, *_desc; | |
1395 | struct list_head *descs_list; | |
1396 | enum dma_status ret; | |
25c5e962 LD |
1397 | int residue, retry; |
1398 | u32 cur_nda, check_nda, cur_ubc, mask, value; | |
be835074 | 1399 | u8 dwidth = 0; |
4c374fc7 | 1400 | unsigned long flags; |
53398f48 | 1401 | bool initd; |
e1f7c9ee LD |
1402 | |
1403 | ret = dma_cookie_status(chan, cookie, txstate); | |
1404 | if (ret == DMA_COMPLETE) | |
1405 | return ret; | |
1406 | ||
1407 | if (!txstate) | |
1408 | return ret; | |
1409 | ||
4c374fc7 | 1410 | spin_lock_irqsave(&atchan->lock, flags); |
e1f7c9ee LD |
1411 | |
1412 | desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); | |
1413 | ||
1414 | /* | |
1415 | * If the transfer has not been started yet, don't need to compute the | |
1416 | * residue, it's the transfer length. | |
1417 | */ | |
1418 | if (!desc->active_xfer) { | |
1419 | dma_set_residue(txstate, desc->xfer_size); | |
4c374fc7 | 1420 | goto spin_unlock; |
e1f7c9ee LD |
1421 | } |
1422 | ||
1423 | residue = desc->xfer_size; | |
4e097820 CP |
1424 | /* |
1425 | * Flush FIFO: only relevant when the transfer is source peripheral | |
9295c41d LD |
1426 | * synchronized. Flush is needed before reading CUBC because data in |
1427 | * the FIFO are not reported by CUBC. Reporting a residue of the | |
1428 | * transfer length while we have data in FIFO can cause issue. | |
1429 | * Usecase: atmel USART has a timeout which means I have received | |
1430 | * characters but there is no more character received for a while. On | |
1431 | * timeout, it requests the residue. If the data are in the DMA FIFO, | |
1432 | * we will return a residue of the transfer length. It means no data | |
1433 | * received. If an application is waiting for these data, it will hang | |
1434 | * since we won't have another USART timeout without receiving new | |
1435 | * data. | |
4e097820 CP |
1436 | */ |
1437 | mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; | |
1438 | value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM; | |
be835074 | 1439 | if ((desc->lld.mbr_cfg & mask) == value) { |
4e097820 CP |
1440 | at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); |
1441 | while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) | |
1442 | cpu_relax(); | |
1443 | } | |
e1f7c9ee | 1444 | |
25c5e962 | 1445 | /* |
53398f48 LD |
1446 | * The easiest way to compute the residue should be to pause the DMA |
1447 | * but doing this can lead to miss some data as some devices don't | |
1448 | * have FIFO. | |
1449 | * We need to read several registers because: | |
1450 | * - DMA is running therefore a descriptor change is possible while | |
1451 | * reading these registers | |
1452 | * - When the block transfer is done, the value of the CUBC register | |
1453 | * is set to its initial value until the fetch of the next descriptor. | |
1454 | * This value will corrupt the residue calculation so we have to skip | |
1455 | * it. | |
1456 | * | |
1457 | * INITD -------- ------------ | |
1458 | * |____________________| | |
1459 | * _______________________ _______________ | |
1460 | * NDA @desc2 \/ @desc3 | |
1461 | * _______________________/\_______________ | |
1462 | * __________ ___________ _______________ | |
1463 | * CUBC 0 \/ MAX desc1 \/ MAX desc2 | |
1464 | * __________/\___________/\_______________ | |
1465 | * | |
1466 | * Since descriptors are aligned on 64 bits, we can assume that | |
1467 | * the update of NDA and CUBC is atomic. | |
25c5e962 | 1468 | * Memory barriers are used to ensure the read order of the registers. |
53398f48 | 1469 | * A max number of retries is set because unlikely it could never ends. |
25c5e962 | 1470 | */ |
25c5e962 | 1471 | for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) { |
25c5e962 | 1472 | check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc; |
53398f48 | 1473 | rmb(); |
25c5e962 | 1474 | cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC); |
53398f48 | 1475 | rmb(); |
c5637476 MJ |
1476 | initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD); |
1477 | rmb(); | |
53398f48 LD |
1478 | cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc; |
1479 | rmb(); | |
1480 | ||
1481 | if ((check_nda == cur_nda) && initd) | |
1482 | break; | |
25c5e962 LD |
1483 | } |
1484 | ||
1485 | if (unlikely(retry >= AT_XDMAC_RESIDUE_MAX_RETRIES)) { | |
1486 | ret = DMA_ERROR; | |
1487 | goto spin_unlock; | |
1488 | } | |
1489 | ||
9295c41d LD |
1490 | /* |
1491 | * Flush FIFO: only relevant when the transfer is source peripheral | |
1492 | * synchronized. Another flush is needed here because CUBC is updated | |
1493 | * when the controller sends the data write command. It can lead to | |
1494 | * report data that are not written in the memory or the device. The | |
1495 | * FIFO flush ensures that data are really written. | |
1496 | */ | |
1497 | if ((desc->lld.mbr_cfg & mask) == value) { | |
1498 | at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); | |
1499 | while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) | |
1500 | cpu_relax(); | |
1501 | } | |
1502 | ||
e1f7c9ee LD |
1503 | /* |
1504 | * Remove size of all microblocks already transferred and the current | |
1505 | * one. Then add the remaining size to transfer of the current | |
1506 | * microblock. | |
1507 | */ | |
1508 | descs_list = &desc->descs_list; | |
1509 | list_for_each_entry_safe(desc, _desc, descs_list, desc_node) { | |
be835074 | 1510 | dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg); |
e1f7c9ee LD |
1511 | residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth; |
1512 | if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda) | |
1513 | break; | |
1514 | } | |
25c5e962 | 1515 | residue += cur_ubc << dwidth; |
e1f7c9ee | 1516 | |
e1f7c9ee LD |
1517 | dma_set_residue(txstate, residue); |
1518 | ||
1519 | dev_dbg(chan2dev(chan), | |
82e24246 VK |
1520 | "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n", |
1521 | __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue); | |
e1f7c9ee | 1522 | |
4c374fc7 LD |
1523 | spin_unlock: |
1524 | spin_unlock_irqrestore(&atchan->lock, flags); | |
e1f7c9ee LD |
1525 | return ret; |
1526 | } | |
1527 | ||
1528 | /* Call must be protected by lock. */ | |
1529 | static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan, | |
1530 | struct at_xdmac_desc *desc) | |
1531 | { | |
1532 | dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); | |
1533 | ||
1534 | /* | |
1535 | * Remove the transfer from the transfer list then move the transfer | |
1536 | * descriptors into the free descriptors list. | |
1537 | */ | |
1538 | list_del(&desc->xfer_node); | |
1539 | list_splice_init(&desc->descs_list, &atchan->free_descs_list); | |
1540 | } | |
1541 | ||
1542 | static void at_xdmac_advance_work(struct at_xdmac_chan *atchan) | |
1543 | { | |
1544 | struct at_xdmac_desc *desc; | |
4c374fc7 | 1545 | unsigned long flags; |
e1f7c9ee | 1546 | |
4c374fc7 | 1547 | spin_lock_irqsave(&atchan->lock, flags); |
e1f7c9ee LD |
1548 | |
1549 | /* | |
1550 | * If channel is enabled, do nothing, advance_work will be triggered | |
1551 | * after the interruption. | |
1552 | */ | |
1553 | if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) { | |
1554 | desc = list_first_entry(&atchan->xfers_list, | |
1555 | struct at_xdmac_desc, | |
1556 | xfer_node); | |
1557 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); | |
1558 | if (!desc->active_xfer) | |
1559 | at_xdmac_start_xfer(atchan, desc); | |
1560 | } | |
1561 | ||
4c374fc7 | 1562 | spin_unlock_irqrestore(&atchan->lock, flags); |
e1f7c9ee LD |
1563 | } |
1564 | ||
1565 | static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) | |
1566 | { | |
1567 | struct at_xdmac_desc *desc; | |
1568 | struct dma_async_tx_descriptor *txd; | |
1569 | ||
1570 | desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); | |
1571 | txd = &desc->tx_dma_desc; | |
1572 | ||
a1d4eaaf DJ |
1573 | if (txd->flags & DMA_PREP_INTERRUPT) |
1574 | dmaengine_desc_get_callback_invoke(txd, NULL); | |
e1f7c9ee LD |
1575 | } |
1576 | ||
1577 | static void at_xdmac_tasklet(unsigned long data) | |
1578 | { | |
1579 | struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data; | |
1580 | struct at_xdmac_desc *desc; | |
1581 | u32 error_mask; | |
1582 | ||
1583 | dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n", | |
1584 | __func__, atchan->status); | |
1585 | ||
1586 | error_mask = AT_XDMAC_CIS_RBEIS | |
1587 | | AT_XDMAC_CIS_WBEIS | |
1588 | | AT_XDMAC_CIS_ROIS; | |
1589 | ||
1590 | if (at_xdmac_chan_is_cyclic(atchan)) { | |
1591 | at_xdmac_handle_cyclic(atchan); | |
1592 | } else if ((atchan->status & AT_XDMAC_CIS_LIS) | |
1593 | || (atchan->status & error_mask)) { | |
1594 | struct dma_async_tx_descriptor *txd; | |
1595 | ||
1596 | if (atchan->status & AT_XDMAC_CIS_RBEIS) | |
1597 | dev_err(chan2dev(&atchan->chan), "read bus error!!!"); | |
1598 | if (atchan->status & AT_XDMAC_CIS_WBEIS) | |
1599 | dev_err(chan2dev(&atchan->chan), "write bus error!!!"); | |
1600 | if (atchan->status & AT_XDMAC_CIS_ROIS) | |
1601 | dev_err(chan2dev(&atchan->chan), "request overflow error!!!"); | |
1602 | ||
1603 | spin_lock_bh(&atchan->lock); | |
1604 | desc = list_first_entry(&atchan->xfers_list, | |
1605 | struct at_xdmac_desc, | |
1606 | xfer_node); | |
1607 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); | |
1608 | BUG_ON(!desc->active_xfer); | |
1609 | ||
1610 | txd = &desc->tx_dma_desc; | |
1611 | ||
1612 | at_xdmac_remove_xfer(atchan, desc); | |
1613 | spin_unlock_bh(&atchan->lock); | |
1614 | ||
1615 | if (!at_xdmac_chan_is_cyclic(atchan)) { | |
1616 | dma_cookie_complete(txd); | |
a1d4eaaf DJ |
1617 | if (txd->flags & DMA_PREP_INTERRUPT) |
1618 | dmaengine_desc_get_callback_invoke(txd, NULL); | |
e1f7c9ee LD |
1619 | } |
1620 | ||
1621 | dma_run_dependencies(txd); | |
1622 | ||
1623 | at_xdmac_advance_work(atchan); | |
1624 | } | |
1625 | } | |
1626 | ||
1627 | static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id) | |
1628 | { | |
1629 | struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id; | |
1630 | struct at_xdmac_chan *atchan; | |
1631 | u32 imr, status, pending; | |
1632 | u32 chan_imr, chan_status; | |
1633 | int i, ret = IRQ_NONE; | |
1634 | ||
1635 | do { | |
1636 | imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM); | |
1637 | status = at_xdmac_read(atxdmac, AT_XDMAC_GIS); | |
1638 | pending = status & imr; | |
1639 | ||
1640 | dev_vdbg(atxdmac->dma.dev, | |
1641 | "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n", | |
1642 | __func__, status, imr, pending); | |
1643 | ||
1644 | if (!pending) | |
1645 | break; | |
1646 | ||
1647 | /* We have to find which channel has generated the interrupt. */ | |
1648 | for (i = 0; i < atxdmac->dma.chancnt; i++) { | |
1649 | if (!((1 << i) & pending)) | |
1650 | continue; | |
1651 | ||
1652 | atchan = &atxdmac->chan[i]; | |
1653 | chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); | |
1654 | chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS); | |
1655 | atchan->status = chan_status & chan_imr; | |
1656 | dev_vdbg(atxdmac->dma.dev, | |
1657 | "%s: chan%d: imr=0x%x, status=0x%x\n", | |
1658 | __func__, i, chan_imr, chan_status); | |
1659 | dev_vdbg(chan2dev(&atchan->chan), | |
1660 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", | |
1661 | __func__, | |
1662 | at_xdmac_chan_read(atchan, AT_XDMAC_CC), | |
1663 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), | |
1664 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), | |
1665 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), | |
1666 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), | |
1667 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); | |
1668 | ||
1669 | if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS)) | |
1670 | at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); | |
1671 | ||
1672 | tasklet_schedule(&atchan->tasklet); | |
1673 | ret = IRQ_HANDLED; | |
1674 | } | |
1675 | ||
1676 | } while (pending); | |
1677 | ||
1678 | return ret; | |
1679 | } | |
1680 | ||
1681 | static void at_xdmac_issue_pending(struct dma_chan *chan) | |
1682 | { | |
1683 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1684 | ||
1685 | dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__); | |
1686 | ||
1687 | if (!at_xdmac_chan_is_cyclic(atchan)) | |
1688 | at_xdmac_advance_work(atchan); | |
1689 | ||
1690 | return; | |
1691 | } | |
1692 | ||
3d138877 LD |
1693 | static int at_xdmac_device_config(struct dma_chan *chan, |
1694 | struct dma_slave_config *config) | |
1695 | { | |
1696 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1697 | int ret; | |
4c374fc7 | 1698 | unsigned long flags; |
3d138877 LD |
1699 | |
1700 | dev_dbg(chan2dev(chan), "%s\n", __func__); | |
1701 | ||
4c374fc7 | 1702 | spin_lock_irqsave(&atchan->lock, flags); |
3d138877 | 1703 | ret = at_xdmac_set_slave_config(chan, config); |
4c374fc7 | 1704 | spin_unlock_irqrestore(&atchan->lock, flags); |
3d138877 LD |
1705 | |
1706 | return ret; | |
1707 | } | |
1708 | ||
1709 | static int at_xdmac_device_pause(struct dma_chan *chan) | |
e1f7c9ee | 1710 | { |
e1f7c9ee LD |
1711 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
1712 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
4c374fc7 | 1713 | unsigned long flags; |
e1f7c9ee | 1714 | |
3d138877 | 1715 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
e1f7c9ee | 1716 | |
cbb85e67 CP |
1717 | if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status)) |
1718 | return 0; | |
1719 | ||
4c374fc7 | 1720 | spin_lock_irqsave(&atchan->lock, flags); |
3d138877 | 1721 | at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); |
cbb85e67 CP |
1722 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CC) |
1723 | & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP)) | |
1724 | cpu_relax(); | |
4c374fc7 | 1725 | spin_unlock_irqrestore(&atchan->lock, flags); |
e1f7c9ee | 1726 | |
3d138877 LD |
1727 | return 0; |
1728 | } | |
e1f7c9ee | 1729 | |
3d138877 LD |
1730 | static int at_xdmac_device_resume(struct dma_chan *chan) |
1731 | { | |
1732 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1733 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
4c374fc7 | 1734 | unsigned long flags; |
e1f7c9ee | 1735 | |
3d138877 | 1736 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
e1f7c9ee | 1737 | |
4c374fc7 | 1738 | spin_lock_irqsave(&atchan->lock, flags); |
0434a231 | 1739 | if (!at_xdmac_chan_is_paused(atchan)) { |
4c374fc7 | 1740 | spin_unlock_irqrestore(&atchan->lock, flags); |
3d138877 | 1741 | return 0; |
0434a231 | 1742 | } |
e1f7c9ee | 1743 | |
3d138877 LD |
1744 | at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); |
1745 | clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); | |
4c374fc7 | 1746 | spin_unlock_irqrestore(&atchan->lock, flags); |
3d138877 LD |
1747 | |
1748 | return 0; | |
1749 | } | |
e1f7c9ee | 1750 | |
3d138877 LD |
1751 | static int at_xdmac_device_terminate_all(struct dma_chan *chan) |
1752 | { | |
1753 | struct at_xdmac_desc *desc, *_desc; | |
1754 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1755 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
4c374fc7 | 1756 | unsigned long flags; |
e1f7c9ee | 1757 | |
3d138877 | 1758 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
e1f7c9ee | 1759 | |
4c374fc7 | 1760 | spin_lock_irqsave(&atchan->lock, flags); |
3d138877 LD |
1761 | at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); |
1762 | while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) | |
1763 | cpu_relax(); | |
e1f7c9ee | 1764 | |
3d138877 LD |
1765 | /* Cancel all pending transfers. */ |
1766 | list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) | |
1767 | at_xdmac_remove_xfer(atchan, desc); | |
e1f7c9ee | 1768 | |
611dcadb | 1769 | clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); |
3d138877 | 1770 | clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); |
4c374fc7 | 1771 | spin_unlock_irqrestore(&atchan->lock, flags); |
e1f7c9ee | 1772 | |
3d138877 | 1773 | return 0; |
e1f7c9ee LD |
1774 | } |
1775 | ||
1776 | static int at_xdmac_alloc_chan_resources(struct dma_chan *chan) | |
1777 | { | |
1778 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1779 | struct at_xdmac_desc *desc; | |
1780 | int i; | |
4c374fc7 | 1781 | unsigned long flags; |
e1f7c9ee | 1782 | |
4c374fc7 | 1783 | spin_lock_irqsave(&atchan->lock, flags); |
e1f7c9ee LD |
1784 | |
1785 | if (at_xdmac_chan_is_enabled(atchan)) { | |
1786 | dev_err(chan2dev(chan), | |
1787 | "can't allocate channel resources (channel enabled)\n"); | |
1788 | i = -EIO; | |
1789 | goto spin_unlock; | |
1790 | } | |
1791 | ||
1792 | if (!list_empty(&atchan->free_descs_list)) { | |
1793 | dev_err(chan2dev(chan), | |
1794 | "can't allocate channel resources (channel not free from a previous use)\n"); | |
1795 | i = -EIO; | |
1796 | goto spin_unlock; | |
1797 | } | |
1798 | ||
1799 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1800 | desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC); | |
1801 | if (!desc) { | |
1802 | dev_warn(chan2dev(chan), | |
1803 | "only %d descriptors have been allocated\n", i); | |
1804 | break; | |
1805 | } | |
1806 | list_add_tail(&desc->desc_node, &atchan->free_descs_list); | |
1807 | } | |
1808 | ||
1809 | dma_cookie_init(chan); | |
1810 | ||
1811 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); | |
1812 | ||
1813 | spin_unlock: | |
4c374fc7 | 1814 | spin_unlock_irqrestore(&atchan->lock, flags); |
e1f7c9ee LD |
1815 | return i; |
1816 | } | |
1817 | ||
1818 | static void at_xdmac_free_chan_resources(struct dma_chan *chan) | |
1819 | { | |
1820 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1821 | struct at_xdmac *atxdmac = to_at_xdmac(chan->device); | |
1822 | struct at_xdmac_desc *desc, *_desc; | |
1823 | ||
1824 | list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) { | |
1825 | dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc); | |
1826 | list_del(&desc->desc_node); | |
1827 | dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys); | |
1828 | } | |
1829 | ||
1830 | return; | |
1831 | } | |
1832 | ||
e1f7c9ee LD |
1833 | #ifdef CONFIG_PM |
1834 | static int atmel_xdmac_prepare(struct device *dev) | |
1835 | { | |
ede2b295 | 1836 | struct at_xdmac *atxdmac = dev_get_drvdata(dev); |
e1f7c9ee LD |
1837 | struct dma_chan *chan, *_chan; |
1838 | ||
1839 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { | |
1840 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1841 | ||
1842 | /* Wait for transfer completion, except in cyclic case. */ | |
1843 | if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan)) | |
1844 | return -EAGAIN; | |
1845 | } | |
1846 | return 0; | |
1847 | } | |
1848 | #else | |
1849 | # define atmel_xdmac_prepare NULL | |
1850 | #endif | |
1851 | ||
1852 | #ifdef CONFIG_PM_SLEEP | |
1853 | static int atmel_xdmac_suspend(struct device *dev) | |
1854 | { | |
ede2b295 | 1855 | struct at_xdmac *atxdmac = dev_get_drvdata(dev); |
e1f7c9ee LD |
1856 | struct dma_chan *chan, *_chan; |
1857 | ||
1858 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { | |
1859 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1860 | ||
734bb9a7 | 1861 | atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC); |
e1f7c9ee LD |
1862 | if (at_xdmac_chan_is_cyclic(atchan)) { |
1863 | if (!at_xdmac_chan_is_paused(atchan)) | |
3d138877 | 1864 | at_xdmac_device_pause(chan); |
e1f7c9ee LD |
1865 | atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); |
1866 | atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA); | |
1867 | atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC); | |
1868 | } | |
1869 | } | |
1870 | atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM); | |
1871 | ||
1872 | at_xdmac_off(atxdmac); | |
1873 | clk_disable_unprepare(atxdmac->clk); | |
1874 | return 0; | |
1875 | } | |
1876 | ||
1877 | static int atmel_xdmac_resume(struct device *dev) | |
1878 | { | |
ede2b295 | 1879 | struct at_xdmac *atxdmac = dev_get_drvdata(dev); |
e1f7c9ee LD |
1880 | struct at_xdmac_chan *atchan; |
1881 | struct dma_chan *chan, *_chan; | |
1882 | int i; | |
87c56dcb | 1883 | int ret; |
e1f7c9ee | 1884 | |
87c56dcb AY |
1885 | ret = clk_prepare_enable(atxdmac->clk); |
1886 | if (ret) | |
1887 | return ret; | |
e1f7c9ee LD |
1888 | |
1889 | /* Clear pending interrupts. */ | |
1890 | for (i = 0; i < atxdmac->dma.chancnt; i++) { | |
1891 | atchan = &atxdmac->chan[i]; | |
1892 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) | |
1893 | cpu_relax(); | |
1894 | } | |
1895 | ||
1896 | at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim); | |
e1f7c9ee LD |
1897 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { |
1898 | atchan = to_at_xdmac_chan(chan); | |
734bb9a7 | 1899 | at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc); |
e1f7c9ee | 1900 | if (at_xdmac_chan_is_cyclic(atchan)) { |
611dcadb SW |
1901 | if (at_xdmac_chan_is_paused(atchan)) |
1902 | at_xdmac_device_resume(chan); | |
e1f7c9ee LD |
1903 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda); |
1904 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc); | |
1905 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim); | |
1906 | wmb(); | |
1907 | at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); | |
1908 | } | |
1909 | } | |
1910 | return 0; | |
1911 | } | |
1912 | #endif /* CONFIG_PM_SLEEP */ | |
1913 | ||
1914 | static int at_xdmac_probe(struct platform_device *pdev) | |
1915 | { | |
1916 | struct resource *res; | |
1917 | struct at_xdmac *atxdmac; | |
1918 | int irq, size, nr_channels, i, ret; | |
1919 | void __iomem *base; | |
1920 | u32 reg; | |
1921 | ||
1922 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1923 | if (!res) | |
1924 | return -EINVAL; | |
1925 | ||
1926 | irq = platform_get_irq(pdev, 0); | |
1927 | if (irq < 0) | |
1928 | return irq; | |
1929 | ||
1930 | base = devm_ioremap_resource(&pdev->dev, res); | |
1931 | if (IS_ERR(base)) | |
1932 | return PTR_ERR(base); | |
1933 | ||
1934 | /* | |
1935 | * Read number of xdmac channels, read helper function can't be used | |
1936 | * since atxdmac is not yet allocated and we need to know the number | |
1937 | * of channels to do the allocation. | |
1938 | */ | |
1939 | reg = readl_relaxed(base + AT_XDMAC_GTYPE); | |
1940 | nr_channels = AT_XDMAC_NB_CH(reg); | |
1941 | if (nr_channels > AT_XDMAC_MAX_CHAN) { | |
1942 | dev_err(&pdev->dev, "invalid number of channels (%u)\n", | |
1943 | nr_channels); | |
1944 | return -EINVAL; | |
1945 | } | |
1946 | ||
1947 | size = sizeof(*atxdmac); | |
1948 | size += nr_channels * sizeof(struct at_xdmac_chan); | |
1949 | atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); | |
1950 | if (!atxdmac) { | |
1951 | dev_err(&pdev->dev, "can't allocate at_xdmac structure\n"); | |
1952 | return -ENOMEM; | |
1953 | } | |
1954 | ||
1955 | atxdmac->regs = base; | |
1956 | atxdmac->irq = irq; | |
1957 | ||
1958 | atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); | |
1959 | if (IS_ERR(atxdmac->clk)) { | |
1960 | dev_err(&pdev->dev, "can't get dma_clk\n"); | |
1961 | return PTR_ERR(atxdmac->clk); | |
1962 | } | |
1963 | ||
1964 | /* Do not use dev res to prevent races with tasklet */ | |
1965 | ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac); | |
1966 | if (ret) { | |
1967 | dev_err(&pdev->dev, "can't request irq\n"); | |
1968 | return ret; | |
1969 | } | |
1970 | ||
1971 | ret = clk_prepare_enable(atxdmac->clk); | |
1972 | if (ret) { | |
1973 | dev_err(&pdev->dev, "can't prepare or enable clock\n"); | |
1974 | goto err_free_irq; | |
1975 | } | |
1976 | ||
1977 | atxdmac->at_xdmac_desc_pool = | |
1978 | dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, | |
1979 | sizeof(struct at_xdmac_desc), 4, 0); | |
1980 | if (!atxdmac->at_xdmac_desc_pool) { | |
1981 | dev_err(&pdev->dev, "no memory for descriptors dma pool\n"); | |
1982 | ret = -ENOMEM; | |
1983 | goto err_clk_disable; | |
1984 | } | |
1985 | ||
1986 | dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask); | |
6007ccb5 | 1987 | dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask); |
e1f7c9ee | 1988 | dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask); |
b206d9a2 | 1989 | dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask); |
67a6eedc | 1990 | dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask); |
e1f7c9ee | 1991 | dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask); |
fef4cbf2 LD |
1992 | /* |
1993 | * Without DMA_PRIVATE the driver is not able to allocate more than | |
1994 | * one channel, second allocation fails in private_candidate. | |
1995 | */ | |
1996 | dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask); | |
e1f7c9ee LD |
1997 | atxdmac->dma.dev = &pdev->dev; |
1998 | atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources; | |
1999 | atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources; | |
2000 | atxdmac->dma.device_tx_status = at_xdmac_tx_status; | |
2001 | atxdmac->dma.device_issue_pending = at_xdmac_issue_pending; | |
2002 | atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic; | |
6007ccb5 | 2003 | atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved; |
e1f7c9ee | 2004 | atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy; |
b206d9a2 | 2005 | atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset; |
67a6eedc | 2006 | atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg; |
e1f7c9ee | 2007 | atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg; |
3d138877 LD |
2008 | atxdmac->dma.device_config = at_xdmac_device_config; |
2009 | atxdmac->dma.device_pause = at_xdmac_device_pause; | |
2010 | atxdmac->dma.device_resume = at_xdmac_device_resume; | |
2011 | atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all; | |
8ac82f88 LD |
2012 | atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; |
2013 | atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; | |
2014 | atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
2015 | atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
e1f7c9ee LD |
2016 | |
2017 | /* Disable all chans and interrupts. */ | |
2018 | at_xdmac_off(atxdmac); | |
2019 | ||
2020 | /* Init channels. */ | |
2021 | INIT_LIST_HEAD(&atxdmac->dma.channels); | |
2022 | for (i = 0; i < nr_channels; i++) { | |
2023 | struct at_xdmac_chan *atchan = &atxdmac->chan[i]; | |
2024 | ||
2025 | atchan->chan.device = &atxdmac->dma; | |
2026 | list_add_tail(&atchan->chan.device_node, | |
2027 | &atxdmac->dma.channels); | |
2028 | ||
2029 | atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i); | |
2030 | atchan->mask = 1 << i; | |
2031 | ||
2032 | spin_lock_init(&atchan->lock); | |
2033 | INIT_LIST_HEAD(&atchan->xfers_list); | |
2034 | INIT_LIST_HEAD(&atchan->free_descs_list); | |
2035 | tasklet_init(&atchan->tasklet, at_xdmac_tasklet, | |
2036 | (unsigned long)atchan); | |
2037 | ||
2038 | /* Clear pending interrupts. */ | |
2039 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) | |
2040 | cpu_relax(); | |
2041 | } | |
2042 | platform_set_drvdata(pdev, atxdmac); | |
2043 | ||
2044 | ret = dma_async_device_register(&atxdmac->dma); | |
2045 | if (ret) { | |
2046 | dev_err(&pdev->dev, "fail to register DMA engine device\n"); | |
2047 | goto err_clk_disable; | |
2048 | } | |
2049 | ||
2050 | ret = of_dma_controller_register(pdev->dev.of_node, | |
2051 | at_xdmac_xlate, atxdmac); | |
2052 | if (ret) { | |
2053 | dev_err(&pdev->dev, "could not register of dma controller\n"); | |
2054 | goto err_dma_unregister; | |
2055 | } | |
2056 | ||
2057 | dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", | |
2058 | nr_channels, atxdmac->regs); | |
2059 | ||
2060 | return 0; | |
2061 | ||
2062 | err_dma_unregister: | |
2063 | dma_async_device_unregister(&atxdmac->dma); | |
2064 | err_clk_disable: | |
2065 | clk_disable_unprepare(atxdmac->clk); | |
2066 | err_free_irq: | |
6a8b0c6b | 2067 | free_irq(atxdmac->irq, atxdmac); |
e1f7c9ee LD |
2068 | return ret; |
2069 | } | |
2070 | ||
2071 | static int at_xdmac_remove(struct platform_device *pdev) | |
2072 | { | |
2073 | struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev); | |
2074 | int i; | |
2075 | ||
2076 | at_xdmac_off(atxdmac); | |
2077 | of_dma_controller_free(pdev->dev.of_node); | |
2078 | dma_async_device_unregister(&atxdmac->dma); | |
2079 | clk_disable_unprepare(atxdmac->clk); | |
2080 | ||
6a8b0c6b | 2081 | free_irq(atxdmac->irq, atxdmac); |
e1f7c9ee LD |
2082 | |
2083 | for (i = 0; i < atxdmac->dma.chancnt; i++) { | |
2084 | struct at_xdmac_chan *atchan = &atxdmac->chan[i]; | |
2085 | ||
2086 | tasklet_kill(&atchan->tasklet); | |
2087 | at_xdmac_free_chan_resources(&atchan->chan); | |
2088 | } | |
2089 | ||
2090 | return 0; | |
2091 | } | |
2092 | ||
2093 | static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = { | |
2094 | .prepare = atmel_xdmac_prepare, | |
2095 | SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume) | |
2096 | }; | |
2097 | ||
2098 | static const struct of_device_id atmel_xdmac_dt_ids[] = { | |
2099 | { | |
2100 | .compatible = "atmel,sama5d4-dma", | |
2101 | }, { | |
2102 | /* sentinel */ | |
2103 | } | |
2104 | }; | |
2105 | MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids); | |
2106 | ||
2107 | static struct platform_driver at_xdmac_driver = { | |
2108 | .probe = at_xdmac_probe, | |
2109 | .remove = at_xdmac_remove, | |
2110 | .driver = { | |
2111 | .name = "at_xdmac", | |
e1f7c9ee LD |
2112 | .of_match_table = of_match_ptr(atmel_xdmac_dt_ids), |
2113 | .pm = &atmel_xdmac_dev_pm_ops, | |
2114 | } | |
2115 | }; | |
2116 | ||
2117 | static int __init at_xdmac_init(void) | |
2118 | { | |
2119 | return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe); | |
2120 | } | |
2121 | subsys_initcall(at_xdmac_init); | |
2122 | ||
2123 | MODULE_DESCRIPTION("Atmel Extended DMA Controller driver"); | |
2124 | MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); | |
2125 | MODULE_LICENSE("GPL"); |