[linux-2.6-block.git] / drivers / dma / at_hdmac_regs.h

/*
 * Header file for the Atmel AHB DMA Controller driver
 *
 * Copyright (C) 2008 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#ifndef AT_HDMAC_REGS_H
#define	AT_HDMAC_REGS_H

#include <linux/platform_data/dma-atmel.h>

#define	AT_DMA_MAX_NR_CHANNELS	8


#define	AT_DMA_GCFG	0x00	/* Global Configuration Register */
#define		AT_DMA_IF_BIGEND(i)	(0x1 << (i))	/* AHB-Lite Interface i in Big-endian mode */
#define		AT_DMA_ARB_CFG	(0x1 << 4)	/* Arbiter mode. */
#define			AT_DMA_ARB_CFG_FIXED		(0x0 << 4)
#define			AT_DMA_ARB_CFG_ROUND_ROBIN	(0x1 << 4)

#define	AT_DMA_EN	0x04	/* Controller Enable Register */
#define		AT_DMA_ENABLE	(0x1 << 0)

#define	AT_DMA_SREQ	0x08	/* Software Single Request Register */
#define		AT_DMA_SSREQ(x)	(0x1 << ((x) << 1))		/* Request a source single transfer on channel x */
#define		AT_DMA_DSREQ(x)	(0x1 << (1 + ((x) << 1)))	/* Request a destination single transfer on channel x */

#define	AT_DMA_CREQ	0x0C	/* Software Chunk Transfer Request Register */
#define		AT_DMA_SCREQ(x)	(0x1 << ((x) << 1))		/* Request a source chunk transfer on channel x */
#define		AT_DMA_DCREQ(x)	(0x1 << (1 + ((x) << 1)))	/* Request a destination chunk transfer on channel x */

#define	AT_DMA_LAST	0x10	/* Software Last Transfer Flag Register */
#define		AT_DMA_SLAST(x)	(0x1 << ((x) << 1))		/* This src rq is last tx of buffer on channel x */
#define		AT_DMA_DLAST(x)	(0x1 << (1 + ((x) << 1)))	/* This dst rq is last tx of buffer on channel x */

#define	AT_DMA_SYNC	0x14	/* Request Synchronization Register */
#define		AT_DMA_SYR(h)	(0x1 << (h))			/* Synchronize handshake line h */

/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
#define	AT_DMA_EBCIER	0x18	/* Enable register */
#define	AT_DMA_EBCIDR	0x1C	/* Disable register */
#define	AT_DMA_EBCIMR	0x20	/* Mask Register */
#define	AT_DMA_EBCISR	0x24	/* Status Register */
#define		AT_DMA_CBTC_OFFSET	8
#define		AT_DMA_ERR_OFFSET	16
#define		AT_DMA_BTC(x)	(0x1 << (x))
#define		AT_DMA_CBTC(x)	(0x1 << (AT_DMA_CBTC_OFFSET + (x)))
#define		AT_DMA_ERR(x)	(0x1 << (AT_DMA_ERR_OFFSET + (x)))

#define	AT_DMA_CHER	0x28	/* Channel Handler Enable Register */
#define		AT_DMA_ENA(x)	(0x1 << (x))
#define		AT_DMA_SUSP(x)	(0x1 << ( 8 + (x)))
#define		AT_DMA_KEEP(x)	(0x1 << (24 + (x)))

#define	AT_DMA_CHDR	0x2C	/* Channel Handler Disable Register */
#define		AT_DMA_DIS(x)	(0x1 << (x))
#define		AT_DMA_RES(x)	(0x1 << ( 8 + (x)))

#define	AT_DMA_CHSR	0x30	/* Channel Handler Status Register */
#define		AT_DMA_EMPT(x)	(0x1 << (16 + (x)))
#define		AT_DMA_STAL(x)	(0x1 << (24 + (x)))


#define	AT_DMA_CH_REGS_BASE	0x3C	/* Channel registers base address */
#define	ch_regs(x)	(AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */

/* Hardware register offset for each channel */
#define	ATC_SADDR_OFFSET	0x00	/* Source Address Register */
#define	ATC_DADDR_OFFSET	0x04	/* Destination Address Register */
#define	ATC_DSCR_OFFSET		0x08	/* Descriptor Address Register */
#define	ATC_CTRLA_OFFSET	0x0C	/* Control A Register */
#define	ATC_CTRLB_OFFSET	0x10	/* Control B Register */
#define	ATC_CFG_OFFSET		0x14	/* Configuration Register */
#define	ATC_SPIP_OFFSET		0x18	/* Src PIP Configuration Register */
#define	ATC_DPIP_OFFSET		0x1C	/* Dst PIP Configuration Register */


/* Bitfield definitions */

/* Bitfields in DSCR */
#define	ATC_DSCR_IF(i)		(0x3 & (i))	/* Dsc feched via AHB-Lite Interface i */

/* Bitfields in CTRLA */
#define	ATC_BTSIZE_MAX		0xFFFFUL	/* Maximum Buffer Transfer Size */
#define	ATC_BTSIZE(x)		(ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
#define	ATC_SCSIZE_MASK		(0x7 << 16)	/* Source Chunk Transfer Size */
#define		ATC_SCSIZE(x)		(ATC_SCSIZE_MASK & ((x) << 16))
#define		ATC_SCSIZE_1		(0x0 << 16)
#define		ATC_SCSIZE_4		(0x1 << 16)
#define		ATC_SCSIZE_8		(0x2 << 16)
#define		ATC_SCSIZE_16		(0x3 << 16)
#define		ATC_SCSIZE_32		(0x4 << 16)
#define		ATC_SCSIZE_64		(0x5 << 16)
#define		ATC_SCSIZE_128		(0x6 << 16)
#define		ATC_SCSIZE_256		(0x7 << 16)
#define	ATC_DCSIZE_MASK		(0x7 << 20)	/* Destination Chunk Transfer Size */
#define		ATC_DCSIZE(x)		(ATC_DCSIZE_MASK & ((x) << 20))
#define		ATC_DCSIZE_1		(0x0 << 20)
#define		ATC_DCSIZE_4		(0x1 << 20)
#define		ATC_DCSIZE_8		(0x2 << 20)
#define		ATC_DCSIZE_16		(0x3 << 20)
#define		ATC_DCSIZE_32		(0x4 << 20)
#define		ATC_DCSIZE_64		(0x5 << 20)
#define		ATC_DCSIZE_128		(0x6 << 20)
#define		ATC_DCSIZE_256		(0x7 << 20)
#define	ATC_SRC_WIDTH_MASK	(0x3 << 24)	/* Source Single Transfer Size */
#define		ATC_SRC_WIDTH(x)	((x) << 24)
#define		ATC_SRC_WIDTH_BYTE	(0x0 << 24)
#define		ATC_SRC_WIDTH_HALFWORD	(0x1 << 24)
#define		ATC_SRC_WIDTH_WORD	(0x2 << 24)
#define	ATC_DST_WIDTH_MASK	(0x3 << 28)	/* Destination Single Transfer Size */
#define		ATC_DST_WIDTH(x)	((x) << 28)
#define		ATC_DST_WIDTH_BYTE	(0x0 << 28)
#define		ATC_DST_WIDTH_HALFWORD	(0x1 << 28)
#define		ATC_DST_WIDTH_WORD	(0x2 << 28)
#define	ATC_DONE		(0x1 << 31)	/* Tx Done (only written back in descriptor) */

/* Bitfields in CTRLB */
#define	ATC_SIF(i)		(0x3 & (i))	/* Src tx done via AHB-Lite Interface i */
#define	ATC_DIF(i)		((0x3 & (i)) <<  4)	/* Dst tx done via AHB-Lite Interface i */
				  /* Specify AHB interfaces */
#define AT_DMA_MEM_IF		0 /* interface 0 as memory interface */
#define AT_DMA_PER_IF		1 /* interface 1 as peripheral interface */

#define	ATC_SRC_PIP		(0x1 <<  8)	/* Source Picture-in-Picture enabled */
#define	ATC_DST_PIP		(0x1 << 12)	/* Destination Picture-in-Picture enabled */
#define	ATC_SRC_DSCR_DIS	(0x1 << 16)	/* Src Descriptor fetch disable */
#define	ATC_DST_DSCR_DIS	(0x1 << 20)	/* Dst Descriptor fetch disable */
#define	ATC_FC_MASK		(0x7 << 21)	/* Choose Flow Controller */
#define		ATC_FC_MEM2MEM		(0x0 << 21)	/* Mem-to-Mem (DMA) */
#define		ATC_FC_MEM2PER		(0x1 << 21)	/* Mem-to-Periph (DMA) */
#define		ATC_FC_PER2MEM		(0x2 << 21)	/* Periph-to-Mem (DMA) */
#define		ATC_FC_PER2PER		(0x3 << 21)	/* Periph-to-Periph (DMA) */
#define		ATC_FC_PER2MEM_PER	(0x4 << 21)	/* Periph-to-Mem (Peripheral) */
#define		ATC_FC_MEM2PER_PER	(0x5 << 21)	/* Mem-to-Periph (Peripheral) */
#define		ATC_FC_PER2PER_SRCPER	(0x6 << 21)	/* Periph-to-Periph (Src Peripheral) */
#define		ATC_FC_PER2PER_DSTPER	(0x7 << 21)	/* Periph-to-Periph (Dst Peripheral) */
#define	ATC_SRC_ADDR_MODE_MASK	(0x3 << 24)
#define		ATC_SRC_ADDR_MODE_INCR	(0x0 << 24)	/* Incrementing Mode */
#define		ATC_SRC_ADDR_MODE_DECR	(0x1 << 24)	/* Decrementing Mode */
#define		ATC_SRC_ADDR_MODE_FIXED	(0x2 << 24)	/* Fixed Mode */
#define	ATC_DST_ADDR_MODE_MASK	(0x3 << 28)
#define		ATC_DST_ADDR_MODE_INCR	(0x0 << 28)	/* Incrementing Mode */
#define		ATC_DST_ADDR_MODE_DECR	(0x1 << 28)	/* Decrementing Mode */
#define		ATC_DST_ADDR_MODE_FIXED	(0x2 << 28)	/* Fixed Mode */
#define	ATC_IEN			(0x1 << 30)	/* BTC interrupt enable (active low) */
#define	ATC_AUTO		(0x1 << 31)	/* Auto multiple buffer tx enable */

/* Bitfields in CFG */
/* are in at_hdmac.h */

/* Bitfields in SPIP */
#define	ATC_SPIP_HOLE(x)	(0xFFFFU & (x))
#define	ATC_SPIP_BOUNDARY(x)	((0x3FF & (x)) << 16)

/* Bitfields in DPIP */
#define	ATC_DPIP_HOLE(x)	(0xFFFFU & (x))
#define	ATC_DPIP_BOUNDARY(x)	((0x3FF & (x)) << 16)


/*--  descriptors  -----------------------------------------------------*/

/* LLI == Linked List Item; aka DMA buffer descriptor */
struct at_lli {
	/* values that are not changed by hardware */
	dma_addr_t	saddr;
	dma_addr_t	daddr;
	/* value that may get written back: */
	u32		ctrla;
	/* more values that are not changed by hardware */
	u32		ctrlb;
	dma_addr_t	dscr;	/* chain to next lli */
};

/**
 * struct at_desc - software descriptor
 * @at_lli: hardware lli structure
 * @txd: support for the async_tx api
 * @desc_node: node on the channed descriptors list
 * @len: descriptor byte count
 * @tx_width: transfer width
 * @total_len: total transaction byte count
 */
struct at_desc {
	/* FIRST values the hardware uses */
	struct at_lli			lli;

	/* THEN values for driver housekeeping */
	struct list_head		tx_list;
	struct dma_async_tx_descriptor	txd;
	struct list_head		desc_node;
	size_t				len;
	u32				tx_width;
	size_t				total_len;

	/* Interleaved data */
	size_t				boundary;
	size_t				dst_hole;
	size_t				src_hole;
};

static inline struct at_desc *
txd_to_at_desc(struct dma_async_tx_descriptor *txd)
{
	return container_of(txd, struct at_desc, txd);
}


/*--  Channels  --------------------------------------------------------*/

/**
 * atc_status - information bits stored in channel status flag
 *
 * Manipulated with atomic operations.
 */
enum atc_status {
	ATC_IS_ERROR = 0,
	ATC_IS_PAUSED = 1,
	ATC_IS_CYCLIC = 24,
};

/**
 * struct at_dma_chan - internal representation of an Atmel HDMAC channel
 * @chan_common: common dmaengine channel object members
 * @device: parent device
 * @ch_regs: memory mapped register base
 * @mask: channel index in a mask
 * @per_if: peripheral interface
 * @mem_if: memory interface
 * @status: transmit status information from irq/prep* functions
 *                to tasklet (use atomic operations)
 * @tasklet: bottom half to finish transaction work
 * @save_cfg: configuration register that is saved on suspend/resume cycle
 * @save_dscr: for cyclic operations, preserve next descriptor address in
 *             the cyclic list on suspend/resume cycle
 * @dma_sconfig: configuration for slave transfers, passed via
 * .device_config
 * @lock: serializes enqueue/dequeue operations to descriptors lists
 * @active_list: list of descriptors dmaengine is being running on
 * @queue: list of descriptors ready to be submitted to engine
 * @free_list: list of descriptors usable by the channel
 * @descs_allocated: records the actual size of the descriptor pool
 */
struct at_dma_chan {
	struct dma_chan		chan_common;
	struct at_dma		*device;
	void __iomem		*ch_regs;
	u8			mask;
	u8			per_if;
	u8			mem_if;
	unsigned long		status;
	struct tasklet_struct	tasklet;
	u32			save_cfg;
	u32			save_dscr;
	struct dma_slave_config dma_sconfig;

	spinlock_t		lock;

	/* these other elements are all protected by lock */
	struct list_head	active_list;
	struct list_head	queue;
	struct list_head	free_list;
	unsigned int		descs_allocated;
};

#define	channel_readl(atchan, name) \
	__raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)

#define	channel_writel(atchan, name, val) \
	__raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)

static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
{
	return container_of(dchan, struct at_dma_chan, chan_common);
}

/*
 * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
 *
 * This can be done by finding most significant bit set.
 */
static inline void convert_burst(u32 *maxburst)
{
	if (*maxburst > 1)
		*maxburst = fls(*maxburst) - 2;
	else
		*maxburst = 0;
}

/*
 * Fix sconfig's bus width according to at_hdmac.
 * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
 */
static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
{
	switch (addr_width) {
	case DMA_SLAVE_BUSWIDTH_2_BYTES:
		return 1;
	case DMA_SLAVE_BUSWIDTH_4_BYTES:
		return 2;
	default:
		/* For 1 byte width or fallback */
		return 0;
	}
}

/*--  Controller  ------------------------------------------------------*/

/**
 * struct at_dma - internal representation of an Atmel HDMA Controller
 * @chan_common: common dmaengine dma_device object members
 * @atdma_devtype: identifier of DMA controller compatibility
 * @ch_regs: memory mapped register base
 * @clk: dma controller clock
 * @save_imr: interrupt mask register that is saved on suspend/resume cycle
 * @all_chan_mask: all channels availlable in a mask
 * @dma_desc_pool: base of DMA descriptor region (DMA address)
 * @chan: channels table to store at_dma_chan structures
 */
struct at_dma {
	struct dma_device	dma_common;
	void __iomem		*regs;
	struct clk		*clk;
	u32			save_imr;

	u8			all_chan_mask;

	struct dma_pool		*dma_desc_pool;
	/* AT THE END channels table */
	struct at_dma_chan	chan[0];
};

#define	dma_readl(atdma, name) \
	__raw_readl((atdma)->regs + AT_DMA_##name)
#define	dma_writel(atdma, name, val) \
	__raw_writel((val), (atdma)->regs + AT_DMA_##name)

static inline struct at_dma *to_at_dma(struct dma_device *ddev)
{
	return container_of(ddev, struct at_dma, dma_common);
}


/*--  Helper functions  ------------------------------------------------*/

static struct device *chan2dev(struct dma_chan *chan)
{
	return &chan->dev->device;
}

#if defined(VERBOSE_DEBUG)
static void vdbg_dump_regs(struct at_dma_chan *atchan)
{
	struct at_dma	*atdma = to_at_dma(atchan->chan_common.device);

	dev_err(chan2dev(&atchan->chan_common),
		"  channel %d : imr = 0x%x, chsr = 0x%x\n",
		atchan->chan_common.chan_id,
		dma_readl(atdma, EBCIMR),
		dma_readl(atdma, CHSR));

	dev_err(chan2dev(&atchan->chan_common),
		"  channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
		channel_readl(atchan, SADDR),
		channel_readl(atchan, DADDR),
		channel_readl(atchan, CTRLA),
		channel_readl(atchan, CTRLB),
		channel_readl(atchan, CFG),
		channel_readl(atchan, DSCR));
}
#else
static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
#endif

static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
{
	dev_crit(chan2dev(&atchan->chan_common),
		 "  desc: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
		 lli->saddr, lli->daddr,
		 lli->ctrla, lli->ctrlb, lli->dscr);
}


static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
{
	u32 ebci;

	/* enable interrupts on buffer transfer completion & error */
	ebci =    AT_DMA_BTC(chan_id)
		| AT_DMA_ERR(chan_id);
	if (on)
		dma_writel(atdma, EBCIER, ebci);
	else
		dma_writel(atdma, EBCIDR, ebci);
}

static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
{
	atc_setup_irq(atdma, chan_id, 1);
}

static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
{
	atc_setup_irq(atdma, chan_id, 0);
}


/**
 * atc_chan_is_enabled - test if given channel is enabled
 * @atchan: channel we want to test status
 */
static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
{
	struct at_dma	*atdma = to_at_dma(atchan->chan_common.device);

	return !!(dma_readl(atdma, CHSR) & atchan->mask);
}

/**
 * atc_chan_is_paused - test channel pause/resume status
 * @atchan: channel we want to test status
 */
static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
{
	return test_bit(ATC_IS_PAUSED, &atchan->status);
}

/**
 * atc_chan_is_cyclic - test if given channel has cyclic property set
 * @atchan: channel we want to test status
 */
static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
{
	return test_bit(ATC_IS_CYCLIC, &atchan->status);
}

/**
 * set_desc_eol - set end-of-link to descriptor so it will end transfer
 * @desc: descriptor, signle or at the end of a chain, to end chain on
 */
static void set_desc_eol(struct at_desc *desc)
{
	u32 ctrlb = desc->lli.ctrlb;

	ctrlb &= ~ATC_IEN;
	ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;

	desc->lli.ctrlb = ctrlb;
	desc->lli.dscr = 0;
}

#endif /* AT_HDMAC_REGS_H */
Commit	Line	Data
dc78baa2 NF	1	/*
	2	* Header file for the Atmel AHB DMA Controller driver
	3	*
	4	* Copyright (C) 2008 Atmel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11	#ifndef AT_HDMAC_REGS_H
	12	#define AT_HDMAC_REGS_H
	13
7cdc39ee	14	#include <linux/platform_data/dma-atmel.h>
dc78baa2 NF	15
	16	#define AT_DMA_MAX_NR_CHANNELS 8
	17
	18
	19	#define AT_DMA_GCFG 0x00 /* Global Configuration Register */
	20	#define AT_DMA_IF_BIGEND(i) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */
	21	#define AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */
	22	#define AT_DMA_ARB_CFG_FIXED (0x0 << 4)
	23	#define AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4)
	24
	25	#define AT_DMA_EN 0x04 /* Controller Enable Register */
	26	#define AT_DMA_ENABLE (0x1 << 0)
	27
	28	#define AT_DMA_SREQ 0x08 /* Software Single Request Register */
	29	#define AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */
	30	#define AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */
	31
	32	#define AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */
	33	#define AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */
	34	#define AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */
	35
	36	#define AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */
	37	#define AT_DMA_SLAST(x) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */
	38	#define AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */
	39
	40	#define AT_DMA_SYNC 0x14 /* Request Synchronization Register */
	41	#define AT_DMA_SYR(h) (0x1 << (h)) /* Synchronize handshake line h */
	42
	43	/* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
	44	#define AT_DMA_EBCIER 0x18 /* Enable register */
	45	#define AT_DMA_EBCIDR 0x1C /* Disable register */
	46	#define AT_DMA_EBCIMR 0x20 /* Mask Register */
	47	#define AT_DMA_EBCISR 0x24 /* Status Register */
	48	#define AT_DMA_CBTC_OFFSET 8
	49	#define AT_DMA_ERR_OFFSET 16
	50	#define AT_DMA_BTC(x) (0x1 << (x))
	51	#define AT_DMA_CBTC(x) (0x1 << (AT_DMA_CBTC_OFFSET + (x)))
	52	#define AT_DMA_ERR(x) (0x1 << (AT_DMA_ERR_OFFSET + (x)))
	53
	54	#define AT_DMA_CHER 0x28 /* Channel Handler Enable Register */
	55	#define AT_DMA_ENA(x) (0x1 << (x))
	56	#define AT_DMA_SUSP(x) (0x1 << ( 8 + (x)))
	57	#define AT_DMA_KEEP(x) (0x1 << (24 + (x)))
	58
	59	#define AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */
	60	#define AT_DMA_DIS(x) (0x1 << (x))
	61	#define AT_DMA_RES(x) (0x1 << ( 8 + (x)))
	62
	63	#define AT_DMA_CHSR 0x30 /* Channel Handler Status Register */
	64	#define AT_DMA_EMPT(x) (0x1 << (16 + (x)))
	65	#define AT_DMA_STAL(x) (0x1 << (24 + (x)))
	66
	67
	68	#define AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */
	69	#define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
	70
	71	/* Hardware register offset for each channel */
	72	#define ATC_SADDR_OFFSET 0x00 /* Source Address Register */
	73	#define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */
	74	#define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */
	75	#define ATC_CTRLA_OFFSET 0x0C /* Control A Register */
	76	#define ATC_CTRLB_OFFSET 0x10 /* Control B Register */
	77	#define ATC_CFG_OFFSET 0x14 /* Configuration Register */
	78	#define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */
79	#define ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */
80
81
82	/* Bitfield definitions */
83
84	/* Bitfields in DSCR */
85	#define ATC_DSCR_IF(i) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */
86
87	/* Bitfields in CTRLA */
88	#define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */
89	#define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
1dd1ea8e NF	90	#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
	91	#define ATC_SCSIZE(x) (ATC_SCSIZE_MASK & ((x) << 16))
	92	#define ATC_SCSIZE_1 (0x0 << 16)
	93	#define ATC_SCSIZE_4 (0x1 << 16)
	94	#define ATC_SCSIZE_8 (0x2 << 16)
	95	#define ATC_SCSIZE_16 (0x3 << 16)
	96	#define ATC_SCSIZE_32 (0x4 << 16)
	97	#define ATC_SCSIZE_64 (0x5 << 16)
	98	#define ATC_SCSIZE_128 (0x6 << 16)
	99	#define ATC_SCSIZE_256 (0x7 << 16)
	100	#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
	101	#define ATC_DCSIZE(x) (ATC_DCSIZE_MASK & ((x) << 20))
	102	#define ATC_DCSIZE_1 (0x0 << 20)
	103	#define ATC_DCSIZE_4 (0x1 << 20)
	104	#define ATC_DCSIZE_8 (0x2 << 20)
	105	#define ATC_DCSIZE_16 (0x3 << 20)
	106	#define ATC_DCSIZE_32 (0x4 << 20)
	107	#define ATC_DCSIZE_64 (0x5 << 20)
	108	#define ATC_DCSIZE_128 (0x6 << 20)
	109	#define ATC_DCSIZE_256 (0x7 << 20)
dc78baa2	110	#define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */
808347f6	111	#define ATC_SRC_WIDTH(x) ((x) << 24)
dc78baa2 NF	112	#define ATC_SRC_WIDTH_BYTE (0x0 << 24)
	113	#define ATC_SRC_WIDTH_HALFWORD (0x1 << 24)
	114	#define ATC_SRC_WIDTH_WORD (0x2 << 24)
	115	#define ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */
808347f6	116	#define ATC_DST_WIDTH(x) ((x) << 28)
dc78baa2 NF	117	#define ATC_DST_WIDTH_BYTE (0x0 << 28)
	118	#define ATC_DST_WIDTH_HALFWORD (0x1 << 28)
	119	#define ATC_DST_WIDTH_WORD (0x2 << 28)
	120	#define ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */
	121
	122	/* Bitfields in CTRLB */
	123	#define ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */
	124	#define ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */
ae14d4b5 NF	125	/* Specify AHB interfaces */
	126	#define AT_DMA_MEM_IF 0 /* interface 0 as memory interface */
	127	#define AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */
	128
dc78baa2 NF	129	#define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */
	130	#define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */
	131	#define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */
	132	#define ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */
	133	#define ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */
	134	#define ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */
	135	#define ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */
	136	#define ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */
	137	#define ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */
	138	#define ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */
	139	#define ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */
808347f6 NF	140	#define ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */
808347f6 NF	141	#define ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */
dc78baa2 NF	142	#define ATC_SRC_ADDR_MODE_MASK (0x3 << 24)
	143	#define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */
	144	#define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */
	145	#define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */
	146	#define ATC_DST_ADDR_MODE_MASK (0x3 << 28)
	147	#define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */
	148	#define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */
	149	#define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */
	150	#define ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */
	151	#define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */
	152
	153	/* Bitfields in CFG */
808347f6	154	/* are in at_hdmac.h */
dc78baa2 NF	155
	156	/* Bitfields in SPIP */
	157	#define ATC_SPIP_HOLE(x) (0xFFFFU & (x))
	158	#define ATC_SPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
	159
	160	/* Bitfields in DPIP */
	161	#define ATC_DPIP_HOLE(x) (0xFFFFU & (x))
	162	#define ATC_DPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
	163
	164
	165	/-- descriptors -----------------------------------------------------/
	166
	167	/* LLI == Linked List Item; aka DMA buffer descriptor */
	168	struct at_lli {
	169	/* values that are not changed by hardware */
	170	dma_addr_t saddr;
	171	dma_addr_t daddr;
	172	/* value that may get written back: */
	173	u32 ctrla;
	174	/* more values that are not changed by hardware */
	175	u32 ctrlb;
	176	dma_addr_t dscr; /* chain to next lli */
	177	};
	178
	179	/**
	180	* struct at_desc - software descriptor
	181	* @at_lli: hardware lli structure
	182	* @txd: support for the async_tx api
	183	* @desc_node: node on the channed descriptors list
bdf6c792	184	* @len: descriptor byte count
d088c33b	185	* @tx_width: transfer width
bdf6c792	186	* @total_len: total transaction byte count
dc78baa2 NF	187	*/
	188	struct at_desc {
	189	/* FIRST values the hardware uses */
	190	struct at_lli lli;
	191
	192	/* THEN values for driver housekeeping */
285a3c71	193	struct list_head tx_list;
dc78baa2 NF	194	struct dma_async_tx_descriptor txd;
	195	struct list_head desc_node;
	196	size_t len;
d088c33b	197	u32 tx_width;
bdf6c792	198	size_t total_len;
5abecfa5 MR	199
	200	/* Interleaved data */
	201	size_t boundary;
	202	size_t dst_hole;
	203	size_t src_hole;
dc78baa2 NF	204	};
	205
	206	static inline struct at_desc *
	207	txd_to_at_desc(struct dma_async_tx_descriptor *txd)
	208	{
	209	return container_of(txd, struct at_desc, txd);
	210	}
	211
	212
	213	/-- Channels --------------------------------------------------------/
	214
53830cc7 NF	215	/**
	216	* atc_status - information bits stored in channel status flag
	217	*
	218	* Manipulated with atomic operations.
	219	*/
	220	enum atc_status {
	221	ATC_IS_ERROR = 0,
23b5e3ad	222	ATC_IS_PAUSED = 1,
53830cc7 NF	223	ATC_IS_CYCLIC = 24,
	224	};
	225
dc78baa2 NF	226	/**
	227	* struct at_dma_chan - internal representation of an Atmel HDMAC channel
	228	* @chan_common: common dmaengine channel object members
	229	* @device: parent device
	230	* @ch_regs: memory mapped register base
	231	* @mask: channel index in a mask
bbe89c8e LD	232	* @per_if: peripheral interface
bbe89c8e LD	233	* @mem_if: memory interface
53830cc7	234	* @status: transmit status information from irq/prep* functions
dc78baa2 NF	235	* to tasklet (use atomic operations)
dc78baa2 NF	236	* @tasklet: bottom half to finish transaction work
c0ba5947 NF	237	* @save_cfg: configuration register that is saved on suspend/resume cycle
	238	* @save_dscr: for cyclic operations, preserve next descriptor address in
	239	* the cyclic list on suspend/resume cycle
3e1152a2 VK	240	* @dma_sconfig: configuration for slave transfers, passed via
3e1152a2 VK	241	* .device_config
dc78baa2	242	* @lock: serializes enqueue/dequeue operations to descriptors lists
dc78baa2 NF	243	* @active_list: list of descriptors dmaengine is being running on
	244	* @queue: list of descriptors ready to be submitted to engine
	245	* @free_list: list of descriptors usable by the channel
	246	* @descs_allocated: records the actual size of the descriptor pool
	247	*/
	248	struct at_dma_chan {
	249	struct dma_chan chan_common;
	250	struct at_dma *device;
	251	void __iomem *ch_regs;
	252	u8 mask;
bbe89c8e LD	253	u8 per_if;
bbe89c8e LD	254	u8 mem_if;
53830cc7	255	unsigned long status;
dc78baa2	256	struct tasklet_struct tasklet;
c0ba5947 NF	257	u32 save_cfg;
c0ba5947 NF	258	u32 save_dscr;
beeaa103	259	struct dma_slave_config dma_sconfig;
dc78baa2 NF	260
	261	spinlock_t lock;
	262
	263	/* these other elements are all protected by lock */
dc78baa2 NF	264	struct list_head active_list;
	265	struct list_head queue;
	266	struct list_head free_list;
	267	unsigned int descs_allocated;
	268	};
	269
	270	#define channel_readl(atchan, name) \
	271	__raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
	272
	273	#define channel_writel(atchan, name, val) \
	274	__raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
	275
	276	static inline struct at_dma_chan to_at_dma_chan(struct dma_chan dchan)
	277	{
	278	return container_of(dchan, struct at_dma_chan, chan_common);
	279	}
	280
beeaa103 NF	281	/*
	282	* Fix sconfig's burst size according to at_hdmac. We need to convert them as:
	283	* 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
	284	*
	285	* This can be done by finding most significant bit set.
	286	*/
	287	static inline void convert_burst(u32 *maxburst)
	288	{
	289	if (*maxburst > 1)
	290	maxburst = fls(maxburst) - 2;
	291	else
	292	*maxburst = 0;
	293	}
	294
	295	/*
	296	* Fix sconfig's bus width according to at_hdmac.
	297	* 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
	298	*/
	299	static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
	300	{
	301	switch (addr_width) {
	302	case DMA_SLAVE_BUSWIDTH_2_BYTES:
	303	return 1;
	304	case DMA_SLAVE_BUSWIDTH_4_BYTES:
	305	return 2;
	306	default:
	307	/* For 1 byte width or fallback */
	308	return 0;
	309	}
	310	}
dc78baa2 NF	311
	312	/-- Controller ------------------------------------------------------/
	313
	314	/**
	315	* struct at_dma - internal representation of an Atmel HDMA Controller
	316	* @chan_common: common dmaengine dma_device object members
67348450	317	* @atdma_devtype: identifier of DMA controller compatibility
dc78baa2 NF	318	* @ch_regs: memory mapped register base
dc78baa2 NF	319	* @clk: dma controller clock
c0ba5947	320	* @save_imr: interrupt mask register that is saved on suspend/resume cycle
dc78baa2 NF	321	* @all_chan_mask: all channels availlable in a mask
	322	* @dma_desc_pool: base of DMA descriptor region (DMA address)
	323	* @chan: channels table to store at_dma_chan structures
	324	*/
	325	struct at_dma {
	326	struct dma_device dma_common;
	327	void __iomem *regs;
	328	struct clk *clk;
c0ba5947	329	u32 save_imr;
dc78baa2 NF	330
	331	u8 all_chan_mask;
	332
	333	struct dma_pool *dma_desc_pool;
	334	/* AT THE END channels table */
	335	struct at_dma_chan chan[0];
	336	};
	337
	338	#define dma_readl(atdma, name) \
	339	__raw_readl((atdma)->regs + AT_DMA_##name)
	340	#define dma_writel(atdma, name, val) \
	341	__raw_writel((val), (atdma)->regs + AT_DMA_##name)
	342
	343	static inline struct at_dma to_at_dma(struct dma_device ddev)
	344	{
	345	return container_of(ddev, struct at_dma, dma_common);
	346	}
	347
	348
	349	/-- Helper functions ------------------------------------------------/
	350
	351	static struct device chan2dev(struct dma_chan chan)
	352	{
	353	return &chan->dev->device;
	354	}
dc78baa2 NF	355
	356	#if defined(VERBOSE_DEBUG)
	357	static void vdbg_dump_regs(struct at_dma_chan *atchan)
	358	{
	359	struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
	360
	361	dev_err(chan2dev(&atchan->chan_common),
	362	" channel %d : imr = 0x%x, chsr = 0x%x\n",
	363	atchan->chan_common.chan_id,
	364	dma_readl(atdma, EBCIMR),
	365	dma_readl(atdma, CHSR));
	366
	367	dev_err(chan2dev(&atchan->chan_common),
808347f6	368	" channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
dc78baa2 NF	369	channel_readl(atchan, SADDR),
	370	channel_readl(atchan, DADDR),
	371	channel_readl(atchan, CTRLA),
	372	channel_readl(atchan, CTRLB),
808347f6	373	channel_readl(atchan, CFG),
dc78baa2 NF	374	channel_readl(atchan, DSCR));
	375	}
	376	#else
	377	static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
	378	#endif
	379
	380	static void atc_dump_lli(struct at_dma_chan atchan, struct at_lli lli)
	381	{
1ba151cd JP	382	dev_crit(chan2dev(&atchan->chan_common),
	383	" desc: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
	384	lli->saddr, lli->daddr,
	385	lli->ctrla, lli->ctrlb, lli->dscr);
dc78baa2 NF	386	}
	387
	388
bda3a47c	389	static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
dc78baa2	390	{
bda3a47c	391	u32 ebci;
dc78baa2	392
9b3aa589	393	/* enable interrupts on buffer transfer completion & error */
bda3a47c NV	394	ebci = AT_DMA_BTC(chan_id)
bda3a47c NV	395	\| AT_DMA_ERR(chan_id);
dc78baa2 NF	396	if (on)
	397	dma_writel(atdma, EBCIER, ebci);
	398	else
	399	dma_writel(atdma, EBCIDR, ebci);
	400	}
	401
bda3a47c	402	static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
dc78baa2	403	{
bda3a47c	404	atc_setup_irq(atdma, chan_id, 1);
dc78baa2 NF	405	}
dc78baa2 NF	406
bda3a47c	407	static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
dc78baa2	408	{
bda3a47c	409	atc_setup_irq(atdma, chan_id, 0);
dc78baa2 NF	410	}
	411
	412
	413	/**
	414	* atc_chan_is_enabled - test if given channel is enabled
	415	* @atchan: channel we want to test status
	416	*/
	417	static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
	418	{
	419	struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
	420
	421	return !!(dma_readl(atdma, CHSR) & atchan->mask);
	422	}
	423
3c477482 NF	424	/**
	425	* atc_chan_is_paused - test channel pause/resume status
	426	* @atchan: channel we want to test status
	427	*/
	428	static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
	429	{
	430	return test_bit(ATC_IS_PAUSED, &atchan->status);
	431	}
	432
	433	/**
	434	* atc_chan_is_cyclic - test if given channel has cyclic property set
	435	* @atchan: channel we want to test status
	436	*/
	437	static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
	438	{
	439	return test_bit(ATC_IS_CYCLIC, &atchan->status);
	440	}
dc78baa2 NF	441
	442	/**
	443	* set_desc_eol - set end-of-link to descriptor so it will end transfer
	444	* @desc: descriptor, signle or at the end of a chain, to end chain on
	445	*/
	446	static void set_desc_eol(struct at_desc *desc)
	447	{
9b3aa589 NF	448	u32 ctrlb = desc->lli.ctrlb;
	449
	450	ctrlb &= ~ATC_IEN;
	451	ctrlb \|= ATC_SRC_DSCR_DIS \| ATC_DST_DSCR_DIS;
	452
	453	desc->lli.ctrlb = ctrlb;
dc78baa2 NF	454	desc->lli.dscr = 0;
	455	}
	456
	457	#endif /* AT_HDMAC_REGS_H */