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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
dc78baa2 NF |
2 | /* |
3 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
4 | * | |
5 | * Copyright (C) 2008 Atmel Corporation | |
ac803b56 | 6 | * Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries |
dc78baa2 | 7 | * |
9102d871 NF |
8 | * This supports the Atmel AHB DMA Controller found in several Atmel SoCs. |
9 | * The only Atmel DMA Controller that is not covered by this driver is the one | |
10 | * found on AT91SAM9263. | |
dc78baa2 NF |
11 | */ |
12 | ||
62971b29 | 13 | #include <dt-bindings/dma/at91.h> |
d8840a7e | 14 | #include <linux/bitfield.h> |
dc78baa2 NF |
15 | #include <linux/clk.h> |
16 | #include <linux/dmaengine.h> | |
dc78baa2 | 17 | #include <linux/dmapool.h> |
e3e672b8 | 18 | #include <linux/dma-mapping.h> |
dc78baa2 NF |
19 | #include <linux/interrupt.h> |
20 | #include <linux/module.h> | |
c5115953 | 21 | #include <linux/of.h> |
5f1d429b | 22 | #include <linux/overflow.h> |
897500c7 | 23 | #include <linux/of_platform.h> |
bbe89c8e | 24 | #include <linux/of_dma.h> |
e3e672b8 TA |
25 | #include <linux/platform_device.h> |
26 | #include <linux/slab.h> | |
dc78baa2 | 27 | |
d2ebfb33 | 28 | #include "dmaengine.h" |
ac803b56 | 29 | #include "virt-dma.h" |
dc78baa2 NF |
30 | |
31 | /* | |
32 | * Glossary | |
33 | * -------- | |
34 | * | |
35 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
36 | * at_dma_ / atdma : ATmel DMA controller entity related | |
37 | * atc_ / atchan : ATmel DMA Channel entity related | |
38 | */ | |
39 | ||
5cecadc3 TA |
40 | #define AT_DMA_MAX_NR_CHANNELS 8 |
41 | ||
d8840a7e TA |
42 | /* Global Configuration Register */ |
43 | #define AT_DMA_GCFG 0x00 | |
44 | #define AT_DMA_IF_BIGEND(i) BIT((i)) /* AHB-Lite Interface i in Big-endian mode */ | |
45 | #define AT_DMA_ARB_CFG BIT(4) /* Arbiter mode. */ | |
5cecadc3 | 46 | |
d8840a7e TA |
47 | /* Controller Enable Register */ |
48 | #define AT_DMA_EN 0x04 | |
49 | #define AT_DMA_ENABLE BIT(0) | |
5cecadc3 | 50 | |
d8840a7e TA |
51 | /* Software Single Request Register */ |
52 | #define AT_DMA_SREQ 0x08 | |
53 | #define AT_DMA_SSREQ(x) BIT((x) << 1) /* Request a source single transfer on channel x */ | |
54 | #define AT_DMA_DSREQ(x) BIT(1 + ((x) << 1)) /* Request a destination single transfer on channel x */ | |
5cecadc3 | 55 | |
d8840a7e TA |
56 | /* Software Chunk Transfer Request Register */ |
57 | #define AT_DMA_CREQ 0x0c | |
58 | #define AT_DMA_SCREQ(x) BIT((x) << 1) /* Request a source chunk transfer on channel x */ | |
59 | #define AT_DMA_DCREQ(x) BIT(1 + ((x) << 1)) /* Request a destination chunk transfer on channel x */ | |
5cecadc3 | 60 | |
d8840a7e TA |
61 | /* Software Last Transfer Flag Register */ |
62 | #define AT_DMA_LAST 0x10 | |
63 | #define AT_DMA_SLAST(x) BIT((x) << 1) /* This src rq is last tx of buffer on channel x */ | |
64 | #define AT_DMA_DLAST(x) BIT(1 + ((x) << 1)) /* This dst rq is last tx of buffer on channel x */ | |
5cecadc3 | 65 | |
d8840a7e TA |
66 | /* Request Synchronization Register */ |
67 | #define AT_DMA_SYNC 0x14 | |
68 | #define AT_DMA_SYR(h) BIT((h)) /* Synchronize handshake line h */ | |
5cecadc3 TA |
69 | |
70 | /* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */ | |
d8840a7e TA |
71 | #define AT_DMA_EBCIER 0x18 /* Enable register */ |
72 | #define AT_DMA_EBCIDR 0x1c /* Disable register */ | |
73 | #define AT_DMA_EBCIMR 0x20 /* Mask Register */ | |
74 | #define AT_DMA_EBCISR 0x24 /* Status Register */ | |
75 | #define AT_DMA_CBTC_OFFSET 8 | |
76 | #define AT_DMA_ERR_OFFSET 16 | |
77 | #define AT_DMA_BTC(x) BIT((x)) | |
78 | #define AT_DMA_CBTC(x) BIT(AT_DMA_CBTC_OFFSET + (x)) | |
79 | #define AT_DMA_ERR(x) BIT(AT_DMA_ERR_OFFSET + (x)) | |
80 | ||
81 | /* Channel Handler Enable Register */ | |
82 | #define AT_DMA_CHER 0x28 | |
83 | #define AT_DMA_ENA(x) BIT((x)) | |
84 | #define AT_DMA_SUSP(x) BIT(8 + (x)) | |
85 | #define AT_DMA_KEEP(x) BIT(24 + (x)) | |
86 | ||
87 | /* Channel Handler Disable Register */ | |
88 | #define AT_DMA_CHDR 0x2c | |
89 | #define AT_DMA_DIS(x) BIT(x) | |
90 | #define AT_DMA_RES(x) BIT(8 + (x)) | |
91 | ||
92 | /* Channel Handler Status Register */ | |
93 | #define AT_DMA_CHSR 0x30 | |
94 | #define AT_DMA_EMPT(x) BIT(16 + (x)) | |
95 | #define AT_DMA_STAL(x) BIT(24 + (x)) | |
96 | ||
97 | /* Channel registers base address */ | |
98 | #define AT_DMA_CH_REGS_BASE 0x3c | |
99 | #define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */ | |
5cecadc3 TA |
100 | |
101 | /* Hardware register offset for each channel */ | |
d8840a7e TA |
102 | #define ATC_SADDR_OFFSET 0x00 /* Source Address Register */ |
103 | #define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */ | |
104 | #define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */ | |
105 | #define ATC_CTRLA_OFFSET 0x0c /* Control A Register */ | |
106 | #define ATC_CTRLB_OFFSET 0x10 /* Control B Register */ | |
107 | #define ATC_CFG_OFFSET 0x14 /* Configuration Register */ | |
108 | #define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */ | |
109 | #define ATC_DPIP_OFFSET 0x1c /* Dst PIP Configuration Register */ | |
5cecadc3 TA |
110 | |
111 | ||
112 | /* Bitfield definitions */ | |
113 | ||
114 | /* Bitfields in DSCR */ | |
d8840a7e | 115 | #define ATC_DSCR_IF GENMASK(1, 0) /* Dsc feched via AHB-Lite Interface */ |
5cecadc3 TA |
116 | |
117 | /* Bitfields in CTRLA */ | |
d8840a7e TA |
118 | #define ATC_BTSIZE_MAX GENMASK(15, 0) /* Maximum Buffer Transfer Size */ |
119 | #define ATC_BTSIZE GENMASK(15, 0) /* Buffer Transfer Size */ | |
120 | #define ATC_SCSIZE GENMASK(18, 16) /* Source Chunk Transfer Size */ | |
121 | #define ATC_DCSIZE GENMASK(22, 20) /* Destination Chunk Transfer Size */ | |
122 | #define ATC_SRC_WIDTH GENMASK(25, 24) /* Source Single Transfer Size */ | |
123 | #define ATC_DST_WIDTH GENMASK(29, 28) /* Destination Single Transfer Size */ | |
124 | #define ATC_DONE BIT(31) /* Tx Done (only written back in descriptor) */ | |
5cecadc3 TA |
125 | |
126 | /* Bitfields in CTRLB */ | |
d8840a7e TA |
127 | #define ATC_SIF GENMASK(1, 0) /* Src tx done via AHB-Lite Interface i */ |
128 | #define ATC_DIF GENMASK(5, 4) /* Dst tx done via AHB-Lite Interface i */ | |
129 | #define AT_DMA_MEM_IF 0x0 /* interface 0 as memory interface */ | |
130 | #define AT_DMA_PER_IF 0x1 /* interface 1 as peripheral interface */ | |
131 | #define ATC_SRC_PIP BIT(8) /* Source Picture-in-Picture enabled */ | |
132 | #define ATC_DST_PIP BIT(12) /* Destination Picture-in-Picture enabled */ | |
133 | #define ATC_SRC_DSCR_DIS BIT(16) /* Src Descriptor fetch disable */ | |
134 | #define ATC_DST_DSCR_DIS BIT(20) /* Dst Descriptor fetch disable */ | |
e14fd2af | 135 | #define ATC_FC GENMASK(23, 21) /* Choose Flow Controller */ |
d8840a7e TA |
136 | #define ATC_FC_MEM2MEM 0x0 /* Mem-to-Mem (DMA) */ |
137 | #define ATC_FC_MEM2PER 0x1 /* Mem-to-Periph (DMA) */ | |
138 | #define ATC_FC_PER2MEM 0x2 /* Periph-to-Mem (DMA) */ | |
139 | #define ATC_FC_PER2PER 0x3 /* Periph-to-Periph (DMA) */ | |
140 | #define ATC_FC_PER2MEM_PER 0x4 /* Periph-to-Mem (Peripheral) */ | |
141 | #define ATC_FC_MEM2PER_PER 0x5 /* Mem-to-Periph (Peripheral) */ | |
142 | #define ATC_FC_PER2PER_SRCPER 0x6 /* Periph-to-Periph (Src Peripheral) */ | |
143 | #define ATC_FC_PER2PER_DSTPER 0x7 /* Periph-to-Periph (Dst Peripheral) */ | |
144 | #define ATC_SRC_ADDR_MODE GENMASK(25, 24) | |
145 | #define ATC_SRC_ADDR_MODE_INCR 0x0 /* Incrementing Mode */ | |
146 | #define ATC_SRC_ADDR_MODE_DECR 0x1 /* Decrementing Mode */ | |
147 | #define ATC_SRC_ADDR_MODE_FIXED 0x2 /* Fixed Mode */ | |
148 | #define ATC_DST_ADDR_MODE GENMASK(29, 28) | |
149 | #define ATC_DST_ADDR_MODE_INCR 0x0 /* Incrementing Mode */ | |
150 | #define ATC_DST_ADDR_MODE_DECR 0x1 /* Decrementing Mode */ | |
151 | #define ATC_DST_ADDR_MODE_FIXED 0x2 /* Fixed Mode */ | |
152 | #define ATC_IEN BIT(30) /* BTC interrupt enable (active low) */ | |
153 | #define ATC_AUTO BIT(31) /* Auto multiple buffer tx enable */ | |
5cecadc3 TA |
154 | |
155 | /* Bitfields in CFG */ | |
d8840a7e TA |
156 | #define ATC_SRC_PER GENMASK(3, 0) /* Channel src rq associated with periph handshaking ifc h */ |
157 | #define ATC_DST_PER GENMASK(7, 4) /* Channel dst rq associated with periph handshaking ifc h */ | |
158 | #define ATC_SRC_REP BIT(8) /* Source Replay Mod */ | |
159 | #define ATC_SRC_H2SEL BIT(9) /* Source Handshaking Mod */ | |
160 | #define ATC_SRC_PER_MSB GENMASK(11, 10) /* Channel src rq (most significant bits) */ | |
161 | #define ATC_DST_REP BIT(12) /* Destination Replay Mod */ | |
162 | #define ATC_DST_H2SEL BIT(13) /* Destination Handshaking Mod */ | |
163 | #define ATC_DST_PER_MSB GENMASK(15, 14) /* Channel dst rq (most significant bits) */ | |
164 | #define ATC_SOD BIT(16) /* Stop On Done */ | |
165 | #define ATC_LOCK_IF BIT(20) /* Interface Lock */ | |
166 | #define ATC_LOCK_B BIT(21) /* AHB Bus Lock */ | |
167 | #define ATC_LOCK_IF_L BIT(22) /* Master Interface Arbiter Lock */ | |
168 | #define ATC_AHB_PROT GENMASK(26, 24) /* AHB Protection */ | |
169 | #define ATC_FIFOCFG GENMASK(29, 28) /* FIFO Request Configuration */ | |
170 | #define ATC_FIFOCFG_LARGESTBURST 0x0 | |
171 | #define ATC_FIFOCFG_HALFFIFO 0x1 | |
172 | #define ATC_FIFOCFG_ENOUGHSPACE 0x2 | |
5cecadc3 TA |
173 | |
174 | /* Bitfields in SPIP */ | |
d8840a7e TA |
175 | #define ATC_SPIP_HOLE GENMASK(15, 0) |
176 | #define ATC_SPIP_BOUNDARY GENMASK(25, 16) | |
5cecadc3 TA |
177 | |
178 | /* Bitfields in DPIP */ | |
d8840a7e TA |
179 | #define ATC_DPIP_HOLE GENMASK(15, 0) |
180 | #define ATC_DPIP_BOUNDARY GENMASK(25, 16) | |
181 | ||
2a6c7e8c PR |
182 | #define ATC_PER_MSB GENMASK(5, 4) /* Extract MSBs of a handshaking identifier */ |
183 | #define ATC_SRC_PER_ID(id) \ | |
184 | ({ typeof(id) _id = (id); \ | |
185 | FIELD_PREP(ATC_SRC_PER_MSB, FIELD_GET(ATC_PER_MSB, _id)) | \ | |
186 | FIELD_PREP(ATC_SRC_PER, _id); }) | |
187 | #define ATC_DST_PER_ID(id) \ | |
188 | ({ typeof(id) _id = (id); \ | |
189 | FIELD_PREP(ATC_DST_PER_MSB, FIELD_GET(ATC_PER_MSB, _id)) | \ | |
190 | FIELD_PREP(ATC_DST_PER, _id); }) | |
d8840a7e | 191 | |
5cecadc3 TA |
192 | |
193 | ||
194 | /*-- descriptors -----------------------------------------------------*/ | |
195 | ||
196 | /* LLI == Linked List Item; aka DMA buffer descriptor */ | |
197 | struct at_lli { | |
198 | /* values that are not changed by hardware */ | |
199 | u32 saddr; | |
200 | u32 daddr; | |
201 | /* value that may get written back: */ | |
202 | u32 ctrla; | |
203 | /* more values that are not changed by hardware */ | |
204 | u32 ctrlb; | |
205 | u32 dscr; /* chain to next lli */ | |
206 | }; | |
207 | ||
ac803b56 TA |
208 | /** |
209 | * struct atdma_sg - atdma scatter gather entry | |
210 | * @len: length of the current Linked List Item. | |
211 | * @lli: linked list item that is passed to the DMA controller | |
212 | * @lli_phys: physical address of the LLI. | |
213 | */ | |
214 | struct atdma_sg { | |
215 | unsigned int len; | |
216 | struct at_lli *lli; | |
217 | dma_addr_t lli_phys; | |
218 | }; | |
219 | ||
5cecadc3 TA |
220 | /** |
221 | * struct at_desc - software descriptor | |
ac803b56 TA |
222 | * @vd: pointer to the virtual dma descriptor. |
223 | * @atchan: pointer to the atmel dma channel. | |
5cecadc3 | 224 | * @total_len: total transaction byte count |
ac803b56 TA |
225 | * @sg_len: number of sg entries. |
226 | * @sg: array of sgs. | |
5cecadc3 TA |
227 | */ |
228 | struct at_desc { | |
ac803b56 TA |
229 | struct virt_dma_desc vd; |
230 | struct at_dma_chan *atchan; | |
5cecadc3 | 231 | size_t total_len; |
ac803b56 | 232 | unsigned int sglen; |
5cecadc3 TA |
233 | /* Interleaved data */ |
234 | size_t boundary; | |
235 | size_t dst_hole; | |
236 | size_t src_hole; | |
237 | ||
238 | /* Memset temporary buffer */ | |
239 | bool memset_buffer; | |
240 | dma_addr_t memset_paddr; | |
241 | int *memset_vaddr; | |
81cd3cb3 | 242 | struct atdma_sg sg[] __counted_by(sglen); |
5cecadc3 TA |
243 | }; |
244 | ||
5cecadc3 TA |
245 | /*-- Channels --------------------------------------------------------*/ |
246 | ||
247 | /** | |
248 | * atc_status - information bits stored in channel status flag | |
249 | * | |
250 | * Manipulated with atomic operations. | |
251 | */ | |
252 | enum atc_status { | |
5cecadc3 TA |
253 | ATC_IS_PAUSED = 1, |
254 | ATC_IS_CYCLIC = 24, | |
255 | }; | |
256 | ||
257 | /** | |
258 | * struct at_dma_chan - internal representation of an Atmel HDMAC channel | |
ac803b56 TA |
259 | * @vc: virtual dma channel entry. |
260 | * @atdma: pointer to the driver data. | |
5cecadc3 TA |
261 | * @ch_regs: memory mapped register base |
262 | * @mask: channel index in a mask | |
263 | * @per_if: peripheral interface | |
264 | * @mem_if: memory interface | |
265 | * @status: transmit status information from irq/prep* functions | |
266 | * to tasklet (use atomic operations) | |
5cecadc3 TA |
267 | * @save_cfg: configuration register that is saved on suspend/resume cycle |
268 | * @save_dscr: for cyclic operations, preserve next descriptor address in | |
269 | * the cyclic list on suspend/resume cycle | |
270 | * @dma_sconfig: configuration for slave transfers, passed via | |
271 | * .device_config | |
ac803b56 | 272 | * @desc: pointer to the atmel dma descriptor. |
5cecadc3 TA |
273 | */ |
274 | struct at_dma_chan { | |
ac803b56 TA |
275 | struct virt_dma_chan vc; |
276 | struct at_dma *atdma; | |
5cecadc3 TA |
277 | void __iomem *ch_regs; |
278 | u8 mask; | |
279 | u8 per_if; | |
280 | u8 mem_if; | |
281 | unsigned long status; | |
5cecadc3 TA |
282 | u32 save_cfg; |
283 | u32 save_dscr; | |
ac803b56 TA |
284 | struct dma_slave_config dma_sconfig; |
285 | bool cyclic; | |
286 | struct at_desc *desc; | |
5cecadc3 TA |
287 | }; |
288 | ||
289 | #define channel_readl(atchan, name) \ | |
290 | __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET) | |
291 | ||
292 | #define channel_writel(atchan, name, val) \ | |
293 | __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET) | |
294 | ||
5cecadc3 TA |
295 | /* |
296 | * Fix sconfig's burst size according to at_hdmac. We need to convert them as: | |
297 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7. | |
298 | * | |
299 | * This can be done by finding most significant bit set. | |
300 | */ | |
301 | static inline void convert_burst(u32 *maxburst) | |
302 | { | |
303 | if (*maxburst > 1) | |
304 | *maxburst = fls(*maxburst) - 2; | |
305 | else | |
306 | *maxburst = 0; | |
307 | } | |
308 | ||
309 | /* | |
310 | * Fix sconfig's bus width according to at_hdmac. | |
311 | * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2. | |
312 | */ | |
313 | static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width) | |
314 | { | |
315 | switch (addr_width) { | |
316 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
317 | return 1; | |
318 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
319 | return 2; | |
320 | default: | |
321 | /* For 1 byte width or fallback */ | |
322 | return 0; | |
323 | } | |
324 | } | |
325 | ||
326 | /*-- Controller ------------------------------------------------------*/ | |
327 | ||
328 | /** | |
329 | * struct at_dma - internal representation of an Atmel HDMA Controller | |
1c1114d8 | 330 | * @dma_device: dmaengine dma_device object members |
5cecadc3 TA |
331 | * @atdma_devtype: identifier of DMA controller compatibility |
332 | * @ch_regs: memory mapped register base | |
333 | * @clk: dma controller clock | |
334 | * @save_imr: interrupt mask register that is saved on suspend/resume cycle | |
335 | * @all_chan_mask: all channels availlable in a mask | |
ac803b56 | 336 | * @lli_pool: hw lli table |
5cecadc3 TA |
337 | * @chan: channels table to store at_dma_chan structures |
338 | */ | |
339 | struct at_dma { | |
1c1114d8 | 340 | struct dma_device dma_device; |
5cecadc3 TA |
341 | void __iomem *regs; |
342 | struct clk *clk; | |
343 | u32 save_imr; | |
344 | ||
345 | u8 all_chan_mask; | |
346 | ||
ac803b56 | 347 | struct dma_pool *lli_pool; |
5cecadc3 TA |
348 | struct dma_pool *memset_pool; |
349 | /* AT THE END channels table */ | |
350 | struct at_dma_chan chan[]; | |
351 | }; | |
352 | ||
353 | #define dma_readl(atdma, name) \ | |
354 | __raw_readl((atdma)->regs + AT_DMA_##name) | |
355 | #define dma_writel(atdma, name, val) \ | |
356 | __raw_writel((val), (atdma)->regs + AT_DMA_##name) | |
357 | ||
ac803b56 TA |
358 | static inline struct at_desc *to_atdma_desc(struct dma_async_tx_descriptor *t) |
359 | { | |
360 | return container_of(t, struct at_desc, vd.tx); | |
361 | } | |
362 | ||
363 | static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *chan) | |
364 | { | |
365 | return container_of(chan, struct at_dma_chan, vc.chan); | |
366 | } | |
367 | ||
5cecadc3 TA |
368 | static inline struct at_dma *to_at_dma(struct dma_device *ddev) |
369 | { | |
1c1114d8 | 370 | return container_of(ddev, struct at_dma, dma_device); |
5cecadc3 TA |
371 | } |
372 | ||
373 | ||
374 | /*-- Helper functions ------------------------------------------------*/ | |
375 | ||
376 | static struct device *chan2dev(struct dma_chan *chan) | |
377 | { | |
378 | return &chan->dev->device; | |
379 | } | |
380 | ||
381 | #if defined(VERBOSE_DEBUG) | |
382 | static void vdbg_dump_regs(struct at_dma_chan *atchan) | |
383 | { | |
ac803b56 | 384 | struct at_dma *atdma = to_at_dma(atchan->vc.chan.device); |
5cecadc3 | 385 | |
ac803b56 | 386 | dev_err(chan2dev(&atchan->vc.chan), |
5cecadc3 | 387 | " channel %d : imr = 0x%x, chsr = 0x%x\n", |
ac803b56 | 388 | atchan->vc.chan.chan_id, |
5cecadc3 TA |
389 | dma_readl(atdma, EBCIMR), |
390 | dma_readl(atdma, CHSR)); | |
391 | ||
ac803b56 | 392 | dev_err(chan2dev(&atchan->vc.chan), |
5cecadc3 TA |
393 | " channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n", |
394 | channel_readl(atchan, SADDR), | |
395 | channel_readl(atchan, DADDR), | |
396 | channel_readl(atchan, CTRLA), | |
397 | channel_readl(atchan, CTRLB), | |
398 | channel_readl(atchan, CFG), | |
399 | channel_readl(atchan, DSCR)); | |
400 | } | |
401 | #else | |
402 | static void vdbg_dump_regs(struct at_dma_chan *atchan) {} | |
403 | #endif | |
404 | ||
405 | static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli) | |
406 | { | |
ac803b56 | 407 | dev_crit(chan2dev(&atchan->vc.chan), |
5cecadc3 TA |
408 | "desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n", |
409 | &lli->saddr, &lli->daddr, | |
410 | lli->ctrla, lli->ctrlb, &lli->dscr); | |
411 | } | |
412 | ||
413 | ||
414 | static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on) | |
415 | { | |
416 | u32 ebci; | |
417 | ||
418 | /* enable interrupts on buffer transfer completion & error */ | |
419 | ebci = AT_DMA_BTC(chan_id) | |
420 | | AT_DMA_ERR(chan_id); | |
421 | if (on) | |
422 | dma_writel(atdma, EBCIER, ebci); | |
423 | else | |
424 | dma_writel(atdma, EBCIDR, ebci); | |
425 | } | |
426 | ||
427 | static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id) | |
428 | { | |
429 | atc_setup_irq(atdma, chan_id, 1); | |
430 | } | |
431 | ||
432 | static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id) | |
433 | { | |
434 | atc_setup_irq(atdma, chan_id, 0); | |
435 | } | |
436 | ||
437 | ||
438 | /** | |
439 | * atc_chan_is_enabled - test if given channel is enabled | |
440 | * @atchan: channel we want to test status | |
441 | */ | |
442 | static inline int atc_chan_is_enabled(struct at_dma_chan *atchan) | |
443 | { | |
ac803b56 | 444 | struct at_dma *atdma = to_at_dma(atchan->vc.chan.device); |
5cecadc3 TA |
445 | |
446 | return !!(dma_readl(atdma, CHSR) & atchan->mask); | |
447 | } | |
448 | ||
449 | /** | |
450 | * atc_chan_is_paused - test channel pause/resume status | |
451 | * @atchan: channel we want to test status | |
452 | */ | |
453 | static inline int atc_chan_is_paused(struct at_dma_chan *atchan) | |
454 | { | |
455 | return test_bit(ATC_IS_PAUSED, &atchan->status); | |
456 | } | |
457 | ||
458 | /** | |
459 | * atc_chan_is_cyclic - test if given channel has cyclic property set | |
460 | * @atchan: channel we want to test status | |
461 | */ | |
462 | static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan) | |
463 | { | |
464 | return test_bit(ATC_IS_CYCLIC, &atchan->status); | |
465 | } | |
466 | ||
467 | /** | |
ac803b56 | 468 | * set_lli_eol - set end-of-link to descriptor so it will end transfer |
5cecadc3 | 469 | * @desc: descriptor, signle or at the end of a chain, to end chain on |
ac803b56 | 470 | * @i: index of the atmel scatter gather entry that is at the end of the chain. |
5cecadc3 | 471 | */ |
ac803b56 | 472 | static void set_lli_eol(struct at_desc *desc, unsigned int i) |
5cecadc3 | 473 | { |
ac803b56 | 474 | u32 ctrlb = desc->sg[i].lli->ctrlb; |
5cecadc3 TA |
475 | |
476 | ctrlb &= ~ATC_IEN; | |
477 | ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS; | |
478 | ||
ac803b56 TA |
479 | desc->sg[i].lli->ctrlb = ctrlb; |
480 | desc->sg[i].lli->dscr = 0; | |
5cecadc3 TA |
481 | } |
482 | ||
d8840a7e TA |
483 | #define ATC_DEFAULT_CFG FIELD_PREP(ATC_FIFOCFG, ATC_FIFOCFG_HALFFIFO) |
484 | #define ATC_DEFAULT_CTRLB (FIELD_PREP(ATC_SIF, AT_DMA_MEM_IF) | \ | |
485 | FIELD_PREP(ATC_DIF, AT_DMA_MEM_IF)) | |
816070ed LD |
486 | #define ATC_DMA_BUSWIDTHS\ |
487 | (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ | |
488 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ | |
489 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ | |
490 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
dc78baa2 | 491 | |
93dce3a6 CP |
492 | #define ATC_MAX_DSCR_TRIALS 10 |
493 | ||
dc78baa2 NF |
494 | /* |
495 | * Initial number of descriptors to allocate for each channel. This could | |
496 | * be increased during dma usage. | |
497 | */ | |
498 | static unsigned int init_nr_desc_per_channel = 64; | |
499 | module_param(init_nr_desc_per_channel, uint, 0644); | |
500 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
501 | "initial descriptors per channel (default: 64)"); | |
502 | ||
33cb6d1e AB |
503 | /** |
504 | * struct at_dma_platform_data - Controller configuration parameters | |
505 | * @nr_channels: Number of channels supported by hardware (max 8) | |
506 | * @cap_mask: dma_capability flags supported by the platform | |
507 | */ | |
508 | struct at_dma_platform_data { | |
509 | unsigned int nr_channels; | |
510 | dma_cap_mask_t cap_mask; | |
511 | }; | |
512 | ||
513 | /** | |
514 | * struct at_dma_slave - Controller-specific information about a slave | |
515 | * @dma_dev: required DMA master device | |
516 | * @cfg: Platform-specific initializer for the CFG register | |
517 | */ | |
518 | struct at_dma_slave { | |
519 | struct device *dma_dev; | |
520 | u32 cfg; | |
521 | }; | |
dc78baa2 | 522 | |
265567fb TF |
523 | static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst, |
524 | size_t len) | |
525 | { | |
526 | unsigned int width; | |
527 | ||
528 | if (!((src | dst | len) & 3)) | |
529 | width = 2; | |
530 | else if (!((src | dst | len) & 1)) | |
531 | width = 1; | |
532 | else | |
533 | width = 0; | |
534 | ||
535 | return width; | |
536 | } | |
537 | ||
ac803b56 | 538 | static void atdma_lli_chain(struct at_desc *desc, unsigned int i) |
dc78baa2 | 539 | { |
ac803b56 | 540 | struct atdma_sg *atdma_sg = &desc->sg[i]; |
dc78baa2 | 541 | |
ac803b56 TA |
542 | if (i) |
543 | desc->sg[i - 1].lli->dscr = atdma_sg->lli_phys; | |
53830cc7 NF |
544 | } |
545 | ||
dc78baa2 NF |
546 | /** |
547 | * atc_dostart - starts the DMA engine for real | |
548 | * @atchan: the channel we want to start | |
dc78baa2 | 549 | */ |
ac803b56 | 550 | static void atc_dostart(struct at_dma_chan *atchan) |
dc78baa2 | 551 | { |
ac803b56 TA |
552 | struct virt_dma_desc *vd = vchan_next_desc(&atchan->vc); |
553 | struct at_desc *desc; | |
dc78baa2 | 554 | |
ac803b56 TA |
555 | if (!vd) { |
556 | atchan->desc = NULL; | |
dc78baa2 NF |
557 | return; |
558 | } | |
559 | ||
560 | vdbg_dump_regs(atchan); | |
561 | ||
ac803b56 TA |
562 | list_del(&vd->node); |
563 | atchan->desc = desc = to_atdma_desc(&vd->tx); | |
564 | ||
dc78baa2 NF |
565 | channel_writel(atchan, SADDR, 0); |
566 | channel_writel(atchan, DADDR, 0); | |
567 | channel_writel(atchan, CTRLA, 0); | |
568 | channel_writel(atchan, CTRLB, 0); | |
ac803b56 TA |
569 | channel_writel(atchan, DSCR, desc->sg[0].lli_phys); |
570 | channel_writel(atchan, SPIP, | |
571 | FIELD_PREP(ATC_SPIP_HOLE, desc->src_hole) | | |
572 | FIELD_PREP(ATC_SPIP_BOUNDARY, desc->boundary)); | |
573 | channel_writel(atchan, DPIP, | |
574 | FIELD_PREP(ATC_DPIP_HOLE, desc->dst_hole) | | |
575 | FIELD_PREP(ATC_DPIP_BOUNDARY, desc->boundary)); | |
576 | ||
580ee844 TA |
577 | /* Don't allow CPU to reorder channel enable. */ |
578 | wmb(); | |
ac803b56 | 579 | dma_writel(atchan->atdma, CHER, atchan->mask); |
dc78baa2 NF |
580 | |
581 | vdbg_dump_regs(atchan); | |
582 | } | |
583 | ||
ac803b56 | 584 | static void atdma_desc_free(struct virt_dma_desc *vd) |
d48de6f1 | 585 | { |
ac803b56 TA |
586 | struct at_dma *atdma = to_at_dma(vd->tx.chan->device); |
587 | struct at_desc *desc = to_atdma_desc(&vd->tx); | |
588 | unsigned int i; | |
d48de6f1 | 589 | |
ac803b56 TA |
590 | for (i = 0; i < desc->sglen; i++) { |
591 | if (desc->sg[i].lli) | |
592 | dma_pool_free(atdma->lli_pool, desc->sg[i].lli, | |
593 | desc->sg[i].lli_phys); | |
bdf6c792 | 594 | } |
d48de6f1 | 595 | |
ac803b56 TA |
596 | /* If the transfer was a memset, free our temporary buffer */ |
597 | if (desc->memset_buffer) { | |
598 | dma_pool_free(atdma->memset_pool, desc->memset_vaddr, | |
599 | desc->memset_paddr); | |
600 | desc->memset_buffer = false; | |
d48de6f1 ES |
601 | } |
602 | ||
ac803b56 | 603 | kfree(desc); |
d48de6f1 ES |
604 | } |
605 | ||
bdf6c792 TF |
606 | /** |
607 | * atc_calc_bytes_left - calculates the number of bytes left according to the | |
608 | * value read from CTRLA. | |
609 | * | |
610 | * @current_len: the number of bytes left before reading CTRLA | |
611 | * @ctrla: the value of CTRLA | |
bdf6c792 | 612 | */ |
f5d79afa | 613 | static inline u32 atc_calc_bytes_left(u32 current_len, u32 ctrla) |
bdf6c792 | 614 | { |
d8840a7e TA |
615 | u32 btsize = FIELD_GET(ATC_BTSIZE, ctrla); |
616 | u32 src_width = FIELD_GET(ATC_SRC_WIDTH, ctrla); | |
bdf6c792 | 617 | |
93dce3a6 CP |
618 | /* |
619 | * According to the datasheet, when reading the Control A Register | |
620 | * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the | |
621 | * number of transfers completed on the Source Interface. | |
622 | * So btsize is always a number of source width transfers. | |
623 | */ | |
624 | return current_len - (btsize << src_width); | |
bdf6c792 TF |
625 | } |
626 | ||
b50cf4bd TA |
627 | /** |
628 | * atc_get_llis_residue - Get residue for a hardware linked list transfer | |
629 | * | |
ac803b56 TA |
630 | * Calculate the residue by removing the length of the Linked List Item (LLI) |
631 | * already transferred from the total length. To get the current LLI we can use | |
632 | * the value of the channel's DSCR register and compare it against the DSCR | |
633 | * value of each LLI. | |
b50cf4bd TA |
634 | * |
635 | * The CTRLA register provides us with the amount of data already read from the | |
ac803b56 TA |
636 | * source for the LLI. So we can compute a more accurate residue by also |
637 | * removing the number of bytes corresponding to this amount of data. | |
b50cf4bd TA |
638 | * |
639 | * However, the DSCR and CTRLA registers cannot be read both atomically. Hence a | |
ac803b56 TA |
640 | * race condition may occur: the first read register may refer to one LLI |
641 | * whereas the second read may refer to a later LLI in the list because of the | |
642 | * DMA transfer progression inbetween the two reads. | |
b50cf4bd TA |
643 | * |
644 | * One solution could have been to pause the DMA transfer, read the DSCR and | |
645 | * CTRLA then resume the DMA transfer. Nonetheless, this approach presents some | |
646 | * drawbacks: | |
647 | * - If the DMA transfer is paused, RX overruns or TX underruns are more likey | |
648 | * to occur depending on the system latency. Taking the USART driver as an | |
649 | * example, it uses a cyclic DMA transfer to read data from the Receive | |
650 | * Holding Register (RHR) to avoid RX overruns since the RHR is not protected | |
651 | * by any FIFO on most Atmel SoCs. So pausing the DMA transfer to compute the | |
652 | * residue would break the USART driver design. | |
653 | * - The atc_pause() function masks interrupts but we'd rather avoid to do so | |
654 | * for system latency purpose. | |
655 | * | |
656 | * Then we'd rather use another solution: the DSCR is read a first time, the | |
657 | * CTRLA is read in turn, next the DSCR is read a second time. If the two | |
658 | * consecutive read values of the DSCR are the same then we assume both refers | |
ac803b56 TA |
659 | * to the very same LLI as well as the CTRLA value read inbetween does. For |
660 | * cyclic tranfers, the assumption is that a full loop is "not so fast". If the | |
661 | * two DSCR values are different, we read again the CTRLA then the DSCR till two | |
662 | * consecutive read values from DSCR are equal or till the maximum trials is | |
663 | * reach. This algorithm is very unlikely not to find a stable value for DSCR. | |
b50cf4bd TA |
664 | * @atchan: pointer to an atmel hdmac channel. |
665 | * @desc: pointer to the descriptor for which the residue is calculated. | |
666 | * @residue: residue to be set to dma_tx_state. | |
667 | * Returns 0 on success, -errno otherwise. | |
668 | */ | |
669 | static int atc_get_llis_residue(struct at_dma_chan *atchan, | |
670 | struct at_desc *desc, u32 *residue) | |
671 | { | |
b50cf4bd TA |
672 | u32 len, ctrla, dscr; |
673 | unsigned int i; | |
674 | ||
675 | len = desc->total_len; | |
676 | dscr = channel_readl(atchan, DSCR); | |
677 | rmb(); /* ensure DSCR is read before CTRLA */ | |
678 | ctrla = channel_readl(atchan, CTRLA); | |
679 | for (i = 0; i < ATC_MAX_DSCR_TRIALS; ++i) { | |
680 | u32 new_dscr; | |
681 | ||
682 | rmb(); /* ensure DSCR is read after CTRLA */ | |
683 | new_dscr = channel_readl(atchan, DSCR); | |
684 | ||
685 | /* | |
686 | * If the DSCR register value has not changed inside the DMA | |
687 | * controller since the previous read, we assume that both the | |
688 | * dscr and ctrla values refers to the very same descriptor. | |
689 | */ | |
690 | if (likely(new_dscr == dscr)) | |
691 | break; | |
692 | ||
693 | /* | |
694 | * DSCR has changed inside the DMA controller, so the previouly | |
695 | * read value of CTRLA may refer to an already processed | |
696 | * descriptor hence could be outdated. We need to update ctrla | |
697 | * to match the current descriptor. | |
698 | */ | |
699 | dscr = new_dscr; | |
700 | rmb(); /* ensure DSCR is read before CTRLA */ | |
701 | ctrla = channel_readl(atchan, CTRLA); | |
702 | } | |
703 | if (unlikely(i == ATC_MAX_DSCR_TRIALS)) | |
704 | return -ETIMEDOUT; | |
705 | ||
706 | /* For the first descriptor we can be more accurate. */ | |
ac803b56 | 707 | if (desc->sg[0].lli->dscr == dscr) { |
b50cf4bd TA |
708 | *residue = atc_calc_bytes_left(len, ctrla); |
709 | return 0; | |
710 | } | |
ac803b56 | 711 | len -= desc->sg[0].len; |
b50cf4bd | 712 | |
ac803b56 TA |
713 | for (i = 1; i < desc->sglen; i++) { |
714 | if (desc->sg[i].lli && desc->sg[i].lli->dscr == dscr) | |
b50cf4bd | 715 | break; |
ac803b56 | 716 | len -= desc->sg[i].len; |
b50cf4bd TA |
717 | } |
718 | ||
719 | /* | |
ac803b56 TA |
720 | * For the current LLI in the chain we can calculate the remaining bytes |
721 | * using the channel's CTRLA register. | |
b50cf4bd TA |
722 | */ |
723 | *residue = atc_calc_bytes_left(len, ctrla); | |
724 | return 0; | |
ac803b56 | 725 | |
b50cf4bd TA |
726 | } |
727 | ||
bdf6c792 | 728 | /** |
91617bf6 | 729 | * atc_get_residue - get the number of bytes residue for a cookie. |
f5d79afa | 730 | * The residue is passed by address and updated on success. |
bdf6c792 TF |
731 | * @chan: DMA channel |
732 | * @cookie: transaction identifier to check status of | |
f5d79afa TA |
733 | * @residue: residue to be updated. |
734 | * Return 0 on success, -errono otherwise. | |
d48de6f1 | 735 | */ |
91617bf6 TA |
736 | static int atc_get_residue(struct dma_chan *chan, dma_cookie_t cookie, |
737 | u32 *residue) | |
d48de6f1 | 738 | { |
ac803b56 TA |
739 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
740 | struct virt_dma_desc *vd; | |
741 | struct at_desc *desc = NULL; | |
b50cf4bd | 742 | u32 len, ctrla; |
d48de6f1 | 743 | |
ac803b56 TA |
744 | vd = vchan_find_desc(&atchan->vc, cookie); |
745 | if (vd) | |
746 | desc = to_atdma_desc(&vd->tx); | |
747 | else if (atchan->desc && atchan->desc->vd.tx.cookie == cookie) | |
748 | desc = atchan->desc; | |
749 | ||
750 | if (!desc) | |
bdf6c792 | 751 | return -EINVAL; |
d48de6f1 | 752 | |
ac803b56 | 753 | if (desc->sg[0].lli->dscr) |
bdf6c792 | 754 | /* hardware linked list transfer */ |
ac803b56 | 755 | return atc_get_llis_residue(atchan, desc, residue); |
bdf6c792 | 756 | |
b50cf4bd | 757 | /* single transfer */ |
ac803b56 | 758 | len = desc->total_len; |
b50cf4bd TA |
759 | ctrla = channel_readl(atchan, CTRLA); |
760 | *residue = atc_calc_bytes_left(len, ctrla); | |
f5d79afa | 761 | return 0; |
d48de6f1 ES |
762 | } |
763 | ||
dc78baa2 NF |
764 | /** |
765 | * atc_handle_error - handle errors reported by DMA controller | |
ac803b56 TA |
766 | * @atchan: channel where error occurs. |
767 | * @i: channel index | |
dc78baa2 | 768 | */ |
ac803b56 | 769 | static void atc_handle_error(struct at_dma_chan *atchan, unsigned int i) |
dc78baa2 | 770 | { |
ac803b56 | 771 | struct at_desc *desc = atchan->desc; |
dc78baa2 | 772 | |
ac803b56 TA |
773 | /* Disable channel on AHB error */ |
774 | dma_writel(atchan->atdma, CHDR, AT_DMA_RES(i) | atchan->mask); | |
4c2e9ba0 | 775 | |
dc78baa2 NF |
776 | /* |
777 | * KERN_CRITICAL may seem harsh, but since this only happens | |
778 | * when someone submits a bad physical address in a | |
779 | * descriptor, we should consider ourselves lucky that the | |
780 | * controller flagged an error instead of scribbling over | |
781 | * random memory locations. | |
782 | */ | |
ac803b56 TA |
783 | dev_crit(chan2dev(&atchan->vc.chan), "Bad descriptor submitted for DMA!\n"); |
784 | dev_crit(chan2dev(&atchan->vc.chan), "cookie: %d\n", | |
785 | desc->vd.tx.cookie); | |
786 | for (i = 0; i < desc->sglen; i++) | |
787 | atc_dump_lli(atchan, desc->sg[i].lli); | |
53830cc7 | 788 | } |
dc78baa2 | 789 | |
ac803b56 TA |
790 | static void atdma_handle_chan_done(struct at_dma_chan *atchan, u32 pending, |
791 | unsigned int i) | |
dc78baa2 | 792 | { |
ac803b56 | 793 | struct at_desc *desc; |
dc78baa2 | 794 | |
ac803b56 TA |
795 | spin_lock(&atchan->vc.lock); |
796 | desc = atchan->desc; | |
dc78baa2 | 797 | |
ac803b56 TA |
798 | if (desc) { |
799 | if (pending & AT_DMA_ERR(i)) { | |
800 | atc_handle_error(atchan, i); | |
801 | /* Pretend the descriptor completed successfully */ | |
802 | } | |
078a6506 | 803 | |
ac803b56 TA |
804 | if (atc_chan_is_cyclic(atchan)) { |
805 | vchan_cyclic_callback(&desc->vd); | |
806 | } else { | |
807 | vchan_cookie_complete(&desc->vd); | |
808 | atchan->desc = NULL; | |
809 | if (!(atc_chan_is_enabled(atchan))) | |
810 | atc_dostart(atchan); | |
811 | } | |
812 | } | |
813 | spin_unlock(&atchan->vc.lock); | |
dc78baa2 NF |
814 | } |
815 | ||
816 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
817 | { | |
0e75c28c | 818 | struct at_dma *atdma = dev_id; |
dc78baa2 NF |
819 | struct at_dma_chan *atchan; |
820 | int i; | |
821 | u32 status, pending, imr; | |
822 | int ret = IRQ_NONE; | |
823 | ||
824 | do { | |
825 | imr = dma_readl(atdma, EBCIMR); | |
826 | status = dma_readl(atdma, EBCISR); | |
827 | pending = status & imr; | |
828 | ||
829 | if (!pending) | |
830 | break; | |
831 | ||
1c1114d8 | 832 | dev_vdbg(atdma->dma_device.dev, |
dc78baa2 NF |
833 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", |
834 | status, imr, pending); | |
835 | ||
1c1114d8 | 836 | for (i = 0; i < atdma->dma_device.chancnt; i++) { |
dc78baa2 | 837 | atchan = &atdma->chan[i]; |
ac803b56 TA |
838 | if (!(pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i)))) |
839 | continue; | |
840 | atdma_handle_chan_done(atchan, pending, i); | |
841 | ret = IRQ_HANDLED; | |
dc78baa2 NF |
842 | } |
843 | ||
844 | } while (pending); | |
845 | ||
846 | return ret; | |
847 | } | |
848 | ||
dc78baa2 | 849 | /*-- DMA Engine API --------------------------------------------------*/ |
5abecfa5 MR |
850 | /** |
851 | * atc_prep_dma_interleaved - prepare memory to memory interleaved operation | |
852 | * @chan: the channel to prepare operation on | |
853 | * @xt: Interleaved transfer template | |
854 | * @flags: tx descriptor status flags | |
855 | */ | |
856 | static struct dma_async_tx_descriptor * | |
857 | atc_prep_dma_interleaved(struct dma_chan *chan, | |
858 | struct dma_interleaved_template *xt, | |
859 | unsigned long flags) | |
860 | { | |
ac803b56 | 861 | struct at_dma *atdma = to_at_dma(chan->device); |
5abecfa5 | 862 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
62a277d4 | 863 | struct data_chunk *first; |
ac803b56 TA |
864 | struct atdma_sg *atdma_sg; |
865 | struct at_desc *desc; | |
866 | struct at_lli *lli; | |
5abecfa5 MR |
867 | size_t xfer_count; |
868 | unsigned int dwidth; | |
869 | u32 ctrla; | |
870 | u32 ctrlb; | |
871 | size_t len = 0; | |
872 | int i; | |
873 | ||
4483320e MS |
874 | if (unlikely(!xt || xt->numf != 1 || !xt->frame_size)) |
875 | return NULL; | |
876 | ||
62a277d4 GS |
877 | first = xt->sgl; |
878 | ||
5abecfa5 | 879 | dev_info(chan2dev(chan), |
2c5d7407 AB |
880 | "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n", |
881 | __func__, &xt->src_start, &xt->dst_start, xt->numf, | |
5abecfa5 MR |
882 | xt->frame_size, flags); |
883 | ||
5abecfa5 MR |
884 | /* |
885 | * The controller can only "skip" X bytes every Y bytes, so we | |
886 | * need to make sure we are given a template that fit that | |
887 | * description, ie a template with chunks that always have the | |
888 | * same size, with the same ICGs. | |
889 | */ | |
890 | for (i = 0; i < xt->frame_size; i++) { | |
891 | struct data_chunk *chunk = xt->sgl + i; | |
892 | ||
893 | if ((chunk->size != xt->sgl->size) || | |
894 | (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) || | |
895 | (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) { | |
896 | dev_err(chan2dev(chan), | |
897 | "%s: the controller can transfer only identical chunks\n", | |
898 | __func__); | |
899 | return NULL; | |
900 | } | |
901 | ||
902 | len += chunk->size; | |
903 | } | |
904 | ||
ac803b56 | 905 | dwidth = atc_get_xfer_width(xt->src_start, xt->dst_start, len); |
5abecfa5 MR |
906 | |
907 | xfer_count = len >> dwidth; | |
908 | if (xfer_count > ATC_BTSIZE_MAX) { | |
909 | dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__); | |
910 | return NULL; | |
911 | } | |
912 | ||
d8840a7e TA |
913 | ctrla = FIELD_PREP(ATC_SRC_WIDTH, dwidth) | |
914 | FIELD_PREP(ATC_DST_WIDTH, dwidth); | |
5abecfa5 | 915 | |
d8840a7e TA |
916 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | |
917 | FIELD_PREP(ATC_SRC_ADDR_MODE, ATC_SRC_ADDR_MODE_INCR) | | |
918 | FIELD_PREP(ATC_DST_ADDR_MODE, ATC_DST_ADDR_MODE_INCR) | | |
919 | ATC_SRC_PIP | ATC_DST_PIP | | |
920 | FIELD_PREP(ATC_FC, ATC_FC_MEM2MEM); | |
5abecfa5 | 921 | |
ac803b56 TA |
922 | desc = kzalloc(struct_size(desc, sg, 1), GFP_ATOMIC); |
923 | if (!desc) | |
924 | return NULL; | |
925 | desc->sglen = 1; | |
926 | ||
927 | atdma_sg = desc->sg; | |
928 | atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, GFP_NOWAIT, | |
929 | &atdma_sg->lli_phys); | |
930 | if (!atdma_sg->lli) { | |
931 | kfree(desc); | |
5abecfa5 MR |
932 | return NULL; |
933 | } | |
ac803b56 | 934 | lli = atdma_sg->lli; |
5abecfa5 | 935 | |
ac803b56 TA |
936 | lli->saddr = xt->src_start; |
937 | lli->daddr = xt->dst_start; | |
938 | lli->ctrla = ctrla | xfer_count; | |
939 | lli->ctrlb = ctrlb; | |
5abecfa5 MR |
940 | |
941 | desc->boundary = first->size >> dwidth; | |
942 | desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1; | |
943 | desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1; | |
944 | ||
ac803b56 TA |
945 | atdma_sg->len = len; |
946 | desc->total_len = len; | |
5abecfa5 | 947 | |
ac803b56 TA |
948 | set_lli_eol(desc, 0); |
949 | return vchan_tx_prep(&atchan->vc, &desc->vd, flags); | |
5abecfa5 MR |
950 | } |
951 | ||
dc78baa2 NF |
952 | /** |
953 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
954 | * @chan: the channel to prepare operation on | |
955 | * @dest: operation virtual destination address | |
956 | * @src: operation virtual source address | |
957 | * @len: operation length | |
958 | * @flags: tx descriptor status flags | |
959 | */ | |
960 | static struct dma_async_tx_descriptor * | |
961 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
962 | size_t len, unsigned long flags) | |
963 | { | |
ac803b56 | 964 | struct at_dma *atdma = to_at_dma(chan->device); |
dc78baa2 NF |
965 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
966 | struct at_desc *desc = NULL; | |
dc78baa2 NF |
967 | size_t xfer_count; |
968 | size_t offset; | |
ac803b56 | 969 | size_t sg_len; |
dc78baa2 NF |
970 | unsigned int src_width; |
971 | unsigned int dst_width; | |
ac803b56 | 972 | unsigned int i; |
dc78baa2 NF |
973 | u32 ctrla; |
974 | u32 ctrlb; | |
975 | ||
ac803b56 TA |
976 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: d%pad s%pad l0x%zx f0x%lx\n", |
977 | &dest, &src, len, flags); | |
dc78baa2 NF |
978 | |
979 | if (unlikely(!len)) { | |
ac803b56 | 980 | dev_err(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); |
dc78baa2 NF |
981 | return NULL; |
982 | } | |
983 | ||
ac803b56 TA |
984 | sg_len = DIV_ROUND_UP(len, ATC_BTSIZE_MAX); |
985 | desc = kzalloc(struct_size(desc, sg, sg_len), GFP_ATOMIC); | |
986 | if (!desc) | |
987 | return NULL; | |
988 | desc->sglen = sg_len; | |
989 | ||
d8840a7e TA |
990 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | |
991 | FIELD_PREP(ATC_SRC_ADDR_MODE, ATC_SRC_ADDR_MODE_INCR) | | |
992 | FIELD_PREP(ATC_DST_ADDR_MODE, ATC_DST_ADDR_MODE_INCR) | | |
993 | FIELD_PREP(ATC_FC, ATC_FC_MEM2MEM); | |
dc78baa2 NF |
994 | |
995 | /* | |
996 | * We can be a lot more clever here, but this should take care | |
997 | * of the most common optimization. | |
998 | */ | |
265567fb TF |
999 | src_width = dst_width = atc_get_xfer_width(src, dest, len); |
1000 | ||
d8840a7e TA |
1001 | ctrla = FIELD_PREP(ATC_SRC_WIDTH, src_width) | |
1002 | FIELD_PREP(ATC_DST_WIDTH, dst_width); | |
dc78baa2 | 1003 | |
ac803b56 TA |
1004 | for (offset = 0, i = 0; offset < len; |
1005 | offset += xfer_count << src_width, i++) { | |
1006 | struct atdma_sg *atdma_sg = &desc->sg[i]; | |
1007 | struct at_lli *lli; | |
dc78baa2 | 1008 | |
ac803b56 TA |
1009 | atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, GFP_NOWAIT, |
1010 | &atdma_sg->lli_phys); | |
1011 | if (!atdma_sg->lli) | |
dc78baa2 | 1012 | goto err_desc_get; |
ac803b56 TA |
1013 | lli = atdma_sg->lli; |
1014 | ||
1015 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
1016 | ATC_BTSIZE_MAX); | |
dc78baa2 | 1017 | |
ac803b56 TA |
1018 | lli->saddr = src + offset; |
1019 | lli->daddr = dest + offset; | |
1020 | lli->ctrla = ctrla | xfer_count; | |
1021 | lli->ctrlb = ctrlb; | |
dc78baa2 | 1022 | |
ac803b56 | 1023 | desc->sg[i].len = xfer_count << src_width; |
dc78baa2 | 1024 | |
ac803b56 | 1025 | atdma_lli_chain(desc, i); |
dc78baa2 NF |
1026 | } |
1027 | ||
ac803b56 | 1028 | desc->total_len = len; |
bdf6c792 | 1029 | |
dc78baa2 | 1030 | /* set end-of-link to the last link descriptor of list*/ |
ac803b56 | 1031 | set_lli_eol(desc, i - 1); |
dc78baa2 | 1032 | |
ac803b56 | 1033 | return vchan_tx_prep(&atchan->vc, &desc->vd, flags); |
dc78baa2 NF |
1034 | |
1035 | err_desc_get: | |
ac803b56 | 1036 | atdma_desc_free(&desc->vd); |
dc78baa2 NF |
1037 | return NULL; |
1038 | } | |
1039 | ||
ac803b56 TA |
1040 | static int atdma_create_memset_lli(struct dma_chan *chan, |
1041 | struct atdma_sg *atdma_sg, | |
1042 | dma_addr_t psrc, dma_addr_t pdst, size_t len) | |
ce2a673d | 1043 | { |
ac803b56 TA |
1044 | struct at_dma *atdma = to_at_dma(chan->device); |
1045 | struct at_lli *lli; | |
ce2a673d | 1046 | size_t xfer_count; |
d8840a7e | 1047 | u32 ctrla = FIELD_PREP(ATC_SRC_WIDTH, 2) | FIELD_PREP(ATC_DST_WIDTH, 2); |
ce2a673d | 1048 | u32 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | |
d8840a7e TA |
1049 | FIELD_PREP(ATC_SRC_ADDR_MODE, ATC_SRC_ADDR_MODE_FIXED) | |
1050 | FIELD_PREP(ATC_DST_ADDR_MODE, ATC_DST_ADDR_MODE_INCR) | | |
1051 | FIELD_PREP(ATC_FC, ATC_FC_MEM2MEM); | |
ce2a673d MR |
1052 | |
1053 | xfer_count = len >> 2; | |
1054 | if (xfer_count > ATC_BTSIZE_MAX) { | |
ac803b56 TA |
1055 | dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__); |
1056 | return -EINVAL; | |
ce2a673d MR |
1057 | } |
1058 | ||
ac803b56 TA |
1059 | atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, GFP_NOWAIT, |
1060 | &atdma_sg->lli_phys); | |
1061 | if (!atdma_sg->lli) | |
1062 | return -ENOMEM; | |
1063 | lli = atdma_sg->lli; | |
ce2a673d | 1064 | |
ac803b56 TA |
1065 | lli->saddr = psrc; |
1066 | lli->daddr = pdst; | |
1067 | lli->ctrla = ctrla | xfer_count; | |
1068 | lli->ctrlb = ctrlb; | |
ce2a673d | 1069 | |
ac803b56 | 1070 | atdma_sg->len = len; |
ce2a673d | 1071 | |
ac803b56 | 1072 | return 0; |
ce2a673d MR |
1073 | } |
1074 | ||
4d112426 MR |
1075 | /** |
1076 | * atc_prep_dma_memset - prepare a memcpy operation | |
1077 | * @chan: the channel to prepare operation on | |
1078 | * @dest: operation virtual destination address | |
1079 | * @value: value to set memory buffer to | |
1080 | * @len: operation length | |
1081 | * @flags: tx descriptor status flags | |
1082 | */ | |
1083 | static struct dma_async_tx_descriptor * | |
1084 | atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, | |
1085 | size_t len, unsigned long flags) | |
1086 | { | |
ac803b56 | 1087 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
4d112426 | 1088 | struct at_dma *atdma = to_at_dma(chan->device); |
ce2a673d MR |
1089 | struct at_desc *desc; |
1090 | void __iomem *vaddr; | |
1091 | dma_addr_t paddr; | |
ceabe10c | 1092 | char fill_pattern; |
ac803b56 | 1093 | int ret; |
4d112426 | 1094 | |
2c5d7407 AB |
1095 | dev_vdbg(chan2dev(chan), "%s: d%pad v0x%x l0x%zx f0x%lx\n", __func__, |
1096 | &dest, value, len, flags); | |
4d112426 MR |
1097 | |
1098 | if (unlikely(!len)) { | |
1099 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); | |
1100 | return NULL; | |
1101 | } | |
1102 | ||
1103 | if (!is_dma_fill_aligned(chan->device, dest, 0, len)) { | |
1104 | dev_dbg(chan2dev(chan), "%s: buffer is not aligned\n", | |
1105 | __func__); | |
1106 | return NULL; | |
1107 | } | |
1108 | ||
247b4d83 | 1109 | vaddr = dma_pool_alloc(atdma->memset_pool, GFP_NOWAIT, &paddr); |
ce2a673d MR |
1110 | if (!vaddr) { |
1111 | dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", | |
4d112426 MR |
1112 | __func__); |
1113 | return NULL; | |
1114 | } | |
ceabe10c BW |
1115 | |
1116 | /* Only the first byte of value is to be used according to dmaengine */ | |
1117 | fill_pattern = (char)value; | |
1118 | ||
1119 | *(u32*)vaddr = (fill_pattern << 24) | | |
1120 | (fill_pattern << 16) | | |
1121 | (fill_pattern << 8) | | |
1122 | fill_pattern; | |
4d112426 | 1123 | |
ac803b56 TA |
1124 | desc = kzalloc(struct_size(desc, sg, 1), GFP_ATOMIC); |
1125 | if (!desc) | |
ce2a673d | 1126 | goto err_free_buffer; |
ac803b56 TA |
1127 | desc->sglen = 1; |
1128 | ||
1129 | ret = atdma_create_memset_lli(chan, desc->sg, paddr, dest, len); | |
1130 | if (ret) | |
1131 | goto err_free_desc; | |
4d112426 | 1132 | |
ce2a673d MR |
1133 | desc->memset_paddr = paddr; |
1134 | desc->memset_vaddr = vaddr; | |
1135 | desc->memset_buffer = true; | |
4d112426 | 1136 | |
4d112426 MR |
1137 | desc->total_len = len; |
1138 | ||
1139 | /* set end-of-link on the descriptor */ | |
ac803b56 | 1140 | set_lli_eol(desc, 0); |
4d112426 | 1141 | |
ac803b56 | 1142 | return vchan_tx_prep(&atchan->vc, &desc->vd, flags); |
4d112426 | 1143 | |
ac803b56 TA |
1144 | err_free_desc: |
1145 | kfree(desc); | |
ce2a673d MR |
1146 | err_free_buffer: |
1147 | dma_pool_free(atdma->memset_pool, vaddr, paddr); | |
4d112426 MR |
1148 | return NULL; |
1149 | } | |
1150 | ||
67d25f0d MR |
1151 | static struct dma_async_tx_descriptor * |
1152 | atc_prep_dma_memset_sg(struct dma_chan *chan, | |
1153 | struct scatterlist *sgl, | |
1154 | unsigned int sg_len, int value, | |
1155 | unsigned long flags) | |
1156 | { | |
1157 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1158 | struct at_dma *atdma = to_at_dma(chan->device); | |
ac803b56 | 1159 | struct at_desc *desc; |
67d25f0d MR |
1160 | struct scatterlist *sg; |
1161 | void __iomem *vaddr; | |
1162 | dma_addr_t paddr; | |
1163 | size_t total_len = 0; | |
1164 | int i; | |
ac803b56 | 1165 | int ret; |
67d25f0d MR |
1166 | |
1167 | dev_vdbg(chan2dev(chan), "%s: v0x%x l0x%zx f0x%lx\n", __func__, | |
1168 | value, sg_len, flags); | |
1169 | ||
1170 | if (unlikely(!sgl || !sg_len)) { | |
1171 | dev_dbg(chan2dev(chan), "%s: scatterlist is empty!\n", | |
1172 | __func__); | |
1173 | return NULL; | |
1174 | } | |
1175 | ||
247b4d83 | 1176 | vaddr = dma_pool_alloc(atdma->memset_pool, GFP_NOWAIT, &paddr); |
67d25f0d MR |
1177 | if (!vaddr) { |
1178 | dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", | |
1179 | __func__); | |
1180 | return NULL; | |
1181 | } | |
1182 | *(u32*)vaddr = value; | |
1183 | ||
ac803b56 TA |
1184 | desc = kzalloc(struct_size(desc, sg, sg_len), GFP_ATOMIC); |
1185 | if (!desc) | |
1186 | goto err_free_dma_buf; | |
1187 | desc->sglen = sg_len; | |
1188 | ||
67d25f0d MR |
1189 | for_each_sg(sgl, sg, sg_len, i) { |
1190 | dma_addr_t dest = sg_dma_address(sg); | |
1191 | size_t len = sg_dma_len(sg); | |
1192 | ||
2c5d7407 AB |
1193 | dev_vdbg(chan2dev(chan), "%s: d%pad, l0x%zx\n", |
1194 | __func__, &dest, len); | |
67d25f0d MR |
1195 | |
1196 | if (!is_dma_fill_aligned(chan->device, dest, 0, len)) { | |
1197 | dev_err(chan2dev(chan), "%s: buffer is not aligned\n", | |
1198 | __func__); | |
ac803b56 | 1199 | goto err_free_desc; |
67d25f0d MR |
1200 | } |
1201 | ||
ac803b56 TA |
1202 | ret = atdma_create_memset_lli(chan, &desc->sg[i], paddr, dest, |
1203 | len); | |
1204 | if (ret) | |
1205 | goto err_free_desc; | |
67d25f0d | 1206 | |
ac803b56 | 1207 | atdma_lli_chain(desc, i); |
67d25f0d MR |
1208 | total_len += len; |
1209 | } | |
1210 | ||
67d25f0d MR |
1211 | desc->memset_paddr = paddr; |
1212 | desc->memset_vaddr = vaddr; | |
1213 | desc->memset_buffer = true; | |
1214 | ||
ac803b56 | 1215 | desc->total_len = total_len; |
67d25f0d MR |
1216 | |
1217 | /* set end-of-link on the descriptor */ | |
ac803b56 | 1218 | set_lli_eol(desc, i - 1); |
67d25f0d | 1219 | |
ac803b56 | 1220 | return vchan_tx_prep(&atchan->vc, &desc->vd, flags); |
67d25f0d | 1221 | |
ac803b56 TA |
1222 | err_free_desc: |
1223 | atdma_desc_free(&desc->vd); | |
1224 | err_free_dma_buf: | |
1225 | dma_pool_free(atdma->memset_pool, vaddr, paddr); | |
67d25f0d MR |
1226 | return NULL; |
1227 | } | |
1228 | ||
808347f6 NF |
1229 | /** |
1230 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
1231 | * @chan: DMA channel | |
1232 | * @sgl: scatterlist to transfer to/from | |
1233 | * @sg_len: number of entries in @scatterlist | |
1234 | * @direction: DMA direction | |
1235 | * @flags: tx descriptor status flags | |
185ecb5f | 1236 | * @context: transaction context (ignored) |
808347f6 NF |
1237 | */ |
1238 | static struct dma_async_tx_descriptor * | |
1239 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 1240 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1241 | unsigned long flags, void *context) |
808347f6 | 1242 | { |
ac803b56 | 1243 | struct at_dma *atdma = to_at_dma(chan->device); |
808347f6 NF |
1244 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
1245 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 1246 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
ac803b56 | 1247 | struct at_desc *desc; |
808347f6 NF |
1248 | u32 ctrla; |
1249 | u32 ctrlb; | |
1250 | dma_addr_t reg; | |
1251 | unsigned int reg_width; | |
1252 | unsigned int mem_width; | |
1253 | unsigned int i; | |
1254 | struct scatterlist *sg; | |
1255 | size_t total_len = 0; | |
1256 | ||
cc52a10a NF |
1257 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
1258 | sg_len, | |
db8196df | 1259 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
808347f6 NF |
1260 | flags); |
1261 | ||
1262 | if (unlikely(!atslave || !sg_len)) { | |
c618a9be | 1263 | dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n"); |
808347f6 NF |
1264 | return NULL; |
1265 | } | |
1266 | ||
ac803b56 TA |
1267 | desc = kzalloc(struct_size(desc, sg, sg_len), GFP_ATOMIC); |
1268 | if (!desc) | |
1269 | return NULL; | |
1270 | desc->sglen = sg_len; | |
1271 | ||
d8840a7e TA |
1272 | ctrla = FIELD_PREP(ATC_SCSIZE, sconfig->src_maxburst) | |
1273 | FIELD_PREP(ATC_DCSIZE, sconfig->dst_maxburst); | |
ae14d4b5 | 1274 | ctrlb = ATC_IEN; |
808347f6 NF |
1275 | |
1276 | switch (direction) { | |
db8196df | 1277 | case DMA_MEM_TO_DEV: |
beeaa103 | 1278 | reg_width = convert_buswidth(sconfig->dst_addr_width); |
d8840a7e TA |
1279 | ctrla |= FIELD_PREP(ATC_DST_WIDTH, reg_width); |
1280 | ctrlb |= FIELD_PREP(ATC_DST_ADDR_MODE, | |
1281 | ATC_DST_ADDR_MODE_FIXED) | | |
1282 | FIELD_PREP(ATC_SRC_ADDR_MODE, ATC_SRC_ADDR_MODE_INCR) | | |
1283 | FIELD_PREP(ATC_FC, ATC_FC_MEM2PER) | | |
1284 | FIELD_PREP(ATC_SIF, atchan->mem_if) | | |
1285 | FIELD_PREP(ATC_DIF, atchan->per_if); | |
beeaa103 | 1286 | reg = sconfig->dst_addr; |
808347f6 | 1287 | for_each_sg(sgl, sg, sg_len, i) { |
ac803b56 TA |
1288 | struct atdma_sg *atdma_sg = &desc->sg[i]; |
1289 | struct at_lli *lli; | |
808347f6 NF |
1290 | u32 len; |
1291 | u32 mem; | |
1292 | ||
ac803b56 TA |
1293 | atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, |
1294 | GFP_NOWAIT, | |
1295 | &atdma_sg->lli_phys); | |
1296 | if (!atdma_sg->lli) | |
808347f6 | 1297 | goto err_desc_get; |
ac803b56 | 1298 | lli = atdma_sg->lli; |
808347f6 | 1299 | |
0f70e8ce | 1300 | mem = sg_dma_address(sg); |
808347f6 | 1301 | len = sg_dma_len(sg); |
c4567976 NF |
1302 | if (unlikely(!len)) { |
1303 | dev_dbg(chan2dev(chan), | |
1304 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
1305 | goto err; | |
1306 | } | |
808347f6 NF |
1307 | mem_width = 2; |
1308 | if (unlikely(mem & 3 || len & 3)) | |
1309 | mem_width = 0; | |
1310 | ||
ac803b56 TA |
1311 | lli->saddr = mem; |
1312 | lli->daddr = reg; | |
1313 | lli->ctrla = ctrla | | |
1314 | FIELD_PREP(ATC_SRC_WIDTH, mem_width) | | |
1315 | len >> mem_width; | |
1316 | lli->ctrlb = ctrlb; | |
808347f6 | 1317 | |
ac803b56 | 1318 | atdma_sg->len = len; |
808347f6 | 1319 | total_len += len; |
ac803b56 TA |
1320 | |
1321 | desc->sg[i].len = len; | |
1322 | atdma_lli_chain(desc, i); | |
808347f6 NF |
1323 | } |
1324 | break; | |
db8196df | 1325 | case DMA_DEV_TO_MEM: |
beeaa103 | 1326 | reg_width = convert_buswidth(sconfig->src_addr_width); |
d8840a7e TA |
1327 | ctrla |= FIELD_PREP(ATC_SRC_WIDTH, reg_width); |
1328 | ctrlb |= FIELD_PREP(ATC_DST_ADDR_MODE, ATC_DST_ADDR_MODE_INCR) | | |
1329 | FIELD_PREP(ATC_SRC_ADDR_MODE, | |
1330 | ATC_SRC_ADDR_MODE_FIXED) | | |
1331 | FIELD_PREP(ATC_FC, ATC_FC_PER2MEM) | | |
1332 | FIELD_PREP(ATC_SIF, atchan->per_if) | | |
1333 | FIELD_PREP(ATC_DIF, atchan->mem_if); | |
808347f6 | 1334 | |
beeaa103 | 1335 | reg = sconfig->src_addr; |
808347f6 | 1336 | for_each_sg(sgl, sg, sg_len, i) { |
ac803b56 TA |
1337 | struct atdma_sg *atdma_sg = &desc->sg[i]; |
1338 | struct at_lli *lli; | |
808347f6 NF |
1339 | u32 len; |
1340 | u32 mem; | |
1341 | ||
ac803b56 TA |
1342 | atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, |
1343 | GFP_NOWAIT, | |
1344 | &atdma_sg->lli_phys); | |
1345 | if (!atdma_sg->lli) | |
808347f6 | 1346 | goto err_desc_get; |
ac803b56 | 1347 | lli = atdma_sg->lli; |
808347f6 | 1348 | |
0f70e8ce | 1349 | mem = sg_dma_address(sg); |
808347f6 | 1350 | len = sg_dma_len(sg); |
c4567976 NF |
1351 | if (unlikely(!len)) { |
1352 | dev_dbg(chan2dev(chan), | |
1353 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
1354 | goto err; | |
1355 | } | |
808347f6 NF |
1356 | mem_width = 2; |
1357 | if (unlikely(mem & 3 || len & 3)) | |
1358 | mem_width = 0; | |
1359 | ||
ac803b56 TA |
1360 | lli->saddr = reg; |
1361 | lli->daddr = mem; | |
1362 | lli->ctrla = ctrla | | |
1363 | FIELD_PREP(ATC_DST_WIDTH, mem_width) | | |
1364 | len >> reg_width; | |
1365 | lli->ctrlb = ctrlb; | |
808347f6 | 1366 | |
ac803b56 | 1367 | desc->sg[i].len = len; |
808347f6 | 1368 | total_len += len; |
ac803b56 TA |
1369 | |
1370 | atdma_lli_chain(desc, i); | |
808347f6 NF |
1371 | } |
1372 | break; | |
1373 | default: | |
1374 | return NULL; | |
1375 | } | |
1376 | ||
1377 | /* set end-of-link to the last link descriptor of list*/ | |
ac803b56 | 1378 | set_lli_eol(desc, i - 1); |
bdf6c792 | 1379 | |
ac803b56 | 1380 | desc->total_len = total_len; |
808347f6 | 1381 | |
ac803b56 | 1382 | return vchan_tx_prep(&atchan->vc, &desc->vd, flags); |
808347f6 NF |
1383 | |
1384 | err_desc_get: | |
1385 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
c4567976 | 1386 | err: |
ac803b56 | 1387 | atdma_desc_free(&desc->vd); |
808347f6 NF |
1388 | return NULL; |
1389 | } | |
1390 | ||
21e3cdb0 | 1391 | /* |
53830cc7 NF |
1392 | * atc_dma_cyclic_check_values |
1393 | * Check for too big/unaligned periods and unaligned DMA buffer | |
1394 | */ | |
1395 | static int | |
1396 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
0e7264cc | 1397 | size_t period_len) |
53830cc7 NF |
1398 | { |
1399 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
1400 | goto err_out; | |
1401 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1402 | goto err_out; | |
1403 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1404 | goto err_out; | |
53830cc7 NF |
1405 | |
1406 | return 0; | |
1407 | ||
1408 | err_out: | |
1409 | return -EINVAL; | |
1410 | } | |
1411 | ||
21e3cdb0 | 1412 | /* |
d73111c6 | 1413 | * atc_dma_cyclic_fill_desc - Fill one period descriptor |
53830cc7 NF |
1414 | */ |
1415 | static int | |
beeaa103 | 1416 | atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, |
ac803b56 | 1417 | unsigned int i, dma_addr_t buf_addr, |
beeaa103 NF |
1418 | unsigned int reg_width, size_t period_len, |
1419 | enum dma_transfer_direction direction) | |
53830cc7 | 1420 | { |
ac803b56 | 1421 | struct at_dma *atdma = to_at_dma(chan->device); |
beeaa103 | 1422 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
beeaa103 | 1423 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
ac803b56 TA |
1424 | struct atdma_sg *atdma_sg = &desc->sg[i]; |
1425 | struct at_lli *lli; | |
53830cc7 | 1426 | |
ac803b56 TA |
1427 | atdma_sg->lli = dma_pool_alloc(atdma->lli_pool, GFP_ATOMIC, |
1428 | &atdma_sg->lli_phys); | |
1429 | if (!atdma_sg->lli) | |
1430 | return -ENOMEM; | |
1431 | lli = atdma_sg->lli; | |
53830cc7 NF |
1432 | |
1433 | switch (direction) { | |
db8196df | 1434 | case DMA_MEM_TO_DEV: |
ac803b56 TA |
1435 | lli->saddr = buf_addr + (period_len * i); |
1436 | lli->daddr = sconfig->dst_addr; | |
1437 | lli->ctrlb = FIELD_PREP(ATC_DST_ADDR_MODE, | |
1438 | ATC_DST_ADDR_MODE_FIXED) | | |
1439 | FIELD_PREP(ATC_SRC_ADDR_MODE, | |
1440 | ATC_SRC_ADDR_MODE_INCR) | | |
1441 | FIELD_PREP(ATC_FC, ATC_FC_MEM2PER) | | |
1442 | FIELD_PREP(ATC_SIF, atchan->mem_if) | | |
1443 | FIELD_PREP(ATC_DIF, atchan->per_if); | |
1444 | ||
53830cc7 NF |
1445 | break; |
1446 | ||
db8196df | 1447 | case DMA_DEV_TO_MEM: |
ac803b56 TA |
1448 | lli->saddr = sconfig->src_addr; |
1449 | lli->daddr = buf_addr + (period_len * i); | |
1450 | lli->ctrlb = FIELD_PREP(ATC_DST_ADDR_MODE, | |
1451 | ATC_DST_ADDR_MODE_INCR) | | |
1452 | FIELD_PREP(ATC_SRC_ADDR_MODE, | |
1453 | ATC_SRC_ADDR_MODE_FIXED) | | |
1454 | FIELD_PREP(ATC_FC, ATC_FC_PER2MEM) | | |
1455 | FIELD_PREP(ATC_SIF, atchan->per_if) | | |
1456 | FIELD_PREP(ATC_DIF, atchan->mem_if); | |
53830cc7 NF |
1457 | break; |
1458 | ||
1459 | default: | |
1460 | return -EINVAL; | |
1461 | } | |
1462 | ||
ac803b56 TA |
1463 | lli->ctrla = FIELD_PREP(ATC_SCSIZE, sconfig->src_maxburst) | |
1464 | FIELD_PREP(ATC_DCSIZE, sconfig->dst_maxburst) | | |
1465 | FIELD_PREP(ATC_DST_WIDTH, reg_width) | | |
1466 | FIELD_PREP(ATC_SRC_WIDTH, reg_width) | | |
1467 | period_len >> reg_width; | |
1468 | desc->sg[i].len = period_len; | |
1469 | ||
53830cc7 NF |
1470 | return 0; |
1471 | } | |
1472 | ||
1473 | /** | |
1474 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
1475 | * @chan: the DMA channel to prepare | |
1476 | * @buf_addr: physical DMA address where the buffer starts | |
1477 | * @buf_len: total number of bytes for the entire buffer | |
1478 | * @period_len: number of bytes for each period | |
1479 | * @direction: transfer direction, to or from device | |
ec8b5e48 | 1480 | * @flags: tx descriptor status flags |
53830cc7 NF |
1481 | */ |
1482 | static struct dma_async_tx_descriptor * | |
1483 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 1484 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 1485 | unsigned long flags) |
53830cc7 NF |
1486 | { |
1487 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1488 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 1489 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
ac803b56 | 1490 | struct at_desc *desc; |
53830cc7 | 1491 | unsigned long was_cyclic; |
beeaa103 | 1492 | unsigned int reg_width; |
53830cc7 NF |
1493 | unsigned int periods = buf_len / period_len; |
1494 | unsigned int i; | |
1495 | ||
2c5d7407 | 1496 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@%pad - %d (%d/%d)\n", |
db8196df | 1497 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
2c5d7407 | 1498 | &buf_addr, |
53830cc7 NF |
1499 | periods, buf_len, period_len); |
1500 | ||
1501 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
1502 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
1503 | return NULL; | |
1504 | } | |
1505 | ||
1506 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
1507 | if (was_cyclic) { | |
1508 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
1509 | return NULL; | |
1510 | } | |
1511 | ||
0e7264cc AS |
1512 | if (unlikely(!is_slave_direction(direction))) |
1513 | goto err_out; | |
1514 | ||
62355887 | 1515 | if (direction == DMA_MEM_TO_DEV) |
beeaa103 NF |
1516 | reg_width = convert_buswidth(sconfig->dst_addr_width); |
1517 | else | |
1518 | reg_width = convert_buswidth(sconfig->src_addr_width); | |
1519 | ||
53830cc7 | 1520 | /* Check for too big/unaligned periods and unaligned DMA buffer */ |
0e7264cc | 1521 | if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len)) |
53830cc7 NF |
1522 | goto err_out; |
1523 | ||
ac803b56 TA |
1524 | desc = kzalloc(struct_size(desc, sg, periods), GFP_ATOMIC); |
1525 | if (!desc) | |
1526 | goto err_out; | |
1527 | desc->sglen = periods; | |
1528 | ||
53830cc7 NF |
1529 | /* build cyclic linked list */ |
1530 | for (i = 0; i < periods; i++) { | |
beeaa103 NF |
1531 | if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr, |
1532 | reg_width, period_len, direction)) | |
ac803b56 TA |
1533 | goto err_fill_desc; |
1534 | atdma_lli_chain(desc, i); | |
53830cc7 | 1535 | } |
ac803b56 | 1536 | desc->total_len = buf_len; |
53830cc7 | 1537 | /* lets make a cyclic list */ |
ac803b56 | 1538 | desc->sg[i - 1].lli->dscr = desc->sg[0].lli_phys; |
53830cc7 | 1539 | |
ac803b56 | 1540 | return vchan_tx_prep(&atchan->vc, &desc->vd, flags); |
53830cc7 | 1541 | |
ac803b56 TA |
1542 | err_fill_desc: |
1543 | atdma_desc_free(&desc->vd); | |
53830cc7 NF |
1544 | err_out: |
1545 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1546 | return NULL; | |
1547 | } | |
1548 | ||
4facfe7f MR |
1549 | static int atc_config(struct dma_chan *chan, |
1550 | struct dma_slave_config *sconfig) | |
beeaa103 NF |
1551 | { |
1552 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1553 | ||
4facfe7f MR |
1554 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
1555 | ||
beeaa103 NF |
1556 | /* Check if it is chan is configured for slave transfers */ |
1557 | if (!chan->private) | |
1558 | return -EINVAL; | |
1559 | ||
1560 | memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig)); | |
1561 | ||
1562 | convert_burst(&atchan->dma_sconfig.src_maxburst); | |
1563 | convert_burst(&atchan->dma_sconfig.dst_maxburst); | |
1564 | ||
1565 | return 0; | |
1566 | } | |
1567 | ||
4facfe7f MR |
1568 | static int atc_pause(struct dma_chan *chan) |
1569 | { | |
1570 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1571 | struct at_dma *atdma = to_at_dma(chan->device); | |
ac803b56 | 1572 | int chan_id = atchan->vc.chan.chan_id; |
4facfe7f | 1573 | unsigned long flags; |
53830cc7 | 1574 | |
4facfe7f MR |
1575 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
1576 | ||
ac803b56 | 1577 | spin_lock_irqsave(&atchan->vc.lock, flags); |
4facfe7f MR |
1578 | |
1579 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); | |
1580 | set_bit(ATC_IS_PAUSED, &atchan->status); | |
1581 | ||
ac803b56 | 1582 | spin_unlock_irqrestore(&atchan->vc.lock, flags); |
4facfe7f MR |
1583 | |
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | static int atc_resume(struct dma_chan *chan) | |
808347f6 NF |
1588 | { |
1589 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1590 | struct at_dma *atdma = to_at_dma(chan->device); | |
ac803b56 | 1591 | int chan_id = atchan->vc.chan.chan_id; |
d8cb04b0 | 1592 | unsigned long flags; |
23b5e3ad | 1593 | |
4facfe7f | 1594 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
c3635c78 | 1595 | |
4facfe7f MR |
1596 | if (!atc_chan_is_paused(atchan)) |
1597 | return 0; | |
808347f6 | 1598 | |
ac803b56 | 1599 | spin_lock_irqsave(&atchan->vc.lock, flags); |
808347f6 | 1600 | |
4facfe7f MR |
1601 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
1602 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
808347f6 | 1603 | |
ac803b56 | 1604 | spin_unlock_irqrestore(&atchan->vc.lock, flags); |
808347f6 | 1605 | |
4facfe7f MR |
1606 | return 0; |
1607 | } | |
c3635c78 | 1608 | |
4facfe7f MR |
1609 | static int atc_terminate_all(struct dma_chan *chan) |
1610 | { | |
1611 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1612 | struct at_dma *atdma = to_at_dma(chan->device); | |
ac803b56 | 1613 | int chan_id = atchan->vc.chan.chan_id; |
4facfe7f | 1614 | unsigned long flags; |
23b5e3ad | 1615 | |
ac803b56 TA |
1616 | LIST_HEAD(list); |
1617 | ||
4facfe7f | 1618 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
23b5e3ad | 1619 | |
4facfe7f MR |
1620 | /* |
1621 | * This is only called when something went wrong elsewhere, so | |
1622 | * we don't really care about the data. Just disable the | |
1623 | * channel. We still have to poll the channel enable bit due | |
1624 | * to AHB/HSB limitations. | |
1625 | */ | |
ac803b56 | 1626 | spin_lock_irqsave(&atchan->vc.lock, flags); |
23b5e3ad | 1627 | |
4facfe7f MR |
1628 | /* disabling channel: must also remove suspend state */ |
1629 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
23b5e3ad | 1630 | |
4facfe7f MR |
1631 | /* confirm that this channel is disabled */ |
1632 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
1633 | cpu_relax(); | |
23b5e3ad | 1634 | |
ac803b56 TA |
1635 | if (atchan->desc) { |
1636 | vchan_terminate_vdesc(&atchan->desc->vd); | |
1637 | atchan->desc = NULL; | |
1638 | } | |
1639 | ||
1640 | vchan_get_all_descriptors(&atchan->vc, &list); | |
4facfe7f | 1641 | |
4facfe7f MR |
1642 | clear_bit(ATC_IS_PAUSED, &atchan->status); |
1643 | /* if channel dedicated to cyclic operations, free it */ | |
1644 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1645 | ||
ac803b56 TA |
1646 | spin_unlock_irqrestore(&atchan->vc.lock, flags); |
1647 | ||
1648 | vchan_dma_desc_free_list(&atchan->vc, &list); | |
6e5ad28d | 1649 | |
c3635c78 | 1650 | return 0; |
808347f6 NF |
1651 | } |
1652 | ||
dc78baa2 | 1653 | /** |
07934481 | 1654 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
1655 | * @chan: DMA channel |
1656 | * @cookie: transaction identifier to check status of | |
07934481 | 1657 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 1658 | * |
07934481 | 1659 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
1660 | * internal state and can be used with dma_async_is_complete() to check |
1661 | * the status of multiple cookies without re-checking hardware state. | |
1662 | */ | |
1663 | static enum dma_status | |
07934481 | 1664 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 1665 | dma_cookie_t cookie, |
07934481 | 1666 | struct dma_tx_state *txstate) |
dc78baa2 NF |
1667 | { |
1668 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1669 | unsigned long flags; |
f5d79afa TA |
1670 | enum dma_status dma_status; |
1671 | u32 residue; | |
1672 | int ret; | |
dc78baa2 | 1673 | |
f5d79afa TA |
1674 | dma_status = dma_cookie_status(chan, cookie, txstate); |
1675 | if (dma_status == DMA_COMPLETE || !txstate) | |
1676 | return dma_status; | |
dc78baa2 | 1677 | |
ac803b56 TA |
1678 | spin_lock_irqsave(&atchan->vc.lock, flags); |
1679 | /* Get number of bytes left in the active transactions */ | |
91617bf6 | 1680 | ret = atc_get_residue(chan, cookie, &residue); |
ac803b56 | 1681 | spin_unlock_irqrestore(&atchan->vc.lock, flags); |
dc78baa2 | 1682 | |
f5d79afa | 1683 | if (unlikely(ret < 0)) { |
d48de6f1 ES |
1684 | dev_vdbg(chan2dev(chan), "get residual bytes error\n"); |
1685 | return DMA_ERROR; | |
c3dbc60c | 1686 | } else { |
f5d79afa | 1687 | dma_set_residue(txstate, residue); |
c3dbc60c | 1688 | } |
23b5e3ad | 1689 | |
f5d79afa TA |
1690 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %u\n", |
1691 | dma_status, cookie, residue); | |
dc78baa2 | 1692 | |
f5d79afa | 1693 | return dma_status; |
dc78baa2 NF |
1694 | } |
1695 | ||
dc78baa2 NF |
1696 | static void atc_issue_pending(struct dma_chan *chan) |
1697 | { | |
fcd37565 | 1698 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
fcd37565 | 1699 | unsigned long flags; |
dc78baa2 | 1700 | |
ac803b56 TA |
1701 | spin_lock_irqsave(&atchan->vc.lock, flags); |
1702 | if (vchan_issue_pending(&atchan->vc) && !atchan->desc) { | |
1703 | if (!(atc_chan_is_enabled(atchan))) | |
1704 | atc_dostart(atchan); | |
1705 | } | |
1706 | spin_unlock_irqrestore(&atchan->vc.lock, flags); | |
dc78baa2 NF |
1707 | } |
1708 | ||
1709 | /** | |
1710 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1711 | * @chan: allocate descriptor resources for this channel | |
dc78baa2 NF |
1712 | * |
1713 | * return - the number of allocated descriptors | |
1714 | */ | |
1715 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1716 | { | |
1717 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1718 | struct at_dma *atdma = to_at_dma(chan->device); | |
808347f6 | 1719 | struct at_dma_slave *atslave; |
808347f6 | 1720 | u32 cfg; |
dc78baa2 NF |
1721 | |
1722 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1723 | ||
1724 | /* ASSERT: channel is idle */ | |
1725 | if (atc_chan_is_enabled(atchan)) { | |
1726 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1727 | return -EIO; | |
1728 | } | |
1729 | ||
808347f6 NF |
1730 | cfg = ATC_DEFAULT_CFG; |
1731 | ||
1732 | atslave = chan->private; | |
1733 | if (atslave) { | |
1734 | /* | |
1735 | * We need controller-specific data to set up slave | |
1736 | * transfers. | |
1737 | */ | |
1c1114d8 | 1738 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_device.dev); |
808347f6 | 1739 | |
ea7e7906 | 1740 | /* if cfg configuration specified take it instead of default */ |
808347f6 NF |
1741 | if (atslave->cfg) |
1742 | cfg = atslave->cfg; | |
1743 | } | |
1744 | ||
dc78baa2 | 1745 | /* channel parameters */ |
808347f6 | 1746 | channel_writel(atchan, CFG, cfg); |
dc78baa2 | 1747 | |
ac803b56 | 1748 | return 0; |
dc78baa2 NF |
1749 | } |
1750 | ||
1751 | /** | |
1752 | * atc_free_chan_resources - free all channel resources | |
1753 | * @chan: DMA channel | |
1754 | */ | |
1755 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1756 | { | |
1757 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
dc78baa2 | 1758 | |
dc78baa2 NF |
1759 | BUG_ON(atc_chan_is_enabled(atchan)); |
1760 | ||
ac803b56 | 1761 | vchan_free_chan_resources(to_virt_chan(chan)); |
53830cc7 | 1762 | atchan->status = 0; |
dc78baa2 | 1763 | |
98f5f932 RG |
1764 | /* |
1765 | * Free atslave allocated in at_dma_xlate() | |
1766 | */ | |
1767 | kfree(chan->private); | |
1768 | chan->private = NULL; | |
1769 | ||
dc78baa2 NF |
1770 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); |
1771 | } | |
1772 | ||
bbe89c8e LD |
1773 | #ifdef CONFIG_OF |
1774 | static bool at_dma_filter(struct dma_chan *chan, void *slave) | |
1775 | { | |
1776 | struct at_dma_slave *atslave = slave; | |
1777 | ||
1778 | if (atslave->dma_dev == chan->device->dev) { | |
1779 | chan->private = atslave; | |
1780 | return true; | |
1781 | } else { | |
1782 | return false; | |
1783 | } | |
1784 | } | |
1785 | ||
1786 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1787 | struct of_dma *of_dma) | |
1788 | { | |
1789 | struct dma_chan *chan; | |
1790 | struct at_dma_chan *atchan; | |
1791 | struct at_dma_slave *atslave; | |
1792 | dma_cap_mask_t mask; | |
1793 | unsigned int per_id; | |
1794 | struct platform_device *dmac_pdev; | |
1795 | ||
1796 | if (dma_spec->args_count != 2) | |
1797 | return NULL; | |
1798 | ||
1799 | dmac_pdev = of_find_device_by_node(dma_spec->np); | |
0cef8e2c YK |
1800 | if (!dmac_pdev) |
1801 | return NULL; | |
bbe89c8e LD |
1802 | |
1803 | dma_cap_zero(mask); | |
1804 | dma_cap_set(DMA_SLAVE, mask); | |
1805 | ||
a6e7f19c | 1806 | atslave = kmalloc(sizeof(*atslave), GFP_KERNEL); |
3832b78b YK |
1807 | if (!atslave) { |
1808 | put_device(&dmac_pdev->dev); | |
bbe89c8e | 1809 | return NULL; |
3832b78b | 1810 | } |
62971b29 | 1811 | |
d8840a7e | 1812 | atslave->cfg = ATC_DST_H2SEL | ATC_SRC_H2SEL; |
bbe89c8e LD |
1813 | /* |
1814 | * We can fill both SRC_PER and DST_PER, one of these fields will be | |
1815 | * ignored depending on DMA transfer direction. | |
1816 | */ | |
62971b29 | 1817 | per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK; |
d8840a7e | 1818 | atslave->cfg |= ATC_DST_PER_ID(per_id) | ATC_SRC_PER_ID(per_id); |
62971b29 LD |
1819 | /* |
1820 | * We have to translate the value we get from the device tree since | |
1821 | * the half FIFO configuration value had to be 0 to keep backward | |
1822 | * compatibility. | |
1823 | */ | |
1824 | switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) { | |
1825 | case AT91_DMA_CFG_FIFOCFG_ALAP: | |
d8840a7e TA |
1826 | atslave->cfg |= FIELD_PREP(ATC_FIFOCFG, |
1827 | ATC_FIFOCFG_LARGESTBURST); | |
62971b29 LD |
1828 | break; |
1829 | case AT91_DMA_CFG_FIFOCFG_ASAP: | |
d8840a7e TA |
1830 | atslave->cfg |= FIELD_PREP(ATC_FIFOCFG, |
1831 | ATC_FIFOCFG_ENOUGHSPACE); | |
62971b29 LD |
1832 | break; |
1833 | case AT91_DMA_CFG_FIFOCFG_HALF: | |
1834 | default: | |
d8840a7e | 1835 | atslave->cfg |= FIELD_PREP(ATC_FIFOCFG, ATC_FIFOCFG_HALFFIFO); |
62971b29 | 1836 | } |
bbe89c8e LD |
1837 | atslave->dma_dev = &dmac_pdev->dev; |
1838 | ||
1839 | chan = dma_request_channel(mask, at_dma_filter, atslave); | |
3832b78b YK |
1840 | if (!chan) { |
1841 | put_device(&dmac_pdev->dev); | |
e097eb74 | 1842 | kfree(atslave); |
bbe89c8e | 1843 | return NULL; |
3832b78b | 1844 | } |
bbe89c8e LD |
1845 | |
1846 | atchan = to_at_dma_chan(chan); | |
1847 | atchan->per_if = dma_spec->args[0] & 0xff; | |
1848 | atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff; | |
1849 | ||
1850 | return chan; | |
1851 | } | |
1852 | #else | |
1853 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1854 | struct of_dma *of_dma) | |
1855 | { | |
1856 | return NULL; | |
1857 | } | |
1858 | #endif | |
dc78baa2 NF |
1859 | |
1860 | /*-- Module Management -----------------------------------------------*/ | |
1861 | ||
02f88be9 NF |
1862 | /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ |
1863 | static struct at_dma_platform_data at91sam9rl_config = { | |
1864 | .nr_channels = 2, | |
1865 | }; | |
1866 | static struct at_dma_platform_data at91sam9g45_config = { | |
1867 | .nr_channels = 8, | |
1868 | }; | |
1869 | ||
c5115953 NF |
1870 | #if defined(CONFIG_OF) |
1871 | static const struct of_device_id atmel_dma_dt_ids[] = { | |
1872 | { | |
1873 | .compatible = "atmel,at91sam9rl-dma", | |
02f88be9 | 1874 | .data = &at91sam9rl_config, |
c5115953 NF |
1875 | }, { |
1876 | .compatible = "atmel,at91sam9g45-dma", | |
02f88be9 | 1877 | .data = &at91sam9g45_config, |
dcc81734 NF |
1878 | }, { |
1879 | /* sentinel */ | |
1880 | } | |
c5115953 NF |
1881 | }; |
1882 | ||
1883 | MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); | |
1884 | #endif | |
1885 | ||
0ab88a01 | 1886 | static const struct platform_device_id atdma_devtypes[] = { |
67348450 NF |
1887 | { |
1888 | .name = "at91sam9rl_dma", | |
02f88be9 | 1889 | .driver_data = (unsigned long) &at91sam9rl_config, |
67348450 NF |
1890 | }, { |
1891 | .name = "at91sam9g45_dma", | |
02f88be9 | 1892 | .driver_data = (unsigned long) &at91sam9g45_config, |
67348450 NF |
1893 | }, { |
1894 | /* sentinel */ | |
1895 | } | |
1896 | }; | |
1897 | ||
7fd63ccd | 1898 | static inline const struct at_dma_platform_data * __init at_dma_get_driver_data( |
02f88be9 | 1899 | struct platform_device *pdev) |
c5115953 NF |
1900 | { |
1901 | if (pdev->dev.of_node) { | |
1902 | const struct of_device_id *match; | |
1903 | match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); | |
1904 | if (match == NULL) | |
02f88be9 NF |
1905 | return NULL; |
1906 | return match->data; | |
c5115953 | 1907 | } |
02f88be9 NF |
1908 | return (struct at_dma_platform_data *) |
1909 | platform_get_device_id(pdev)->driver_data; | |
c5115953 NF |
1910 | } |
1911 | ||
dc78baa2 NF |
1912 | /** |
1913 | * at_dma_off - disable DMA controller | |
1914 | * @atdma: the Atmel HDAMC device | |
1915 | */ | |
1916 | static void at_dma_off(struct at_dma *atdma) | |
1917 | { | |
1918 | dma_writel(atdma, EN, 0); | |
1919 | ||
1920 | /* disable all interrupts */ | |
1921 | dma_writel(atdma, EBCIDR, -1L); | |
1922 | ||
1923 | /* confirm that all channels are disabled */ | |
1924 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1925 | cpu_relax(); | |
1926 | } | |
1927 | ||
1928 | static int __init at_dma_probe(struct platform_device *pdev) | |
1929 | { | |
dc78baa2 | 1930 | struct at_dma *atdma; |
dc78baa2 NF |
1931 | int irq; |
1932 | int err; | |
1933 | int i; | |
7fd63ccd | 1934 | const struct at_dma_platform_data *plat_dat; |
67348450 | 1935 | |
02f88be9 NF |
1936 | /* setup platform data for each SoC */ |
1937 | dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); | |
5abecfa5 | 1938 | dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask); |
02f88be9 | 1939 | dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); |
4d112426 | 1940 | dma_cap_set(DMA_MEMSET, at91sam9g45_config.cap_mask); |
67d25f0d | 1941 | dma_cap_set(DMA_MEMSET_SG, at91sam9g45_config.cap_mask); |
4d112426 | 1942 | dma_cap_set(DMA_PRIVATE, at91sam9g45_config.cap_mask); |
02f88be9 | 1943 | dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); |
67348450 NF |
1944 | |
1945 | /* get DMA parameters from controller type */ | |
02f88be9 NF |
1946 | plat_dat = at_dma_get_driver_data(pdev); |
1947 | if (!plat_dat) | |
1948 | return -ENODEV; | |
dc78baa2 | 1949 | |
5f1d429b TA |
1950 | atdma = devm_kzalloc(&pdev->dev, |
1951 | struct_size(atdma, chan, plat_dat->nr_channels), | |
1952 | GFP_KERNEL); | |
1953 | if (!atdma) | |
1954 | return -ENOMEM; | |
1955 | ||
8bfe4a61 TA |
1956 | atdma->regs = devm_platform_ioremap_resource(pdev, 0); |
1957 | if (IS_ERR(atdma->regs)) | |
1958 | return PTR_ERR(atdma->regs); | |
dc78baa2 NF |
1959 | |
1960 | irq = platform_get_irq(pdev, 0); | |
1961 | if (irq < 0) | |
1962 | return irq; | |
1963 | ||
67348450 | 1964 | /* discover transaction capabilities */ |
1c1114d8 | 1965 | atdma->dma_device.cap_mask = plat_dat->cap_mask; |
02f88be9 | 1966 | atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; |
dc78baa2 | 1967 | |
4c15a4c7 | 1968 | atdma->clk = devm_clk_get(&pdev->dev, "dma_clk"); |
8bfe4a61 TA |
1969 | if (IS_ERR(atdma->clk)) |
1970 | return PTR_ERR(atdma->clk); | |
1971 | ||
f784d9c9 BB |
1972 | err = clk_prepare_enable(atdma->clk); |
1973 | if (err) | |
4c15a4c7 | 1974 | return err; |
dc78baa2 NF |
1975 | |
1976 | /* force dma off, just in case */ | |
1977 | at_dma_off(atdma); | |
1978 | ||
1979 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1980 | if (err) | |
1981 | goto err_irq; | |
1982 | ||
1983 | platform_set_drvdata(pdev, atdma); | |
1984 | ||
1985 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
ac803b56 TA |
1986 | atdma->lli_pool = dma_pool_create("at_hdmac_lli_pool", |
1987 | &pdev->dev, sizeof(struct at_lli), | |
1988 | 4 /* word alignment */, 0); | |
1989 | if (!atdma->lli_pool) { | |
1990 | dev_err(&pdev->dev, "Unable to allocate DMA LLI descriptor pool\n"); | |
dc78baa2 | 1991 | err = -ENOMEM; |
4d112426 MR |
1992 | goto err_desc_pool_create; |
1993 | } | |
1994 | ||
1995 | /* create a pool of consistent memory blocks for memset blocks */ | |
1996 | atdma->memset_pool = dma_pool_create("at_hdmac_memset_pool", | |
1997 | &pdev->dev, sizeof(int), 4, 0); | |
1998 | if (!atdma->memset_pool) { | |
1999 | dev_err(&pdev->dev, "No memory for memset dma pool\n"); | |
2000 | err = -ENOMEM; | |
2001 | goto err_memset_pool_create; | |
dc78baa2 NF |
2002 | } |
2003 | ||
2004 | /* clear any pending interrupt */ | |
2005 | while (dma_readl(atdma, EBCISR)) | |
2006 | cpu_relax(); | |
2007 | ||
2008 | /* initialize channels related values */ | |
1c1114d8 | 2009 | INIT_LIST_HEAD(&atdma->dma_device.channels); |
02f88be9 | 2010 | for (i = 0; i < plat_dat->nr_channels; i++) { |
dc78baa2 NF |
2011 | struct at_dma_chan *atchan = &atdma->chan[i]; |
2012 | ||
bbe89c8e LD |
2013 | atchan->mem_if = AT_DMA_MEM_IF; |
2014 | atchan->per_if = AT_DMA_PER_IF; | |
dc78baa2 NF |
2015 | |
2016 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
dc78baa2 NF |
2017 | atchan->mask = 1 << i; |
2018 | ||
ac803b56 TA |
2019 | atchan->atdma = atdma; |
2020 | atchan->vc.desc_free = atdma_desc_free; | |
2021 | vchan_init(&atchan->vc, &atdma->dma_device); | |
bda3a47c | 2022 | atc_enable_chan_irq(atdma, i); |
dc78baa2 NF |
2023 | } |
2024 | ||
2025 | /* set base routines */ | |
1c1114d8 TA |
2026 | atdma->dma_device.device_alloc_chan_resources = atc_alloc_chan_resources; |
2027 | atdma->dma_device.device_free_chan_resources = atc_free_chan_resources; | |
2028 | atdma->dma_device.device_tx_status = atc_tx_status; | |
2029 | atdma->dma_device.device_issue_pending = atc_issue_pending; | |
2030 | atdma->dma_device.dev = &pdev->dev; | |
dc78baa2 NF |
2031 | |
2032 | /* set prep routines based on capability */ | |
1c1114d8 TA |
2033 | if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_device.cap_mask)) |
2034 | atdma->dma_device.device_prep_interleaved_dma = atc_prep_dma_interleaved; | |
5abecfa5 | 2035 | |
1c1114d8 TA |
2036 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_device.cap_mask)) |
2037 | atdma->dma_device.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
dc78baa2 | 2038 | |
1c1114d8 TA |
2039 | if (dma_has_cap(DMA_MEMSET, atdma->dma_device.cap_mask)) { |
2040 | atdma->dma_device.device_prep_dma_memset = atc_prep_dma_memset; | |
2041 | atdma->dma_device.device_prep_dma_memset_sg = atc_prep_dma_memset_sg; | |
2042 | atdma->dma_device.fill_align = DMAENGINE_ALIGN_4_BYTES; | |
4d112426 MR |
2043 | } |
2044 | ||
1c1114d8 TA |
2045 | if (dma_has_cap(DMA_SLAVE, atdma->dma_device.cap_mask)) { |
2046 | atdma->dma_device.device_prep_slave_sg = atc_prep_slave_sg; | |
d7db8080 | 2047 | /* controller can do slave DMA: can trigger cyclic transfers */ |
1c1114d8 TA |
2048 | dma_cap_set(DMA_CYCLIC, atdma->dma_device.cap_mask); |
2049 | atdma->dma_device.device_prep_dma_cyclic = atc_prep_dma_cyclic; | |
2050 | atdma->dma_device.device_config = atc_config; | |
2051 | atdma->dma_device.device_pause = atc_pause; | |
2052 | atdma->dma_device.device_resume = atc_resume; | |
2053 | atdma->dma_device.device_terminate_all = atc_terminate_all; | |
2054 | atdma->dma_device.src_addr_widths = ATC_DMA_BUSWIDTHS; | |
2055 | atdma->dma_device.dst_addr_widths = ATC_DMA_BUSWIDTHS; | |
2056 | atdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
2057 | atdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
d7db8080 | 2058 | } |
808347f6 | 2059 | |
dc78baa2 NF |
2060 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
2061 | ||
c678fa66 | 2062 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n", |
1c1114d8 TA |
2063 | dma_has_cap(DMA_MEMCPY, atdma->dma_device.cap_mask) ? "cpy " : "", |
2064 | dma_has_cap(DMA_MEMSET, atdma->dma_device.cap_mask) ? "set " : "", | |
2065 | dma_has_cap(DMA_SLAVE, atdma->dma_device.cap_mask) ? "slave " : "", | |
02f88be9 | 2066 | plat_dat->nr_channels); |
dc78baa2 | 2067 | |
1c1114d8 | 2068 | err = dma_async_device_register(&atdma->dma_device); |
c47e6403 TA |
2069 | if (err) { |
2070 | dev_err(&pdev->dev, "Unable to register: %d.\n", err); | |
2071 | goto err_dma_async_device_register; | |
2072 | } | |
dc78baa2 | 2073 | |
bbe89c8e LD |
2074 | /* |
2075 | * Do not return an error if the dmac node is not present in order to | |
2076 | * not break the existing way of requesting channel with | |
2077 | * dma_request_channel(). | |
2078 | */ | |
2079 | if (pdev->dev.of_node) { | |
2080 | err = of_dma_controller_register(pdev->dev.of_node, | |
2081 | at_dma_xlate, atdma); | |
2082 | if (err) { | |
2083 | dev_err(&pdev->dev, "could not register of_dma_controller\n"); | |
2084 | goto err_of_dma_controller_register; | |
2085 | } | |
2086 | } | |
2087 | ||
dc78baa2 NF |
2088 | return 0; |
2089 | ||
bbe89c8e | 2090 | err_of_dma_controller_register: |
1c1114d8 | 2091 | dma_async_device_unregister(&atdma->dma_device); |
c47e6403 | 2092 | err_dma_async_device_register: |
4d112426 MR |
2093 | dma_pool_destroy(atdma->memset_pool); |
2094 | err_memset_pool_create: | |
ac803b56 | 2095 | dma_pool_destroy(atdma->lli_pool); |
4d112426 | 2096 | err_desc_pool_create: |
dc78baa2 NF |
2097 | free_irq(platform_get_irq(pdev, 0), atdma); |
2098 | err_irq: | |
f784d9c9 | 2099 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2100 | return err; |
2101 | } | |
2102 | ||
ae3f38e4 | 2103 | static void at_dma_remove(struct platform_device *pdev) |
dc78baa2 NF |
2104 | { |
2105 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
2106 | struct dma_chan *chan, *_chan; | |
dc78baa2 NF |
2107 | |
2108 | at_dma_off(atdma); | |
77e75fda RG |
2109 | if (pdev->dev.of_node) |
2110 | of_dma_controller_free(pdev->dev.of_node); | |
1c1114d8 | 2111 | dma_async_device_unregister(&atdma->dma_device); |
dc78baa2 | 2112 | |
4d112426 | 2113 | dma_pool_destroy(atdma->memset_pool); |
ac803b56 | 2114 | dma_pool_destroy(atdma->lli_pool); |
dc78baa2 NF |
2115 | free_irq(platform_get_irq(pdev, 0), atdma); |
2116 | ||
1c1114d8 | 2117 | list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels, |
dc78baa2 | 2118 | device_node) { |
dc78baa2 | 2119 | /* Disable interrupts */ |
bda3a47c | 2120 | atc_disable_chan_irq(atdma, chan->chan_id); |
dc78baa2 NF |
2121 | list_del(&chan->device_node); |
2122 | } | |
2123 | ||
f784d9c9 | 2124 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2125 | } |
2126 | ||
2127 | static void at_dma_shutdown(struct platform_device *pdev) | |
2128 | { | |
2129 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
2130 | ||
2131 | at_dma_off(platform_get_drvdata(pdev)); | |
f784d9c9 | 2132 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2133 | } |
2134 | ||
c0ba5947 NF |
2135 | static int at_dma_prepare(struct device *dev) |
2136 | { | |
5c4a74a4 | 2137 | struct at_dma *atdma = dev_get_drvdata(dev); |
c0ba5947 NF |
2138 | struct dma_chan *chan, *_chan; |
2139 | ||
1c1114d8 | 2140 | list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels, |
c0ba5947 NF |
2141 | device_node) { |
2142 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2143 | /* wait for transaction completion (except in cyclic case) */ | |
3c477482 | 2144 | if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2145 | return -EAGAIN; |
2146 | } | |
2147 | return 0; | |
2148 | } | |
2149 | ||
2150 | static void atc_suspend_cyclic(struct at_dma_chan *atchan) | |
2151 | { | |
ac803b56 | 2152 | struct dma_chan *chan = &atchan->vc.chan; |
c0ba5947 NF |
2153 | |
2154 | /* Channel should be paused by user | |
2155 | * do it anyway even if it is not done already */ | |
3c477482 | 2156 | if (!atc_chan_is_paused(atchan)) { |
c0ba5947 NF |
2157 | dev_warn(chan2dev(chan), |
2158 | "cyclic channel not paused, should be done by channel user\n"); | |
4facfe7f | 2159 | atc_pause(chan); |
c0ba5947 NF |
2160 | } |
2161 | ||
2162 | /* now preserve additional data for cyclic operations */ | |
2163 | /* next descriptor address in the cyclic list */ | |
2164 | atchan->save_dscr = channel_readl(atchan, DSCR); | |
2165 | ||
2166 | vdbg_dump_regs(atchan); | |
2167 | } | |
2168 | ||
33f82d14 | 2169 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 2170 | { |
5c4a74a4 | 2171 | struct at_dma *atdma = dev_get_drvdata(dev); |
c0ba5947 | 2172 | struct dma_chan *chan, *_chan; |
dc78baa2 | 2173 | |
c0ba5947 | 2174 | /* preserve data */ |
1c1114d8 | 2175 | list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels, |
c0ba5947 NF |
2176 | device_node) { |
2177 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2178 | ||
3c477482 | 2179 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2180 | atc_suspend_cyclic(atchan); |
2181 | atchan->save_cfg = channel_readl(atchan, CFG); | |
2182 | } | |
2183 | atdma->save_imr = dma_readl(atdma, EBCIMR); | |
2184 | ||
2185 | /* disable DMA controller */ | |
2186 | at_dma_off(atdma); | |
f784d9c9 | 2187 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2188 | return 0; |
2189 | } | |
2190 | ||
c0ba5947 NF |
2191 | static void atc_resume_cyclic(struct at_dma_chan *atchan) |
2192 | { | |
ac803b56 | 2193 | struct at_dma *atdma = to_at_dma(atchan->vc.chan.device); |
c0ba5947 NF |
2194 | |
2195 | /* restore channel status for cyclic descriptors list: | |
2196 | * next descriptor in the cyclic list at the time of suspend */ | |
2197 | channel_writel(atchan, SADDR, 0); | |
2198 | channel_writel(atchan, DADDR, 0); | |
2199 | channel_writel(atchan, CTRLA, 0); | |
2200 | channel_writel(atchan, CTRLB, 0); | |
2201 | channel_writel(atchan, DSCR, atchan->save_dscr); | |
2202 | dma_writel(atdma, CHER, atchan->mask); | |
2203 | ||
2204 | /* channel pause status should be removed by channel user | |
2205 | * We cannot take the initiative to do it here */ | |
2206 | ||
2207 | vdbg_dump_regs(atchan); | |
2208 | } | |
2209 | ||
33f82d14 | 2210 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 2211 | { |
5c4a74a4 | 2212 | struct at_dma *atdma = dev_get_drvdata(dev); |
c0ba5947 | 2213 | struct dma_chan *chan, *_chan; |
dc78baa2 | 2214 | |
c0ba5947 | 2215 | /* bring back DMA controller */ |
f784d9c9 | 2216 | clk_prepare_enable(atdma->clk); |
dc78baa2 | 2217 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
c0ba5947 NF |
2218 | |
2219 | /* clear any pending interrupt */ | |
2220 | while (dma_readl(atdma, EBCISR)) | |
2221 | cpu_relax(); | |
2222 | ||
2223 | /* restore saved data */ | |
2224 | dma_writel(atdma, EBCIER, atdma->save_imr); | |
1c1114d8 | 2225 | list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels, |
c0ba5947 NF |
2226 | device_node) { |
2227 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2228 | ||
2229 | channel_writel(atchan, CFG, atchan->save_cfg); | |
3c477482 | 2230 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2231 | atc_resume_cyclic(atchan); |
2232 | } | |
dc78baa2 | 2233 | return 0; |
dc78baa2 NF |
2234 | } |
2235 | ||
c23cd8c9 | 2236 | static const struct dev_pm_ops __maybe_unused at_dma_dev_pm_ops = { |
c0ba5947 | 2237 | .prepare = at_dma_prepare, |
33f82d14 DW |
2238 | .suspend_noirq = at_dma_suspend_noirq, |
2239 | .resume_noirq = at_dma_resume_noirq, | |
2240 | }; | |
2241 | ||
dc78baa2 | 2242 | static struct platform_driver at_dma_driver = { |
ae3f38e4 | 2243 | .remove_new = at_dma_remove, |
dc78baa2 | 2244 | .shutdown = at_dma_shutdown, |
67348450 | 2245 | .id_table = atdma_devtypes, |
dc78baa2 NF |
2246 | .driver = { |
2247 | .name = "at_hdmac", | |
c23cd8c9 | 2248 | .pm = pm_ptr(&at_dma_dev_pm_ops), |
c5115953 | 2249 | .of_match_table = of_match_ptr(atmel_dma_dt_ids), |
dc78baa2 NF |
2250 | }, |
2251 | }; | |
2252 | ||
2253 | static int __init at_dma_init(void) | |
2254 | { | |
2255 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
2256 | } | |
93d0bec2 | 2257 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
2258 | |
2259 | static void __exit at_dma_exit(void) | |
2260 | { | |
2261 | platform_driver_unregister(&at_dma_driver); | |
2262 | } | |
2263 | module_exit(at_dma_exit); | |
2264 | ||
2265 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
2266 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
ac803b56 | 2267 | MODULE_AUTHOR("Tudor Ambarus <tudor.ambarus@microchip.com>"); |
dc78baa2 NF |
2268 | MODULE_LICENSE("GPL"); |
2269 | MODULE_ALIAS("platform:at_hdmac"); |