Commit | Line | Data |
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dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
9102d871 NF |
12 | * This supports the Atmel AHB DMA Controller found in several Atmel SoCs. |
13 | * The only Atmel DMA Controller that is not covered by this driver is the one | |
14 | * found on AT91SAM9263. | |
dc78baa2 NF |
15 | */ |
16 | ||
62971b29 | 17 | #include <dt-bindings/dma/at91.h> |
dc78baa2 NF |
18 | #include <linux/clk.h> |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
c5115953 NF |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
bbe89c8e | 28 | #include <linux/of_dma.h> |
dc78baa2 NF |
29 | |
30 | #include "at_hdmac_regs.h" | |
d2ebfb33 | 31 | #include "dmaengine.h" |
dc78baa2 NF |
32 | |
33 | /* | |
34 | * Glossary | |
35 | * -------- | |
36 | * | |
37 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
38 | * at_dma_ / atdma : ATmel DMA controller entity related | |
39 | * atc_ / atchan : ATmel DMA Channel entity related | |
40 | */ | |
41 | ||
42 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
ae14d4b5 NF |
43 | #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ |
44 | |ATC_DIF(AT_DMA_MEM_IF)) | |
816070ed LD |
45 | #define ATC_DMA_BUSWIDTHS\ |
46 | (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ | |
47 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ | |
48 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ | |
49 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
dc78baa2 | 50 | |
93dce3a6 CP |
51 | #define ATC_MAX_DSCR_TRIALS 10 |
52 | ||
dc78baa2 NF |
53 | /* |
54 | * Initial number of descriptors to allocate for each channel. This could | |
55 | * be increased during dma usage. | |
56 | */ | |
57 | static unsigned int init_nr_desc_per_channel = 64; | |
58 | module_param(init_nr_desc_per_channel, uint, 0644); | |
59 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
60 | "initial descriptors per channel (default: 64)"); | |
61 | ||
62 | ||
63 | /* prototypes */ | |
64 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
d48de6f1 | 65 | static void atc_issue_pending(struct dma_chan *chan); |
dc78baa2 NF |
66 | |
67 | ||
68 | /*----------------------------------------------------------------------*/ | |
69 | ||
265567fb TF |
70 | static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst, |
71 | size_t len) | |
72 | { | |
73 | unsigned int width; | |
74 | ||
75 | if (!((src | dst | len) & 3)) | |
76 | width = 2; | |
77 | else if (!((src | dst | len) & 1)) | |
78 | width = 1; | |
79 | else | |
80 | width = 0; | |
81 | ||
82 | return width; | |
83 | } | |
84 | ||
dc78baa2 NF |
85 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) |
86 | { | |
87 | return list_first_entry(&atchan->active_list, | |
88 | struct at_desc, desc_node); | |
89 | } | |
90 | ||
91 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
92 | { | |
93 | return list_first_entry(&atchan->queue, | |
94 | struct at_desc, desc_node); | |
95 | } | |
96 | ||
97 | /** | |
421f91d2 | 98 | * atc_alloc_descriptor - allocate and return an initialized descriptor |
dc78baa2 NF |
99 | * @chan: the channel to allocate descriptors for |
100 | * @gfp_flags: GFP allocation flags | |
101 | * | |
102 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
103 | * to make initial allocation more convenient. This bit will be cleared | |
104 | * and control will be given to client at usage time (during | |
105 | * preparation functions). | |
106 | */ | |
107 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
108 | gfp_t gfp_flags) | |
109 | { | |
110 | struct at_desc *desc = NULL; | |
111 | struct at_dma *atdma = to_at_dma(chan->device); | |
112 | dma_addr_t phys; | |
113 | ||
12154c87 | 114 | desc = dma_pool_zalloc(atdma->dma_desc_pool, gfp_flags, &phys); |
dc78baa2 | 115 | if (desc) { |
285a3c71 | 116 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
117 | dma_async_tx_descriptor_init(&desc->txd, chan); |
118 | /* txd.flags will be overwritten in prep functions */ | |
119 | desc->txd.flags = DMA_CTRL_ACK; | |
120 | desc->txd.tx_submit = atc_tx_submit; | |
121 | desc->txd.phys = phys; | |
122 | } | |
123 | ||
124 | return desc; | |
125 | } | |
126 | ||
127 | /** | |
af901ca1 | 128 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
129 | * @atchan: channel we want a new descriptor for |
130 | */ | |
131 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
132 | { | |
133 | struct at_desc *desc, *_desc; | |
134 | struct at_desc *ret = NULL; | |
d8cb04b0 | 135 | unsigned long flags; |
dc78baa2 | 136 | unsigned int i = 0; |
dc78baa2 | 137 | |
d8cb04b0 | 138 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
139 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { |
140 | i++; | |
141 | if (async_tx_test_ack(&desc->txd)) { | |
142 | list_del(&desc->desc_node); | |
143 | ret = desc; | |
144 | break; | |
145 | } | |
146 | dev_dbg(chan2dev(&atchan->chan_common), | |
147 | "desc %p not ACKed\n", desc); | |
148 | } | |
d8cb04b0 | 149 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
150 | dev_vdbg(chan2dev(&atchan->chan_common), |
151 | "scanned %u descriptors on freelist\n", i); | |
152 | ||
153 | /* no more descriptor available in initial pool: create one more */ | |
154 | if (!ret) { | |
155 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
156 | if (ret) { | |
d8cb04b0 | 157 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 158 | atchan->descs_allocated++; |
d8cb04b0 | 159 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
160 | } else { |
161 | dev_err(chan2dev(&atchan->chan_common), | |
162 | "not enough descriptors available\n"); | |
163 | } | |
164 | } | |
165 | ||
166 | return ret; | |
167 | } | |
168 | ||
169 | /** | |
170 | * atc_desc_put - move a descriptor, including any children, to the free list | |
171 | * @atchan: channel we work on | |
172 | * @desc: descriptor, at the head of a chain, to move to free list | |
173 | */ | |
174 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
175 | { | |
176 | if (desc) { | |
177 | struct at_desc *child; | |
d8cb04b0 | 178 | unsigned long flags; |
dc78baa2 | 179 | |
d8cb04b0 | 180 | spin_lock_irqsave(&atchan->lock, flags); |
285a3c71 | 181 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
182 | dev_vdbg(chan2dev(&atchan->chan_common), |
183 | "moving child desc %p to freelist\n", | |
184 | child); | |
285a3c71 | 185 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
186 | dev_vdbg(chan2dev(&atchan->chan_common), |
187 | "moving desc %p to freelist\n", desc); | |
188 | list_add(&desc->desc_node, &atchan->free_list); | |
d8cb04b0 | 189 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
190 | } |
191 | } | |
192 | ||
53830cc7 | 193 | /** |
d73111c6 MI |
194 | * atc_desc_chain - build chain adding a descriptor |
195 | * @first: address of first descriptor of the chain | |
196 | * @prev: address of previous descriptor of the chain | |
53830cc7 NF |
197 | * @desc: descriptor to queue |
198 | * | |
199 | * Called from prep_* functions | |
200 | */ | |
201 | static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, | |
202 | struct at_desc *desc) | |
203 | { | |
204 | if (!(*first)) { | |
205 | *first = desc; | |
206 | } else { | |
207 | /* inform the HW lli about chaining */ | |
208 | (*prev)->lli.dscr = desc->txd.phys; | |
209 | /* insert the link descriptor to the LD ring */ | |
210 | list_add_tail(&desc->desc_node, | |
211 | &(*first)->tx_list); | |
212 | } | |
213 | *prev = desc; | |
214 | } | |
215 | ||
dc78baa2 NF |
216 | /** |
217 | * atc_dostart - starts the DMA engine for real | |
218 | * @atchan: the channel we want to start | |
219 | * @first: first descriptor in the list we want to begin with | |
220 | * | |
221 | * Called with atchan->lock held and bh disabled | |
222 | */ | |
223 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
224 | { | |
225 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
226 | ||
227 | /* ASSERT: channel is idle */ | |
228 | if (atc_chan_is_enabled(atchan)) { | |
229 | dev_err(chan2dev(&atchan->chan_common), | |
230 | "BUG: Attempted to start non-idle channel\n"); | |
231 | dev_err(chan2dev(&atchan->chan_common), | |
232 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
233 | channel_readl(atchan, SADDR), | |
234 | channel_readl(atchan, DADDR), | |
235 | channel_readl(atchan, CTRLA), | |
236 | channel_readl(atchan, CTRLB), | |
237 | channel_readl(atchan, DSCR)); | |
238 | ||
239 | /* The tasklet will hopefully advance the queue... */ | |
240 | return; | |
241 | } | |
242 | ||
243 | vdbg_dump_regs(atchan); | |
244 | ||
dc78baa2 NF |
245 | channel_writel(atchan, SADDR, 0); |
246 | channel_writel(atchan, DADDR, 0); | |
247 | channel_writel(atchan, CTRLA, 0); | |
248 | channel_writel(atchan, CTRLB, 0); | |
249 | channel_writel(atchan, DSCR, first->txd.phys); | |
5abecfa5 MR |
250 | channel_writel(atchan, SPIP, ATC_SPIP_HOLE(first->src_hole) | |
251 | ATC_SPIP_BOUNDARY(first->boundary)); | |
252 | channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) | | |
253 | ATC_DPIP_BOUNDARY(first->boundary)); | |
dc78baa2 NF |
254 | dma_writel(atdma, CHER, atchan->mask); |
255 | ||
256 | vdbg_dump_regs(atchan); | |
257 | } | |
258 | ||
d48de6f1 | 259 | /* |
bdf6c792 TF |
260 | * atc_get_desc_by_cookie - get the descriptor of a cookie |
261 | * @atchan: the DMA channel | |
262 | * @cookie: the cookie to get the descriptor for | |
d48de6f1 | 263 | */ |
bdf6c792 TF |
264 | static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan, |
265 | dma_cookie_t cookie) | |
d48de6f1 | 266 | { |
bdf6c792 | 267 | struct at_desc *desc, *_desc; |
d48de6f1 | 268 | |
bdf6c792 TF |
269 | list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) { |
270 | if (desc->txd.cookie == cookie) | |
271 | return desc; | |
272 | } | |
d48de6f1 | 273 | |
bdf6c792 TF |
274 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { |
275 | if (desc->txd.cookie == cookie) | |
276 | return desc; | |
d48de6f1 ES |
277 | } |
278 | ||
bdf6c792 | 279 | return NULL; |
d48de6f1 ES |
280 | } |
281 | ||
bdf6c792 TF |
282 | /** |
283 | * atc_calc_bytes_left - calculates the number of bytes left according to the | |
284 | * value read from CTRLA. | |
285 | * | |
286 | * @current_len: the number of bytes left before reading CTRLA | |
287 | * @ctrla: the value of CTRLA | |
bdf6c792 | 288 | */ |
93dce3a6 | 289 | static inline int atc_calc_bytes_left(int current_len, u32 ctrla) |
bdf6c792 | 290 | { |
93dce3a6 CP |
291 | u32 btsize = (ctrla & ATC_BTSIZE_MAX); |
292 | u32 src_width = ATC_REG_TO_SRC_WIDTH(ctrla); | |
bdf6c792 | 293 | |
93dce3a6 CP |
294 | /* |
295 | * According to the datasheet, when reading the Control A Register | |
296 | * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the | |
297 | * number of transfers completed on the Source Interface. | |
298 | * So btsize is always a number of source width transfers. | |
299 | */ | |
300 | return current_len - (btsize << src_width); | |
bdf6c792 TF |
301 | } |
302 | ||
303 | /** | |
304 | * atc_get_bytes_left - get the number of bytes residue for a cookie | |
305 | * @chan: DMA channel | |
306 | * @cookie: transaction identifier to check status of | |
d48de6f1 | 307 | */ |
bdf6c792 | 308 | static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) |
d48de6f1 ES |
309 | { |
310 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d48de6f1 | 311 | struct at_desc *desc_first = atc_first_active(atchan); |
bdf6c792 TF |
312 | struct at_desc *desc; |
313 | int ret; | |
93dce3a6 | 314 | u32 ctrla, dscr, trials; |
d48de6f1 ES |
315 | |
316 | /* | |
bdf6c792 TF |
317 | * If the cookie doesn't match to the currently running transfer then |
318 | * we can return the total length of the associated DMA transfer, | |
319 | * because it is still queued. | |
d48de6f1 | 320 | */ |
bdf6c792 TF |
321 | desc = atc_get_desc_by_cookie(atchan, cookie); |
322 | if (desc == NULL) | |
323 | return -EINVAL; | |
324 | else if (desc != desc_first) | |
325 | return desc->total_len; | |
d48de6f1 | 326 | |
bdf6c792 TF |
327 | /* cookie matches to the currently running transfer */ |
328 | ret = desc_first->total_len; | |
6758ddaf | 329 | |
bdf6c792 TF |
330 | if (desc_first->lli.dscr) { |
331 | /* hardware linked list transfer */ | |
332 | ||
333 | /* | |
334 | * Calculate the residue by removing the length of the child | |
335 | * descriptors already transferred from the total length. | |
336 | * To get the current child descriptor we can use the value of | |
337 | * the channel's DSCR register and compare it against the value | |
338 | * of the hardware linked list structure of each child | |
339 | * descriptor. | |
93dce3a6 CP |
340 | * |
341 | * The CTRLA register provides us with the amount of data | |
342 | * already read from the source for the current child | |
343 | * descriptor. So we can compute a more accurate residue by also | |
344 | * removing the number of bytes corresponding to this amount of | |
345 | * data. | |
346 | * | |
347 | * However, the DSCR and CTRLA registers cannot be read both | |
348 | * atomically. Hence a race condition may occur: the first read | |
349 | * register may refer to one child descriptor whereas the second | |
350 | * read may refer to a later child descriptor in the list | |
351 | * because of the DMA transfer progression inbetween the two | |
352 | * reads. | |
353 | * | |
354 | * One solution could have been to pause the DMA transfer, read | |
355 | * the DSCR and CTRLA then resume the DMA transfer. Nonetheless, | |
356 | * this approach presents some drawbacks: | |
357 | * - If the DMA transfer is paused, RX overruns or TX underruns | |
358 | * are more likey to occur depending on the system latency. | |
359 | * Taking the USART driver as an example, it uses a cyclic DMA | |
360 | * transfer to read data from the Receive Holding Register | |
361 | * (RHR) to avoid RX overruns since the RHR is not protected | |
362 | * by any FIFO on most Atmel SoCs. So pausing the DMA transfer | |
363 | * to compute the residue would break the USART driver design. | |
364 | * - The atc_pause() function masks interrupts but we'd rather | |
365 | * avoid to do so for system latency purpose. | |
366 | * | |
367 | * Then we'd rather use another solution: the DSCR is read a | |
368 | * first time, the CTRLA is read in turn, next the DSCR is read | |
369 | * a second time. If the two consecutive read values of the DSCR | |
370 | * are the same then we assume both refers to the very same | |
371 | * child descriptor as well as the CTRLA value read inbetween | |
372 | * does. For cyclic tranfers, the assumption is that a full loop | |
373 | * is "not so fast". | |
374 | * If the two DSCR values are different, we read again the CTRLA | |
375 | * then the DSCR till two consecutive read values from DSCR are | |
376 | * equal or till the maxium trials is reach. | |
377 | * This algorithm is very unlikely not to find a stable value for | |
378 | * DSCR. | |
bdf6c792 TF |
379 | */ |
380 | ||
bdf6c792 | 381 | dscr = channel_readl(atchan, DSCR); |
93dce3a6 CP |
382 | rmb(); /* ensure DSCR is read before CTRLA */ |
383 | ctrla = channel_readl(atchan, CTRLA); | |
384 | for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) { | |
385 | u32 new_dscr; | |
386 | ||
387 | rmb(); /* ensure DSCR is read after CTRLA */ | |
388 | new_dscr = channel_readl(atchan, DSCR); | |
389 | ||
390 | /* | |
391 | * If the DSCR register value has not changed inside the | |
392 | * DMA controller since the previous read, we assume | |
393 | * that both the dscr and ctrla values refers to the | |
394 | * very same descriptor. | |
395 | */ | |
396 | if (likely(new_dscr == dscr)) | |
397 | break; | |
398 | ||
399 | /* | |
400 | * DSCR has changed inside the DMA controller, so the | |
401 | * previouly read value of CTRLA may refer to an already | |
402 | * processed descriptor hence could be outdated. | |
403 | * We need to update ctrla to match the current | |
404 | * descriptor. | |
405 | */ | |
406 | dscr = new_dscr; | |
407 | rmb(); /* ensure DSCR is read before CTRLA */ | |
408 | ctrla = channel_readl(atchan, CTRLA); | |
409 | } | |
410 | if (unlikely(trials >= ATC_MAX_DSCR_TRIALS)) | |
411 | return -ETIMEDOUT; | |
bdf6c792 TF |
412 | |
413 | /* for the first descriptor we can be more accurate */ | |
414 | if (desc_first->lli.dscr == dscr) | |
93dce3a6 | 415 | return atc_calc_bytes_left(ret, ctrla); |
bdf6c792 TF |
416 | |
417 | ret -= desc_first->len; | |
418 | list_for_each_entry(desc, &desc_first->tx_list, desc_node) { | |
419 | if (desc->lli.dscr == dscr) | |
420 | break; | |
421 | ||
422 | ret -= desc->len; | |
c3dbc60c | 423 | } |
6758ddaf | 424 | |
d48de6f1 | 425 | /* |
93dce3a6 | 426 | * For the current descriptor in the chain we can calculate |
bdf6c792 | 427 | * the remaining bytes using the channel's register. |
d48de6f1 | 428 | */ |
93dce3a6 | 429 | ret = atc_calc_bytes_left(ret, ctrla); |
bdf6c792 TF |
430 | } else { |
431 | /* single transfer */ | |
93dce3a6 CP |
432 | ctrla = channel_readl(atchan, CTRLA); |
433 | ret = atc_calc_bytes_left(ret, ctrla); | |
d48de6f1 | 434 | } |
d48de6f1 | 435 | |
d48de6f1 ES |
436 | return ret; |
437 | } | |
438 | ||
dc78baa2 NF |
439 | /** |
440 | * atc_chain_complete - finish work for one transaction chain | |
441 | * @atchan: channel we work on | |
442 | * @desc: descriptor at the head of the chain we want do complete | |
443 | * | |
444 | * Called with atchan->lock held and bh disabled */ | |
445 | static void | |
446 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
447 | { | |
dc78baa2 | 448 | struct dma_async_tx_descriptor *txd = &desc->txd; |
4d112426 | 449 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); |
dc78baa2 NF |
450 | |
451 | dev_vdbg(chan2dev(&atchan->chan_common), | |
452 | "descriptor %u complete\n", txd->cookie); | |
453 | ||
d4116052 VK |
454 | /* mark the descriptor as complete for non cyclic cases only */ |
455 | if (!atc_chan_is_cyclic(atchan)) | |
456 | dma_cookie_complete(txd); | |
dc78baa2 | 457 | |
4d112426 | 458 | /* If the transfer was a memset, free our temporary buffer */ |
ce2a673d | 459 | if (desc->memset_buffer) { |
4d112426 MR |
460 | dma_pool_free(atdma->memset_pool, desc->memset_vaddr, |
461 | desc->memset_paddr); | |
ce2a673d | 462 | desc->memset_buffer = false; |
4d112426 MR |
463 | } |
464 | ||
dc78baa2 | 465 | /* move children to free_list */ |
285a3c71 | 466 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
467 | /* move myself to free_list */ |
468 | list_move(&desc->desc_node, &atchan->free_list); | |
469 | ||
d38a8c62 | 470 | dma_descriptor_unmap(txd); |
53830cc7 NF |
471 | /* for cyclic transfers, |
472 | * no need to replay callback function while stopping */ | |
3c477482 | 473 | if (!atc_chan_is_cyclic(atchan)) { |
53830cc7 NF |
474 | /* |
475 | * The API requires that no submissions are done from a | |
476 | * callback, so we don't need to drop the lock here | |
477 | */ | |
dff232da | 478 | dmaengine_desc_get_callback_invoke(txd, NULL); |
53830cc7 | 479 | } |
dc78baa2 NF |
480 | |
481 | dma_run_dependencies(txd); | |
482 | } | |
483 | ||
484 | /** | |
485 | * atc_complete_all - finish work for all transactions | |
486 | * @atchan: channel to complete transactions for | |
487 | * | |
488 | * Eventually submit queued descriptors if any | |
489 | * | |
490 | * Assume channel is idle while calling this function | |
491 | * Called with atchan->lock held and bh disabled | |
492 | */ | |
493 | static void atc_complete_all(struct at_dma_chan *atchan) | |
494 | { | |
495 | struct at_desc *desc, *_desc; | |
496 | LIST_HEAD(list); | |
497 | ||
498 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
499 | ||
dc78baa2 NF |
500 | /* |
501 | * Submit queued descriptors ASAP, i.e. before we go through | |
502 | * the completed ones. | |
503 | */ | |
504 | if (!list_empty(&atchan->queue)) | |
505 | atc_dostart(atchan, atc_first_queued(atchan)); | |
506 | /* empty active_list now it is completed */ | |
507 | list_splice_init(&atchan->active_list, &list); | |
508 | /* empty queue list by moving descriptors (if any) to active_list */ | |
509 | list_splice_init(&atchan->queue, &atchan->active_list); | |
510 | ||
511 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
512 | atc_chain_complete(atchan, desc); | |
513 | } | |
514 | ||
dc78baa2 NF |
515 | /** |
516 | * atc_advance_work - at the end of a transaction, move forward | |
517 | * @atchan: channel where the transaction ended | |
518 | * | |
519 | * Called with atchan->lock held and bh disabled | |
520 | */ | |
521 | static void atc_advance_work(struct at_dma_chan *atchan) | |
522 | { | |
523 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
524 | ||
d202f051 LD |
525 | if (atc_chan_is_enabled(atchan)) |
526 | return; | |
527 | ||
dc78baa2 NF |
528 | if (list_empty(&atchan->active_list) || |
529 | list_is_singular(&atchan->active_list)) { | |
530 | atc_complete_all(atchan); | |
531 | } else { | |
532 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
533 | /* advance work */ | |
534 | atc_dostart(atchan, atc_first_active(atchan)); | |
535 | } | |
536 | } | |
537 | ||
538 | ||
539 | /** | |
540 | * atc_handle_error - handle errors reported by DMA controller | |
541 | * @atchan: channel where error occurs | |
542 | * | |
543 | * Called with atchan->lock held and bh disabled | |
544 | */ | |
545 | static void atc_handle_error(struct at_dma_chan *atchan) | |
546 | { | |
547 | struct at_desc *bad_desc; | |
548 | struct at_desc *child; | |
549 | ||
550 | /* | |
551 | * The descriptor currently at the head of the active list is | |
552 | * broked. Since we don't have any way to report errors, we'll | |
553 | * just have to scream loudly and try to carry on. | |
554 | */ | |
555 | bad_desc = atc_first_active(atchan); | |
556 | list_del_init(&bad_desc->desc_node); | |
557 | ||
558 | /* As we are stopped, take advantage to push queued descriptors | |
559 | * in active_list */ | |
560 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
561 | ||
562 | /* Try to restart the controller */ | |
563 | if (!list_empty(&atchan->active_list)) | |
564 | atc_dostart(atchan, atc_first_active(atchan)); | |
565 | ||
566 | /* | |
567 | * KERN_CRITICAL may seem harsh, but since this only happens | |
568 | * when someone submits a bad physical address in a | |
569 | * descriptor, we should consider ourselves lucky that the | |
570 | * controller flagged an error instead of scribbling over | |
571 | * random memory locations. | |
572 | */ | |
573 | dev_crit(chan2dev(&atchan->chan_common), | |
574 | "Bad descriptor submitted for DMA!\n"); | |
575 | dev_crit(chan2dev(&atchan->chan_common), | |
576 | " cookie: %d\n", bad_desc->txd.cookie); | |
577 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 578 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
579 | atc_dump_lli(atchan, &child->lli); |
580 | ||
581 | /* Pretend the descriptor completed successfully */ | |
582 | atc_chain_complete(atchan, bad_desc); | |
583 | } | |
584 | ||
53830cc7 NF |
585 | /** |
586 | * atc_handle_cyclic - at the end of a period, run callback function | |
587 | * @atchan: channel used for cyclic operations | |
588 | * | |
589 | * Called with atchan->lock held and bh disabled | |
590 | */ | |
591 | static void atc_handle_cyclic(struct at_dma_chan *atchan) | |
592 | { | |
593 | struct at_desc *first = atc_first_active(atchan); | |
594 | struct dma_async_tx_descriptor *txd = &first->txd; | |
53830cc7 NF |
595 | |
596 | dev_vdbg(chan2dev(&atchan->chan_common), | |
597 | "new cyclic period llp 0x%08x\n", | |
598 | channel_readl(atchan, DSCR)); | |
599 | ||
dff232da | 600 | dmaengine_desc_get_callback_invoke(txd, NULL); |
53830cc7 | 601 | } |
dc78baa2 NF |
602 | |
603 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
604 | ||
605 | static void atc_tasklet(unsigned long data) | |
606 | { | |
607 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
d8cb04b0 | 608 | unsigned long flags; |
dc78baa2 | 609 | |
d8cb04b0 | 610 | spin_lock_irqsave(&atchan->lock, flags); |
53830cc7 | 611 | if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) |
dc78baa2 | 612 | atc_handle_error(atchan); |
3c477482 | 613 | else if (atc_chan_is_cyclic(atchan)) |
53830cc7 | 614 | atc_handle_cyclic(atchan); |
dc78baa2 NF |
615 | else |
616 | atc_advance_work(atchan); | |
617 | ||
d8cb04b0 | 618 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
619 | } |
620 | ||
621 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
622 | { | |
623 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
624 | struct at_dma_chan *atchan; | |
625 | int i; | |
626 | u32 status, pending, imr; | |
627 | int ret = IRQ_NONE; | |
628 | ||
629 | do { | |
630 | imr = dma_readl(atdma, EBCIMR); | |
631 | status = dma_readl(atdma, EBCISR); | |
632 | pending = status & imr; | |
633 | ||
634 | if (!pending) | |
635 | break; | |
636 | ||
637 | dev_vdbg(atdma->dma_common.dev, | |
638 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
639 | status, imr, pending); | |
640 | ||
641 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
642 | atchan = &atdma->chan[i]; | |
9b3aa589 | 643 | if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { |
dc78baa2 NF |
644 | if (pending & AT_DMA_ERR(i)) { |
645 | /* Disable channel on AHB error */ | |
23b5e3ad NF |
646 | dma_writel(atdma, CHDR, |
647 | AT_DMA_RES(i) | atchan->mask); | |
dc78baa2 | 648 | /* Give information to tasklet */ |
53830cc7 | 649 | set_bit(ATC_IS_ERROR, &atchan->status); |
dc78baa2 NF |
650 | } |
651 | tasklet_schedule(&atchan->tasklet); | |
652 | ret = IRQ_HANDLED; | |
653 | } | |
654 | } | |
655 | ||
656 | } while (pending); | |
657 | ||
658 | return ret; | |
659 | } | |
660 | ||
661 | ||
662 | /*-- DMA Engine API --------------------------------------------------*/ | |
663 | ||
664 | /** | |
665 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
666 | * @desc: descriptor at the head of the transaction chain | |
667 | * | |
668 | * Queue chain if DMA engine is working already | |
669 | * | |
670 | * Cookie increment and adding to active_list or queue must be atomic | |
671 | */ | |
672 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
673 | { | |
674 | struct at_desc *desc = txd_to_at_desc(tx); | |
675 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
676 | dma_cookie_t cookie; | |
d8cb04b0 | 677 | unsigned long flags; |
dc78baa2 | 678 | |
d8cb04b0 | 679 | spin_lock_irqsave(&atchan->lock, flags); |
884485e1 | 680 | cookie = dma_cookie_assign(tx); |
dc78baa2 NF |
681 | |
682 | if (list_empty(&atchan->active_list)) { | |
683 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
684 | desc->txd.cookie); | |
685 | atc_dostart(atchan, desc); | |
686 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
687 | } else { | |
688 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
689 | desc->txd.cookie); | |
690 | list_add_tail(&desc->desc_node, &atchan->queue); | |
691 | } | |
692 | ||
d8cb04b0 | 693 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
694 | |
695 | return cookie; | |
696 | } | |
697 | ||
5abecfa5 MR |
698 | /** |
699 | * atc_prep_dma_interleaved - prepare memory to memory interleaved operation | |
700 | * @chan: the channel to prepare operation on | |
701 | * @xt: Interleaved transfer template | |
702 | * @flags: tx descriptor status flags | |
703 | */ | |
704 | static struct dma_async_tx_descriptor * | |
705 | atc_prep_dma_interleaved(struct dma_chan *chan, | |
706 | struct dma_interleaved_template *xt, | |
707 | unsigned long flags) | |
708 | { | |
709 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
62a277d4 | 710 | struct data_chunk *first; |
5abecfa5 MR |
711 | struct at_desc *desc = NULL; |
712 | size_t xfer_count; | |
713 | unsigned int dwidth; | |
714 | u32 ctrla; | |
715 | u32 ctrlb; | |
716 | size_t len = 0; | |
717 | int i; | |
718 | ||
4483320e MS |
719 | if (unlikely(!xt || xt->numf != 1 || !xt->frame_size)) |
720 | return NULL; | |
721 | ||
62a277d4 GS |
722 | first = xt->sgl; |
723 | ||
5abecfa5 | 724 | dev_info(chan2dev(chan), |
2c5d7407 AB |
725 | "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n", |
726 | __func__, &xt->src_start, &xt->dst_start, xt->numf, | |
5abecfa5 MR |
727 | xt->frame_size, flags); |
728 | ||
5abecfa5 MR |
729 | /* |
730 | * The controller can only "skip" X bytes every Y bytes, so we | |
731 | * need to make sure we are given a template that fit that | |
732 | * description, ie a template with chunks that always have the | |
733 | * same size, with the same ICGs. | |
734 | */ | |
735 | for (i = 0; i < xt->frame_size; i++) { | |
736 | struct data_chunk *chunk = xt->sgl + i; | |
737 | ||
738 | if ((chunk->size != xt->sgl->size) || | |
739 | (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) || | |
740 | (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) { | |
741 | dev_err(chan2dev(chan), | |
742 | "%s: the controller can transfer only identical chunks\n", | |
743 | __func__); | |
744 | return NULL; | |
745 | } | |
746 | ||
747 | len += chunk->size; | |
748 | } | |
749 | ||
750 | dwidth = atc_get_xfer_width(xt->src_start, | |
751 | xt->dst_start, len); | |
752 | ||
753 | xfer_count = len >> dwidth; | |
754 | if (xfer_count > ATC_BTSIZE_MAX) { | |
755 | dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__); | |
756 | return NULL; | |
757 | } | |
758 | ||
759 | ctrla = ATC_SRC_WIDTH(dwidth) | | |
760 | ATC_DST_WIDTH(dwidth); | |
761 | ||
762 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | |
763 | | ATC_SRC_ADDR_MODE_INCR | |
764 | | ATC_DST_ADDR_MODE_INCR | |
765 | | ATC_SRC_PIP | |
766 | | ATC_DST_PIP | |
767 | | ATC_FC_MEM2MEM; | |
768 | ||
769 | /* create the transfer */ | |
770 | desc = atc_desc_get(atchan); | |
771 | if (!desc) { | |
772 | dev_err(chan2dev(chan), | |
773 | "%s: couldn't allocate our descriptor\n", __func__); | |
774 | return NULL; | |
775 | } | |
776 | ||
777 | desc->lli.saddr = xt->src_start; | |
778 | desc->lli.daddr = xt->dst_start; | |
779 | desc->lli.ctrla = ctrla | xfer_count; | |
780 | desc->lli.ctrlb = ctrlb; | |
781 | ||
782 | desc->boundary = first->size >> dwidth; | |
783 | desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1; | |
784 | desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1; | |
785 | ||
786 | desc->txd.cookie = -EBUSY; | |
787 | desc->total_len = desc->len = len; | |
5abecfa5 MR |
788 | |
789 | /* set end-of-link to the last link descriptor of list*/ | |
790 | set_desc_eol(desc); | |
791 | ||
792 | desc->txd.flags = flags; /* client is in control of this ack */ | |
793 | ||
794 | return &desc->txd; | |
795 | } | |
796 | ||
dc78baa2 NF |
797 | /** |
798 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
799 | * @chan: the channel to prepare operation on | |
800 | * @dest: operation virtual destination address | |
801 | * @src: operation virtual source address | |
802 | * @len: operation length | |
803 | * @flags: tx descriptor status flags | |
804 | */ | |
805 | static struct dma_async_tx_descriptor * | |
806 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
807 | size_t len, unsigned long flags) | |
808 | { | |
809 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
810 | struct at_desc *desc = NULL; | |
811 | struct at_desc *first = NULL; | |
812 | struct at_desc *prev = NULL; | |
813 | size_t xfer_count; | |
814 | size_t offset; | |
815 | unsigned int src_width; | |
816 | unsigned int dst_width; | |
817 | u32 ctrla; | |
818 | u32 ctrlb; | |
819 | ||
2c5d7407 AB |
820 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d%pad s%pad l0x%zx f0x%lx\n", |
821 | &dest, &src, len, flags); | |
dc78baa2 NF |
822 | |
823 | if (unlikely(!len)) { | |
824 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
825 | return NULL; | |
826 | } | |
827 | ||
9b3aa589 | 828 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
dc78baa2 NF |
829 | | ATC_SRC_ADDR_MODE_INCR |
830 | | ATC_DST_ADDR_MODE_INCR | |
831 | | ATC_FC_MEM2MEM; | |
832 | ||
833 | /* | |
834 | * We can be a lot more clever here, but this should take care | |
835 | * of the most common optimization. | |
836 | */ | |
265567fb TF |
837 | src_width = dst_width = atc_get_xfer_width(src, dest, len); |
838 | ||
839 | ctrla = ATC_SRC_WIDTH(src_width) | | |
840 | ATC_DST_WIDTH(dst_width); | |
dc78baa2 NF |
841 | |
842 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
843 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
844 | ATC_BTSIZE_MAX); | |
845 | ||
846 | desc = atc_desc_get(atchan); | |
847 | if (!desc) | |
848 | goto err_desc_get; | |
849 | ||
850 | desc->lli.saddr = src + offset; | |
851 | desc->lli.daddr = dest + offset; | |
852 | desc->lli.ctrla = ctrla | xfer_count; | |
853 | desc->lli.ctrlb = ctrlb; | |
854 | ||
855 | desc->txd.cookie = 0; | |
bdf6c792 | 856 | desc->len = xfer_count << src_width; |
dc78baa2 | 857 | |
e257e156 | 858 | atc_desc_chain(&first, &prev, desc); |
dc78baa2 NF |
859 | } |
860 | ||
861 | /* First descriptor of the chain embedds additional information */ | |
862 | first->txd.cookie = -EBUSY; | |
bdf6c792 TF |
863 | first->total_len = len; |
864 | ||
dc78baa2 NF |
865 | /* set end-of-link to the last link descriptor of list*/ |
866 | set_desc_eol(desc); | |
867 | ||
568f7f0c | 868 | first->txd.flags = flags; /* client is in control of this ack */ |
dc78baa2 NF |
869 | |
870 | return &first->txd; | |
871 | ||
872 | err_desc_get: | |
873 | atc_desc_put(atchan, first); | |
874 | return NULL; | |
875 | } | |
876 | ||
ce2a673d MR |
877 | static struct at_desc *atc_create_memset_desc(struct dma_chan *chan, |
878 | dma_addr_t psrc, | |
879 | dma_addr_t pdst, | |
880 | size_t len) | |
881 | { | |
882 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
883 | struct at_desc *desc; | |
884 | size_t xfer_count; | |
885 | ||
886 | u32 ctrla = ATC_SRC_WIDTH(2) | ATC_DST_WIDTH(2); | |
887 | u32 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | | |
888 | ATC_SRC_ADDR_MODE_FIXED | | |
889 | ATC_DST_ADDR_MODE_INCR | | |
890 | ATC_FC_MEM2MEM; | |
891 | ||
892 | xfer_count = len >> 2; | |
893 | if (xfer_count > ATC_BTSIZE_MAX) { | |
894 | dev_err(chan2dev(chan), "%s: buffer is too big\n", | |
895 | __func__); | |
896 | return NULL; | |
897 | } | |
898 | ||
899 | desc = atc_desc_get(atchan); | |
900 | if (!desc) { | |
901 | dev_err(chan2dev(chan), "%s: can't get a descriptor\n", | |
902 | __func__); | |
903 | return NULL; | |
904 | } | |
905 | ||
906 | desc->lli.saddr = psrc; | |
907 | desc->lli.daddr = pdst; | |
908 | desc->lli.ctrla = ctrla | xfer_count; | |
909 | desc->lli.ctrlb = ctrlb; | |
910 | ||
911 | desc->txd.cookie = 0; | |
912 | desc->len = len; | |
913 | ||
914 | return desc; | |
915 | } | |
916 | ||
4d112426 MR |
917 | /** |
918 | * atc_prep_dma_memset - prepare a memcpy operation | |
919 | * @chan: the channel to prepare operation on | |
920 | * @dest: operation virtual destination address | |
921 | * @value: value to set memory buffer to | |
922 | * @len: operation length | |
923 | * @flags: tx descriptor status flags | |
924 | */ | |
925 | static struct dma_async_tx_descriptor * | |
926 | atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, | |
927 | size_t len, unsigned long flags) | |
928 | { | |
4d112426 | 929 | struct at_dma *atdma = to_at_dma(chan->device); |
ce2a673d MR |
930 | struct at_desc *desc; |
931 | void __iomem *vaddr; | |
932 | dma_addr_t paddr; | |
4d112426 | 933 | |
2c5d7407 AB |
934 | dev_vdbg(chan2dev(chan), "%s: d%pad v0x%x l0x%zx f0x%lx\n", __func__, |
935 | &dest, value, len, flags); | |
4d112426 MR |
936 | |
937 | if (unlikely(!len)) { | |
938 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); | |
939 | return NULL; | |
940 | } | |
941 | ||
942 | if (!is_dma_fill_aligned(chan->device, dest, 0, len)) { | |
943 | dev_dbg(chan2dev(chan), "%s: buffer is not aligned\n", | |
944 | __func__); | |
945 | return NULL; | |
946 | } | |
947 | ||
ce2a673d MR |
948 | vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr); |
949 | if (!vaddr) { | |
950 | dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", | |
4d112426 MR |
951 | __func__); |
952 | return NULL; | |
953 | } | |
ce2a673d | 954 | *(u32*)vaddr = value; |
4d112426 | 955 | |
ce2a673d | 956 | desc = atc_create_memset_desc(chan, paddr, dest, len); |
4d112426 | 957 | if (!desc) { |
ce2a673d | 958 | dev_err(chan2dev(chan), "%s: couldn't get a descriptor\n", |
4d112426 | 959 | __func__); |
ce2a673d | 960 | goto err_free_buffer; |
4d112426 MR |
961 | } |
962 | ||
ce2a673d MR |
963 | desc->memset_paddr = paddr; |
964 | desc->memset_vaddr = vaddr; | |
965 | desc->memset_buffer = true; | |
4d112426 MR |
966 | |
967 | desc->txd.cookie = -EBUSY; | |
4d112426 MR |
968 | desc->total_len = len; |
969 | ||
970 | /* set end-of-link on the descriptor */ | |
971 | set_desc_eol(desc); | |
972 | ||
973 | desc->txd.flags = flags; | |
974 | ||
975 | return &desc->txd; | |
976 | ||
ce2a673d MR |
977 | err_free_buffer: |
978 | dma_pool_free(atdma->memset_pool, vaddr, paddr); | |
4d112426 MR |
979 | return NULL; |
980 | } | |
981 | ||
67d25f0d MR |
982 | static struct dma_async_tx_descriptor * |
983 | atc_prep_dma_memset_sg(struct dma_chan *chan, | |
984 | struct scatterlist *sgl, | |
985 | unsigned int sg_len, int value, | |
986 | unsigned long flags) | |
987 | { | |
988 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
989 | struct at_dma *atdma = to_at_dma(chan->device); | |
990 | struct at_desc *desc = NULL, *first = NULL, *prev = NULL; | |
991 | struct scatterlist *sg; | |
992 | void __iomem *vaddr; | |
993 | dma_addr_t paddr; | |
994 | size_t total_len = 0; | |
995 | int i; | |
996 | ||
997 | dev_vdbg(chan2dev(chan), "%s: v0x%x l0x%zx f0x%lx\n", __func__, | |
998 | value, sg_len, flags); | |
999 | ||
1000 | if (unlikely(!sgl || !sg_len)) { | |
1001 | dev_dbg(chan2dev(chan), "%s: scatterlist is empty!\n", | |
1002 | __func__); | |
1003 | return NULL; | |
1004 | } | |
1005 | ||
1006 | vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr); | |
1007 | if (!vaddr) { | |
1008 | dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", | |
1009 | __func__); | |
1010 | return NULL; | |
1011 | } | |
1012 | *(u32*)vaddr = value; | |
1013 | ||
1014 | for_each_sg(sgl, sg, sg_len, i) { | |
1015 | dma_addr_t dest = sg_dma_address(sg); | |
1016 | size_t len = sg_dma_len(sg); | |
1017 | ||
2c5d7407 AB |
1018 | dev_vdbg(chan2dev(chan), "%s: d%pad, l0x%zx\n", |
1019 | __func__, &dest, len); | |
67d25f0d MR |
1020 | |
1021 | if (!is_dma_fill_aligned(chan->device, dest, 0, len)) { | |
1022 | dev_err(chan2dev(chan), "%s: buffer is not aligned\n", | |
1023 | __func__); | |
1024 | goto err_put_desc; | |
1025 | } | |
1026 | ||
1027 | desc = atc_create_memset_desc(chan, paddr, dest, len); | |
1028 | if (!desc) | |
1029 | goto err_put_desc; | |
1030 | ||
1031 | atc_desc_chain(&first, &prev, desc); | |
1032 | ||
1033 | total_len += len; | |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * Only set the buffer pointers on the last descriptor to | |
1038 | * avoid free'ing while we have our transfer still going | |
1039 | */ | |
1040 | desc->memset_paddr = paddr; | |
1041 | desc->memset_vaddr = vaddr; | |
1042 | desc->memset_buffer = true; | |
1043 | ||
1044 | first->txd.cookie = -EBUSY; | |
1045 | first->total_len = total_len; | |
1046 | ||
1047 | /* set end-of-link on the descriptor */ | |
1048 | set_desc_eol(desc); | |
1049 | ||
1050 | first->txd.flags = flags; | |
1051 | ||
1052 | return &first->txd; | |
1053 | ||
1054 | err_put_desc: | |
1055 | atc_desc_put(atchan, first); | |
1056 | return NULL; | |
1057 | } | |
1058 | ||
808347f6 NF |
1059 | /** |
1060 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
1061 | * @chan: DMA channel | |
1062 | * @sgl: scatterlist to transfer to/from | |
1063 | * @sg_len: number of entries in @scatterlist | |
1064 | * @direction: DMA direction | |
1065 | * @flags: tx descriptor status flags | |
185ecb5f | 1066 | * @context: transaction context (ignored) |
808347f6 NF |
1067 | */ |
1068 | static struct dma_async_tx_descriptor * | |
1069 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 1070 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1071 | unsigned long flags, void *context) |
808347f6 NF |
1072 | { |
1073 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1074 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 1075 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
808347f6 NF |
1076 | struct at_desc *first = NULL; |
1077 | struct at_desc *prev = NULL; | |
1078 | u32 ctrla; | |
1079 | u32 ctrlb; | |
1080 | dma_addr_t reg; | |
1081 | unsigned int reg_width; | |
1082 | unsigned int mem_width; | |
1083 | unsigned int i; | |
1084 | struct scatterlist *sg; | |
1085 | size_t total_len = 0; | |
1086 | ||
cc52a10a NF |
1087 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
1088 | sg_len, | |
db8196df | 1089 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
808347f6 NF |
1090 | flags); |
1091 | ||
1092 | if (unlikely(!atslave || !sg_len)) { | |
c618a9be | 1093 | dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n"); |
808347f6 NF |
1094 | return NULL; |
1095 | } | |
1096 | ||
1dd1ea8e NF |
1097 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
1098 | | ATC_DCSIZE(sconfig->dst_maxburst); | |
ae14d4b5 | 1099 | ctrlb = ATC_IEN; |
808347f6 NF |
1100 | |
1101 | switch (direction) { | |
db8196df | 1102 | case DMA_MEM_TO_DEV: |
beeaa103 | 1103 | reg_width = convert_buswidth(sconfig->dst_addr_width); |
808347f6 NF |
1104 | ctrla |= ATC_DST_WIDTH(reg_width); |
1105 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
1106 | | ATC_SRC_ADDR_MODE_INCR | |
ae14d4b5 | 1107 | | ATC_FC_MEM2PER |
bbe89c8e | 1108 | | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if); |
beeaa103 | 1109 | reg = sconfig->dst_addr; |
808347f6 NF |
1110 | for_each_sg(sgl, sg, sg_len, i) { |
1111 | struct at_desc *desc; | |
1112 | u32 len; | |
1113 | u32 mem; | |
1114 | ||
1115 | desc = atc_desc_get(atchan); | |
1116 | if (!desc) | |
1117 | goto err_desc_get; | |
1118 | ||
0f70e8ce | 1119 | mem = sg_dma_address(sg); |
808347f6 | 1120 | len = sg_dma_len(sg); |
c4567976 NF |
1121 | if (unlikely(!len)) { |
1122 | dev_dbg(chan2dev(chan), | |
1123 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
1124 | goto err; | |
1125 | } | |
808347f6 NF |
1126 | mem_width = 2; |
1127 | if (unlikely(mem & 3 || len & 3)) | |
1128 | mem_width = 0; | |
1129 | ||
1130 | desc->lli.saddr = mem; | |
1131 | desc->lli.daddr = reg; | |
1132 | desc->lli.ctrla = ctrla | |
1133 | | ATC_SRC_WIDTH(mem_width) | |
1134 | | len >> mem_width; | |
1135 | desc->lli.ctrlb = ctrlb; | |
bdf6c792 | 1136 | desc->len = len; |
808347f6 | 1137 | |
e257e156 | 1138 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
1139 | total_len += len; |
1140 | } | |
1141 | break; | |
db8196df | 1142 | case DMA_DEV_TO_MEM: |
beeaa103 | 1143 | reg_width = convert_buswidth(sconfig->src_addr_width); |
808347f6 NF |
1144 | ctrla |= ATC_SRC_WIDTH(reg_width); |
1145 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
1146 | | ATC_SRC_ADDR_MODE_FIXED | |
ae14d4b5 | 1147 | | ATC_FC_PER2MEM |
bbe89c8e | 1148 | | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if); |
808347f6 | 1149 | |
beeaa103 | 1150 | reg = sconfig->src_addr; |
808347f6 NF |
1151 | for_each_sg(sgl, sg, sg_len, i) { |
1152 | struct at_desc *desc; | |
1153 | u32 len; | |
1154 | u32 mem; | |
1155 | ||
1156 | desc = atc_desc_get(atchan); | |
1157 | if (!desc) | |
1158 | goto err_desc_get; | |
1159 | ||
0f70e8ce | 1160 | mem = sg_dma_address(sg); |
808347f6 | 1161 | len = sg_dma_len(sg); |
c4567976 NF |
1162 | if (unlikely(!len)) { |
1163 | dev_dbg(chan2dev(chan), | |
1164 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
1165 | goto err; | |
1166 | } | |
808347f6 NF |
1167 | mem_width = 2; |
1168 | if (unlikely(mem & 3 || len & 3)) | |
1169 | mem_width = 0; | |
1170 | ||
1171 | desc->lli.saddr = reg; | |
1172 | desc->lli.daddr = mem; | |
1173 | desc->lli.ctrla = ctrla | |
1174 | | ATC_DST_WIDTH(mem_width) | |
59a609d9 | 1175 | | len >> reg_width; |
808347f6 | 1176 | desc->lli.ctrlb = ctrlb; |
bdf6c792 | 1177 | desc->len = len; |
808347f6 | 1178 | |
e257e156 | 1179 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
1180 | total_len += len; |
1181 | } | |
1182 | break; | |
1183 | default: | |
1184 | return NULL; | |
1185 | } | |
1186 | ||
1187 | /* set end-of-link to the last link descriptor of list*/ | |
1188 | set_desc_eol(prev); | |
1189 | ||
1190 | /* First descriptor of the chain embedds additional information */ | |
1191 | first->txd.cookie = -EBUSY; | |
bdf6c792 TF |
1192 | first->total_len = total_len; |
1193 | ||
568f7f0c NF |
1194 | /* first link descriptor of list is responsible of flags */ |
1195 | first->txd.flags = flags; /* client is in control of this ack */ | |
808347f6 NF |
1196 | |
1197 | return &first->txd; | |
1198 | ||
1199 | err_desc_get: | |
1200 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
c4567976 | 1201 | err: |
808347f6 NF |
1202 | atc_desc_put(atchan, first); |
1203 | return NULL; | |
1204 | } | |
1205 | ||
53830cc7 NF |
1206 | /** |
1207 | * atc_dma_cyclic_check_values | |
1208 | * Check for too big/unaligned periods and unaligned DMA buffer | |
1209 | */ | |
1210 | static int | |
1211 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
0e7264cc | 1212 | size_t period_len) |
53830cc7 NF |
1213 | { |
1214 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
1215 | goto err_out; | |
1216 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1217 | goto err_out; | |
1218 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1219 | goto err_out; | |
53830cc7 NF |
1220 | |
1221 | return 0; | |
1222 | ||
1223 | err_out: | |
1224 | return -EINVAL; | |
1225 | } | |
1226 | ||
1227 | /** | |
d73111c6 | 1228 | * atc_dma_cyclic_fill_desc - Fill one period descriptor |
53830cc7 NF |
1229 | */ |
1230 | static int | |
beeaa103 | 1231 | atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, |
53830cc7 | 1232 | unsigned int period_index, dma_addr_t buf_addr, |
beeaa103 NF |
1233 | unsigned int reg_width, size_t period_len, |
1234 | enum dma_transfer_direction direction) | |
53830cc7 | 1235 | { |
beeaa103 | 1236 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
beeaa103 NF |
1237 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
1238 | u32 ctrla; | |
53830cc7 NF |
1239 | |
1240 | /* prepare common CRTLA value */ | |
1dd1ea8e NF |
1241 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
1242 | | ATC_DCSIZE(sconfig->dst_maxburst) | |
53830cc7 NF |
1243 | | ATC_DST_WIDTH(reg_width) |
1244 | | ATC_SRC_WIDTH(reg_width) | |
1245 | | period_len >> reg_width; | |
1246 | ||
1247 | switch (direction) { | |
db8196df | 1248 | case DMA_MEM_TO_DEV: |
53830cc7 | 1249 | desc->lli.saddr = buf_addr + (period_len * period_index); |
beeaa103 | 1250 | desc->lli.daddr = sconfig->dst_addr; |
53830cc7 | 1251 | desc->lli.ctrla = ctrla; |
ae14d4b5 | 1252 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED |
53830cc7 | 1253 | | ATC_SRC_ADDR_MODE_INCR |
ae14d4b5 | 1254 | | ATC_FC_MEM2PER |
bbe89c8e LD |
1255 | | ATC_SIF(atchan->mem_if) |
1256 | | ATC_DIF(atchan->per_if); | |
bdf6c792 | 1257 | desc->len = period_len; |
53830cc7 NF |
1258 | break; |
1259 | ||
db8196df | 1260 | case DMA_DEV_TO_MEM: |
beeaa103 | 1261 | desc->lli.saddr = sconfig->src_addr; |
53830cc7 NF |
1262 | desc->lli.daddr = buf_addr + (period_len * period_index); |
1263 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 1264 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR |
53830cc7 | 1265 | | ATC_SRC_ADDR_MODE_FIXED |
ae14d4b5 | 1266 | | ATC_FC_PER2MEM |
bbe89c8e LD |
1267 | | ATC_SIF(atchan->per_if) |
1268 | | ATC_DIF(atchan->mem_if); | |
bdf6c792 | 1269 | desc->len = period_len; |
53830cc7 NF |
1270 | break; |
1271 | ||
1272 | default: | |
1273 | return -EINVAL; | |
1274 | } | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | /** | |
1280 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
1281 | * @chan: the DMA channel to prepare | |
1282 | * @buf_addr: physical DMA address where the buffer starts | |
1283 | * @buf_len: total number of bytes for the entire buffer | |
1284 | * @period_len: number of bytes for each period | |
1285 | * @direction: transfer direction, to or from device | |
ec8b5e48 | 1286 | * @flags: tx descriptor status flags |
53830cc7 NF |
1287 | */ |
1288 | static struct dma_async_tx_descriptor * | |
1289 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 1290 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 1291 | unsigned long flags) |
53830cc7 NF |
1292 | { |
1293 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1294 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 1295 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
53830cc7 NF |
1296 | struct at_desc *first = NULL; |
1297 | struct at_desc *prev = NULL; | |
1298 | unsigned long was_cyclic; | |
beeaa103 | 1299 | unsigned int reg_width; |
53830cc7 NF |
1300 | unsigned int periods = buf_len / period_len; |
1301 | unsigned int i; | |
1302 | ||
2c5d7407 | 1303 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@%pad - %d (%d/%d)\n", |
db8196df | 1304 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
2c5d7407 | 1305 | &buf_addr, |
53830cc7 NF |
1306 | periods, buf_len, period_len); |
1307 | ||
1308 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
1309 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
1310 | return NULL; | |
1311 | } | |
1312 | ||
1313 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
1314 | if (was_cyclic) { | |
1315 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
1316 | return NULL; | |
1317 | } | |
1318 | ||
0e7264cc AS |
1319 | if (unlikely(!is_slave_direction(direction))) |
1320 | goto err_out; | |
1321 | ||
62355887 | 1322 | if (direction == DMA_MEM_TO_DEV) |
beeaa103 NF |
1323 | reg_width = convert_buswidth(sconfig->dst_addr_width); |
1324 | else | |
1325 | reg_width = convert_buswidth(sconfig->src_addr_width); | |
1326 | ||
53830cc7 | 1327 | /* Check for too big/unaligned periods and unaligned DMA buffer */ |
0e7264cc | 1328 | if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len)) |
53830cc7 NF |
1329 | goto err_out; |
1330 | ||
1331 | /* build cyclic linked list */ | |
1332 | for (i = 0; i < periods; i++) { | |
1333 | struct at_desc *desc; | |
1334 | ||
1335 | desc = atc_desc_get(atchan); | |
1336 | if (!desc) | |
1337 | goto err_desc_get; | |
1338 | ||
beeaa103 NF |
1339 | if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr, |
1340 | reg_width, period_len, direction)) | |
53830cc7 NF |
1341 | goto err_desc_get; |
1342 | ||
1343 | atc_desc_chain(&first, &prev, desc); | |
1344 | } | |
1345 | ||
1346 | /* lets make a cyclic list */ | |
1347 | prev->lli.dscr = first->txd.phys; | |
1348 | ||
1349 | /* First descriptor of the chain embedds additional information */ | |
1350 | first->txd.cookie = -EBUSY; | |
bdf6c792 | 1351 | first->total_len = buf_len; |
53830cc7 NF |
1352 | |
1353 | return &first->txd; | |
1354 | ||
1355 | err_desc_get: | |
1356 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
1357 | atc_desc_put(atchan, first); | |
1358 | err_out: | |
1359 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1360 | return NULL; | |
1361 | } | |
1362 | ||
4facfe7f MR |
1363 | static int atc_config(struct dma_chan *chan, |
1364 | struct dma_slave_config *sconfig) | |
beeaa103 NF |
1365 | { |
1366 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1367 | ||
4facfe7f MR |
1368 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
1369 | ||
beeaa103 NF |
1370 | /* Check if it is chan is configured for slave transfers */ |
1371 | if (!chan->private) | |
1372 | return -EINVAL; | |
1373 | ||
1374 | memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig)); | |
1375 | ||
1376 | convert_burst(&atchan->dma_sconfig.src_maxburst); | |
1377 | convert_burst(&atchan->dma_sconfig.dst_maxburst); | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
4facfe7f MR |
1382 | static int atc_pause(struct dma_chan *chan) |
1383 | { | |
1384 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1385 | struct at_dma *atdma = to_at_dma(chan->device); | |
1386 | int chan_id = atchan->chan_common.chan_id; | |
1387 | unsigned long flags; | |
53830cc7 | 1388 | |
4facfe7f MR |
1389 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
1390 | ||
1391 | spin_lock_irqsave(&atchan->lock, flags); | |
1392 | ||
1393 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); | |
1394 | set_bit(ATC_IS_PAUSED, &atchan->status); | |
1395 | ||
1396 | spin_unlock_irqrestore(&atchan->lock, flags); | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | static int atc_resume(struct dma_chan *chan) | |
808347f6 NF |
1402 | { |
1403 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1404 | struct at_dma *atdma = to_at_dma(chan->device); | |
23b5e3ad | 1405 | int chan_id = atchan->chan_common.chan_id; |
d8cb04b0 | 1406 | unsigned long flags; |
23b5e3ad | 1407 | |
4facfe7f | 1408 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
c3635c78 | 1409 | |
4facfe7f MR |
1410 | if (!atc_chan_is_paused(atchan)) |
1411 | return 0; | |
808347f6 | 1412 | |
4facfe7f | 1413 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 1414 | |
4facfe7f MR |
1415 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
1416 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
808347f6 | 1417 | |
4facfe7f | 1418 | spin_unlock_irqrestore(&atchan->lock, flags); |
808347f6 | 1419 | |
4facfe7f MR |
1420 | return 0; |
1421 | } | |
c3635c78 | 1422 | |
4facfe7f MR |
1423 | static int atc_terminate_all(struct dma_chan *chan) |
1424 | { | |
1425 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1426 | struct at_dma *atdma = to_at_dma(chan->device); | |
1427 | int chan_id = atchan->chan_common.chan_id; | |
1428 | struct at_desc *desc, *_desc; | |
1429 | unsigned long flags; | |
23b5e3ad | 1430 | |
4facfe7f | 1431 | LIST_HEAD(list); |
23b5e3ad | 1432 | |
4facfe7f | 1433 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
23b5e3ad | 1434 | |
4facfe7f MR |
1435 | /* |
1436 | * This is only called when something went wrong elsewhere, so | |
1437 | * we don't really care about the data. Just disable the | |
1438 | * channel. We still have to poll the channel enable bit due | |
1439 | * to AHB/HSB limitations. | |
1440 | */ | |
1441 | spin_lock_irqsave(&atchan->lock, flags); | |
23b5e3ad | 1442 | |
4facfe7f MR |
1443 | /* disabling channel: must also remove suspend state */ |
1444 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
23b5e3ad | 1445 | |
4facfe7f MR |
1446 | /* confirm that this channel is disabled */ |
1447 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
1448 | cpu_relax(); | |
23b5e3ad | 1449 | |
4facfe7f MR |
1450 | /* active_list entries will end up before queued entries */ |
1451 | list_splice_init(&atchan->queue, &list); | |
1452 | list_splice_init(&atchan->active_list, &list); | |
1453 | ||
1454 | /* Flush all pending and queued descriptors */ | |
1455 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1456 | atc_chain_complete(atchan, desc); | |
1457 | ||
1458 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
1459 | /* if channel dedicated to cyclic operations, free it */ | |
1460 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1461 | ||
1462 | spin_unlock_irqrestore(&atchan->lock, flags); | |
b0ebeb9c | 1463 | |
c3635c78 | 1464 | return 0; |
808347f6 NF |
1465 | } |
1466 | ||
dc78baa2 | 1467 | /** |
07934481 | 1468 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
1469 | * @chan: DMA channel |
1470 | * @cookie: transaction identifier to check status of | |
07934481 | 1471 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 1472 | * |
07934481 | 1473 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
1474 | * internal state and can be used with dma_async_is_complete() to check |
1475 | * the status of multiple cookies without re-checking hardware state. | |
1476 | */ | |
1477 | static enum dma_status | |
07934481 | 1478 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 1479 | dma_cookie_t cookie, |
07934481 | 1480 | struct dma_tx_state *txstate) |
dc78baa2 NF |
1481 | { |
1482 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1483 | unsigned long flags; |
dc78baa2 | 1484 | enum dma_status ret; |
d48de6f1 | 1485 | int bytes = 0; |
dc78baa2 | 1486 | |
96a2af41 | 1487 | ret = dma_cookie_status(chan, cookie, txstate); |
6d203d1e | 1488 | if (ret == DMA_COMPLETE) |
d48de6f1 ES |
1489 | return ret; |
1490 | /* | |
1491 | * There's no point calculating the residue if there's | |
1492 | * no txstate to store the value. | |
1493 | */ | |
1494 | if (!txstate) | |
1495 | return DMA_ERROR; | |
dc78baa2 | 1496 | |
d48de6f1 | 1497 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1498 | |
d48de6f1 | 1499 | /* Get number of bytes left in the active transactions */ |
bdf6c792 | 1500 | bytes = atc_get_bytes_left(chan, cookie); |
96a2af41 | 1501 | |
d8cb04b0 | 1502 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 | 1503 | |
d48de6f1 ES |
1504 | if (unlikely(bytes < 0)) { |
1505 | dev_vdbg(chan2dev(chan), "get residual bytes error\n"); | |
1506 | return DMA_ERROR; | |
c3dbc60c | 1507 | } else { |
d48de6f1 | 1508 | dma_set_residue(txstate, bytes); |
c3dbc60c | 1509 | } |
23b5e3ad | 1510 | |
d48de6f1 ES |
1511 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n", |
1512 | ret, cookie, bytes); | |
dc78baa2 NF |
1513 | |
1514 | return ret; | |
1515 | } | |
1516 | ||
1517 | /** | |
1518 | * atc_issue_pending - try to finish work | |
1519 | * @chan: target DMA channel | |
1520 | */ | |
1521 | static void atc_issue_pending(struct dma_chan *chan) | |
1522 | { | |
1523 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1524 | unsigned long flags; |
dc78baa2 NF |
1525 | |
1526 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
1527 | ||
53830cc7 | 1528 | /* Not needed for cyclic transfers */ |
3c477482 | 1529 | if (atc_chan_is_cyclic(atchan)) |
53830cc7 NF |
1530 | return; |
1531 | ||
d8cb04b0 | 1532 | spin_lock_irqsave(&atchan->lock, flags); |
d202f051 | 1533 | atc_advance_work(atchan); |
d8cb04b0 | 1534 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1535 | } |
1536 | ||
1537 | /** | |
1538 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1539 | * @chan: allocate descriptor resources for this channel | |
1540 | * @client: current client requesting the channel be ready for requests | |
1541 | * | |
1542 | * return - the number of allocated descriptors | |
1543 | */ | |
1544 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1545 | { | |
1546 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1547 | struct at_dma *atdma = to_at_dma(chan->device); | |
1548 | struct at_desc *desc; | |
808347f6 | 1549 | struct at_dma_slave *atslave; |
d8cb04b0 | 1550 | unsigned long flags; |
dc78baa2 | 1551 | int i; |
808347f6 | 1552 | u32 cfg; |
dc78baa2 NF |
1553 | LIST_HEAD(tmp_list); |
1554 | ||
1555 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1556 | ||
1557 | /* ASSERT: channel is idle */ | |
1558 | if (atc_chan_is_enabled(atchan)) { | |
1559 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1560 | return -EIO; | |
1561 | } | |
1562 | ||
808347f6 NF |
1563 | cfg = ATC_DEFAULT_CFG; |
1564 | ||
1565 | atslave = chan->private; | |
1566 | if (atslave) { | |
1567 | /* | |
1568 | * We need controller-specific data to set up slave | |
1569 | * transfers. | |
1570 | */ | |
1571 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
1572 | ||
ea7e7906 | 1573 | /* if cfg configuration specified take it instead of default */ |
808347f6 NF |
1574 | if (atslave->cfg) |
1575 | cfg = atslave->cfg; | |
1576 | } | |
1577 | ||
1578 | /* have we already been set up? | |
1579 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
1580 | if (!list_empty(&atchan->free_list)) |
1581 | return atchan->descs_allocated; | |
1582 | ||
1583 | /* Allocate initial pool of descriptors */ | |
1584 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1585 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
1586 | if (!desc) { | |
1587 | dev_err(atdma->dma_common.dev, | |
1588 | "Only %d initial descriptors\n", i); | |
1589 | break; | |
1590 | } | |
1591 | list_add_tail(&desc->desc_node, &tmp_list); | |
1592 | } | |
1593 | ||
d8cb04b0 | 1594 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
1595 | atchan->descs_allocated = i; |
1596 | list_splice(&tmp_list, &atchan->free_list); | |
d3ee98cd | 1597 | dma_cookie_init(chan); |
d8cb04b0 | 1598 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1599 | |
1600 | /* channel parameters */ | |
808347f6 | 1601 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
1602 | |
1603 | dev_dbg(chan2dev(chan), | |
1604 | "alloc_chan_resources: allocated %d descriptors\n", | |
1605 | atchan->descs_allocated); | |
1606 | ||
1607 | return atchan->descs_allocated; | |
1608 | } | |
1609 | ||
1610 | /** | |
1611 | * atc_free_chan_resources - free all channel resources | |
1612 | * @chan: DMA channel | |
1613 | */ | |
1614 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1615 | { | |
1616 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1617 | struct at_dma *atdma = to_at_dma(chan->device); | |
1618 | struct at_desc *desc, *_desc; | |
1619 | LIST_HEAD(list); | |
1620 | ||
1621 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
1622 | atchan->descs_allocated); | |
1623 | ||
1624 | /* ASSERT: channel is idle */ | |
1625 | BUG_ON(!list_empty(&atchan->active_list)); | |
1626 | BUG_ON(!list_empty(&atchan->queue)); | |
1627 | BUG_ON(atc_chan_is_enabled(atchan)); | |
1628 | ||
1629 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
1630 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
1631 | list_del(&desc->desc_node); | |
1632 | /* free link descriptor */ | |
1633 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
1634 | } | |
1635 | list_splice_init(&atchan->free_list, &list); | |
1636 | atchan->descs_allocated = 0; | |
53830cc7 | 1637 | atchan->status = 0; |
dc78baa2 | 1638 | |
98f5f932 RG |
1639 | /* |
1640 | * Free atslave allocated in at_dma_xlate() | |
1641 | */ | |
1642 | kfree(chan->private); | |
1643 | chan->private = NULL; | |
1644 | ||
dc78baa2 NF |
1645 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); |
1646 | } | |
1647 | ||
bbe89c8e LD |
1648 | #ifdef CONFIG_OF |
1649 | static bool at_dma_filter(struct dma_chan *chan, void *slave) | |
1650 | { | |
1651 | struct at_dma_slave *atslave = slave; | |
1652 | ||
1653 | if (atslave->dma_dev == chan->device->dev) { | |
1654 | chan->private = atslave; | |
1655 | return true; | |
1656 | } else { | |
1657 | return false; | |
1658 | } | |
1659 | } | |
1660 | ||
1661 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1662 | struct of_dma *of_dma) | |
1663 | { | |
1664 | struct dma_chan *chan; | |
1665 | struct at_dma_chan *atchan; | |
1666 | struct at_dma_slave *atslave; | |
1667 | dma_cap_mask_t mask; | |
1668 | unsigned int per_id; | |
1669 | struct platform_device *dmac_pdev; | |
1670 | ||
1671 | if (dma_spec->args_count != 2) | |
1672 | return NULL; | |
1673 | ||
1674 | dmac_pdev = of_find_device_by_node(dma_spec->np); | |
1675 | ||
1676 | dma_cap_zero(mask); | |
1677 | dma_cap_set(DMA_SLAVE, mask); | |
1678 | ||
98f5f932 | 1679 | atslave = kzalloc(sizeof(*atslave), GFP_KERNEL); |
bbe89c8e LD |
1680 | if (!atslave) |
1681 | return NULL; | |
62971b29 LD |
1682 | |
1683 | atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW; | |
bbe89c8e LD |
1684 | /* |
1685 | * We can fill both SRC_PER and DST_PER, one of these fields will be | |
1686 | * ignored depending on DMA transfer direction. | |
1687 | */ | |
62971b29 LD |
1688 | per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK; |
1689 | atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id) | |
6c22770f | 1690 | | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id); |
62971b29 LD |
1691 | /* |
1692 | * We have to translate the value we get from the device tree since | |
1693 | * the half FIFO configuration value had to be 0 to keep backward | |
1694 | * compatibility. | |
1695 | */ | |
1696 | switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) { | |
1697 | case AT91_DMA_CFG_FIFOCFG_ALAP: | |
1698 | atslave->cfg |= ATC_FIFOCFG_LARGESTBURST; | |
1699 | break; | |
1700 | case AT91_DMA_CFG_FIFOCFG_ASAP: | |
1701 | atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE; | |
1702 | break; | |
1703 | case AT91_DMA_CFG_FIFOCFG_HALF: | |
1704 | default: | |
1705 | atslave->cfg |= ATC_FIFOCFG_HALFFIFO; | |
1706 | } | |
bbe89c8e LD |
1707 | atslave->dma_dev = &dmac_pdev->dev; |
1708 | ||
1709 | chan = dma_request_channel(mask, at_dma_filter, atslave); | |
1710 | if (!chan) | |
1711 | return NULL; | |
1712 | ||
1713 | atchan = to_at_dma_chan(chan); | |
1714 | atchan->per_if = dma_spec->args[0] & 0xff; | |
1715 | atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff; | |
1716 | ||
1717 | return chan; | |
1718 | } | |
1719 | #else | |
1720 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1721 | struct of_dma *of_dma) | |
1722 | { | |
1723 | return NULL; | |
1724 | } | |
1725 | #endif | |
dc78baa2 NF |
1726 | |
1727 | /*-- Module Management -----------------------------------------------*/ | |
1728 | ||
02f88be9 NF |
1729 | /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ |
1730 | static struct at_dma_platform_data at91sam9rl_config = { | |
1731 | .nr_channels = 2, | |
1732 | }; | |
1733 | static struct at_dma_platform_data at91sam9g45_config = { | |
1734 | .nr_channels = 8, | |
1735 | }; | |
1736 | ||
c5115953 NF |
1737 | #if defined(CONFIG_OF) |
1738 | static const struct of_device_id atmel_dma_dt_ids[] = { | |
1739 | { | |
1740 | .compatible = "atmel,at91sam9rl-dma", | |
02f88be9 | 1741 | .data = &at91sam9rl_config, |
c5115953 NF |
1742 | }, { |
1743 | .compatible = "atmel,at91sam9g45-dma", | |
02f88be9 | 1744 | .data = &at91sam9g45_config, |
dcc81734 NF |
1745 | }, { |
1746 | /* sentinel */ | |
1747 | } | |
c5115953 NF |
1748 | }; |
1749 | ||
1750 | MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); | |
1751 | #endif | |
1752 | ||
0ab88a01 | 1753 | static const struct platform_device_id atdma_devtypes[] = { |
67348450 NF |
1754 | { |
1755 | .name = "at91sam9rl_dma", | |
02f88be9 | 1756 | .driver_data = (unsigned long) &at91sam9rl_config, |
67348450 NF |
1757 | }, { |
1758 | .name = "at91sam9g45_dma", | |
02f88be9 | 1759 | .driver_data = (unsigned long) &at91sam9g45_config, |
67348450 NF |
1760 | }, { |
1761 | /* sentinel */ | |
1762 | } | |
1763 | }; | |
1764 | ||
7fd63ccd | 1765 | static inline const struct at_dma_platform_data * __init at_dma_get_driver_data( |
02f88be9 | 1766 | struct platform_device *pdev) |
c5115953 NF |
1767 | { |
1768 | if (pdev->dev.of_node) { | |
1769 | const struct of_device_id *match; | |
1770 | match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); | |
1771 | if (match == NULL) | |
02f88be9 NF |
1772 | return NULL; |
1773 | return match->data; | |
c5115953 | 1774 | } |
02f88be9 NF |
1775 | return (struct at_dma_platform_data *) |
1776 | platform_get_device_id(pdev)->driver_data; | |
c5115953 NF |
1777 | } |
1778 | ||
dc78baa2 NF |
1779 | /** |
1780 | * at_dma_off - disable DMA controller | |
1781 | * @atdma: the Atmel HDAMC device | |
1782 | */ | |
1783 | static void at_dma_off(struct at_dma *atdma) | |
1784 | { | |
1785 | dma_writel(atdma, EN, 0); | |
1786 | ||
1787 | /* disable all interrupts */ | |
1788 | dma_writel(atdma, EBCIDR, -1L); | |
1789 | ||
1790 | /* confirm that all channels are disabled */ | |
1791 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1792 | cpu_relax(); | |
1793 | } | |
1794 | ||
1795 | static int __init at_dma_probe(struct platform_device *pdev) | |
1796 | { | |
dc78baa2 NF |
1797 | struct resource *io; |
1798 | struct at_dma *atdma; | |
1799 | size_t size; | |
1800 | int irq; | |
1801 | int err; | |
1802 | int i; | |
7fd63ccd | 1803 | const struct at_dma_platform_data *plat_dat; |
67348450 | 1804 | |
02f88be9 NF |
1805 | /* setup platform data for each SoC */ |
1806 | dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); | |
5abecfa5 | 1807 | dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask); |
02f88be9 | 1808 | dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); |
4d112426 | 1809 | dma_cap_set(DMA_MEMSET, at91sam9g45_config.cap_mask); |
67d25f0d | 1810 | dma_cap_set(DMA_MEMSET_SG, at91sam9g45_config.cap_mask); |
4d112426 | 1811 | dma_cap_set(DMA_PRIVATE, at91sam9g45_config.cap_mask); |
02f88be9 | 1812 | dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); |
67348450 NF |
1813 | |
1814 | /* get DMA parameters from controller type */ | |
02f88be9 NF |
1815 | plat_dat = at_dma_get_driver_data(pdev); |
1816 | if (!plat_dat) | |
1817 | return -ENODEV; | |
dc78baa2 NF |
1818 | |
1819 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1820 | if (!io) | |
1821 | return -EINVAL; | |
1822 | ||
1823 | irq = platform_get_irq(pdev, 0); | |
1824 | if (irq < 0) | |
1825 | return irq; | |
1826 | ||
1827 | size = sizeof(struct at_dma); | |
02f88be9 | 1828 | size += plat_dat->nr_channels * sizeof(struct at_dma_chan); |
dc78baa2 NF |
1829 | atdma = kzalloc(size, GFP_KERNEL); |
1830 | if (!atdma) | |
1831 | return -ENOMEM; | |
1832 | ||
67348450 | 1833 | /* discover transaction capabilities */ |
02f88be9 NF |
1834 | atdma->dma_common.cap_mask = plat_dat->cap_mask; |
1835 | atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; | |
dc78baa2 | 1836 | |
114df7d6 | 1837 | size = resource_size(io); |
dc78baa2 NF |
1838 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { |
1839 | err = -EBUSY; | |
1840 | goto err_kfree; | |
1841 | } | |
1842 | ||
1843 | atdma->regs = ioremap(io->start, size); | |
1844 | if (!atdma->regs) { | |
1845 | err = -ENOMEM; | |
1846 | goto err_release_r; | |
1847 | } | |
1848 | ||
1849 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1850 | if (IS_ERR(atdma->clk)) { | |
1851 | err = PTR_ERR(atdma->clk); | |
1852 | goto err_clk; | |
1853 | } | |
f784d9c9 BB |
1854 | err = clk_prepare_enable(atdma->clk); |
1855 | if (err) | |
1856 | goto err_clk_prepare; | |
dc78baa2 NF |
1857 | |
1858 | /* force dma off, just in case */ | |
1859 | at_dma_off(atdma); | |
1860 | ||
1861 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1862 | if (err) | |
1863 | goto err_irq; | |
1864 | ||
1865 | platform_set_drvdata(pdev, atdma); | |
1866 | ||
1867 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1868 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1869 | &pdev->dev, sizeof(struct at_desc), | |
1870 | 4 /* word alignment */, 0); | |
1871 | if (!atdma->dma_desc_pool) { | |
1872 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1873 | err = -ENOMEM; | |
4d112426 MR |
1874 | goto err_desc_pool_create; |
1875 | } | |
1876 | ||
1877 | /* create a pool of consistent memory blocks for memset blocks */ | |
1878 | atdma->memset_pool = dma_pool_create("at_hdmac_memset_pool", | |
1879 | &pdev->dev, sizeof(int), 4, 0); | |
1880 | if (!atdma->memset_pool) { | |
1881 | dev_err(&pdev->dev, "No memory for memset dma pool\n"); | |
1882 | err = -ENOMEM; | |
1883 | goto err_memset_pool_create; | |
dc78baa2 NF |
1884 | } |
1885 | ||
1886 | /* clear any pending interrupt */ | |
1887 | while (dma_readl(atdma, EBCISR)) | |
1888 | cpu_relax(); | |
1889 | ||
1890 | /* initialize channels related values */ | |
1891 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
02f88be9 | 1892 | for (i = 0; i < plat_dat->nr_channels; i++) { |
dc78baa2 NF |
1893 | struct at_dma_chan *atchan = &atdma->chan[i]; |
1894 | ||
bbe89c8e LD |
1895 | atchan->mem_if = AT_DMA_MEM_IF; |
1896 | atchan->per_if = AT_DMA_PER_IF; | |
dc78baa2 | 1897 | atchan->chan_common.device = &atdma->dma_common; |
d3ee98cd | 1898 | dma_cookie_init(&atchan->chan_common); |
dc78baa2 NF |
1899 | list_add_tail(&atchan->chan_common.device_node, |
1900 | &atdma->dma_common.channels); | |
1901 | ||
1902 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1903 | spin_lock_init(&atchan->lock); | |
1904 | atchan->mask = 1 << i; | |
1905 | ||
1906 | INIT_LIST_HEAD(&atchan->active_list); | |
1907 | INIT_LIST_HEAD(&atchan->queue); | |
1908 | INIT_LIST_HEAD(&atchan->free_list); | |
1909 | ||
1910 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1911 | (unsigned long)atchan); | |
bda3a47c | 1912 | atc_enable_chan_irq(atdma, i); |
dc78baa2 NF |
1913 | } |
1914 | ||
1915 | /* set base routines */ | |
1916 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1917 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1918 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1919 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1920 | atdma->dma_common.dev = &pdev->dev; | |
1921 | ||
1922 | /* set prep routines based on capability */ | |
5abecfa5 MR |
1923 | if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_common.cap_mask)) |
1924 | atdma->dma_common.device_prep_interleaved_dma = atc_prep_dma_interleaved; | |
1925 | ||
dc78baa2 NF |
1926 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) |
1927 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1928 | ||
4d112426 MR |
1929 | if (dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask)) { |
1930 | atdma->dma_common.device_prep_dma_memset = atc_prep_dma_memset; | |
67d25f0d | 1931 | atdma->dma_common.device_prep_dma_memset_sg = atc_prep_dma_memset_sg; |
4d112426 MR |
1932 | atdma->dma_common.fill_align = DMAENGINE_ALIGN_4_BYTES; |
1933 | } | |
1934 | ||
d7db8080 | 1935 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { |
808347f6 | 1936 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; |
d7db8080 NF |
1937 | /* controller can do slave DMA: can trigger cyclic transfers */ |
1938 | dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); | |
53830cc7 | 1939 | atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; |
4facfe7f MR |
1940 | atdma->dma_common.device_config = atc_config; |
1941 | atdma->dma_common.device_pause = atc_pause; | |
1942 | atdma->dma_common.device_resume = atc_resume; | |
1943 | atdma->dma_common.device_terminate_all = atc_terminate_all; | |
816070ed LD |
1944 | atdma->dma_common.src_addr_widths = ATC_DMA_BUSWIDTHS; |
1945 | atdma->dma_common.dst_addr_widths = ATC_DMA_BUSWIDTHS; | |
1946 | atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
1947 | atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
d7db8080 | 1948 | } |
808347f6 | 1949 | |
dc78baa2 NF |
1950 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
1951 | ||
c678fa66 | 1952 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n", |
dc78baa2 | 1953 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", |
4d112426 | 1954 | dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask) ? "set " : "", |
dc78baa2 | 1955 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", |
02f88be9 | 1956 | plat_dat->nr_channels); |
dc78baa2 NF |
1957 | |
1958 | dma_async_device_register(&atdma->dma_common); | |
1959 | ||
bbe89c8e LD |
1960 | /* |
1961 | * Do not return an error if the dmac node is not present in order to | |
1962 | * not break the existing way of requesting channel with | |
1963 | * dma_request_channel(). | |
1964 | */ | |
1965 | if (pdev->dev.of_node) { | |
1966 | err = of_dma_controller_register(pdev->dev.of_node, | |
1967 | at_dma_xlate, atdma); | |
1968 | if (err) { | |
1969 | dev_err(&pdev->dev, "could not register of_dma_controller\n"); | |
1970 | goto err_of_dma_controller_register; | |
1971 | } | |
1972 | } | |
1973 | ||
dc78baa2 NF |
1974 | return 0; |
1975 | ||
bbe89c8e LD |
1976 | err_of_dma_controller_register: |
1977 | dma_async_device_unregister(&atdma->dma_common); | |
4d112426 MR |
1978 | dma_pool_destroy(atdma->memset_pool); |
1979 | err_memset_pool_create: | |
bbe89c8e | 1980 | dma_pool_destroy(atdma->dma_desc_pool); |
4d112426 | 1981 | err_desc_pool_create: |
dc78baa2 NF |
1982 | free_irq(platform_get_irq(pdev, 0), atdma); |
1983 | err_irq: | |
f784d9c9 BB |
1984 | clk_disable_unprepare(atdma->clk); |
1985 | err_clk_prepare: | |
dc78baa2 NF |
1986 | clk_put(atdma->clk); |
1987 | err_clk: | |
1988 | iounmap(atdma->regs); | |
1989 | atdma->regs = NULL; | |
1990 | err_release_r: | |
1991 | release_mem_region(io->start, size); | |
1992 | err_kfree: | |
1993 | kfree(atdma); | |
1994 | return err; | |
1995 | } | |
1996 | ||
1d1bbd30 | 1997 | static int at_dma_remove(struct platform_device *pdev) |
dc78baa2 NF |
1998 | { |
1999 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
2000 | struct dma_chan *chan, *_chan; | |
2001 | struct resource *io; | |
2002 | ||
2003 | at_dma_off(atdma); | |
77e75fda RG |
2004 | if (pdev->dev.of_node) |
2005 | of_dma_controller_free(pdev->dev.of_node); | |
dc78baa2 NF |
2006 | dma_async_device_unregister(&atdma->dma_common); |
2007 | ||
4d112426 | 2008 | dma_pool_destroy(atdma->memset_pool); |
dc78baa2 | 2009 | dma_pool_destroy(atdma->dma_desc_pool); |
dc78baa2 NF |
2010 | free_irq(platform_get_irq(pdev, 0), atdma); |
2011 | ||
2012 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2013 | device_node) { | |
2014 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2015 | ||
2016 | /* Disable interrupts */ | |
bda3a47c | 2017 | atc_disable_chan_irq(atdma, chan->chan_id); |
dc78baa2 NF |
2018 | |
2019 | tasklet_kill(&atchan->tasklet); | |
2020 | list_del(&chan->device_node); | |
2021 | } | |
2022 | ||
f784d9c9 | 2023 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2024 | clk_put(atdma->clk); |
2025 | ||
2026 | iounmap(atdma->regs); | |
2027 | atdma->regs = NULL; | |
2028 | ||
2029 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
114df7d6 | 2030 | release_mem_region(io->start, resource_size(io)); |
dc78baa2 NF |
2031 | |
2032 | kfree(atdma); | |
2033 | ||
2034 | return 0; | |
2035 | } | |
2036 | ||
2037 | static void at_dma_shutdown(struct platform_device *pdev) | |
2038 | { | |
2039 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
2040 | ||
2041 | at_dma_off(platform_get_drvdata(pdev)); | |
f784d9c9 | 2042 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2043 | } |
2044 | ||
c0ba5947 NF |
2045 | static int at_dma_prepare(struct device *dev) |
2046 | { | |
5c4a74a4 | 2047 | struct at_dma *atdma = dev_get_drvdata(dev); |
c0ba5947 NF |
2048 | struct dma_chan *chan, *_chan; |
2049 | ||
2050 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2051 | device_node) { | |
2052 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2053 | /* wait for transaction completion (except in cyclic case) */ | |
3c477482 | 2054 | if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2055 | return -EAGAIN; |
2056 | } | |
2057 | return 0; | |
2058 | } | |
2059 | ||
2060 | static void atc_suspend_cyclic(struct at_dma_chan *atchan) | |
2061 | { | |
2062 | struct dma_chan *chan = &atchan->chan_common; | |
2063 | ||
2064 | /* Channel should be paused by user | |
2065 | * do it anyway even if it is not done already */ | |
3c477482 | 2066 | if (!atc_chan_is_paused(atchan)) { |
c0ba5947 NF |
2067 | dev_warn(chan2dev(chan), |
2068 | "cyclic channel not paused, should be done by channel user\n"); | |
4facfe7f | 2069 | atc_pause(chan); |
c0ba5947 NF |
2070 | } |
2071 | ||
2072 | /* now preserve additional data for cyclic operations */ | |
2073 | /* next descriptor address in the cyclic list */ | |
2074 | atchan->save_dscr = channel_readl(atchan, DSCR); | |
2075 | ||
2076 | vdbg_dump_regs(atchan); | |
2077 | } | |
2078 | ||
33f82d14 | 2079 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 2080 | { |
5c4a74a4 | 2081 | struct at_dma *atdma = dev_get_drvdata(dev); |
c0ba5947 | 2082 | struct dma_chan *chan, *_chan; |
dc78baa2 | 2083 | |
c0ba5947 NF |
2084 | /* preserve data */ |
2085 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2086 | device_node) { | |
2087 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2088 | ||
3c477482 | 2089 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2090 | atc_suspend_cyclic(atchan); |
2091 | atchan->save_cfg = channel_readl(atchan, CFG); | |
2092 | } | |
2093 | atdma->save_imr = dma_readl(atdma, EBCIMR); | |
2094 | ||
2095 | /* disable DMA controller */ | |
2096 | at_dma_off(atdma); | |
f784d9c9 | 2097 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2098 | return 0; |
2099 | } | |
2100 | ||
c0ba5947 NF |
2101 | static void atc_resume_cyclic(struct at_dma_chan *atchan) |
2102 | { | |
2103 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
2104 | ||
2105 | /* restore channel status for cyclic descriptors list: | |
2106 | * next descriptor in the cyclic list at the time of suspend */ | |
2107 | channel_writel(atchan, SADDR, 0); | |
2108 | channel_writel(atchan, DADDR, 0); | |
2109 | channel_writel(atchan, CTRLA, 0); | |
2110 | channel_writel(atchan, CTRLB, 0); | |
2111 | channel_writel(atchan, DSCR, atchan->save_dscr); | |
2112 | dma_writel(atdma, CHER, atchan->mask); | |
2113 | ||
2114 | /* channel pause status should be removed by channel user | |
2115 | * We cannot take the initiative to do it here */ | |
2116 | ||
2117 | vdbg_dump_regs(atchan); | |
2118 | } | |
2119 | ||
33f82d14 | 2120 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 2121 | { |
5c4a74a4 | 2122 | struct at_dma *atdma = dev_get_drvdata(dev); |
c0ba5947 | 2123 | struct dma_chan *chan, *_chan; |
dc78baa2 | 2124 | |
c0ba5947 | 2125 | /* bring back DMA controller */ |
f784d9c9 | 2126 | clk_prepare_enable(atdma->clk); |
dc78baa2 | 2127 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
c0ba5947 NF |
2128 | |
2129 | /* clear any pending interrupt */ | |
2130 | while (dma_readl(atdma, EBCISR)) | |
2131 | cpu_relax(); | |
2132 | ||
2133 | /* restore saved data */ | |
2134 | dma_writel(atdma, EBCIER, atdma->save_imr); | |
2135 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2136 | device_node) { | |
2137 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2138 | ||
2139 | channel_writel(atchan, CFG, atchan->save_cfg); | |
3c477482 | 2140 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2141 | atc_resume_cyclic(atchan); |
2142 | } | |
dc78baa2 | 2143 | return 0; |
dc78baa2 NF |
2144 | } |
2145 | ||
47145210 | 2146 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
c0ba5947 | 2147 | .prepare = at_dma_prepare, |
33f82d14 DW |
2148 | .suspend_noirq = at_dma_suspend_noirq, |
2149 | .resume_noirq = at_dma_resume_noirq, | |
2150 | }; | |
2151 | ||
dc78baa2 | 2152 | static struct platform_driver at_dma_driver = { |
1d1bbd30 | 2153 | .remove = at_dma_remove, |
dc78baa2 | 2154 | .shutdown = at_dma_shutdown, |
67348450 | 2155 | .id_table = atdma_devtypes, |
dc78baa2 NF |
2156 | .driver = { |
2157 | .name = "at_hdmac", | |
33f82d14 | 2158 | .pm = &at_dma_dev_pm_ops, |
c5115953 | 2159 | .of_match_table = of_match_ptr(atmel_dma_dt_ids), |
dc78baa2 NF |
2160 | }, |
2161 | }; | |
2162 | ||
2163 | static int __init at_dma_init(void) | |
2164 | { | |
2165 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
2166 | } | |
93d0bec2 | 2167 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
2168 | |
2169 | static void __exit at_dma_exit(void) | |
2170 | { | |
2171 | platform_driver_unregister(&at_dma_driver); | |
2172 | } | |
2173 | module_exit(at_dma_exit); | |
2174 | ||
2175 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
2176 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
2177 | MODULE_LICENSE("GPL"); | |
2178 | MODULE_ALIAS("platform:at_hdmac"); |