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dmaengine: apple-admac: Do not use devres for IRQs
[linux-2.6-block.git] / drivers / dma / apple-admac.c
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b127315d
MP		 1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Audio DMA Controller (ADMAC) on t8103 (M1) and other Apple chips
4 *
5 * Copyright (C) The Asahi Linux Contributors
6 */
7
8#include <linux/bits.h>
9#include <linux/bitfield.h>
10#include <linux/device.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/of_dma.h>
15#include <linux/interrupt.h>
16#include <linux/spinlock.h>
17
18#include "dmaengine.h"
19
20#define NCHANNELS_MAX 64
21#define IRQ_NOUTPUTS 4
22
23#define RING_WRITE_SLOT GENMASK(1, 0)
24#define RING_READ_SLOT GENMASK(5, 4)
25#define RING_FULL BIT(9)
26#define RING_EMPTY BIT(8)
27#define RING_ERR BIT(10)
28
29#define STATUS_DESC_DONE BIT(0)
30#define STATUS_ERR BIT(6)
31
32#define FLAG_DESC_NOTIFY BIT(16)
33
34#define REG_TX_START 0x0000
35#define REG_TX_STOP 0x0004
36#define REG_RX_START 0x0008
37#define REG_RX_STOP 0x000c
38
39#define REG_CHAN_CTL(ch) (0x8000 + (ch) * 0x200)
40#define REG_CHAN_CTL_RST_RINGS BIT(0)
41
42#define REG_DESC_RING(ch) (0x8070 + (ch) * 0x200)
43#define REG_REPORT_RING(ch) (0x8074 + (ch) * 0x200)
44
45#define REG_RESIDUE(ch) (0x8064 + (ch) * 0x200)
46
47#define REG_BUS_WIDTH(ch) (0x8040 + (ch) * 0x200)
48
49#define BUS_WIDTH_8BIT 0x00
50#define BUS_WIDTH_16BIT 0x01
51#define BUS_WIDTH_32BIT 0x02
52#define BUS_WIDTH_FRAME_2_WORDS 0x10
53#define BUS_WIDTH_FRAME_4_WORDS 0x20
54
55#define CHAN_BUFSIZE 0x8000
56
57#define REG_CHAN_FIFOCTL(ch) (0x8054 + (ch) * 0x200)
58#define CHAN_FIFOCTL_LIMIT GENMASK(31, 16)
59#define CHAN_FIFOCTL_THRESHOLD GENMASK(15, 0)
60
61#define REG_DESC_WRITE(ch) (0x10000 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000)
62#define REG_REPORT_READ(ch) (0x10100 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000)
63
64#define REG_TX_INTSTATE(idx) (0x0030 + (idx) * 4)
65#define REG_RX_INTSTATE(idx) (0x0040 + (idx) * 4)
66#define REG_CHAN_INTSTATUS(ch, idx) (0x8010 + (ch) * 0x200 + (idx) * 4)
67#define REG_CHAN_INTMASK(ch, idx) (0x8020 + (ch) * 0x200 + (idx) * 4)
68
69struct admac_data;
70struct admac_tx;
71
72struct admac_chan {
73 unsigned int no;
74 struct admac_data *host;
75 struct dma_chan chan;
76 struct tasklet_struct tasklet;
77
78 spinlock_t lock;
79 struct admac_tx *current_tx;
80 int nperiod_acks;
81
82 /*
83 * We maintain a 'submitted' and 'issued' list mainly for interface
84 * correctness. Typical use of the driver (per channel) will be
85 * prepping, submitting and issuing a single cyclic transaction which
86 * will stay current until terminate_all is called.
87 */
88 struct list_head submitted;
89 struct list_head issued;
90
91 struct list_head to_free;
92};
93
94struct admac_data {
95 struct dma_device dma;
96 struct device *dev;
97 __iomem void *base;
98
07243159 99 int irq;
b127315d
MP		 100 int irq_index;
101 int nchannels;
102 struct admac_chan channels[];
103};
104
105struct admac_tx {
106 struct dma_async_tx_descriptor tx;
107 bool cyclic;
108 dma_addr_t buf_addr;
109 dma_addr_t buf_end;
110 size_t buf_len;
111 size_t period_len;
112
113 size_t submitted_pos;
114 size_t reclaimed_pos;
115
116 struct list_head node;
117};
118
119static void admac_modify(struct admac_data *ad, int reg, u32 mask, u32 val)
120{
121 void __iomem *addr = ad->base + reg;
122 u32 curr = readl_relaxed(addr);
123
124 writel_relaxed((curr & ~mask) | (val & mask), addr);
125}
126
127static struct admac_chan *to_admac_chan(struct dma_chan *chan)
128{
129 return container_of(chan, struct admac_chan, chan);
130}
131
132static struct admac_tx *to_admac_tx(struct dma_async_tx_descriptor *tx)
133{
134 return container_of(tx, struct admac_tx, tx);
135}
136
137static enum dma_transfer_direction admac_chan_direction(int channo)
138{
139 /* Channel directions are hardwired */
140 return (channo & 1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
141}
142
143static dma_cookie_t admac_tx_submit(struct dma_async_tx_descriptor *tx)
144{
145 struct admac_tx *adtx = to_admac_tx(tx);
146 struct admac_chan *adchan = to_admac_chan(tx->chan);
147 unsigned long flags;
148 dma_cookie_t cookie;
149
150 spin_lock_irqsave(&adchan->lock, flags);
151 cookie = dma_cookie_assign(tx);
152 list_add_tail(&adtx->node, &adchan->submitted);
153 spin_unlock_irqrestore(&adchan->lock, flags);
154
155 return cookie;
156}
157
158static int admac_desc_free(struct dma_async_tx_descriptor *tx)
159{
160 kfree(to_admac_tx(tx));
161
162 return 0;
163}
164
165static struct dma_async_tx_descriptor *admac_prep_dma_cyclic(
166 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
167 size_t period_len, enum dma_transfer_direction direction,
168 unsigned long flags)
169{
170 struct admac_chan *adchan = container_of(chan, struct admac_chan, chan);
171 struct admac_tx *adtx;
172
173 if (direction != admac_chan_direction(adchan->no))
174 return NULL;
175
176 adtx = kzalloc(sizeof(*adtx), GFP_NOWAIT);
177 if (!adtx)
178 return NULL;
179
180 adtx->cyclic = true;
181
182 adtx->buf_addr = buf_addr;
183 adtx->buf_len = buf_len;
184 adtx->buf_end = buf_addr + buf_len;
185 adtx->period_len = period_len;
186
187 adtx->submitted_pos = 0;
188 adtx->reclaimed_pos = 0;
189
190 dma_async_tx_descriptor_init(&adtx->tx, chan);
191 adtx->tx.tx_submit = admac_tx_submit;
192 adtx->tx.desc_free = admac_desc_free;
193
194 return &adtx->tx;
195}
196
197/*
198 * Write one hardware descriptor for a dmaengine cyclic transaction.
199 */
200static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo,
201 struct admac_tx *tx)
202{
203 dma_addr_t addr;
204
205 addr = tx->buf_addr + (tx->submitted_pos % tx->buf_len);
206
207 /* If happens means we have buggy code */
208 WARN_ON_ONCE(addr + tx->period_len > tx->buf_end);
209
11a72ae9 210 dev_dbg(ad->dev, "ch%d descriptor: addr=0x%pad len=0x%zx flags=0x%lx\n",
b127315d
MP		 211 channo, &addr, tx->period_len, FLAG_DESC_NOTIFY);
212
ce4b461b
GU		 213 writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
214 writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
215 writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo));
216 writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo));
b127315d
MP		 217
218 tx->submitted_pos += tx->period_len;
219 tx->submitted_pos %= 2 * tx->buf_len;
220}
221
222/*
223 * Write all the hardware descriptors for a dmaengine cyclic
224 * transaction there is space for.
225 */
226static void admac_cyclic_write_desc(struct admac_data *ad, int channo,
227 struct admac_tx *tx)
228{
229 int i;
230
231 for (i = 0; i < 4; i++) {
232 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL)
233 break;
234 admac_cyclic_write_one_desc(ad, channo, tx);
235 }
236}
237
238static int admac_ring_noccupied_slots(int ringval)
239{
240 int wrslot = FIELD_GET(RING_WRITE_SLOT, ringval);
241 int rdslot = FIELD_GET(RING_READ_SLOT, ringval);
242
243 if (wrslot != rdslot) {
244 return (wrslot + 4 - rdslot) % 4;
245 } else {
246 WARN_ON((ringval & (RING_FULL | RING_EMPTY)) == 0);
247
248 if (ringval & RING_FULL)
249 return 4;
250 else
251 return 0;
252 }
253}
254
255/*
256 * Read from hardware the residue of a cyclic dmaengine transaction.
257 */
258static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo,
259 struct admac_tx *adtx)
260{
261 u32 ring1, ring2;
262 u32 residue1, residue2;
263 int nreports;
264 size_t pos;
265
266 ring1 = readl_relaxed(ad->base + REG_REPORT_RING(channo));
267 residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo));
268 ring2 = readl_relaxed(ad->base + REG_REPORT_RING(channo));
269 residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo));
270
271 if (residue2 > residue1) {
272 /*
273 * Controller must have loaded next descriptor between
274 * the two residue reads
275 */
276 nreports = admac_ring_noccupied_slots(ring1) + 1;
277 } else {
278 /* No descriptor load between the two reads, ring2 is safe to use */
279 nreports = admac_ring_noccupied_slots(ring2);
280 }
281
282 pos = adtx->reclaimed_pos + adtx->period_len * (nreports + 1) - residue2;
283
284 return adtx->buf_len - pos % adtx->buf_len;
285}
286
287static enum dma_status admac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
288 struct dma_tx_state *txstate)
289{
290 struct admac_chan *adchan = to_admac_chan(chan);
291 struct admac_data *ad = adchan->host;
292 struct admac_tx *adtx;
293
294 enum dma_status ret;
295 size_t residue;
296 unsigned long flags;
297
298 ret = dma_cookie_status(chan, cookie, txstate);
299 if (ret == DMA_COMPLETE || !txstate)
300 return ret;
301
302 spin_lock_irqsave(&adchan->lock, flags);
303 adtx = adchan->current_tx;
304
305 if (adtx && adtx->tx.cookie == cookie) {
306 ret = DMA_IN_PROGRESS;
307 residue = admac_cyclic_read_residue(ad, adchan->no, adtx);
308 } else {
309 ret = DMA_IN_PROGRESS;
310 residue = 0;
311 list_for_each_entry(adtx, &adchan->issued, node) {
312 if (adtx->tx.cookie == cookie) {
313 residue = adtx->buf_len;
314 break;
315 }
316 }
317 }
318 spin_unlock_irqrestore(&adchan->lock, flags);
319
320 dma_set_residue(txstate, residue);
321 return ret;
322}
323
324static void admac_start_chan(struct admac_chan *adchan)
325{
326 struct admac_data *ad = adchan->host;
327 u32 startbit = 1 << (adchan->no / 2);
328
329 writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
330 ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index));
331 writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
332 ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index));
333
334 switch (admac_chan_direction(adchan->no)) {
335 case DMA_MEM_TO_DEV:
336 writel_relaxed(startbit, ad->base + REG_TX_START);
337 break;
338 case DMA_DEV_TO_MEM:
339 writel_relaxed(startbit, ad->base + REG_RX_START);
340 break;
341 default:
342 break;
343 }
344 dev_dbg(adchan->host->dev, "ch%d start\n", adchan->no);
345}
346
347static void admac_stop_chan(struct admac_chan *adchan)
348{
349 struct admac_data *ad = adchan->host;
350 u32 stopbit = 1 << (adchan->no / 2);
351
352 switch (admac_chan_direction(adchan->no)) {
353 case DMA_MEM_TO_DEV:
354 writel_relaxed(stopbit, ad->base + REG_TX_STOP);
355 break;
356 case DMA_DEV_TO_MEM:
357 writel_relaxed(stopbit, ad->base + REG_RX_STOP);
358 break;
359 default:
360 break;
361 }
362 dev_dbg(adchan->host->dev, "ch%d stop\n", adchan->no);
363}
364
365static void admac_reset_rings(struct admac_chan *adchan)
366{
367 struct admac_data *ad = adchan->host;
368
369 writel_relaxed(REG_CHAN_CTL_RST_RINGS,
370 ad->base + REG_CHAN_CTL(adchan->no));
371 writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no));
372}
373
374static void admac_start_current_tx(struct admac_chan *adchan)
375{
376 struct admac_data *ad = adchan->host;
377 int ch = adchan->no;
378
379 admac_reset_rings(adchan);
380 writel_relaxed(0, ad->base + REG_CHAN_CTL(ch));
381
382 admac_cyclic_write_one_desc(ad, ch, adchan->current_tx);
383 admac_start_chan(adchan);
384 admac_cyclic_write_desc(ad, ch, adchan->current_tx);
385}
386
387static void admac_issue_pending(struct dma_chan *chan)
388{
389 struct admac_chan *adchan = to_admac_chan(chan);
390 struct admac_tx *tx;
391 unsigned long flags;
392
393 spin_lock_irqsave(&adchan->lock, flags);
394 list_splice_tail_init(&adchan->submitted, &adchan->issued);
395 if (!list_empty(&adchan->issued) && !adchan->current_tx) {
396 tx = list_first_entry(&adchan->issued, struct admac_tx, node);
397 list_del(&tx->node);
398
399 adchan->current_tx = tx;
400 adchan->nperiod_acks = 0;
401 admac_start_current_tx(adchan);
402 }
403 spin_unlock_irqrestore(&adchan->lock, flags);
404}
405
406static int admac_pause(struct dma_chan *chan)
407{
408 struct admac_chan *adchan = to_admac_chan(chan);
409
410 admac_stop_chan(adchan);
411
412 return 0;
413}
414
415static int admac_resume(struct dma_chan *chan)
416{
417 struct admac_chan *adchan = to_admac_chan(chan);
418
419 admac_start_chan(adchan);
420
421 return 0;
422}
423
424static int admac_terminate_all(struct dma_chan *chan)
425{
426 struct admac_chan *adchan = to_admac_chan(chan);
427 unsigned long flags;
428
429 spin_lock_irqsave(&adchan->lock, flags);
430 admac_stop_chan(adchan);
431 admac_reset_rings(adchan);
432
433 adchan->current_tx = NULL;
434 /*
435 * Descriptors can only be freed after the tasklet
436 * has been killed (in admac_synchronize).
437 */
438 list_splice_tail_init(&adchan->submitted, &adchan->to_free);
439 list_splice_tail_init(&adchan->issued, &adchan->to_free);
440 spin_unlock_irqrestore(&adchan->lock, flags);
441
442 return 0;
443}
444
445static void admac_synchronize(struct dma_chan *chan)
446{
447 struct admac_chan *adchan = to_admac_chan(chan);
448 struct admac_tx *adtx, *_adtx;
449 unsigned long flags;
450 LIST_HEAD(head);
451
452 spin_lock_irqsave(&adchan->lock, flags);
453 list_splice_tail_init(&adchan->to_free, &head);
454 spin_unlock_irqrestore(&adchan->lock, flags);
455
456 tasklet_kill(&adchan->tasklet);
457
458 list_for_each_entry_safe(adtx, _adtx, &head, node) {
459 list_del(&adtx->node);
460 admac_desc_free(&adtx->tx);
461 }
462}
463
464static int admac_alloc_chan_resources(struct dma_chan *chan)
465{
466 struct admac_chan *adchan = to_admac_chan(chan);
467
468 dma_cookie_init(&adchan->chan);
469 return 0;
470}
471
472static void admac_free_chan_resources(struct dma_chan *chan)
473{
474 admac_terminate_all(chan);
475 admac_synchronize(chan);
476}
477
478static struct dma_chan *admac_dma_of_xlate(struct of_phandle_args *dma_spec,
479 struct of_dma *ofdma)
480{
481 struct admac_data *ad = (struct admac_data *) ofdma->of_dma_data;
482 unsigned int index;
483
484 if (dma_spec->args_count != 1)
485 return NULL;
486
487 index = dma_spec->args[0];
488
489 if (index >= ad->nchannels) {
490 dev_err(ad->dev, "channel index %u out of bounds\n", index);
491 return NULL;
492 }
493
494 return &ad->channels[index].chan;
495}
496
497static int admac_drain_reports(struct admac_data *ad, int channo)
498{
499 int count;
500
501 for (count = 0; count < 4; count++) {
502 u32 countval_hi, countval_lo, unk1, flags;
503
504 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY)
505 break;
506
507 countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo));
508 countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo));
509 unk1 = readl_relaxed(ad->base + REG_REPORT_READ(channo));
510 flags = readl_relaxed(ad->base + REG_REPORT_READ(channo));
511
512 dev_dbg(ad->dev, "ch%d report: countval=0x%llx unk1=0x%x flags=0x%x\n",
513 channo, ((u64) countval_hi) << 32 | countval_lo, unk1, flags);
514 }
515
516 return count;
517}
518
519static void admac_handle_status_err(struct admac_data *ad, int channo)
520{
521 bool handled = false;
522
523 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) {
524 writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo));
525 dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n", channo);
526 handled = true;
527 }
528
529 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) {
530 writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo));
531 dev_err_ratelimited(ad->dev, "ch%d report ring error\n", channo);
532 handled = true;
533 }
534
535 if (unlikely(!handled)) {
536 dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n", channo);
537 admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index),
538 STATUS_ERR, 0);
539 }
540}
541
542static void admac_handle_status_desc_done(struct admac_data *ad, int channo)
543{
544 struct admac_chan *adchan = &ad->channels[channo];
545 unsigned long flags;
546 int nreports;
547
548 writel_relaxed(STATUS_DESC_DONE,
549 ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index));
550
551 spin_lock_irqsave(&adchan->lock, flags);
552 nreports = admac_drain_reports(ad, channo);
553
554 if (adchan->current_tx) {
555 struct admac_tx *tx = adchan->current_tx;
556
557 adchan->nperiod_acks += nreports;
558 tx->reclaimed_pos += nreports * tx->period_len;
559 tx->reclaimed_pos %= 2 * tx->buf_len;
560
561 admac_cyclic_write_desc(ad, channo, tx);
562 tasklet_schedule(&adchan->tasklet);
563 }
564 spin_unlock_irqrestore(&adchan->lock, flags);
565}
566
567static void admac_handle_chan_int(struct admac_data *ad, int no)
568{
569 u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index));
570
571 if (cause & STATUS_ERR)
572 admac_handle_status_err(ad, no);
573
574 if (cause & STATUS_DESC_DONE)
575 admac_handle_status_desc_done(ad, no);
576}
577
578static irqreturn_t admac_interrupt(int irq, void *devid)
579{
580 struct admac_data *ad = devid;
581 u32 rx_intstate, tx_intstate;
582 int i;
583
584 rx_intstate = readl_relaxed(ad->base + REG_RX_INTSTATE(ad->irq_index));
585 tx_intstate = readl_relaxed(ad->base + REG_TX_INTSTATE(ad->irq_index));
586
587 if (!tx_intstate && !rx_intstate)
588 return IRQ_NONE;
589
590 for (i = 0; i < ad->nchannels; i += 2) {
591 if (tx_intstate & 1)
592 admac_handle_chan_int(ad, i);
593 tx_intstate >>= 1;
594 }
595
596 for (i = 1; i < ad->nchannels; i += 2) {
597 if (rx_intstate & 1)
598 admac_handle_chan_int(ad, i);
599 rx_intstate >>= 1;
600 }
601
602 return IRQ_HANDLED;
603}
604
605static void admac_chan_tasklet(struct tasklet_struct *t)
606{
607 struct admac_chan *adchan = from_tasklet(adchan, t, tasklet);
608 struct admac_tx *adtx;
609 struct dmaengine_desc_callback cb;
610 struct dmaengine_result tx_result;
611 int nacks;
612
613 spin_lock_irq(&adchan->lock);
614 adtx = adchan->current_tx;
615 nacks = adchan->nperiod_acks;
616 adchan->nperiod_acks = 0;
617 spin_unlock_irq(&adchan->lock);
618
619 if (!adtx || !nacks)
620 return;
621
622 tx_result.result = DMA_TRANS_NOERROR;
623 tx_result.residue = 0;
624
625 dmaengine_desc_get_callback(&adtx->tx, &cb);
626 while (nacks--)
627 dmaengine_desc_callback_invoke(&cb, &tx_result);
628}
629
630static int admac_device_config(struct dma_chan *chan,
631 struct dma_slave_config *config)
632{
633 struct admac_chan *adchan = to_admac_chan(chan);
634 struct admac_data *ad = adchan->host;
635 bool is_tx = admac_chan_direction(adchan->no) == DMA_MEM_TO_DEV;
636 int wordsize = 0;
637 u32 bus_width = 0;
638
639 switch (is_tx ? config->dst_addr_width : config->src_addr_width) {
640 case DMA_SLAVE_BUSWIDTH_1_BYTE:
641 wordsize = 1;
642 bus_width |= BUS_WIDTH_8BIT;
643 break;
644 case DMA_SLAVE_BUSWIDTH_2_BYTES:
645 wordsize = 2;
646 bus_width |= BUS_WIDTH_16BIT;
647 break;
648 case DMA_SLAVE_BUSWIDTH_4_BYTES:
649 wordsize = 4;
650 bus_width |= BUS_WIDTH_32BIT;
651 break;
652 default:
653 return -EINVAL;
654 }
655
656 /*
657 * We take port_window_size to be the number of words in a frame.
658 *
659 * The controller has some means of out-of-band signalling, to the peripheral,
660 * of words position in a frame. That's where the importance of this control
661 * comes from.
662 */
663 switch (is_tx ? config->dst_port_window_size : config->src_port_window_size) {
664 case 0 ... 1:
665 break;
666 case 2:
667 bus_width |= BUS_WIDTH_FRAME_2_WORDS;
668 break;
669 case 4:
670 bus_width |= BUS_WIDTH_FRAME_4_WORDS;
671 break;
672 default:
673 return -EINVAL;
674 }
675
676 writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no));
677
678 /*
679 * By FIFOCTL_LIMIT we seem to set the maximal number of bytes allowed to be
680 * held in controller's per-channel FIFO. Transfers seem to be triggered
681 * around the time FIFO occupancy touches FIFOCTL_THRESHOLD.
682 *
683 * The numbers we set are more or less arbitrary.
684 */
685 writel_relaxed(FIELD_PREP(CHAN_FIFOCTL_LIMIT, 0x30 * wordsize)
686 | FIELD_PREP(CHAN_FIFOCTL_THRESHOLD, 0x18 * wordsize),
687 ad->base + REG_CHAN_FIFOCTL(adchan->no));
688
689 return 0;
690}
691
692static int admac_probe(struct platform_device *pdev)
693{
694 struct device_node *np = pdev->dev.of_node;
695 struct admac_data *ad;
696 struct dma_device *dma;
697 int nchannels;
698 int err, irq, i;
699
700 err = of_property_read_u32(np, "dma-channels", &nchannels);
701 if (err || nchannels > NCHANNELS_MAX) {
702 dev_err(&pdev->dev, "missing or invalid dma-channels property\n");
703 return -EINVAL;
704 }
705
706 ad = devm_kzalloc(&pdev->dev, struct_size(ad, channels, nchannels), GFP_KERNEL);
707 if (!ad)
708 return -ENOMEM;
709
710 platform_set_drvdata(pdev, ad);
711 ad->dev = &pdev->dev;
712 ad->nchannels = nchannels;
713
714 /*
715 * The controller has 4 IRQ outputs. Try them all until
716 * we find one we can use.
717 */
718 for (i = 0; i < IRQ_NOUTPUTS; i++) {
719 irq = platform_get_irq_optional(pdev, i);
720 if (irq >= 0) {
721 ad->irq_index = i;
722 break;
723 }
724 }
725
726 if (irq < 0)
727 return dev_err_probe(&pdev->dev, irq, "no usable interrupt\n");
07243159 728 ad->irq = irq;
b127315d
MP		 729
730 ad->base = devm_platform_ioremap_resource(pdev, 0);
731 if (IS_ERR(ad->base))
732 return dev_err_probe(&pdev->dev, PTR_ERR(ad->base),
733 "unable to obtain MMIO resource\n");
734
735 dma = &ad->dma;
736
737 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
738 dma_cap_set(DMA_CYCLIC, dma->cap_mask);
739
740 dma->dev = &pdev->dev;
741 dma->device_alloc_chan_resources = admac_alloc_chan_resources;
742 dma->device_free_chan_resources = admac_free_chan_resources;
743 dma->device_tx_status = admac_tx_status;
744 dma->device_issue_pending = admac_issue_pending;
745 dma->device_terminate_all = admac_terminate_all;
746 dma->device_synchronize = admac_synchronize;
747 dma->device_prep_dma_cyclic = admac_prep_dma_cyclic;
748 dma->device_config = admac_device_config;
749 dma->device_pause = admac_pause;
750 dma->device_resume = admac_resume;
751
752 dma->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
753 dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
754 dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
755 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
756 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
757
758 INIT_LIST_HEAD(&dma->channels);
759 for (i = 0; i < nchannels; i++) {
760 struct admac_chan *adchan = &ad->channels[i];
761
762 adchan->host = ad;
763 adchan->no = i;
764 adchan->chan.device = &ad->dma;
765 spin_lock_init(&adchan->lock);
766 INIT_LIST_HEAD(&adchan->submitted);
767 INIT_LIST_HEAD(&adchan->issued);
768 INIT_LIST_HEAD(&adchan->to_free);
769 list_add_tail(&adchan->chan.device_node, &dma->channels);
770 tasklet_setup(&adchan->tasklet, admac_chan_tasklet);
771 }
772
07243159 773 err = request_irq(irq, admac_interrupt, 0, dev_name(&pdev->dev), ad);
b127315d 774 if (err)
07243159
MP		 775 return dev_err_probe(&pdev->dev, err,
776 "unable to register interrupt\n");
777
778 err = dma_async_device_register(&ad->dma);
779 if (err) {
780 dev_err_probe(&pdev->dev, err, "failed to register DMA device\n");
781 goto free_irq;
782 }
b127315d
MP		 783
784 err = of_dma_controller_register(pdev->dev.of_node, admac_dma_of_xlate, ad);
785 if (err) {
786 dma_async_device_unregister(&ad->dma);
07243159
MP		 787 dev_err_probe(&pdev->dev, err, "failed to register with OF\n");
788 goto free_irq;
b127315d
MP		 789 }
790
791 return 0;
07243159
MP		 792
793free_irq:
794 free_irq(ad->irq, ad);
795 return err;
b127315d
MP		 796}
797
798static int admac_remove(struct platform_device *pdev)
799{
800 struct admac_data *ad = platform_get_drvdata(pdev);
801
802 of_dma_controller_free(pdev->dev.of_node);
803 dma_async_device_unregister(&ad->dma);
07243159 804 free_irq(ad->irq, ad);
b127315d
MP		 805
806 return 0;
807}
808
809static const struct of_device_id admac_of_match[] = {
810 { .compatible = "apple,admac", },
811 { }
812};
813MODULE_DEVICE_TABLE(of, admac_of_match);
814
815static struct platform_driver apple_admac_driver = {
816 .driver = {
817 .name = "apple-admac",
818 .of_match_table = admac_of_match,
819 },
820 .probe = admac_probe,
821 .remove = admac_remove,
822};
823module_platform_driver(apple_admac_driver);
824
825MODULE_AUTHOR("Martin Povišer <povik+lin@cutebit.org>");
826MODULE_DESCRIPTION("Driver for Audio DMA Controller (ADMAC) on Apple SoCs");
827MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)