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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
e8b5e11d | 22 | * The full GNU General Public License is in this distribution in the |
e8689e63 LW |
23 | * file called COPYING. |
24 | * | |
25 | * Documentation: ARM DDI 0196G == PL080 | |
26 | * Documentation: ARM DDI 0218E == PL081 | |
27 | * | |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to | |
29 | * any channel. | |
30 | * | |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
69 | * Only the former works sanely with scatter lists, so we only implement | |
70 | * the DMAC flow control method. However, peripherals which use the LBREQ | |
71 | * and LSREQ signals (eg, MMCI) are unable to use this mode, which through | |
72 | * these hardware restrictions prevents them from using scatter DMA. | |
e8689e63 LW |
73 | * |
74 | * Global TODO: | |
75 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
76 | */ | |
77 | #include <linux/device.h> | |
78 | #include <linux/init.h> | |
79 | #include <linux/module.h> | |
e8689e63 LW |
80 | #include <linux/interrupt.h> |
81 | #include <linux/slab.h> | |
82 | #include <linux/dmapool.h> | |
e8689e63 | 83 | #include <linux/dmaengine.h> |
730404ac | 84 | #include <linux/amba/bus.h> |
e8689e63 LW |
85 | #include <linux/amba/pl08x.h> |
86 | #include <linux/debugfs.h> | |
87 | #include <linux/seq_file.h> | |
88 | ||
89 | #include <asm/hardware/pl080.h> | |
e8689e63 LW |
90 | |
91 | #define DRIVER_NAME "pl08xdmac" | |
92 | ||
93 | /** | |
94 | * struct vendor_data - vendor-specific config parameters | |
e8b5e11d | 95 | * for PL08x derivatives |
e8689e63 LW |
96 | * @channels: the number of channels available in this variant |
97 | * @dualmaster: whether this version supports dual AHB masters | |
98 | * or not. | |
99 | */ | |
100 | struct vendor_data { | |
e8689e63 LW |
101 | u8 channels; |
102 | bool dualmaster; | |
103 | }; | |
104 | ||
105 | /* | |
106 | * PL08X private data structures | |
e8b5e11d RKAL |
107 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
108 | * start & end do not - their bus bit info is in cctl. | |
e8689e63 | 109 | */ |
7cb72ad9 | 110 | struct pl08x_lli { |
e8689e63 LW |
111 | dma_addr_t src; |
112 | dma_addr_t dst; | |
113 | dma_addr_t next; | |
114 | u32 cctl; | |
115 | }; | |
116 | ||
117 | /** | |
118 | * struct pl08x_driver_data - the local state holder for the PL08x | |
119 | * @slave: slave engine for this instance | |
120 | * @memcpy: memcpy engine for this instance | |
121 | * @base: virtual memory base (remapped) for the PL08x | |
122 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
123 | * @vd: vendor data for this PL08x variant | |
124 | * @pd: platform data passed in from the platform/machine | |
125 | * @phy_chans: array of data for the physical channels | |
126 | * @pool: a pool for the LLI descriptors | |
127 | * @pool_ctr: counter of LLIs in the pool | |
128 | * @lock: a spinlock for this struct | |
129 | */ | |
130 | struct pl08x_driver_data { | |
131 | struct dma_device slave; | |
132 | struct dma_device memcpy; | |
133 | void __iomem *base; | |
134 | struct amba_device *adev; | |
f96ca9ec | 135 | const struct vendor_data *vd; |
e8689e63 LW |
136 | struct pl08x_platform_data *pd; |
137 | struct pl08x_phy_chan *phy_chans; | |
138 | struct dma_pool *pool; | |
139 | int pool_ctr; | |
140 | spinlock_t lock; | |
141 | }; | |
142 | ||
143 | /* | |
144 | * PL08X specific defines | |
145 | */ | |
146 | ||
147 | /* | |
148 | * Memory boundaries: the manual for PL08x says that the controller | |
149 | * cannot read past a 1KiB boundary, so these defines are used to | |
150 | * create transfer LLIs that do not cross such boundaries. | |
151 | */ | |
152 | #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */ | |
153 | #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT) | |
154 | ||
155 | /* Minimum period between work queue runs */ | |
156 | #define PL08X_WQ_PERIODMIN 20 | |
157 | ||
158 | /* Size (bytes) of each LLI buffer allocated for one transfer */ | |
159 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
160 | ||
e8b5e11d | 161 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
e8689e63 | 162 | #define PL08X_MAX_ALLOCS 0x40 |
7cb72ad9 | 163 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
164 | #define PL08X_ALIGN 8 |
165 | ||
166 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
167 | { | |
168 | return container_of(chan, struct pl08x_dma_chan, chan); | |
169 | } | |
170 | ||
171 | /* | |
172 | * Physical channel handling | |
173 | */ | |
174 | ||
175 | /* Whether a certain channel is busy or not */ | |
176 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
177 | { | |
178 | unsigned int val; | |
179 | ||
180 | val = readl(ch->base + PL080_CH_CONFIG); | |
181 | return val & PL080_CONFIG_ACTIVE; | |
182 | } | |
183 | ||
184 | /* | |
185 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 186 | * The next LLI pointer and the configuration interrupt bit have |
e8689e63 LW |
187 | * been set when the LLIs were constructed |
188 | */ | |
189 | static void pl08x_set_cregs(struct pl08x_driver_data *pl08x, | |
190 | struct pl08x_phy_chan *ch) | |
191 | { | |
192 | /* Wait for channel inactive */ | |
193 | while (pl08x_phy_channel_busy(ch)) | |
19386b32 | 194 | cpu_relax(); |
e8689e63 LW |
195 | |
196 | dev_vdbg(&pl08x->adev->dev, | |
9c132992 RKAL |
197 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " |
198 | "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n", | |
e8689e63 LW |
199 | ch->id, |
200 | ch->csrc, | |
201 | ch->cdst, | |
202 | ch->cctl, | |
203 | ch->clli, | |
204 | ch->ccfg); | |
205 | ||
206 | writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR); | |
207 | writel(ch->cdst, ch->base + PL080_CH_DST_ADDR); | |
208 | writel(ch->clli, ch->base + PL080_CH_LLI); | |
209 | writel(ch->cctl, ch->base + PL080_CH_CONTROL); | |
210 | writel(ch->ccfg, ch->base + PL080_CH_CONFIG); | |
211 | } | |
212 | ||
213 | static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan) | |
214 | { | |
215 | struct pl08x_channel_data *cd = plchan->cd; | |
216 | struct pl08x_phy_chan *phychan = plchan->phychan; | |
217 | struct pl08x_txd *txd = plchan->at; | |
218 | ||
219 | /* Copy the basic control register calculated at transfer config */ | |
220 | phychan->csrc = txd->csrc; | |
221 | phychan->cdst = txd->cdst; | |
222 | phychan->clli = txd->clli; | |
223 | phychan->cctl = txd->cctl; | |
224 | ||
225 | /* Assign the signal to the proper control registers */ | |
226 | phychan->ccfg = cd->ccfg; | |
227 | phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK; | |
228 | phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK; | |
229 | /* If it wasn't set from AMBA, ignore it */ | |
230 | if (txd->direction == DMA_TO_DEVICE) | |
231 | /* Select signal as destination */ | |
232 | phychan->ccfg |= | |
233 | (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT); | |
234 | else if (txd->direction == DMA_FROM_DEVICE) | |
235 | /* Select signal as source */ | |
236 | phychan->ccfg |= | |
237 | (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT); | |
238 | /* Always enable error interrupts */ | |
239 | phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK; | |
240 | /* Always enable terminal interrupts */ | |
241 | phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK; | |
242 | } | |
243 | ||
244 | /* | |
245 | * Enable the DMA channel | |
246 | * Assumes all other configuration bits have been set | |
247 | * as desired before this code is called | |
248 | */ | |
249 | static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x, | |
250 | struct pl08x_phy_chan *ch) | |
251 | { | |
252 | u32 val; | |
253 | ||
254 | /* | |
255 | * Do not access config register until channel shows as disabled | |
256 | */ | |
257 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id)) | |
19386b32 | 258 | cpu_relax(); |
e8689e63 LW |
259 | |
260 | /* | |
261 | * Do not access config register until channel shows as inactive | |
262 | */ | |
263 | val = readl(ch->base + PL080_CH_CONFIG); | |
264 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) | |
265 | val = readl(ch->base + PL080_CH_CONFIG); | |
266 | ||
267 | writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG); | |
268 | } | |
269 | ||
270 | /* | |
271 | * Overall DMAC remains enabled always. | |
272 | * | |
273 | * Disabling individual channels could lose data. | |
274 | * | |
275 | * Disable the peripheral DMA after disabling the DMAC | |
276 | * in order to allow the DMAC FIFO to drain, and | |
277 | * hence allow the channel to show inactive | |
278 | * | |
279 | */ | |
280 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
281 | { | |
282 | u32 val; | |
283 | ||
284 | /* Set the HALT bit and wait for the FIFO to drain */ | |
285 | val = readl(ch->base + PL080_CH_CONFIG); | |
286 | val |= PL080_CONFIG_HALT; | |
287 | writel(val, ch->base + PL080_CH_CONFIG); | |
288 | ||
289 | /* Wait for channel inactive */ | |
290 | while (pl08x_phy_channel_busy(ch)) | |
19386b32 | 291 | cpu_relax(); |
e8689e63 LW |
292 | } |
293 | ||
294 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
295 | { | |
296 | u32 val; | |
297 | ||
298 | /* Clear the HALT bit */ | |
299 | val = readl(ch->base + PL080_CH_CONFIG); | |
300 | val &= ~PL080_CONFIG_HALT; | |
301 | writel(val, ch->base + PL080_CH_CONFIG); | |
302 | } | |
303 | ||
304 | ||
305 | /* Stops the channel */ | |
306 | static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch) | |
307 | { | |
308 | u32 val; | |
309 | ||
310 | pl08x_pause_phy_chan(ch); | |
311 | ||
312 | /* Disable channel */ | |
313 | val = readl(ch->base + PL080_CH_CONFIG); | |
314 | val &= ~PL080_CONFIG_ENABLE; | |
315 | val &= ~PL080_CONFIG_ERR_IRQ_MASK; | |
316 | val &= ~PL080_CONFIG_TC_IRQ_MASK; | |
317 | writel(val, ch->base + PL080_CH_CONFIG); | |
318 | } | |
319 | ||
320 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
321 | { | |
322 | /* The source width defines the number of bytes */ | |
323 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
324 | ||
325 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
326 | case PL080_WIDTH_8BIT: | |
327 | break; | |
328 | case PL080_WIDTH_16BIT: | |
329 | bytes *= 2; | |
330 | break; | |
331 | case PL080_WIDTH_32BIT: | |
332 | bytes *= 4; | |
333 | break; | |
334 | } | |
335 | return bytes; | |
336 | } | |
337 | ||
338 | /* The channel should be paused when calling this */ | |
339 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
340 | { | |
341 | struct pl08x_phy_chan *ch; | |
342 | struct pl08x_txd *txdi = NULL; | |
343 | struct pl08x_txd *txd; | |
344 | unsigned long flags; | |
cace6585 | 345 | size_t bytes = 0; |
e8689e63 LW |
346 | |
347 | spin_lock_irqsave(&plchan->lock, flags); | |
348 | ||
349 | ch = plchan->phychan; | |
350 | txd = plchan->at; | |
351 | ||
352 | /* | |
353 | * Next follow the LLIs to get the number of pending bytes in the | |
354 | * currently active transaction. | |
355 | */ | |
356 | if (ch && txd) { | |
7cb72ad9 RKAL |
357 | struct pl08x_lli *llis_va = txd->llis_va; |
358 | struct pl08x_lli *llis_bus = (struct pl08x_lli *) txd->llis_bus; | |
4c0df6a3 | 359 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 LW |
360 | |
361 | /* First get the bytes in the current active LLI */ | |
362 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); | |
363 | ||
364 | if (clli) { | |
365 | int i = 0; | |
366 | ||
367 | /* Forward to the LLI pointed to by clli */ | |
368 | while ((clli != (u32) &(llis_bus[i])) && | |
369 | (i < MAX_NUM_TSFR_LLIS)) | |
370 | i++; | |
371 | ||
372 | while (clli) { | |
373 | bytes += get_bytes_in_cctl(llis_va[i].cctl); | |
374 | /* | |
e8b5e11d | 375 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 LW |
376 | */ |
377 | clli = llis_va[i].next; | |
378 | i++; | |
379 | } | |
380 | } | |
381 | } | |
382 | ||
383 | /* Sum up all queued transactions */ | |
384 | if (!list_empty(&plchan->desc_list)) { | |
385 | list_for_each_entry(txdi, &plchan->desc_list, node) { | |
386 | bytes += txdi->len; | |
387 | } | |
388 | ||
389 | } | |
390 | ||
391 | spin_unlock_irqrestore(&plchan->lock, flags); | |
392 | ||
393 | return bytes; | |
394 | } | |
395 | ||
396 | /* | |
397 | * Allocate a physical channel for a virtual channel | |
398 | */ | |
399 | static struct pl08x_phy_chan * | |
400 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
401 | struct pl08x_dma_chan *virt_chan) | |
402 | { | |
403 | struct pl08x_phy_chan *ch = NULL; | |
404 | unsigned long flags; | |
405 | int i; | |
406 | ||
407 | /* | |
408 | * Try to locate a physical channel to be used for | |
409 | * this transfer. If all are taken return NULL and | |
410 | * the requester will have to cope by using some fallback | |
411 | * PIO mode or retrying later. | |
412 | */ | |
413 | for (i = 0; i < pl08x->vd->channels; i++) { | |
414 | ch = &pl08x->phy_chans[i]; | |
415 | ||
416 | spin_lock_irqsave(&ch->lock, flags); | |
417 | ||
418 | if (!ch->serving) { | |
419 | ch->serving = virt_chan; | |
420 | ch->signal = -1; | |
421 | spin_unlock_irqrestore(&ch->lock, flags); | |
422 | break; | |
423 | } | |
424 | ||
425 | spin_unlock_irqrestore(&ch->lock, flags); | |
426 | } | |
427 | ||
428 | if (i == pl08x->vd->channels) { | |
429 | /* No physical channel available, cope with it */ | |
430 | return NULL; | |
431 | } | |
432 | ||
433 | return ch; | |
434 | } | |
435 | ||
436 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, | |
437 | struct pl08x_phy_chan *ch) | |
438 | { | |
439 | unsigned long flags; | |
440 | ||
441 | /* Stop the channel and clear its interrupts */ | |
442 | pl08x_stop_phy_chan(ch); | |
443 | writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR); | |
444 | writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR); | |
445 | ||
446 | /* Mark it as free */ | |
447 | spin_lock_irqsave(&ch->lock, flags); | |
448 | ch->serving = NULL; | |
449 | spin_unlock_irqrestore(&ch->lock, flags); | |
450 | } | |
451 | ||
452 | /* | |
453 | * LLI handling | |
454 | */ | |
455 | ||
456 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
457 | { | |
458 | switch (coded) { | |
459 | case PL080_WIDTH_8BIT: | |
460 | return 1; | |
461 | case PL080_WIDTH_16BIT: | |
462 | return 2; | |
463 | case PL080_WIDTH_32BIT: | |
464 | return 4; | |
465 | default: | |
466 | break; | |
467 | } | |
468 | BUG(); | |
469 | return 0; | |
470 | } | |
471 | ||
472 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 473 | size_t tsize) |
e8689e63 LW |
474 | { |
475 | u32 retbits = cctl; | |
476 | ||
e8b5e11d | 477 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
478 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
479 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
480 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
481 | ||
482 | /* Then set the bits according to the parameters */ | |
483 | switch (srcwidth) { | |
484 | case 1: | |
485 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
486 | break; | |
487 | case 2: | |
488 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
489 | break; | |
490 | case 4: | |
491 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
492 | break; | |
493 | default: | |
494 | BUG(); | |
495 | break; | |
496 | } | |
497 | ||
498 | switch (dstwidth) { | |
499 | case 1: | |
500 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
501 | break; | |
502 | case 2: | |
503 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
504 | break; | |
505 | case 4: | |
506 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
507 | break; | |
508 | default: | |
509 | BUG(); | |
510 | break; | |
511 | } | |
512 | ||
513 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
514 | return retbits; | |
515 | } | |
516 | ||
517 | /* | |
518 | * Autoselect a master bus to use for the transfer | |
519 | * this prefers the destination bus if both available | |
520 | * if fixed address on one bus the other will be chosen | |
521 | */ | |
3e2a037c | 522 | static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus, |
e8689e63 LW |
523 | struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus, |
524 | struct pl08x_bus_data **sbus, u32 cctl) | |
525 | { | |
526 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
527 | *mbus = src_bus; | |
528 | *sbus = dst_bus; | |
529 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { | |
530 | *mbus = dst_bus; | |
531 | *sbus = src_bus; | |
532 | } else { | |
533 | if (dst_bus->buswidth == 4) { | |
534 | *mbus = dst_bus; | |
535 | *sbus = src_bus; | |
536 | } else if (src_bus->buswidth == 4) { | |
537 | *mbus = src_bus; | |
538 | *sbus = dst_bus; | |
539 | } else if (dst_bus->buswidth == 2) { | |
540 | *mbus = dst_bus; | |
541 | *sbus = src_bus; | |
542 | } else if (src_bus->buswidth == 2) { | |
543 | *mbus = src_bus; | |
544 | *sbus = dst_bus; | |
545 | } else { | |
546 | /* src_bus->buswidth == 1 */ | |
547 | *mbus = dst_bus; | |
548 | *sbus = src_bus; | |
549 | } | |
550 | } | |
551 | } | |
552 | ||
553 | /* | |
554 | * Fills in one LLI for a certain transfer descriptor | |
555 | * and advance the counter | |
556 | */ | |
3e2a037c | 557 | static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, |
e8689e63 LW |
558 | struct pl08x_txd *txd, int num_llis, int len, |
559 | u32 cctl, u32 *remainder) | |
560 | { | |
7cb72ad9 | 561 | struct pl08x_lli *llis_va = txd->llis_va; |
56b61882 | 562 | dma_addr_t llis_bus = txd->llis_bus; |
e8689e63 LW |
563 | |
564 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
565 | ||
566 | llis_va[num_llis].cctl = cctl; | |
567 | llis_va[num_llis].src = txd->srcbus.addr; | |
568 | llis_va[num_llis].dst = txd->dstbus.addr; | |
569 | ||
570 | /* | |
571 | * On versions with dual masters, you can optionally AND on | |
572 | * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read | |
573 | * in new LLIs with that controller, but we always try to | |
574 | * choose AHB1 to point into memory. The idea is to have AHB2 | |
575 | * fixed on the peripheral and AHB1 messing around in the | |
576 | * memory. So we don't manipulate this bit currently. | |
577 | */ | |
578 | ||
56b61882 | 579 | llis_va[num_llis].next = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli); |
e8689e63 LW |
580 | |
581 | if (cctl & PL080_CONTROL_SRC_INCR) | |
582 | txd->srcbus.addr += len; | |
583 | if (cctl & PL080_CONTROL_DST_INCR) | |
584 | txd->dstbus.addr += len; | |
585 | ||
cace6585 RKAL |
586 | BUG_ON(*remainder < len); |
587 | ||
e8689e63 LW |
588 | *remainder -= len; |
589 | ||
590 | return num_llis + 1; | |
591 | } | |
592 | ||
593 | /* | |
594 | * Return number of bytes to fill to boundary, or len | |
595 | */ | |
cace6585 | 596 | static inline size_t pl08x_pre_boundary(u32 addr, size_t len) |
e8689e63 LW |
597 | { |
598 | u32 boundary; | |
599 | ||
600 | boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1) | |
601 | << PL08X_BOUNDARY_SHIFT; | |
602 | ||
603 | if (boundary < addr + len) | |
604 | return boundary - addr; | |
605 | else | |
606 | return len; | |
607 | } | |
608 | ||
609 | /* | |
610 | * This fills in the table of LLIs for the transfer descriptor | |
611 | * Note that we assume we never have to change the burst sizes | |
612 | * Return 0 for error | |
613 | */ | |
614 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
615 | struct pl08x_txd *txd) | |
616 | { | |
617 | struct pl08x_channel_data *cd = txd->cd; | |
618 | struct pl08x_bus_data *mbus, *sbus; | |
cace6585 | 619 | size_t remainder; |
e8689e63 LW |
620 | int num_llis = 0; |
621 | u32 cctl; | |
cace6585 RKAL |
622 | size_t max_bytes_per_lli; |
623 | size_t total_bytes = 0; | |
7cb72ad9 | 624 | struct pl08x_lli *llis_va; |
e8689e63 | 625 | |
e8689e63 LW |
626 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, |
627 | &txd->llis_bus); | |
628 | if (!txd->llis_va) { | |
629 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
630 | return 0; | |
631 | } | |
632 | ||
633 | pl08x->pool_ctr++; | |
634 | ||
635 | /* | |
636 | * Initialize bus values for this transfer | |
637 | * from the passed optimal values | |
638 | */ | |
639 | if (!cd) { | |
640 | dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__); | |
641 | return 0; | |
642 | } | |
643 | ||
644 | /* Get the default CCTL from the platform data */ | |
645 | cctl = cd->cctl; | |
646 | ||
647 | /* | |
648 | * On the PL080 we have two bus masters and we | |
649 | * should select one for source and one for | |
650 | * destination. We try to use AHB2 for the | |
651 | * bus which does not increment (typically the | |
652 | * peripheral) else we just choose something. | |
653 | */ | |
654 | cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); | |
655 | if (pl08x->vd->dualmaster) { | |
656 | if (cctl & PL080_CONTROL_SRC_INCR) | |
657 | /* Source increments, use AHB2 for destination */ | |
658 | cctl |= PL080_CONTROL_DST_AHB2; | |
659 | else if (cctl & PL080_CONTROL_DST_INCR) | |
660 | /* Destination increments, use AHB2 for source */ | |
661 | cctl |= PL080_CONTROL_SRC_AHB2; | |
662 | else | |
663 | /* Just pick something, source AHB1 dest AHB2 */ | |
664 | cctl |= PL080_CONTROL_DST_AHB2; | |
665 | } | |
666 | ||
667 | /* Find maximum width of the source bus */ | |
668 | txd->srcbus.maxwidth = | |
669 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> | |
670 | PL080_CONTROL_SWIDTH_SHIFT); | |
671 | ||
672 | /* Find maximum width of the destination bus */ | |
673 | txd->dstbus.maxwidth = | |
674 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> | |
675 | PL080_CONTROL_DWIDTH_SHIFT); | |
676 | ||
677 | /* Set up the bus widths to the maximum */ | |
678 | txd->srcbus.buswidth = txd->srcbus.maxwidth; | |
679 | txd->dstbus.buswidth = txd->dstbus.maxwidth; | |
680 | dev_vdbg(&pl08x->adev->dev, | |
681 | "%s source bus is %d bytes wide, dest bus is %d bytes wide\n", | |
682 | __func__, txd->srcbus.buswidth, txd->dstbus.buswidth); | |
683 | ||
684 | ||
685 | /* | |
686 | * Bytes transferred == tsize * MIN(buswidths), not max(buswidths) | |
687 | */ | |
688 | max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) * | |
689 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
690 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 691 | "%s max bytes per lli = %zu\n", |
e8689e63 LW |
692 | __func__, max_bytes_per_lli); |
693 | ||
694 | /* We need to count this down to zero */ | |
695 | remainder = txd->len; | |
696 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 697 | "%s remainder = %zu\n", |
e8689e63 LW |
698 | __func__, remainder); |
699 | ||
700 | /* | |
701 | * Choose bus to align to | |
702 | * - prefers destination bus if both available | |
703 | * - if fixed address on one bus chooses other | |
e8b5e11d | 704 | * - modifies cctl to choose an appropriate master |
e8689e63 LW |
705 | */ |
706 | pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus, | |
707 | &mbus, &sbus, cctl); | |
708 | ||
709 | ||
710 | /* | |
711 | * The lowest bit of the LLI register | |
712 | * is also used to indicate which master to | |
713 | * use for reading the LLIs. | |
714 | */ | |
715 | ||
716 | if (txd->len < mbus->buswidth) { | |
717 | /* | |
718 | * Less than a bus width available | |
719 | * - send as single bytes | |
720 | */ | |
721 | while (remainder) { | |
722 | dev_vdbg(&pl08x->adev->dev, | |
723 | "%s single byte LLIs for a transfer of " | |
9c132992 | 724 | "less than a bus width (remain 0x%08x)\n", |
e8689e63 LW |
725 | __func__, remainder); |
726 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); | |
727 | num_llis = | |
728 | pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1, | |
729 | cctl, &remainder); | |
730 | total_bytes++; | |
731 | } | |
732 | } else { | |
733 | /* | |
734 | * Make one byte LLIs until master bus is aligned | |
735 | * - slave will then be aligned also | |
736 | */ | |
737 | while ((mbus->addr) % (mbus->buswidth)) { | |
738 | dev_vdbg(&pl08x->adev->dev, | |
739 | "%s adjustment lli for less than bus width " | |
9c132992 | 740 | "(remain 0x%08x)\n", |
e8689e63 LW |
741 | __func__, remainder); |
742 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); | |
743 | num_llis = pl08x_fill_lli_for_desc | |
744 | (pl08x, txd, num_llis, 1, cctl, &remainder); | |
745 | total_bytes++; | |
746 | } | |
747 | ||
748 | /* | |
749 | * Master now aligned | |
750 | * - if slave is not then we must set its width down | |
751 | */ | |
752 | if (sbus->addr % sbus->buswidth) { | |
753 | dev_dbg(&pl08x->adev->dev, | |
754 | "%s set down bus width to one byte\n", | |
755 | __func__); | |
756 | ||
757 | sbus->buswidth = 1; | |
758 | } | |
759 | ||
760 | /* | |
761 | * Make largest possible LLIs until less than one bus | |
762 | * width left | |
763 | */ | |
764 | while (remainder > (mbus->buswidth - 1)) { | |
cace6585 | 765 | size_t lli_len, target_len, tsize, odd_bytes; |
e8689e63 LW |
766 | |
767 | /* | |
768 | * If enough left try to send max possible, | |
769 | * otherwise try to send the remainder | |
770 | */ | |
771 | target_len = remainder; | |
772 | if (remainder > max_bytes_per_lli) | |
773 | target_len = max_bytes_per_lli; | |
774 | ||
775 | /* | |
e8b5e11d | 776 | * Set bus lengths for incrementing buses |
e8689e63 LW |
777 | * to number of bytes which fill to next memory |
778 | * boundary | |
779 | */ | |
780 | if (cctl & PL080_CONTROL_SRC_INCR) | |
781 | txd->srcbus.fill_bytes = | |
782 | pl08x_pre_boundary( | |
783 | txd->srcbus.addr, | |
784 | remainder); | |
785 | else | |
786 | txd->srcbus.fill_bytes = | |
787 | max_bytes_per_lli; | |
788 | ||
789 | if (cctl & PL080_CONTROL_DST_INCR) | |
790 | txd->dstbus.fill_bytes = | |
791 | pl08x_pre_boundary( | |
792 | txd->dstbus.addr, | |
793 | remainder); | |
794 | else | |
795 | txd->dstbus.fill_bytes = | |
796 | max_bytes_per_lli; | |
797 | ||
798 | /* | |
799 | * Find the nearest | |
800 | */ | |
801 | lli_len = min(txd->srcbus.fill_bytes, | |
802 | txd->dstbus.fill_bytes); | |
803 | ||
804 | BUG_ON(lli_len > remainder); | |
805 | ||
806 | if (lli_len <= 0) { | |
807 | dev_err(&pl08x->adev->dev, | |
cace6585 | 808 | "%s lli_len is %zu, <= 0\n", |
e8689e63 LW |
809 | __func__, lli_len); |
810 | return 0; | |
811 | } | |
812 | ||
813 | if (lli_len == target_len) { | |
814 | /* | |
815 | * Can send what we wanted | |
816 | */ | |
817 | /* | |
818 | * Maintain alignment | |
819 | */ | |
820 | lli_len = (lli_len/mbus->buswidth) * | |
821 | mbus->buswidth; | |
822 | odd_bytes = 0; | |
823 | } else { | |
824 | /* | |
825 | * So now we know how many bytes to transfer | |
826 | * to get to the nearest boundary | |
e8b5e11d | 827 | * The next LLI will past the boundary |
e8689e63 LW |
828 | * - however we may be working to a boundary |
829 | * on the slave bus | |
830 | * We need to ensure the master stays aligned | |
831 | */ | |
832 | odd_bytes = lli_len % mbus->buswidth; | |
833 | /* | |
834 | * - and that we are working in multiples | |
835 | * of the bus widths | |
836 | */ | |
837 | lli_len -= odd_bytes; | |
838 | ||
839 | } | |
840 | ||
841 | if (lli_len) { | |
842 | /* | |
843 | * Check against minimum bus alignment: | |
844 | * Calculate actual transfer size in relation | |
845 | * to bus width an get a maximum remainder of | |
846 | * the smallest bus width - 1 | |
847 | */ | |
848 | /* FIXME: use round_down()? */ | |
849 | tsize = lli_len / min(mbus->buswidth, | |
850 | sbus->buswidth); | |
851 | lli_len = tsize * min(mbus->buswidth, | |
852 | sbus->buswidth); | |
853 | ||
854 | if (target_len != lli_len) { | |
855 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 856 | "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n", |
e8689e63 LW |
857 | __func__, target_len, lli_len, txd->len); |
858 | } | |
859 | ||
860 | cctl = pl08x_cctl_bits(cctl, | |
861 | txd->srcbus.buswidth, | |
862 | txd->dstbus.buswidth, | |
863 | tsize); | |
864 | ||
865 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 866 | "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n", |
e8689e63 LW |
867 | __func__, lli_len, remainder); |
868 | num_llis = pl08x_fill_lli_for_desc(pl08x, txd, | |
869 | num_llis, lli_len, cctl, | |
870 | &remainder); | |
871 | total_bytes += lli_len; | |
872 | } | |
873 | ||
874 | ||
875 | if (odd_bytes) { | |
876 | /* | |
877 | * Creep past the boundary, | |
878 | * maintaining master alignment | |
879 | */ | |
880 | int j; | |
881 | for (j = 0; (j < mbus->buswidth) | |
882 | && (remainder); j++) { | |
883 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); | |
884 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 885 | "%s align with boundary, single byte (remain 0x%08zx)\n", |
e8689e63 LW |
886 | __func__, remainder); |
887 | num_llis = | |
888 | pl08x_fill_lli_for_desc(pl08x, | |
889 | txd, num_llis, 1, | |
890 | cctl, &remainder); | |
891 | total_bytes++; | |
892 | } | |
893 | } | |
894 | } | |
895 | ||
896 | /* | |
897 | * Send any odd bytes | |
898 | */ | |
e8689e63 LW |
899 | while (remainder) { |
900 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); | |
901 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 902 | "%s align with boundary, single odd byte (remain %zu)\n", |
e8689e63 LW |
903 | __func__, remainder); |
904 | num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis, | |
905 | 1, cctl, &remainder); | |
906 | total_bytes++; | |
907 | } | |
908 | } | |
909 | if (total_bytes != txd->len) { | |
910 | dev_err(&pl08x->adev->dev, | |
cace6585 | 911 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", |
e8689e63 LW |
912 | __func__, total_bytes, txd->len); |
913 | return 0; | |
914 | } | |
915 | ||
916 | if (num_llis >= MAX_NUM_TSFR_LLIS) { | |
917 | dev_err(&pl08x->adev->dev, | |
918 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
919 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
920 | return 0; | |
921 | } | |
b58b6b5b RKAL |
922 | |
923 | llis_va = txd->llis_va; | |
e8689e63 | 924 | /* |
b58b6b5b | 925 | * The final LLI terminates the LLI. |
e8689e63 | 926 | */ |
b58b6b5b RKAL |
927 | llis_va[num_llis - 1].next = 0; |
928 | /* | |
929 | * The final LLI element shall also fire an interrupt | |
930 | */ | |
931 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; | |
e8689e63 LW |
932 | |
933 | /* Now store the channel register values */ | |
934 | txd->csrc = llis_va[0].src; | |
935 | txd->cdst = llis_va[0].dst; | |
b58b6b5b | 936 | txd->clli = llis_va[0].next; |
e8689e63 LW |
937 | txd->cctl = llis_va[0].cctl; |
938 | /* ccfg will be set at physical channel allocation time */ | |
939 | ||
940 | #ifdef VERBOSE_DEBUG | |
941 | { | |
942 | int i; | |
943 | ||
944 | for (i = 0; i < num_llis; i++) { | |
945 | dev_vdbg(&pl08x->adev->dev, | |
9c132992 | 946 | "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n", |
e8689e63 LW |
947 | i, |
948 | &llis_va[i], | |
949 | llis_va[i].src, | |
950 | llis_va[i].dst, | |
951 | llis_va[i].cctl, | |
952 | llis_va[i].next | |
953 | ); | |
954 | } | |
955 | } | |
956 | #endif | |
957 | ||
958 | return num_llis; | |
959 | } | |
960 | ||
961 | /* You should call this with the struct pl08x lock held */ | |
962 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, | |
963 | struct pl08x_txd *txd) | |
964 | { | |
e8689e63 | 965 | /* Free the LLI */ |
56b61882 | 966 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); |
e8689e63 LW |
967 | |
968 | pl08x->pool_ctr--; | |
969 | ||
970 | kfree(txd); | |
971 | } | |
972 | ||
973 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, | |
974 | struct pl08x_dma_chan *plchan) | |
975 | { | |
976 | struct pl08x_txd *txdi = NULL; | |
977 | struct pl08x_txd *next; | |
978 | ||
979 | if (!list_empty(&plchan->desc_list)) { | |
980 | list_for_each_entry_safe(txdi, | |
981 | next, &plchan->desc_list, node) { | |
982 | list_del(&txdi->node); | |
983 | pl08x_free_txd(pl08x, txdi); | |
984 | } | |
985 | ||
986 | } | |
987 | } | |
988 | ||
989 | /* | |
990 | * The DMA ENGINE API | |
991 | */ | |
992 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
993 | { | |
994 | return 0; | |
995 | } | |
996 | ||
997 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
998 | { | |
999 | } | |
1000 | ||
1001 | /* | |
1002 | * This should be called with the channel plchan->lock held | |
1003 | */ | |
1004 | static int prep_phy_channel(struct pl08x_dma_chan *plchan, | |
1005 | struct pl08x_txd *txd) | |
1006 | { | |
1007 | struct pl08x_driver_data *pl08x = plchan->host; | |
1008 | struct pl08x_phy_chan *ch; | |
1009 | int ret; | |
1010 | ||
1011 | /* Check if we already have a channel */ | |
1012 | if (plchan->phychan) | |
1013 | return 0; | |
1014 | ||
1015 | ch = pl08x_get_phy_channel(pl08x, plchan); | |
1016 | if (!ch) { | |
1017 | /* No physical channel available, cope with it */ | |
1018 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
1019 | return -EBUSY; | |
1020 | } | |
1021 | ||
1022 | /* | |
1023 | * OK we have a physical channel: for memcpy() this is all we | |
1024 | * need, but for slaves the physical signals may be muxed! | |
1025 | * Can the platform allow us to use this channel? | |
1026 | */ | |
1027 | if (plchan->slave && | |
1028 | ch->signal < 0 && | |
1029 | pl08x->pd->get_signal) { | |
1030 | ret = pl08x->pd->get_signal(plchan); | |
1031 | if (ret < 0) { | |
1032 | dev_dbg(&pl08x->adev->dev, | |
1033 | "unable to use physical channel %d for transfer on %s due to platform restrictions\n", | |
1034 | ch->id, plchan->name); | |
1035 | /* Release physical channel & return */ | |
1036 | pl08x_put_phy_channel(pl08x, ch); | |
1037 | return -EBUSY; | |
1038 | } | |
1039 | ch->signal = ret; | |
1040 | } | |
1041 | ||
1042 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n", | |
1043 | ch->id, | |
1044 | ch->signal, | |
1045 | plchan->name); | |
1046 | ||
1047 | plchan->phychan = ch; | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
8c8cc2b1 RKAL |
1052 | static void release_phy_channel(struct pl08x_dma_chan *plchan) |
1053 | { | |
1054 | struct pl08x_driver_data *pl08x = plchan->host; | |
1055 | ||
1056 | if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) { | |
1057 | pl08x->pd->put_signal(plchan); | |
1058 | plchan->phychan->signal = -1; | |
1059 | } | |
1060 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
1061 | plchan->phychan = NULL; | |
1062 | } | |
1063 | ||
e8689e63 LW |
1064 | static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) |
1065 | { | |
1066 | struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); | |
1067 | ||
91aa5fad RKAL |
1068 | plchan->chan.cookie += 1; |
1069 | if (plchan->chan.cookie < 0) | |
1070 | plchan->chan.cookie = 1; | |
1071 | tx->cookie = plchan->chan.cookie; | |
e8689e63 LW |
1072 | /* This unlock follows the lock in the prep() function */ |
1073 | spin_unlock_irqrestore(&plchan->lock, plchan->lockflags); | |
1074 | ||
1075 | return tx->cookie; | |
1076 | } | |
1077 | ||
1078 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( | |
1079 | struct dma_chan *chan, unsigned long flags) | |
1080 | { | |
1081 | struct dma_async_tx_descriptor *retval = NULL; | |
1082 | ||
1083 | return retval; | |
1084 | } | |
1085 | ||
1086 | /* | |
1087 | * Code accessing dma_async_is_complete() in a tight loop | |
1088 | * may give problems - could schedule where indicated. | |
1089 | * If slaves are relying on interrupts to signal completion this | |
1090 | * function must not be called with interrupts disabled | |
1091 | */ | |
1092 | static enum dma_status | |
1093 | pl08x_dma_tx_status(struct dma_chan *chan, | |
1094 | dma_cookie_t cookie, | |
1095 | struct dma_tx_state *txstate) | |
1096 | { | |
1097 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1098 | dma_cookie_t last_used; | |
1099 | dma_cookie_t last_complete; | |
1100 | enum dma_status ret; | |
1101 | u32 bytesleft = 0; | |
1102 | ||
91aa5fad | 1103 | last_used = plchan->chan.cookie; |
e8689e63 LW |
1104 | last_complete = plchan->lc; |
1105 | ||
1106 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
1107 | if (ret == DMA_SUCCESS) { | |
1108 | dma_set_tx_state(txstate, last_complete, last_used, 0); | |
1109 | return ret; | |
1110 | } | |
1111 | ||
1112 | /* | |
1113 | * schedule(); could be inserted here | |
1114 | */ | |
1115 | ||
1116 | /* | |
1117 | * This cookie not complete yet | |
1118 | */ | |
91aa5fad | 1119 | last_used = plchan->chan.cookie; |
e8689e63 LW |
1120 | last_complete = plchan->lc; |
1121 | ||
1122 | /* Get number of bytes left in the active transactions and queue */ | |
1123 | bytesleft = pl08x_getbytes_chan(plchan); | |
1124 | ||
1125 | dma_set_tx_state(txstate, last_complete, last_used, | |
1126 | bytesleft); | |
1127 | ||
1128 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1129 | return DMA_PAUSED; | |
1130 | ||
1131 | /* Whether waiting or running, we're in progress */ | |
1132 | return DMA_IN_PROGRESS; | |
1133 | } | |
1134 | ||
1135 | /* PrimeCell DMA extension */ | |
1136 | struct burst_table { | |
1137 | int burstwords; | |
1138 | u32 reg; | |
1139 | }; | |
1140 | ||
1141 | static const struct burst_table burst_sizes[] = { | |
1142 | { | |
1143 | .burstwords = 256, | |
1144 | .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1145 | (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1146 | }, | |
1147 | { | |
1148 | .burstwords = 128, | |
1149 | .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1150 | (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1151 | }, | |
1152 | { | |
1153 | .burstwords = 64, | |
1154 | .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1155 | (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1156 | }, | |
1157 | { | |
1158 | .burstwords = 32, | |
1159 | .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1160 | (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1161 | }, | |
1162 | { | |
1163 | .burstwords = 16, | |
1164 | .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1165 | (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1166 | }, | |
1167 | { | |
1168 | .burstwords = 8, | |
1169 | .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1170 | (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1171 | }, | |
1172 | { | |
1173 | .burstwords = 4, | |
1174 | .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1175 | (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1176 | }, | |
1177 | { | |
1178 | .burstwords = 1, | |
1179 | .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) | | |
1180 | (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT), | |
1181 | }, | |
1182 | }; | |
1183 | ||
1184 | static void dma_set_runtime_config(struct dma_chan *chan, | |
1185 | struct dma_slave_config *config) | |
1186 | { | |
1187 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1188 | struct pl08x_driver_data *pl08x = plchan->host; | |
1189 | struct pl08x_channel_data *cd = plchan->cd; | |
1190 | enum dma_slave_buswidth addr_width; | |
1191 | u32 maxburst; | |
1192 | u32 cctl = 0; | |
1193 | /* Mask out all except src and dst channel */ | |
1194 | u32 ccfg = cd->ccfg & 0x000003DEU; | |
4440aacf | 1195 | int i; |
e8689e63 LW |
1196 | |
1197 | /* Transfer direction */ | |
1198 | plchan->runtime_direction = config->direction; | |
1199 | if (config->direction == DMA_TO_DEVICE) { | |
1200 | plchan->runtime_addr = config->dst_addr; | |
1201 | cctl |= PL080_CONTROL_SRC_INCR; | |
1202 | ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1203 | addr_width = config->dst_addr_width; | |
1204 | maxburst = config->dst_maxburst; | |
1205 | } else if (config->direction == DMA_FROM_DEVICE) { | |
1206 | plchan->runtime_addr = config->src_addr; | |
1207 | cctl |= PL080_CONTROL_DST_INCR; | |
1208 | ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1209 | addr_width = config->src_addr_width; | |
1210 | maxburst = config->src_maxburst; | |
1211 | } else { | |
1212 | dev_err(&pl08x->adev->dev, | |
1213 | "bad runtime_config: alien transfer direction\n"); | |
1214 | return; | |
1215 | } | |
1216 | ||
1217 | switch (addr_width) { | |
1218 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1219 | cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) | | |
1220 | (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT); | |
1221 | break; | |
1222 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1223 | cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) | | |
1224 | (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT); | |
1225 | break; | |
1226 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1227 | cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) | | |
1228 | (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT); | |
1229 | break; | |
1230 | default: | |
1231 | dev_err(&pl08x->adev->dev, | |
1232 | "bad runtime_config: alien address width\n"); | |
1233 | return; | |
1234 | } | |
1235 | ||
1236 | /* | |
1237 | * Now decide on a maxburst: | |
4440aacf RKAL |
1238 | * If this channel will only request single transfers, set this |
1239 | * down to ONE element. Also select one element if no maxburst | |
1240 | * is specified. | |
e8689e63 | 1241 | */ |
4440aacf | 1242 | if (plchan->cd->single || maxburst == 0) { |
e8689e63 LW |
1243 | cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) | |
1244 | (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT); | |
1245 | } else { | |
4440aacf | 1246 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) |
e8689e63 LW |
1247 | if (burst_sizes[i].burstwords <= maxburst) |
1248 | break; | |
e8689e63 LW |
1249 | cctl |= burst_sizes[i].reg; |
1250 | } | |
1251 | ||
1252 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1253 | cctl &= ~PL080_CONTROL_PROT_MASK; | |
1254 | cctl |= PL080_CONTROL_PROT_SYS; | |
1255 | ||
1256 | /* Modify the default channel data to fit PrimeCell request */ | |
1257 | cd->cctl = cctl; | |
1258 | cd->ccfg = ccfg; | |
1259 | ||
1260 | dev_dbg(&pl08x->adev->dev, | |
1261 | "configured channel %s (%s) for %s, data width %d, " | |
9c132992 | 1262 | "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n", |
e8689e63 LW |
1263 | dma_chan_name(chan), plchan->name, |
1264 | (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", | |
1265 | addr_width, | |
1266 | maxburst, | |
1267 | cctl, ccfg); | |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * Slave transactions callback to the slave device to allow | |
1272 | * synchronization of slave DMA signals with the DMAC enable | |
1273 | */ | |
1274 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1275 | { | |
1276 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1277 | struct pl08x_driver_data *pl08x = plchan->host; | |
1278 | unsigned long flags; | |
1279 | ||
1280 | spin_lock_irqsave(&plchan->lock, flags); | |
9c0bb43b RKAL |
1281 | /* Something is already active, or we're waiting for a channel... */ |
1282 | if (plchan->at || plchan->state == PL08X_CHAN_WAITING) { | |
1283 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1284 | return; |
9c0bb43b | 1285 | } |
e8689e63 LW |
1286 | |
1287 | /* Take the first element in the queue and execute it */ | |
1288 | if (!list_empty(&plchan->desc_list)) { | |
1289 | struct pl08x_txd *next; | |
1290 | ||
1291 | next = list_first_entry(&plchan->desc_list, | |
1292 | struct pl08x_txd, | |
1293 | node); | |
1294 | list_del(&next->node); | |
1295 | plchan->at = next; | |
1296 | plchan->state = PL08X_CHAN_RUNNING; | |
1297 | ||
1298 | /* Configure the physical channel for the active txd */ | |
1299 | pl08x_config_phychan_for_txd(plchan); | |
1300 | pl08x_set_cregs(pl08x, plchan->phychan); | |
1301 | pl08x_enable_phy_chan(pl08x, plchan->phychan); | |
1302 | } | |
1303 | ||
1304 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1305 | } | |
1306 | ||
1307 | static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, | |
1308 | struct pl08x_txd *txd) | |
1309 | { | |
1310 | int num_llis; | |
1311 | struct pl08x_driver_data *pl08x = plchan->host; | |
1312 | int ret; | |
1313 | ||
1314 | num_llis = pl08x_fill_llis_for_desc(pl08x, txd); | |
dafa7317 RKAL |
1315 | if (!num_llis) { |
1316 | kfree(txd); | |
e8689e63 | 1317 | return -EINVAL; |
dafa7317 | 1318 | } |
e8689e63 LW |
1319 | |
1320 | spin_lock_irqsave(&plchan->lock, plchan->lockflags); | |
1321 | ||
b58b6b5b | 1322 | list_add_tail(&txd->node, &plchan->desc_list); |
e8689e63 LW |
1323 | |
1324 | /* | |
1325 | * See if we already have a physical channel allocated, | |
1326 | * else this is the time to try to get one. | |
1327 | */ | |
1328 | ret = prep_phy_channel(plchan, txd); | |
1329 | if (ret) { | |
1330 | /* | |
1331 | * No physical channel available, we will | |
1332 | * stack up the memcpy channels until there is a channel | |
1333 | * available to handle it whereas slave transfers may | |
1334 | * have been denied due to platform channel muxing restrictions | |
1335 | * and since there is no guarantee that this will ever be | |
e8b5e11d RKAL |
1336 | * resolved, and since the signal must be acquired AFTER |
1337 | * acquiring the physical channel, we will let them be NACK:ed | |
e8689e63 LW |
1338 | * with -EBUSY here. The drivers can alway retry the prep() |
1339 | * call if they are eager on doing this using DMA. | |
1340 | */ | |
1341 | if (plchan->slave) { | |
1342 | pl08x_free_txd_list(pl08x, plchan); | |
1343 | spin_unlock_irqrestore(&plchan->lock, plchan->lockflags); | |
1344 | return -EBUSY; | |
1345 | } | |
1346 | /* Do this memcpy whenever there is a channel ready */ | |
1347 | plchan->state = PL08X_CHAN_WAITING; | |
1348 | plchan->waiting = txd; | |
1349 | } else | |
1350 | /* | |
1351 | * Else we're all set, paused and ready to roll, | |
1352 | * status will switch to PL08X_CHAN_RUNNING when | |
1353 | * we call issue_pending(). If there is something | |
1354 | * running on the channel already we don't change | |
1355 | * its state. | |
1356 | */ | |
1357 | if (plchan->state == PL08X_CHAN_IDLE) | |
1358 | plchan->state = PL08X_CHAN_PAUSED; | |
1359 | ||
1360 | /* | |
1361 | * Notice that we leave plchan->lock locked on purpose: | |
1362 | * it will be unlocked in the subsequent tx_submit() | |
1363 | * call. This is a consequence of the current API. | |
1364 | */ | |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
ac3cd20d RKAL |
1369 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
1370 | { | |
1371 | struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT); | |
1372 | ||
1373 | if (txd) { | |
1374 | dma_async_tx_descriptor_init(&txd->tx, &plchan->chan); | |
1375 | txd->tx.tx_submit = pl08x_tx_submit; | |
1376 | INIT_LIST_HEAD(&txd->node); | |
1377 | } | |
1378 | return txd; | |
1379 | } | |
1380 | ||
e8689e63 LW |
1381 | /* |
1382 | * Initialize a descriptor to be used by memcpy submit | |
1383 | */ | |
1384 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1385 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1386 | size_t len, unsigned long flags) | |
1387 | { | |
1388 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1389 | struct pl08x_driver_data *pl08x = plchan->host; | |
1390 | struct pl08x_txd *txd; | |
1391 | int ret; | |
1392 | ||
ac3cd20d | 1393 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1394 | if (!txd) { |
1395 | dev_err(&pl08x->adev->dev, | |
1396 | "%s no memory for descriptor\n", __func__); | |
1397 | return NULL; | |
1398 | } | |
1399 | ||
e8689e63 LW |
1400 | txd->direction = DMA_NONE; |
1401 | txd->srcbus.addr = src; | |
1402 | txd->dstbus.addr = dest; | |
1403 | ||
1404 | /* Set platform data for m2m */ | |
1405 | txd->cd = &pl08x->pd->memcpy_channel; | |
1406 | /* Both to be incremented or the code will break */ | |
1407 | txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; | |
e8689e63 LW |
1408 | txd->len = len; |
1409 | ||
e8689e63 LW |
1410 | ret = pl08x_prep_channel_resources(plchan, txd); |
1411 | if (ret) | |
1412 | return NULL; | |
1413 | /* | |
1414 | * NB: the channel lock is held at this point so tx_submit() | |
1415 | * must be called in direct succession. | |
1416 | */ | |
1417 | ||
1418 | return &txd->tx; | |
1419 | } | |
1420 | ||
3e2a037c | 1421 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 LW |
1422 | struct dma_chan *chan, struct scatterlist *sgl, |
1423 | unsigned int sg_len, enum dma_data_direction direction, | |
1424 | unsigned long flags) | |
1425 | { | |
1426 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1427 | struct pl08x_driver_data *pl08x = plchan->host; | |
1428 | struct pl08x_txd *txd; | |
1429 | int ret; | |
1430 | ||
1431 | /* | |
1432 | * Current implementation ASSUMES only one sg | |
1433 | */ | |
1434 | if (sg_len != 1) { | |
1435 | dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n", | |
1436 | __func__); | |
1437 | BUG(); | |
1438 | } | |
1439 | ||
1440 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", | |
1441 | __func__, sgl->length, plchan->name); | |
1442 | ||
ac3cd20d | 1443 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1444 | if (!txd) { |
1445 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1446 | return NULL; | |
1447 | } | |
1448 | ||
e8689e63 LW |
1449 | if (direction != plchan->runtime_direction) |
1450 | dev_err(&pl08x->adev->dev, "%s DMA setup does not match " | |
1451 | "the direction configured for the PrimeCell\n", | |
1452 | __func__); | |
1453 | ||
1454 | /* | |
1455 | * Set up addresses, the PrimeCell configured address | |
1456 | * will take precedence since this may configure the | |
1457 | * channel target address dynamically at runtime. | |
1458 | */ | |
1459 | txd->direction = direction; | |
1460 | if (direction == DMA_TO_DEVICE) { | |
1461 | txd->srcbus.addr = sgl->dma_address; | |
1462 | if (plchan->runtime_addr) | |
1463 | txd->dstbus.addr = plchan->runtime_addr; | |
1464 | else | |
1465 | txd->dstbus.addr = plchan->cd->addr; | |
1466 | } else if (direction == DMA_FROM_DEVICE) { | |
1467 | if (plchan->runtime_addr) | |
1468 | txd->srcbus.addr = plchan->runtime_addr; | |
1469 | else | |
1470 | txd->srcbus.addr = plchan->cd->addr; | |
1471 | txd->dstbus.addr = sgl->dma_address; | |
1472 | } else { | |
1473 | dev_err(&pl08x->adev->dev, | |
1474 | "%s direction unsupported\n", __func__); | |
1475 | return NULL; | |
1476 | } | |
1477 | txd->cd = plchan->cd; | |
e8689e63 | 1478 | txd->len = sgl->length; |
e8689e63 LW |
1479 | |
1480 | ret = pl08x_prep_channel_resources(plchan, txd); | |
1481 | if (ret) | |
1482 | return NULL; | |
1483 | /* | |
1484 | * NB: the channel lock is held at this point so tx_submit() | |
1485 | * must be called in direct succession. | |
1486 | */ | |
1487 | ||
1488 | return &txd->tx; | |
1489 | } | |
1490 | ||
1491 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1492 | unsigned long arg) | |
1493 | { | |
1494 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1495 | struct pl08x_driver_data *pl08x = plchan->host; | |
1496 | unsigned long flags; | |
1497 | int ret = 0; | |
1498 | ||
1499 | /* Controls applicable to inactive channels */ | |
1500 | if (cmd == DMA_SLAVE_CONFIG) { | |
1501 | dma_set_runtime_config(chan, | |
1502 | (struct dma_slave_config *) | |
1503 | arg); | |
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | /* | |
1508 | * Anything succeeds on channels with no physical allocation and | |
1509 | * no queued transfers. | |
1510 | */ | |
1511 | spin_lock_irqsave(&plchan->lock, flags); | |
1512 | if (!plchan->phychan && !plchan->at) { | |
1513 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | switch (cmd) { | |
1518 | case DMA_TERMINATE_ALL: | |
1519 | plchan->state = PL08X_CHAN_IDLE; | |
1520 | ||
1521 | if (plchan->phychan) { | |
1522 | pl08x_stop_phy_chan(plchan->phychan); | |
1523 | ||
1524 | /* | |
1525 | * Mark physical channel as free and free any slave | |
1526 | * signal | |
1527 | */ | |
8c8cc2b1 | 1528 | release_phy_channel(plchan); |
e8689e63 | 1529 | } |
e8689e63 LW |
1530 | /* Dequeue jobs and free LLIs */ |
1531 | if (plchan->at) { | |
1532 | pl08x_free_txd(pl08x, plchan->at); | |
1533 | plchan->at = NULL; | |
1534 | } | |
1535 | /* Dequeue jobs not yet fired as well */ | |
1536 | pl08x_free_txd_list(pl08x, plchan); | |
1537 | break; | |
1538 | case DMA_PAUSE: | |
1539 | pl08x_pause_phy_chan(plchan->phychan); | |
1540 | plchan->state = PL08X_CHAN_PAUSED; | |
1541 | break; | |
1542 | case DMA_RESUME: | |
1543 | pl08x_resume_phy_chan(plchan->phychan); | |
1544 | plchan->state = PL08X_CHAN_RUNNING; | |
1545 | break; | |
1546 | default: | |
1547 | /* Unknown command */ | |
1548 | ret = -ENXIO; | |
1549 | break; | |
1550 | } | |
1551 | ||
1552 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1553 | ||
1554 | return ret; | |
1555 | } | |
1556 | ||
1557 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1558 | { | |
1559 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1560 | char *name = chan_id; | |
1561 | ||
1562 | /* Check that the channel is not taken! */ | |
1563 | if (!strcmp(plchan->name, name)) | |
1564 | return true; | |
1565 | ||
1566 | return false; | |
1567 | } | |
1568 | ||
1569 | /* | |
1570 | * Just check that the device is there and active | |
1571 | * TODO: turn this bit on/off depending on the number of | |
1572 | * physical channels actually used, if it is zero... well | |
1573 | * shut it off. That will save some power. Cut the clock | |
1574 | * at the same time. | |
1575 | */ | |
1576 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1577 | { | |
1578 | u32 val; | |
1579 | ||
1580 | val = readl(pl08x->base + PL080_CONFIG); | |
1581 | val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE); | |
e8b5e11d | 1582 | /* We implicitly clear bit 1 and that means little-endian mode */ |
e8689e63 LW |
1583 | val |= PL080_CONFIG_ENABLE; |
1584 | writel(val, pl08x->base + PL080_CONFIG); | |
1585 | } | |
1586 | ||
1587 | static void pl08x_tasklet(unsigned long data) | |
1588 | { | |
1589 | struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; | |
e8689e63 | 1590 | struct pl08x_driver_data *pl08x = plchan->host; |
bf072af4 | 1591 | unsigned long flags; |
e8689e63 | 1592 | |
bf072af4 | 1593 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 LW |
1594 | |
1595 | if (plchan->at) { | |
1596 | dma_async_tx_callback callback = | |
1597 | plchan->at->tx.callback; | |
1598 | void *callback_param = | |
1599 | plchan->at->tx.callback_param; | |
1600 | ||
1601 | /* | |
1602 | * Update last completed | |
1603 | */ | |
91aa5fad | 1604 | plchan->lc = plchan->at->tx.cookie; |
e8689e63 LW |
1605 | |
1606 | /* | |
1607 | * Callback to signal completion | |
1608 | */ | |
1609 | if (callback) | |
1610 | callback(callback_param); | |
1611 | ||
e8689e63 | 1612 | /* |
b58b6b5b | 1613 | * Free the descriptor |
e8689e63 | 1614 | */ |
b58b6b5b RKAL |
1615 | pl08x_free_txd(pl08x, plchan->at); |
1616 | plchan->at = NULL; | |
e8689e63 LW |
1617 | } |
1618 | /* | |
1619 | * If a new descriptor is queued, set it up | |
1620 | * plchan->at is NULL here | |
1621 | */ | |
1622 | if (!list_empty(&plchan->desc_list)) { | |
1623 | struct pl08x_txd *next; | |
1624 | ||
1625 | next = list_first_entry(&plchan->desc_list, | |
1626 | struct pl08x_txd, | |
1627 | node); | |
1628 | list_del(&next->node); | |
1629 | plchan->at = next; | |
1630 | /* Configure the physical channel for the next txd */ | |
1631 | pl08x_config_phychan_for_txd(plchan); | |
1632 | pl08x_set_cregs(pl08x, plchan->phychan); | |
1633 | pl08x_enable_phy_chan(pl08x, plchan->phychan); | |
1634 | } else { | |
1635 | struct pl08x_dma_chan *waiting = NULL; | |
1636 | ||
1637 | /* | |
1638 | * No more jobs, so free up the physical channel | |
1639 | * Free any allocated signal on slave transfers too | |
1640 | */ | |
8c8cc2b1 | 1641 | release_phy_channel(plchan); |
e8689e63 LW |
1642 | plchan->state = PL08X_CHAN_IDLE; |
1643 | ||
1644 | /* | |
1645 | * And NOW before anyone else can grab that free:d | |
1646 | * up physical channel, see if there is some memcpy | |
1647 | * pending that seriously needs to start because of | |
1648 | * being stacked up while we were choking the | |
1649 | * physical channels with data. | |
1650 | */ | |
1651 | list_for_each_entry(waiting, &pl08x->memcpy.channels, | |
1652 | chan.device_node) { | |
1653 | if (waiting->state == PL08X_CHAN_WAITING && | |
1654 | waiting->waiting != NULL) { | |
1655 | int ret; | |
1656 | ||
1657 | /* This should REALLY not fail now */ | |
1658 | ret = prep_phy_channel(waiting, | |
1659 | waiting->waiting); | |
1660 | BUG_ON(ret); | |
1661 | waiting->state = PL08X_CHAN_RUNNING; | |
1662 | waiting->waiting = NULL; | |
1663 | pl08x_issue_pending(&waiting->chan); | |
1664 | break; | |
1665 | } | |
1666 | } | |
1667 | } | |
1668 | ||
bf072af4 | 1669 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1670 | } |
1671 | ||
1672 | static irqreturn_t pl08x_irq(int irq, void *dev) | |
1673 | { | |
1674 | struct pl08x_driver_data *pl08x = dev; | |
1675 | u32 mask = 0; | |
1676 | u32 val; | |
1677 | int i; | |
1678 | ||
1679 | val = readl(pl08x->base + PL080_ERR_STATUS); | |
1680 | if (val) { | |
1681 | /* | |
1682 | * An error interrupt (on one or more channels) | |
1683 | */ | |
1684 | dev_err(&pl08x->adev->dev, | |
1685 | "%s error interrupt, register value 0x%08x\n", | |
1686 | __func__, val); | |
1687 | /* | |
1688 | * Simply clear ALL PL08X error interrupts, | |
1689 | * regardless of channel and cause | |
1690 | * FIXME: should be 0x00000003 on PL081 really. | |
1691 | */ | |
1692 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); | |
1693 | } | |
1694 | val = readl(pl08x->base + PL080_INT_STATUS); | |
1695 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1696 | if ((1 << i) & val) { | |
1697 | /* Locate physical channel */ | |
1698 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1699 | struct pl08x_dma_chan *plchan = phychan->serving; | |
1700 | ||
1701 | /* Schedule tasklet on this channel */ | |
1702 | tasklet_schedule(&plchan->tasklet); | |
1703 | ||
1704 | mask |= (1 << i); | |
1705 | } | |
1706 | } | |
1707 | /* | |
1708 | * Clear only the terminal interrupts on channels we processed | |
1709 | */ | |
1710 | writel(mask, pl08x->base + PL080_TC_CLEAR); | |
1711 | ||
1712 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1713 | } | |
1714 | ||
1715 | /* | |
1716 | * Initialise the DMAC memcpy/slave channels. | |
1717 | * Make a local wrapper to hold required data | |
1718 | */ | |
1719 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
1720 | struct dma_device *dmadev, | |
1721 | unsigned int channels, | |
1722 | bool slave) | |
1723 | { | |
1724 | struct pl08x_dma_chan *chan; | |
1725 | int i; | |
1726 | ||
1727 | INIT_LIST_HEAD(&dmadev->channels); | |
1728 | /* | |
1729 | * Register as many many memcpy as we have physical channels, | |
1730 | * we won't always be able to use all but the code will have | |
1731 | * to cope with that situation. | |
1732 | */ | |
1733 | for (i = 0; i < channels; i++) { | |
1734 | chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL); | |
1735 | if (!chan) { | |
1736 | dev_err(&pl08x->adev->dev, | |
1737 | "%s no memory for channel\n", __func__); | |
1738 | return -ENOMEM; | |
1739 | } | |
1740 | ||
1741 | chan->host = pl08x; | |
1742 | chan->state = PL08X_CHAN_IDLE; | |
1743 | ||
1744 | if (slave) { | |
1745 | chan->slave = true; | |
1746 | chan->name = pl08x->pd->slave_channels[i].bus_id; | |
1747 | chan->cd = &pl08x->pd->slave_channels[i]; | |
1748 | } else { | |
1749 | chan->cd = &pl08x->pd->memcpy_channel; | |
1750 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1751 | if (!chan->name) { | |
1752 | kfree(chan); | |
1753 | return -ENOMEM; | |
1754 | } | |
1755 | } | |
b58b6b5b RKAL |
1756 | if (chan->cd->circular_buffer) { |
1757 | dev_err(&pl08x->adev->dev, | |
1758 | "channel %s: circular buffers not supported\n", | |
1759 | chan->name); | |
1760 | kfree(chan); | |
1761 | continue; | |
1762 | } | |
e8689e63 LW |
1763 | dev_info(&pl08x->adev->dev, |
1764 | "initialize virtual channel \"%s\"\n", | |
1765 | chan->name); | |
1766 | ||
1767 | chan->chan.device = dmadev; | |
91aa5fad RKAL |
1768 | chan->chan.cookie = 0; |
1769 | chan->lc = 0; | |
e8689e63 LW |
1770 | |
1771 | spin_lock_init(&chan->lock); | |
1772 | INIT_LIST_HEAD(&chan->desc_list); | |
1773 | tasklet_init(&chan->tasklet, pl08x_tasklet, | |
1774 | (unsigned long) chan); | |
1775 | ||
1776 | list_add_tail(&chan->chan.device_node, &dmadev->channels); | |
1777 | } | |
1778 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1779 | i, slave ? "slave" : "memcpy"); | |
1780 | return i; | |
1781 | } | |
1782 | ||
1783 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1784 | { | |
1785 | struct pl08x_dma_chan *chan = NULL; | |
1786 | struct pl08x_dma_chan *next; | |
1787 | ||
1788 | list_for_each_entry_safe(chan, | |
1789 | next, &dmadev->channels, chan.device_node) { | |
1790 | list_del(&chan->chan.device_node); | |
1791 | kfree(chan); | |
1792 | } | |
1793 | } | |
1794 | ||
1795 | #ifdef CONFIG_DEBUG_FS | |
1796 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1797 | { | |
1798 | switch (state) { | |
1799 | case PL08X_CHAN_IDLE: | |
1800 | return "idle"; | |
1801 | case PL08X_CHAN_RUNNING: | |
1802 | return "running"; | |
1803 | case PL08X_CHAN_PAUSED: | |
1804 | return "paused"; | |
1805 | case PL08X_CHAN_WAITING: | |
1806 | return "waiting"; | |
1807 | default: | |
1808 | break; | |
1809 | } | |
1810 | return "UNKNOWN STATE"; | |
1811 | } | |
1812 | ||
1813 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1814 | { | |
1815 | struct pl08x_driver_data *pl08x = s->private; | |
1816 | struct pl08x_dma_chan *chan; | |
1817 | struct pl08x_phy_chan *ch; | |
1818 | unsigned long flags; | |
1819 | int i; | |
1820 | ||
1821 | seq_printf(s, "PL08x physical channels:\n"); | |
1822 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1823 | seq_printf(s, "--------\t-----\n"); | |
1824 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1825 | struct pl08x_dma_chan *virt_chan; | |
1826 | ||
1827 | ch = &pl08x->phy_chans[i]; | |
1828 | ||
1829 | spin_lock_irqsave(&ch->lock, flags); | |
1830 | virt_chan = ch->serving; | |
1831 | ||
1832 | seq_printf(s, "%d\t\t%s\n", | |
1833 | ch->id, virt_chan ? virt_chan->name : "(none)"); | |
1834 | ||
1835 | spin_unlock_irqrestore(&ch->lock, flags); | |
1836 | } | |
1837 | ||
1838 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1839 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1840 | seq_printf(s, "--------\t------\n"); | |
1841 | list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) { | |
3e2a037c | 1842 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1843 | pl08x_state_str(chan->state)); |
1844 | } | |
1845 | ||
1846 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1847 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1848 | seq_printf(s, "--------\t------\n"); | |
1849 | list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) { | |
3e2a037c | 1850 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1851 | pl08x_state_str(chan->state)); |
1852 | } | |
1853 | ||
1854 | return 0; | |
1855 | } | |
1856 | ||
1857 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1858 | { | |
1859 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1860 | } | |
1861 | ||
1862 | static const struct file_operations pl08x_debugfs_operations = { | |
1863 | .open = pl08x_debugfs_open, | |
1864 | .read = seq_read, | |
1865 | .llseek = seq_lseek, | |
1866 | .release = single_release, | |
1867 | }; | |
1868 | ||
1869 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1870 | { | |
1871 | /* Expose a simple debugfs interface to view all clocks */ | |
1872 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO, | |
1873 | NULL, pl08x, | |
1874 | &pl08x_debugfs_operations); | |
1875 | } | |
1876 | ||
1877 | #else | |
1878 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1879 | { | |
1880 | } | |
1881 | #endif | |
1882 | ||
1883 | static int pl08x_probe(struct amba_device *adev, struct amba_id *id) | |
1884 | { | |
1885 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1886 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1887 | int ret = 0; |
1888 | int i; | |
1889 | ||
1890 | ret = amba_request_regions(adev, NULL); | |
1891 | if (ret) | |
1892 | return ret; | |
1893 | ||
1894 | /* Create the driver state holder */ | |
1895 | pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL); | |
1896 | if (!pl08x) { | |
1897 | ret = -ENOMEM; | |
1898 | goto out_no_pl08x; | |
1899 | } | |
1900 | ||
1901 | /* Initialize memcpy engine */ | |
1902 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1903 | pl08x->memcpy.dev = &adev->dev; | |
1904 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1905 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1906 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1907 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1908 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1909 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1910 | pl08x->memcpy.device_control = pl08x_control; | |
1911 | ||
1912 | /* Initialize slave engine */ | |
1913 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1914 | pl08x->slave.dev = &adev->dev; | |
1915 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1916 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1917 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1918 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1919 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1920 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1921 | pl08x->slave.device_control = pl08x_control; | |
1922 | ||
1923 | /* Get the platform data */ | |
1924 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1925 | if (!pl08x->pd) { | |
1926 | dev_err(&adev->dev, "no platform data supplied\n"); | |
1927 | goto out_no_platdata; | |
1928 | } | |
1929 | ||
1930 | /* Assign useful pointers to the driver state */ | |
1931 | pl08x->adev = adev; | |
1932 | pl08x->vd = vd; | |
1933 | ||
1934 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ | |
1935 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
1936 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
1937 | if (!pl08x->pool) { | |
1938 | ret = -ENOMEM; | |
1939 | goto out_no_lli_pool; | |
1940 | } | |
1941 | ||
1942 | spin_lock_init(&pl08x->lock); | |
1943 | ||
1944 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); | |
1945 | if (!pl08x->base) { | |
1946 | ret = -ENOMEM; | |
1947 | goto out_no_ioremap; | |
1948 | } | |
1949 | ||
1950 | /* Turn on the PL08x */ | |
1951 | pl08x_ensure_on(pl08x); | |
1952 | ||
1953 | /* | |
1954 | * Attach the interrupt handler | |
1955 | */ | |
1956 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); | |
1957 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
1958 | ||
1959 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 1960 | DRIVER_NAME, pl08x); |
e8689e63 LW |
1961 | if (ret) { |
1962 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
1963 | __func__, adev->irq[0]); | |
1964 | goto out_no_irq; | |
1965 | } | |
1966 | ||
1967 | /* Initialize physical channels */ | |
1968 | pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)), | |
1969 | GFP_KERNEL); | |
1970 | if (!pl08x->phy_chans) { | |
1971 | dev_err(&adev->dev, "%s failed to allocate " | |
1972 | "physical channel holders\n", | |
1973 | __func__); | |
1974 | goto out_no_phychans; | |
1975 | } | |
1976 | ||
1977 | for (i = 0; i < vd->channels; i++) { | |
1978 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
1979 | ||
1980 | ch->id = i; | |
1981 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
1982 | spin_lock_init(&ch->lock); | |
1983 | ch->serving = NULL; | |
1984 | ch->signal = -1; | |
1985 | dev_info(&adev->dev, | |
1986 | "physical channel %d is %s\n", i, | |
1987 | pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
1988 | } | |
1989 | ||
1990 | /* Register as many memcpy channels as there are physical channels */ | |
1991 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
1992 | pl08x->vd->channels, false); | |
1993 | if (ret <= 0) { | |
1994 | dev_warn(&pl08x->adev->dev, | |
1995 | "%s failed to enumerate memcpy channels - %d\n", | |
1996 | __func__, ret); | |
1997 | goto out_no_memcpy; | |
1998 | } | |
1999 | pl08x->memcpy.chancnt = ret; | |
2000 | ||
2001 | /* Register slave channels */ | |
2002 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
2003 | pl08x->pd->num_slave_channels, | |
2004 | true); | |
2005 | if (ret <= 0) { | |
2006 | dev_warn(&pl08x->adev->dev, | |
2007 | "%s failed to enumerate slave channels - %d\n", | |
2008 | __func__, ret); | |
2009 | goto out_no_slave; | |
2010 | } | |
2011 | pl08x->slave.chancnt = ret; | |
2012 | ||
2013 | ret = dma_async_device_register(&pl08x->memcpy); | |
2014 | if (ret) { | |
2015 | dev_warn(&pl08x->adev->dev, | |
2016 | "%s failed to register memcpy as an async device - %d\n", | |
2017 | __func__, ret); | |
2018 | goto out_no_memcpy_reg; | |
2019 | } | |
2020 | ||
2021 | ret = dma_async_device_register(&pl08x->slave); | |
2022 | if (ret) { | |
2023 | dev_warn(&pl08x->adev->dev, | |
2024 | "%s failed to register slave as an async device - %d\n", | |
2025 | __func__, ret); | |
2026 | goto out_no_slave_reg; | |
2027 | } | |
2028 | ||
2029 | amba_set_drvdata(adev, pl08x); | |
2030 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
2031 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
2032 | amba_part(adev), amba_rev(adev), | |
2033 | (unsigned long long)adev->res.start, adev->irq[0]); | |
e8689e63 LW |
2034 | return 0; |
2035 | ||
2036 | out_no_slave_reg: | |
2037 | dma_async_device_unregister(&pl08x->memcpy); | |
2038 | out_no_memcpy_reg: | |
2039 | pl08x_free_virtual_channels(&pl08x->slave); | |
2040 | out_no_slave: | |
2041 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2042 | out_no_memcpy: | |
2043 | kfree(pl08x->phy_chans); | |
2044 | out_no_phychans: | |
2045 | free_irq(adev->irq[0], pl08x); | |
2046 | out_no_irq: | |
2047 | iounmap(pl08x->base); | |
2048 | out_no_ioremap: | |
2049 | dma_pool_destroy(pl08x->pool); | |
2050 | out_no_lli_pool: | |
2051 | out_no_platdata: | |
2052 | kfree(pl08x); | |
2053 | out_no_pl08x: | |
2054 | amba_release_regions(adev); | |
2055 | return ret; | |
2056 | } | |
2057 | ||
2058 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2059 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
2060 | .channels = 8, |
2061 | .dualmaster = true, | |
2062 | }; | |
2063 | ||
2064 | static struct vendor_data vendor_pl081 = { | |
e8689e63 LW |
2065 | .channels = 2, |
2066 | .dualmaster = false, | |
2067 | }; | |
2068 | ||
2069 | static struct amba_id pl08x_ids[] = { | |
2070 | /* PL080 */ | |
2071 | { | |
2072 | .id = 0x00041080, | |
2073 | .mask = 0x000fffff, | |
2074 | .data = &vendor_pl080, | |
2075 | }, | |
2076 | /* PL081 */ | |
2077 | { | |
2078 | .id = 0x00041081, | |
2079 | .mask = 0x000fffff, | |
2080 | .data = &vendor_pl081, | |
2081 | }, | |
2082 | /* Nomadik 8815 PL080 variant */ | |
2083 | { | |
2084 | .id = 0x00280880, | |
2085 | .mask = 0x00ffffff, | |
2086 | .data = &vendor_pl080, | |
2087 | }, | |
2088 | { 0, 0 }, | |
2089 | }; | |
2090 | ||
2091 | static struct amba_driver pl08x_amba_driver = { | |
2092 | .drv.name = DRIVER_NAME, | |
2093 | .id_table = pl08x_ids, | |
2094 | .probe = pl08x_probe, | |
2095 | }; | |
2096 | ||
2097 | static int __init pl08x_init(void) | |
2098 | { | |
2099 | int retval; | |
2100 | retval = amba_driver_register(&pl08x_amba_driver); | |
2101 | if (retval) | |
2102 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2103 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2104 | retval); |
2105 | return retval; | |
2106 | } | |
2107 | subsys_initcall(pl08x_init); |