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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
e8689e63 | 27 | * |
94ae8522 RKAL |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
29 | * channel. | |
e8689e63 LW |
30 | * |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
e8689e63 LW |
69 | * Global TODO: |
70 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
71 | */ | |
730404ac | 72 | #include <linux/amba/bus.h> |
e8689e63 LW |
73 | #include <linux/amba/pl08x.h> |
74 | #include <linux/debugfs.h> | |
0c38d701 VK |
75 | #include <linux/delay.h> |
76 | #include <linux/device.h> | |
77 | #include <linux/dmaengine.h> | |
78 | #include <linux/dmapool.h> | |
8516f52f | 79 | #include <linux/dma-mapping.h> |
0c38d701 VK |
80 | #include <linux/init.h> |
81 | #include <linux/interrupt.h> | |
82 | #include <linux/module.h> | |
b7b6018b | 83 | #include <linux/pm_runtime.h> |
e8689e63 | 84 | #include <linux/seq_file.h> |
0c38d701 | 85 | #include <linux/slab.h> |
e8689e63 | 86 | #include <asm/hardware/pl080.h> |
e8689e63 | 87 | |
d2ebfb33 RKAL |
88 | #include "dmaengine.h" |
89 | ||
e8689e63 LW |
90 | #define DRIVER_NAME "pl08xdmac" |
91 | ||
7703eac9 | 92 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 93 | struct pl08x_driver_data; |
7703eac9 | 94 | |
e8689e63 | 95 | /** |
94ae8522 | 96 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 97 | * @channels: the number of channels available in this variant |
94ae8522 | 98 | * @dualmaster: whether this version supports dual AHB masters or not. |
affa115e LW |
99 | * @nomadik: whether the channels have Nomadik security extension bits |
100 | * that need to be checked for permission before use and some registers are | |
101 | * missing | |
e8689e63 LW |
102 | */ |
103 | struct vendor_data { | |
e8689e63 LW |
104 | u8 channels; |
105 | bool dualmaster; | |
affa115e | 106 | bool nomadik; |
e8689e63 LW |
107 | }; |
108 | ||
109 | /* | |
110 | * PL08X private data structures | |
e8b5e11d | 111 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
e25761d7 RKAL |
112 | * start & end do not - their bus bit info is in cctl. Also note that these |
113 | * are fixed 32-bit quantities. | |
e8689e63 | 114 | */ |
7cb72ad9 | 115 | struct pl08x_lli { |
e25761d7 RKAL |
116 | u32 src; |
117 | u32 dst; | |
bfddfb45 | 118 | u32 lli; |
e8689e63 LW |
119 | u32 cctl; |
120 | }; | |
121 | ||
b23f204c RK |
122 | /** |
123 | * struct pl08x_bus_data - information of source or destination | |
124 | * busses for a transfer | |
125 | * @addr: current address | |
126 | * @maxwidth: the maximum width of a transfer on this bus | |
127 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
128 | */ | |
129 | struct pl08x_bus_data { | |
130 | dma_addr_t addr; | |
131 | u8 maxwidth; | |
132 | u8 buswidth; | |
133 | }; | |
134 | ||
135 | /** | |
136 | * struct pl08x_phy_chan - holder for the physical channels | |
137 | * @id: physical index to this channel | |
138 | * @lock: a lock to use when altering an instance of this struct | |
139 | * @signal: the physical signal (aka channel) serving this physical channel | |
140 | * right now | |
141 | * @serving: the virtual channel currently being served by this physical | |
142 | * channel | |
143 | */ | |
144 | struct pl08x_phy_chan { | |
145 | unsigned int id; | |
146 | void __iomem *base; | |
147 | spinlock_t lock; | |
148 | int signal; | |
149 | struct pl08x_dma_chan *serving; | |
150 | }; | |
151 | ||
152 | /** | |
153 | * struct pl08x_sg - structure containing data per sg | |
154 | * @src_addr: src address of sg | |
155 | * @dst_addr: dst address of sg | |
156 | * @len: transfer len in bytes | |
157 | * @node: node for txd's dsg_list | |
158 | */ | |
159 | struct pl08x_sg { | |
160 | dma_addr_t src_addr; | |
161 | dma_addr_t dst_addr; | |
162 | size_t len; | |
163 | struct list_head node; | |
164 | }; | |
165 | ||
166 | /** | |
167 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
168 | * @tx: async tx descriptor | |
169 | * @node: node for txd list for channels | |
170 | * @dsg_list: list of children sg's | |
171 | * @direction: direction of transfer | |
172 | * @llis_bus: DMA memory address (physical) start for the LLIs | |
173 | * @llis_va: virtual memory address start for the LLIs | |
174 | * @cctl: control reg values for current txd | |
175 | * @ccfg: config reg values for current txd | |
176 | */ | |
177 | struct pl08x_txd { | |
178 | struct dma_async_tx_descriptor tx; | |
179 | struct list_head node; | |
180 | struct list_head dsg_list; | |
181 | enum dma_transfer_direction direction; | |
182 | dma_addr_t llis_bus; | |
183 | struct pl08x_lli *llis_va; | |
184 | /* Default cctl value for LLIs */ | |
185 | u32 cctl; | |
186 | /* | |
187 | * Settings to be put into the physical channel when we | |
188 | * trigger this txd. Other registers are in llis_va[0]. | |
189 | */ | |
190 | u32 ccfg; | |
191 | }; | |
192 | ||
193 | /** | |
194 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | |
195 | * states | |
196 | * @PL08X_CHAN_IDLE: the channel is idle | |
197 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
198 | * channel and is running a transfer on it | |
199 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
200 | * channel, but the transfer is currently paused | |
201 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
202 | * channel to become available (only pertains to memcpy channels) | |
203 | */ | |
204 | enum pl08x_dma_chan_state { | |
205 | PL08X_CHAN_IDLE, | |
206 | PL08X_CHAN_RUNNING, | |
207 | PL08X_CHAN_PAUSED, | |
208 | PL08X_CHAN_WAITING, | |
209 | }; | |
210 | ||
211 | /** | |
212 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
213 | * @chan: wrappped abstract channel | |
214 | * @phychan: the physical channel utilized by this channel, if there is one | |
215 | * @phychan_hold: if non-zero, hold on to the physical channel even if we | |
216 | * have no pending entries | |
217 | * @tasklet: tasklet scheduled by the IRQ to handle actual work etc | |
218 | * @name: name of channel | |
219 | * @cd: channel platform data | |
220 | * @runtime_addr: address for RX/TX according to the runtime config | |
221 | * @runtime_direction: current direction of this channel according to | |
222 | * runtime config | |
223 | * @pend_list: queued transactions pending on this channel | |
224 | * @at: active transaction on this channel | |
225 | * @lock: a lock for this channel data | |
226 | * @host: a pointer to the host (internal use) | |
227 | * @state: whether the channel is idle, paused, running etc | |
228 | * @slave: whether this channel is a device (slave) or for memcpy | |
b23f204c RK |
229 | * @waiting: a TX descriptor on this channel which is waiting for a physical |
230 | * channel to become available | |
231 | */ | |
232 | struct pl08x_dma_chan { | |
233 | struct dma_chan chan; | |
234 | struct pl08x_phy_chan *phychan; | |
235 | int phychan_hold; | |
236 | struct tasklet_struct tasklet; | |
550ec36f | 237 | const char *name; |
b23f204c | 238 | const struct pl08x_channel_data *cd; |
ed91c13d | 239 | struct dma_slave_config cfg; |
b23f204c RK |
240 | u32 src_cctl; |
241 | u32 dst_cctl; | |
242 | enum dma_transfer_direction runtime_direction; | |
243 | struct list_head pend_list; | |
244 | struct pl08x_txd *at; | |
245 | spinlock_t lock; | |
246 | struct pl08x_driver_data *host; | |
247 | enum pl08x_dma_chan_state state; | |
248 | bool slave; | |
b23f204c RK |
249 | struct pl08x_txd *waiting; |
250 | }; | |
251 | ||
e8689e63 LW |
252 | /** |
253 | * struct pl08x_driver_data - the local state holder for the PL08x | |
254 | * @slave: slave engine for this instance | |
255 | * @memcpy: memcpy engine for this instance | |
256 | * @base: virtual memory base (remapped) for the PL08x | |
257 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
258 | * @vd: vendor data for this PL08x variant | |
259 | * @pd: platform data passed in from the platform/machine | |
260 | * @phy_chans: array of data for the physical channels | |
261 | * @pool: a pool for the LLI descriptors | |
262 | * @pool_ctr: counter of LLIs in the pool | |
3e27ee84 VK |
263 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
264 | * fetches | |
30749cb4 | 265 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
266 | * @lock: a spinlock for this struct |
267 | */ | |
268 | struct pl08x_driver_data { | |
269 | struct dma_device slave; | |
270 | struct dma_device memcpy; | |
271 | void __iomem *base; | |
272 | struct amba_device *adev; | |
f96ca9ec | 273 | const struct vendor_data *vd; |
e8689e63 LW |
274 | struct pl08x_platform_data *pd; |
275 | struct pl08x_phy_chan *phy_chans; | |
276 | struct dma_pool *pool; | |
277 | int pool_ctr; | |
30749cb4 RKAL |
278 | u8 lli_buses; |
279 | u8 mem_buses; | |
e8689e63 LW |
280 | }; |
281 | ||
282 | /* | |
283 | * PL08X specific defines | |
284 | */ | |
285 | ||
e8689e63 LW |
286 | /* Size (bytes) of each LLI buffer allocated for one transfer */ |
287 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
288 | ||
e8b5e11d | 289 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
7cb72ad9 | 290 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
291 | #define PL08X_ALIGN 8 |
292 | ||
293 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
294 | { | |
295 | return container_of(chan, struct pl08x_dma_chan, chan); | |
296 | } | |
297 | ||
501e67e8 RKAL |
298 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
299 | { | |
300 | return container_of(tx, struct pl08x_txd, tx); | |
301 | } | |
302 | ||
e8689e63 LW |
303 | /* |
304 | * Physical channel handling | |
305 | */ | |
306 | ||
307 | /* Whether a certain channel is busy or not */ | |
308 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
309 | { | |
310 | unsigned int val; | |
311 | ||
312 | val = readl(ch->base + PL080_CH_CONFIG); | |
313 | return val & PL080_CONFIG_ACTIVE; | |
314 | } | |
315 | ||
316 | /* | |
317 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 318 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
319 | * been set when the LLIs were constructed. Poke them into the hardware |
320 | * and start the transfer. | |
e8689e63 | 321 | */ |
c885bee4 RKAL |
322 | static void pl08x_start_txd(struct pl08x_dma_chan *plchan, |
323 | struct pl08x_txd *txd) | |
e8689e63 | 324 | { |
c885bee4 | 325 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 326 | struct pl08x_phy_chan *phychan = plchan->phychan; |
19524d77 | 327 | struct pl08x_lli *lli = &txd->llis_va[0]; |
09b3c323 | 328 | u32 val; |
c885bee4 RKAL |
329 | |
330 | plchan->at = txd; | |
e8689e63 | 331 | |
c885bee4 RKAL |
332 | /* Wait for channel inactive */ |
333 | while (pl08x_phy_channel_busy(phychan)) | |
334 | cpu_relax(); | |
e8689e63 | 335 | |
c885bee4 RKAL |
336 | dev_vdbg(&pl08x->adev->dev, |
337 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
19524d77 RKAL |
338 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
339 | phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, | |
09b3c323 | 340 | txd->ccfg); |
19524d77 RKAL |
341 | |
342 | writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); | |
343 | writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); | |
344 | writel(lli->lli, phychan->base + PL080_CH_LLI); | |
345 | writel(lli->cctl, phychan->base + PL080_CH_CONTROL); | |
09b3c323 | 346 | writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); |
c885bee4 RKAL |
347 | |
348 | /* Enable the DMA channel */ | |
349 | /* Do not access config register until channel shows as disabled */ | |
350 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 351 | cpu_relax(); |
e8689e63 | 352 | |
c885bee4 RKAL |
353 | /* Do not access config register until channel shows as inactive */ |
354 | val = readl(phychan->base + PL080_CH_CONFIG); | |
e8689e63 | 355 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
c885bee4 | 356 | val = readl(phychan->base + PL080_CH_CONFIG); |
e8689e63 | 357 | |
c885bee4 | 358 | writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); |
e8689e63 LW |
359 | } |
360 | ||
361 | /* | |
81796616 | 362 | * Pause the channel by setting the HALT bit. |
e8689e63 | 363 | * |
81796616 RKAL |
364 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
365 | * the FIFO can only drain if the peripheral is still requesting data. | |
366 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 367 | * |
81796616 RKAL |
368 | * For P->M transfers, disable the peripheral first to stop it filling |
369 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
370 | */ |
371 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
372 | { | |
373 | u32 val; | |
81796616 | 374 | int timeout; |
e8689e63 LW |
375 | |
376 | /* Set the HALT bit and wait for the FIFO to drain */ | |
377 | val = readl(ch->base + PL080_CH_CONFIG); | |
378 | val |= PL080_CONFIG_HALT; | |
379 | writel(val, ch->base + PL080_CH_CONFIG); | |
380 | ||
381 | /* Wait for channel inactive */ | |
81796616 RKAL |
382 | for (timeout = 1000; timeout; timeout--) { |
383 | if (!pl08x_phy_channel_busy(ch)) | |
384 | break; | |
385 | udelay(1); | |
386 | } | |
387 | if (pl08x_phy_channel_busy(ch)) | |
388 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
389 | } |
390 | ||
391 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
392 | { | |
393 | u32 val; | |
394 | ||
395 | /* Clear the HALT bit */ | |
396 | val = readl(ch->base + PL080_CH_CONFIG); | |
397 | val &= ~PL080_CONFIG_HALT; | |
398 | writel(val, ch->base + PL080_CH_CONFIG); | |
399 | } | |
400 | ||
fb526210 RKAL |
401 | /* |
402 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
403 | * clears any pending interrupt status. This should not be used for | |
404 | * an on-going transfer, but as a method of shutting down a channel | |
405 | * (eg, when it's no longer used) or terminating a transfer. | |
406 | */ | |
407 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
408 | struct pl08x_phy_chan *ch) | |
e8689e63 | 409 | { |
fb526210 | 410 | u32 val = readl(ch->base + PL080_CH_CONFIG); |
e8689e63 | 411 | |
fb526210 RKAL |
412 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
413 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 414 | |
e8689e63 | 415 | writel(val, ch->base + PL080_CH_CONFIG); |
fb526210 RKAL |
416 | |
417 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
418 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
419 | } |
420 | ||
421 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
422 | { | |
423 | /* The source width defines the number of bytes */ | |
424 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
425 | ||
426 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
427 | case PL080_WIDTH_8BIT: | |
428 | break; | |
429 | case PL080_WIDTH_16BIT: | |
430 | bytes *= 2; | |
431 | break; | |
432 | case PL080_WIDTH_32BIT: | |
433 | bytes *= 4; | |
434 | break; | |
435 | } | |
436 | return bytes; | |
437 | } | |
438 | ||
439 | /* The channel should be paused when calling this */ | |
440 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
441 | { | |
442 | struct pl08x_phy_chan *ch; | |
e8689e63 LW |
443 | struct pl08x_txd *txd; |
444 | unsigned long flags; | |
cace6585 | 445 | size_t bytes = 0; |
e8689e63 LW |
446 | |
447 | spin_lock_irqsave(&plchan->lock, flags); | |
e8689e63 LW |
448 | ch = plchan->phychan; |
449 | txd = plchan->at; | |
450 | ||
451 | /* | |
db9f136a RKAL |
452 | * Follow the LLIs to get the number of remaining |
453 | * bytes in the currently active transaction. | |
e8689e63 LW |
454 | */ |
455 | if (ch && txd) { | |
4c0df6a3 | 456 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 457 | |
db9f136a | 458 | /* First get the remaining bytes in the active transfer */ |
e8689e63 LW |
459 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
460 | ||
461 | if (clli) { | |
db9f136a RKAL |
462 | struct pl08x_lli *llis_va = txd->llis_va; |
463 | dma_addr_t llis_bus = txd->llis_bus; | |
464 | int index; | |
465 | ||
466 | BUG_ON(clli < llis_bus || clli >= llis_bus + | |
467 | sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); | |
e8689e63 | 468 | |
db9f136a RKAL |
469 | /* |
470 | * Locate the next LLI - as this is an array, | |
471 | * it's simple maths to find. | |
472 | */ | |
473 | index = (clli - llis_bus) / sizeof(struct pl08x_lli); | |
474 | ||
475 | for (; index < MAX_NUM_TSFR_LLIS; index++) { | |
476 | bytes += get_bytes_in_cctl(llis_va[index].cctl); | |
e8689e63 | 477 | |
e8689e63 | 478 | /* |
e8b5e11d | 479 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 | 480 | */ |
db9f136a RKAL |
481 | if (!llis_va[index].lli) |
482 | break; | |
e8689e63 LW |
483 | } |
484 | } | |
485 | } | |
486 | ||
487 | /* Sum up all queued transactions */ | |
15c17232 | 488 | if (!list_empty(&plchan->pend_list)) { |
db9f136a | 489 | struct pl08x_txd *txdi; |
15c17232 | 490 | list_for_each_entry(txdi, &plchan->pend_list, node) { |
b7f69d9d VK |
491 | struct pl08x_sg *dsg; |
492 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
493 | bytes += dsg->len; | |
e8689e63 | 494 | } |
e8689e63 LW |
495 | } |
496 | ||
497 | spin_unlock_irqrestore(&plchan->lock, flags); | |
498 | ||
499 | return bytes; | |
500 | } | |
501 | ||
502 | /* | |
503 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
504 | * |
505 | * Try to locate a physical channel to be used for this transfer. If all | |
506 | * are taken return NULL and the requester will have to cope by using | |
507 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
508 | */ |
509 | static struct pl08x_phy_chan * | |
510 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
511 | struct pl08x_dma_chan *virt_chan) | |
512 | { | |
513 | struct pl08x_phy_chan *ch = NULL; | |
514 | unsigned long flags; | |
515 | int i; | |
516 | ||
e8689e63 LW |
517 | for (i = 0; i < pl08x->vd->channels; i++) { |
518 | ch = &pl08x->phy_chans[i]; | |
519 | ||
520 | spin_lock_irqsave(&ch->lock, flags); | |
521 | ||
affa115e | 522 | if (!ch->locked && !ch->serving) { |
e8689e63 LW |
523 | ch->serving = virt_chan; |
524 | ch->signal = -1; | |
525 | spin_unlock_irqrestore(&ch->lock, flags); | |
526 | break; | |
527 | } | |
528 | ||
529 | spin_unlock_irqrestore(&ch->lock, flags); | |
530 | } | |
531 | ||
532 | if (i == pl08x->vd->channels) { | |
533 | /* No physical channel available, cope with it */ | |
534 | return NULL; | |
535 | } | |
536 | ||
537 | return ch; | |
538 | } | |
539 | ||
540 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, | |
541 | struct pl08x_phy_chan *ch) | |
542 | { | |
543 | unsigned long flags; | |
544 | ||
fb526210 RKAL |
545 | spin_lock_irqsave(&ch->lock, flags); |
546 | ||
e8689e63 | 547 | /* Stop the channel and clear its interrupts */ |
fb526210 | 548 | pl08x_terminate_phy_chan(pl08x, ch); |
e8689e63 LW |
549 | |
550 | /* Mark it as free */ | |
e8689e63 LW |
551 | ch->serving = NULL; |
552 | spin_unlock_irqrestore(&ch->lock, flags); | |
553 | } | |
554 | ||
555 | /* | |
556 | * LLI handling | |
557 | */ | |
558 | ||
559 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
560 | { | |
561 | switch (coded) { | |
562 | case PL080_WIDTH_8BIT: | |
563 | return 1; | |
564 | case PL080_WIDTH_16BIT: | |
565 | return 2; | |
566 | case PL080_WIDTH_32BIT: | |
567 | return 4; | |
568 | default: | |
569 | break; | |
570 | } | |
571 | BUG(); | |
572 | return 0; | |
573 | } | |
574 | ||
575 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 576 | size_t tsize) |
e8689e63 LW |
577 | { |
578 | u32 retbits = cctl; | |
579 | ||
e8b5e11d | 580 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
581 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
582 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
583 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
584 | ||
585 | /* Then set the bits according to the parameters */ | |
586 | switch (srcwidth) { | |
587 | case 1: | |
588 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
589 | break; | |
590 | case 2: | |
591 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
592 | break; | |
593 | case 4: | |
594 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
595 | break; | |
596 | default: | |
597 | BUG(); | |
598 | break; | |
599 | } | |
600 | ||
601 | switch (dstwidth) { | |
602 | case 1: | |
603 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
604 | break; | |
605 | case 2: | |
606 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
607 | break; | |
608 | case 4: | |
609 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
610 | break; | |
611 | default: | |
612 | BUG(); | |
613 | break; | |
614 | } | |
615 | ||
616 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
617 | return retbits; | |
618 | } | |
619 | ||
542361f8 RKAL |
620 | struct pl08x_lli_build_data { |
621 | struct pl08x_txd *txd; | |
542361f8 RKAL |
622 | struct pl08x_bus_data srcbus; |
623 | struct pl08x_bus_data dstbus; | |
624 | size_t remainder; | |
25c94f7f | 625 | u32 lli_bus; |
542361f8 RKAL |
626 | }; |
627 | ||
e8689e63 | 628 | /* |
0532e6fc VK |
629 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
630 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
631 | * masters address with width requirements of transfer (by sending few byte by | |
632 | * byte data), slave is still not aligned, then its width will be reduced to | |
633 | * BYTE. | |
634 | * - prefers the destination bus if both available | |
036f05fd | 635 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 636 | */ |
542361f8 RKAL |
637 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
638 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
639 | { |
640 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
641 | *mbus = &bd->dstbus; |
642 | *sbus = &bd->srcbus; | |
036f05fd VK |
643 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
644 | *mbus = &bd->srcbus; | |
645 | *sbus = &bd->dstbus; | |
e8689e63 | 646 | } else { |
036f05fd | 647 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
648 | *mbus = &bd->dstbus; |
649 | *sbus = &bd->srcbus; | |
036f05fd | 650 | } else { |
542361f8 RKAL |
651 | *mbus = &bd->srcbus; |
652 | *sbus = &bd->dstbus; | |
e8689e63 LW |
653 | } |
654 | } | |
655 | } | |
656 | ||
657 | /* | |
94ae8522 | 658 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 659 | */ |
542361f8 RKAL |
660 | static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd, |
661 | int num_llis, int len, u32 cctl) | |
e8689e63 | 662 | { |
542361f8 RKAL |
663 | struct pl08x_lli *llis_va = bd->txd->llis_va; |
664 | dma_addr_t llis_bus = bd->txd->llis_bus; | |
e8689e63 LW |
665 | |
666 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
667 | ||
30749cb4 | 668 | llis_va[num_llis].cctl = cctl; |
542361f8 RKAL |
669 | llis_va[num_llis].src = bd->srcbus.addr; |
670 | llis_va[num_llis].dst = bd->dstbus.addr; | |
3e27ee84 VK |
671 | llis_va[num_llis].lli = llis_bus + (num_llis + 1) * |
672 | sizeof(struct pl08x_lli); | |
25c94f7f | 673 | llis_va[num_llis].lli |= bd->lli_bus; |
e8689e63 LW |
674 | |
675 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 676 | bd->srcbus.addr += len; |
e8689e63 | 677 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 678 | bd->dstbus.addr += len; |
e8689e63 | 679 | |
542361f8 | 680 | BUG_ON(bd->remainder < len); |
cace6585 | 681 | |
542361f8 | 682 | bd->remainder -= len; |
e8689e63 LW |
683 | } |
684 | ||
03af500f VK |
685 | static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd, |
686 | u32 *cctl, u32 len, int num_llis, size_t *total_bytes) | |
e8689e63 | 687 | { |
03af500f VK |
688 | *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); |
689 | pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl); | |
690 | (*total_bytes) += len; | |
e8689e63 LW |
691 | } |
692 | ||
693 | /* | |
694 | * This fills in the table of LLIs for the transfer descriptor | |
695 | * Note that we assume we never have to change the burst sizes | |
696 | * Return 0 for error | |
697 | */ | |
698 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
699 | struct pl08x_txd *txd) | |
700 | { | |
e8689e63 | 701 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 702 | struct pl08x_lli_build_data bd; |
e8689e63 | 703 | int num_llis = 0; |
03af500f | 704 | u32 cctl, early_bytes = 0; |
b7f69d9d | 705 | size_t max_bytes_per_lli, total_bytes; |
7cb72ad9 | 706 | struct pl08x_lli *llis_va; |
b7f69d9d | 707 | struct pl08x_sg *dsg; |
e8689e63 | 708 | |
3e27ee84 | 709 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
710 | if (!txd->llis_va) { |
711 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
712 | return 0; | |
713 | } | |
714 | ||
715 | pl08x->pool_ctr++; | |
716 | ||
542361f8 | 717 | bd.txd = txd; |
25c94f7f | 718 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 719 | cctl = txd->cctl; |
542361f8 | 720 | |
e8689e63 | 721 | /* Find maximum width of the source bus */ |
542361f8 | 722 | bd.srcbus.maxwidth = |
e8689e63 LW |
723 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
724 | PL080_CONTROL_SWIDTH_SHIFT); | |
725 | ||
726 | /* Find maximum width of the destination bus */ | |
542361f8 | 727 | bd.dstbus.maxwidth = |
e8689e63 LW |
728 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
729 | PL080_CONTROL_DWIDTH_SHIFT); | |
730 | ||
b7f69d9d VK |
731 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
732 | total_bytes = 0; | |
733 | cctl = txd->cctl; | |
e8689e63 | 734 | |
b7f69d9d VK |
735 | bd.srcbus.addr = dsg->src_addr; |
736 | bd.dstbus.addr = dsg->dst_addr; | |
737 | bd.remainder = dsg->len; | |
738 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
739 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 740 | |
b7f69d9d | 741 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 742 | |
b7f69d9d VK |
743 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", |
744 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
745 | bd.srcbus.buswidth, | |
746 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
747 | bd.dstbus.buswidth, | |
748 | bd.remainder); | |
749 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
750 | mbus == &bd.srcbus ? "src" : "dst", | |
751 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 752 | |
b7f69d9d VK |
753 | /* |
754 | * Zero length is only allowed if all these requirements are | |
755 | * met: | |
756 | * - flow controller is peripheral. | |
757 | * - src.addr is aligned to src.width | |
758 | * - dst.addr is aligned to dst.width | |
759 | * | |
760 | * sg_len == 1 should be true, as there can be two cases here: | |
761 | * | |
762 | * - Memory addresses are contiguous and are not scattered. | |
763 | * Here, Only one sg will be passed by user driver, with | |
764 | * memory address and zero length. We pass this to controller | |
765 | * and after the transfer it will receive the last burst | |
766 | * request from peripheral and so transfer finishes. | |
767 | * | |
768 | * - Memory addresses are scattered and are not contiguous. | |
769 | * Here, Obviously as DMA controller doesn't know when a lli's | |
770 | * transfer gets over, it can't load next lli. So in this | |
771 | * case, there has to be an assumption that only one lli is | |
772 | * supported. Thus, we can't have scattered addresses. | |
773 | */ | |
774 | if (!bd.remainder) { | |
775 | u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
776 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
777 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && | |
0a235657 | 778 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
779 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
780 | __func__); | |
781 | return 0; | |
782 | } | |
0a235657 | 783 | |
b7f69d9d | 784 | if ((bd.srcbus.addr % bd.srcbus.buswidth) || |
880db3ff | 785 | (bd.dstbus.addr % bd.dstbus.buswidth)) { |
b7f69d9d VK |
786 | dev_err(&pl08x->adev->dev, |
787 | "%s src & dst address must be aligned to src" | |
788 | " & dst width if peripheral is flow controller", | |
789 | __func__); | |
790 | return 0; | |
791 | } | |
03af500f | 792 | |
b7f69d9d VK |
793 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, |
794 | bd.dstbus.buswidth, 0); | |
795 | pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl); | |
796 | break; | |
797 | } | |
e8689e63 LW |
798 | |
799 | /* | |
b7f69d9d VK |
800 | * Send byte by byte for following cases |
801 | * - Less than a bus width available | |
802 | * - until master bus is aligned | |
e8689e63 | 803 | */ |
b7f69d9d VK |
804 | if (bd.remainder < mbus->buswidth) |
805 | early_bytes = bd.remainder; | |
806 | else if ((mbus->addr) % (mbus->buswidth)) { | |
807 | early_bytes = mbus->buswidth - (mbus->addr) % | |
808 | (mbus->buswidth); | |
809 | if ((bd.remainder - early_bytes) < mbus->buswidth) | |
810 | early_bytes = bd.remainder; | |
811 | } | |
e8689e63 | 812 | |
b7f69d9d VK |
813 | if (early_bytes) { |
814 | dev_vdbg(&pl08x->adev->dev, | |
815 | "%s byte width LLIs (remain 0x%08x)\n", | |
816 | __func__, bd.remainder); | |
817 | prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++, | |
818 | &total_bytes); | |
e8689e63 LW |
819 | } |
820 | ||
b7f69d9d VK |
821 | if (bd.remainder) { |
822 | /* | |
823 | * Master now aligned | |
824 | * - if slave is not then we must set its width down | |
825 | */ | |
826 | if (sbus->addr % sbus->buswidth) { | |
827 | dev_dbg(&pl08x->adev->dev, | |
828 | "%s set down bus width to one byte\n", | |
829 | __func__); | |
fa6a940b | 830 | |
b7f69d9d VK |
831 | sbus->buswidth = 1; |
832 | } | |
e8689e63 LW |
833 | |
834 | /* | |
b7f69d9d VK |
835 | * Bytes transferred = tsize * src width, not |
836 | * MIN(buswidths) | |
e8689e63 | 837 | */ |
b7f69d9d VK |
838 | max_bytes_per_lli = bd.srcbus.buswidth * |
839 | PL080_CONTROL_TRANSFER_SIZE_MASK; | |
840 | dev_vdbg(&pl08x->adev->dev, | |
841 | "%s max bytes per lli = %zu\n", | |
842 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
843 | |
844 | /* | |
b7f69d9d VK |
845 | * Make largest possible LLIs until less than one bus |
846 | * width left | |
e8689e63 | 847 | */ |
b7f69d9d VK |
848 | while (bd.remainder > (mbus->buswidth - 1)) { |
849 | size_t lli_len, tsize, width; | |
e8689e63 | 850 | |
b7f69d9d VK |
851 | /* |
852 | * If enough left try to send max possible, | |
853 | * otherwise try to send the remainder | |
854 | */ | |
855 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 856 | |
b7f69d9d VK |
857 | /* |
858 | * Check against maximum bus alignment: | |
859 | * Calculate actual transfer size in relation to | |
860 | * bus width an get a maximum remainder of the | |
861 | * highest bus width - 1 | |
862 | */ | |
863 | width = max(mbus->buswidth, sbus->buswidth); | |
864 | lli_len = (lli_len / width) * width; | |
865 | tsize = lli_len / bd.srcbus.buswidth; | |
866 | ||
867 | dev_vdbg(&pl08x->adev->dev, | |
868 | "%s fill lli with single lli chunk of " | |
869 | "size 0x%08zx (remainder 0x%08zx)\n", | |
870 | __func__, lli_len, bd.remainder); | |
871 | ||
872 | cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, | |
16a2e7d3 | 873 | bd.dstbus.buswidth, tsize); |
b7f69d9d VK |
874 | pl08x_fill_lli_for_desc(&bd, num_llis++, |
875 | lli_len, cctl); | |
876 | total_bytes += lli_len; | |
877 | } | |
e8689e63 | 878 | |
b7f69d9d VK |
879 | /* |
880 | * Send any odd bytes | |
881 | */ | |
882 | if (bd.remainder) { | |
883 | dev_vdbg(&pl08x->adev->dev, | |
884 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
885 | __func__, bd.remainder); | |
886 | prep_byte_width_lli(&bd, &cctl, bd.remainder, | |
887 | num_llis++, &total_bytes); | |
888 | } | |
e8689e63 | 889 | } |
16a2e7d3 | 890 | |
b7f69d9d VK |
891 | if (total_bytes != dsg->len) { |
892 | dev_err(&pl08x->adev->dev, | |
893 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
894 | __func__, total_bytes, dsg->len); | |
895 | return 0; | |
896 | } | |
e8689e63 | 897 | |
b7f69d9d VK |
898 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
899 | dev_err(&pl08x->adev->dev, | |
900 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
901 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
902 | return 0; | |
903 | } | |
e8689e63 | 904 | } |
b58b6b5b RKAL |
905 | |
906 | llis_va = txd->llis_va; | |
94ae8522 | 907 | /* The final LLI terminates the LLI. */ |
bfddfb45 | 908 | llis_va[num_llis - 1].lli = 0; |
94ae8522 | 909 | /* The final LLI element shall also fire an interrupt. */ |
b58b6b5b | 910 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 911 | |
e8689e63 LW |
912 | #ifdef VERBOSE_DEBUG |
913 | { | |
914 | int i; | |
915 | ||
fc74eb79 RKAL |
916 | dev_vdbg(&pl08x->adev->dev, |
917 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
918 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
e8689e63 LW |
919 | for (i = 0; i < num_llis; i++) { |
920 | dev_vdbg(&pl08x->adev->dev, | |
fc74eb79 RKAL |
921 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
922 | i, &llis_va[i], llis_va[i].src, | |
923 | llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl | |
e8689e63 LW |
924 | ); |
925 | } | |
926 | } | |
927 | #endif | |
928 | ||
929 | return num_llis; | |
930 | } | |
931 | ||
932 | /* You should call this with the struct pl08x lock held */ | |
933 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, | |
934 | struct pl08x_txd *txd) | |
935 | { | |
b7f69d9d VK |
936 | struct pl08x_sg *dsg, *_dsg; |
937 | ||
e8689e63 | 938 | /* Free the LLI */ |
c1205646 VK |
939 | if (txd->llis_va) |
940 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 LW |
941 | |
942 | pl08x->pool_ctr--; | |
943 | ||
b7f69d9d VK |
944 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
945 | list_del(&dsg->node); | |
946 | kfree(dsg); | |
947 | } | |
948 | ||
e8689e63 LW |
949 | kfree(txd); |
950 | } | |
951 | ||
952 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, | |
953 | struct pl08x_dma_chan *plchan) | |
954 | { | |
955 | struct pl08x_txd *txdi = NULL; | |
956 | struct pl08x_txd *next; | |
957 | ||
15c17232 | 958 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 | 959 | list_for_each_entry_safe(txdi, |
15c17232 | 960 | next, &plchan->pend_list, node) { |
e8689e63 LW |
961 | list_del(&txdi->node); |
962 | pl08x_free_txd(pl08x, txdi); | |
963 | } | |
e8689e63 LW |
964 | } |
965 | } | |
966 | ||
967 | /* | |
968 | * The DMA ENGINE API | |
969 | */ | |
970 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
971 | { | |
972 | return 0; | |
973 | } | |
974 | ||
975 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
976 | { | |
977 | } | |
978 | ||
979 | /* | |
980 | * This should be called with the channel plchan->lock held | |
981 | */ | |
982 | static int prep_phy_channel(struct pl08x_dma_chan *plchan, | |
983 | struct pl08x_txd *txd) | |
984 | { | |
985 | struct pl08x_driver_data *pl08x = plchan->host; | |
986 | struct pl08x_phy_chan *ch; | |
987 | int ret; | |
988 | ||
989 | /* Check if we already have a channel */ | |
8f0d30f9 VK |
990 | if (plchan->phychan) { |
991 | ch = plchan->phychan; | |
992 | goto got_channel; | |
993 | } | |
e8689e63 LW |
994 | |
995 | ch = pl08x_get_phy_channel(pl08x, plchan); | |
996 | if (!ch) { | |
997 | /* No physical channel available, cope with it */ | |
998 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
999 | return -EBUSY; | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * OK we have a physical channel: for memcpy() this is all we | |
1004 | * need, but for slaves the physical signals may be muxed! | |
1005 | * Can the platform allow us to use this channel? | |
1006 | */ | |
16ca8105 | 1007 | if (plchan->slave && pl08x->pd->get_signal) { |
aeea1808 | 1008 | ret = pl08x->pd->get_signal(plchan->cd); |
e8689e63 LW |
1009 | if (ret < 0) { |
1010 | dev_dbg(&pl08x->adev->dev, | |
1011 | "unable to use physical channel %d for transfer on %s due to platform restrictions\n", | |
1012 | ch->id, plchan->name); | |
1013 | /* Release physical channel & return */ | |
1014 | pl08x_put_phy_channel(pl08x, ch); | |
1015 | return -EBUSY; | |
1016 | } | |
1017 | ch->signal = ret; | |
1018 | } | |
1019 | ||
8f0d30f9 | 1020 | plchan->phychan = ch; |
e8689e63 LW |
1021 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n", |
1022 | ch->id, | |
1023 | ch->signal, | |
1024 | plchan->name); | |
1025 | ||
8f0d30f9 VK |
1026 | got_channel: |
1027 | /* Assign the flow control signal to this channel */ | |
1028 | if (txd->direction == DMA_MEM_TO_DEV) | |
1029 | txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
1030 | else if (txd->direction == DMA_DEV_TO_MEM) | |
1031 | txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
1032 | ||
8087aacd | 1033 | plchan->phychan_hold++; |
e8689e63 LW |
1034 | |
1035 | return 0; | |
1036 | } | |
1037 | ||
8c8cc2b1 RKAL |
1038 | static void release_phy_channel(struct pl08x_dma_chan *plchan) |
1039 | { | |
1040 | struct pl08x_driver_data *pl08x = plchan->host; | |
1041 | ||
1042 | if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) { | |
aeea1808 | 1043 | pl08x->pd->put_signal(plchan->cd, plchan->phychan->signal); |
8c8cc2b1 RKAL |
1044 | plchan->phychan->signal = -1; |
1045 | } | |
1046 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
1047 | plchan->phychan = NULL; | |
1048 | } | |
1049 | ||
e8689e63 LW |
1050 | static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) |
1051 | { | |
1052 | struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); | |
501e67e8 | 1053 | struct pl08x_txd *txd = to_pl08x_txd(tx); |
c370e594 | 1054 | unsigned long flags; |
884485e1 | 1055 | dma_cookie_t cookie; |
c370e594 RKAL |
1056 | |
1057 | spin_lock_irqsave(&plchan->lock, flags); | |
884485e1 | 1058 | cookie = dma_cookie_assign(tx); |
501e67e8 RKAL |
1059 | |
1060 | /* Put this onto the pending list */ | |
1061 | list_add_tail(&txd->node, &plchan->pend_list); | |
1062 | ||
1063 | /* | |
1064 | * If there was no physical channel available for this memcpy, | |
1065 | * stack the request up and indicate that the channel is waiting | |
1066 | * for a free physical channel. | |
1067 | */ | |
1068 | if (!plchan->slave && !plchan->phychan) { | |
1069 | /* Do this memcpy whenever there is a channel ready */ | |
1070 | plchan->state = PL08X_CHAN_WAITING; | |
1071 | plchan->waiting = txd; | |
8087aacd RKAL |
1072 | } else { |
1073 | plchan->phychan_hold--; | |
501e67e8 RKAL |
1074 | } |
1075 | ||
c370e594 | 1076 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 | 1077 | |
884485e1 | 1078 | return cookie; |
e8689e63 LW |
1079 | } |
1080 | ||
1081 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( | |
1082 | struct dma_chan *chan, unsigned long flags) | |
1083 | { | |
1084 | struct dma_async_tx_descriptor *retval = NULL; | |
1085 | ||
1086 | return retval; | |
1087 | } | |
1088 | ||
1089 | /* | |
94ae8522 RKAL |
1090 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1091 | * If slaves are relying on interrupts to signal completion this function | |
1092 | * must not be called with interrupts disabled. | |
e8689e63 | 1093 | */ |
3e27ee84 VK |
1094 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1095 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1096 | { |
1097 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 | 1098 | enum dma_status ret; |
e8689e63 | 1099 | |
96a2af41 RKAL |
1100 | ret = dma_cookie_status(chan, cookie, txstate); |
1101 | if (ret == DMA_SUCCESS) | |
e8689e63 | 1102 | return ret; |
e8689e63 | 1103 | |
e8689e63 LW |
1104 | /* |
1105 | * This cookie not complete yet | |
96a2af41 | 1106 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1107 | */ |
96a2af41 | 1108 | dma_set_residue(txstate, pl08x_getbytes_chan(plchan)); |
e8689e63 LW |
1109 | |
1110 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1111 | return DMA_PAUSED; | |
1112 | ||
1113 | /* Whether waiting or running, we're in progress */ | |
1114 | return DMA_IN_PROGRESS; | |
1115 | } | |
1116 | ||
1117 | /* PrimeCell DMA extension */ | |
1118 | struct burst_table { | |
760596c6 | 1119 | u32 burstwords; |
e8689e63 LW |
1120 | u32 reg; |
1121 | }; | |
1122 | ||
1123 | static const struct burst_table burst_sizes[] = { | |
1124 | { | |
1125 | .burstwords = 256, | |
760596c6 | 1126 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1127 | }, |
1128 | { | |
1129 | .burstwords = 128, | |
760596c6 | 1130 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1131 | }, |
1132 | { | |
1133 | .burstwords = 64, | |
760596c6 | 1134 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1135 | }, |
1136 | { | |
1137 | .burstwords = 32, | |
760596c6 | 1138 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1139 | }, |
1140 | { | |
1141 | .burstwords = 16, | |
760596c6 | 1142 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1143 | }, |
1144 | { | |
1145 | .burstwords = 8, | |
760596c6 | 1146 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1147 | }, |
1148 | { | |
1149 | .burstwords = 4, | |
760596c6 | 1150 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1151 | }, |
1152 | { | |
760596c6 RKAL |
1153 | .burstwords = 0, |
1154 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1155 | }, |
1156 | }; | |
1157 | ||
121c8476 RKAL |
1158 | /* |
1159 | * Given the source and destination available bus masks, select which | |
1160 | * will be routed to each port. We try to have source and destination | |
1161 | * on separate ports, but always respect the allowable settings. | |
1162 | */ | |
1163 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1164 | { | |
1165 | u32 cctl = 0; | |
1166 | ||
1167 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1168 | cctl |= PL080_CONTROL_DST_AHB2; | |
1169 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1170 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1171 | ||
1172 | return cctl; | |
1173 | } | |
1174 | ||
f14c426c RKAL |
1175 | static u32 pl08x_cctl(u32 cctl) |
1176 | { | |
1177 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1178 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1179 | PL080_CONTROL_PROT_MASK); | |
1180 | ||
1181 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1182 | return cctl | PL080_CONTROL_PROT_SYS; | |
1183 | } | |
1184 | ||
aa88cdaa RKAL |
1185 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1186 | { | |
1187 | switch (width) { | |
1188 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1189 | return PL080_WIDTH_8BIT; | |
1190 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1191 | return PL080_WIDTH_16BIT; | |
1192 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1193 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1194 | default: |
1195 | return ~0; | |
aa88cdaa | 1196 | } |
aa88cdaa RKAL |
1197 | } |
1198 | ||
760596c6 RKAL |
1199 | static u32 pl08x_burst(u32 maxburst) |
1200 | { | |
1201 | int i; | |
1202 | ||
1203 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1204 | if (burst_sizes[i].burstwords <= maxburst) | |
1205 | break; | |
1206 | ||
1207 | return burst_sizes[i].reg; | |
1208 | } | |
1209 | ||
f0fd9446 RKAL |
1210 | static int dma_set_runtime_config(struct dma_chan *chan, |
1211 | struct dma_slave_config *config) | |
e8689e63 LW |
1212 | { |
1213 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1214 | struct pl08x_driver_data *pl08x = plchan->host; | |
e8689e63 | 1215 | enum dma_slave_buswidth addr_width; |
760596c6 | 1216 | u32 width, burst, maxburst; |
e8689e63 | 1217 | u32 cctl = 0; |
b7f75865 RKAL |
1218 | |
1219 | if (!plchan->slave) | |
1220 | return -EINVAL; | |
e8689e63 LW |
1221 | |
1222 | /* Transfer direction */ | |
1223 | plchan->runtime_direction = config->direction; | |
db8196df | 1224 | if (config->direction == DMA_MEM_TO_DEV) { |
e8689e63 LW |
1225 | addr_width = config->dst_addr_width; |
1226 | maxburst = config->dst_maxburst; | |
db8196df | 1227 | } else if (config->direction == DMA_DEV_TO_MEM) { |
e8689e63 LW |
1228 | addr_width = config->src_addr_width; |
1229 | maxburst = config->src_maxburst; | |
1230 | } else { | |
1231 | dev_err(&pl08x->adev->dev, | |
1232 | "bad runtime_config: alien transfer direction\n"); | |
f0fd9446 | 1233 | return -EINVAL; |
e8689e63 LW |
1234 | } |
1235 | ||
aa88cdaa RKAL |
1236 | width = pl08x_width(addr_width); |
1237 | if (width == ~0) { | |
e8689e63 LW |
1238 | dev_err(&pl08x->adev->dev, |
1239 | "bad runtime_config: alien address width\n"); | |
f0fd9446 | 1240 | return -EINVAL; |
e8689e63 LW |
1241 | } |
1242 | ||
ed91c13d RK |
1243 | plchan->cfg = *config; |
1244 | ||
aa88cdaa RKAL |
1245 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; |
1246 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1247 | ||
e8689e63 | 1248 | /* |
4440aacf RKAL |
1249 | * If this channel will only request single transfers, set this |
1250 | * down to ONE element. Also select one element if no maxburst | |
1251 | * is specified. | |
e8689e63 | 1252 | */ |
760596c6 RKAL |
1253 | if (plchan->cd->single) |
1254 | maxburst = 1; | |
1255 | ||
1256 | burst = pl08x_burst(maxburst); | |
1257 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1258 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
e8689e63 | 1259 | |
db8196df | 1260 | if (plchan->runtime_direction == DMA_DEV_TO_MEM) { |
409ec8db | 1261 | plchan->src_cctl = pl08x_cctl(cctl); |
b207b4d0 | 1262 | } else { |
409ec8db | 1263 | plchan->dst_cctl = pl08x_cctl(cctl); |
b207b4d0 | 1264 | } |
f0fd9446 | 1265 | |
e8689e63 LW |
1266 | dev_dbg(&pl08x->adev->dev, |
1267 | "configured channel %s (%s) for %s, data width %d, " | |
4983a04f | 1268 | "maxburst %d words, LE, CCTL=0x%08x\n", |
e8689e63 | 1269 | dma_chan_name(chan), plchan->name, |
db8196df | 1270 | (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX", |
e8689e63 LW |
1271 | addr_width, |
1272 | maxburst, | |
4983a04f | 1273 | cctl); |
f0fd9446 RKAL |
1274 | |
1275 | return 0; | |
e8689e63 LW |
1276 | } |
1277 | ||
1278 | /* | |
1279 | * Slave transactions callback to the slave device to allow | |
1280 | * synchronization of slave DMA signals with the DMAC enable | |
1281 | */ | |
1282 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1283 | { | |
1284 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1285 | unsigned long flags; |
1286 | ||
1287 | spin_lock_irqsave(&plchan->lock, flags); | |
9c0bb43b RKAL |
1288 | /* Something is already active, or we're waiting for a channel... */ |
1289 | if (plchan->at || plchan->state == PL08X_CHAN_WAITING) { | |
1290 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1291 | return; |
9c0bb43b | 1292 | } |
e8689e63 LW |
1293 | |
1294 | /* Take the first element in the queue and execute it */ | |
15c17232 | 1295 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 LW |
1296 | struct pl08x_txd *next; |
1297 | ||
15c17232 | 1298 | next = list_first_entry(&plchan->pend_list, |
e8689e63 LW |
1299 | struct pl08x_txd, |
1300 | node); | |
1301 | list_del(&next->node); | |
e8689e63 LW |
1302 | plchan->state = PL08X_CHAN_RUNNING; |
1303 | ||
c885bee4 | 1304 | pl08x_start_txd(plchan, next); |
e8689e63 LW |
1305 | } |
1306 | ||
1307 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1308 | } | |
1309 | ||
1310 | static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, | |
1311 | struct pl08x_txd *txd) | |
1312 | { | |
e8689e63 | 1313 | struct pl08x_driver_data *pl08x = plchan->host; |
c370e594 RKAL |
1314 | unsigned long flags; |
1315 | int num_llis, ret; | |
e8689e63 LW |
1316 | |
1317 | num_llis = pl08x_fill_llis_for_desc(pl08x, txd); | |
dafa7317 | 1318 | if (!num_llis) { |
57001a60 VK |
1319 | spin_lock_irqsave(&plchan->lock, flags); |
1320 | pl08x_free_txd(pl08x, txd); | |
1321 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1322 | return -EINVAL; |
dafa7317 | 1323 | } |
e8689e63 | 1324 | |
c370e594 | 1325 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1326 | |
e8689e63 LW |
1327 | /* |
1328 | * See if we already have a physical channel allocated, | |
1329 | * else this is the time to try to get one. | |
1330 | */ | |
1331 | ret = prep_phy_channel(plchan, txd); | |
1332 | if (ret) { | |
1333 | /* | |
501e67e8 RKAL |
1334 | * No physical channel was available. |
1335 | * | |
1336 | * memcpy transfers can be sorted out at submission time. | |
1337 | * | |
1338 | * Slave transfers may have been denied due to platform | |
1339 | * channel muxing restrictions. Since there is no guarantee | |
1340 | * that this will ever be resolved, and the signal must be | |
1341 | * acquired AFTER acquiring the physical channel, we will let | |
1342 | * them be NACK:ed with -EBUSY here. The drivers can retry | |
1343 | * the prep() call if they are eager on doing this using DMA. | |
e8689e63 LW |
1344 | */ |
1345 | if (plchan->slave) { | |
1346 | pl08x_free_txd_list(pl08x, plchan); | |
501e67e8 | 1347 | pl08x_free_txd(pl08x, txd); |
c370e594 | 1348 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1349 | return -EBUSY; |
1350 | } | |
e8689e63 LW |
1351 | } else |
1352 | /* | |
94ae8522 RKAL |
1353 | * Else we're all set, paused and ready to roll, status |
1354 | * will switch to PL08X_CHAN_RUNNING when we call | |
1355 | * issue_pending(). If there is something running on the | |
1356 | * channel already we don't change its state. | |
e8689e63 LW |
1357 | */ |
1358 | if (plchan->state == PL08X_CHAN_IDLE) | |
1359 | plchan->state = PL08X_CHAN_PAUSED; | |
1360 | ||
c370e594 | 1361 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1362 | |
1363 | return 0; | |
1364 | } | |
1365 | ||
c0428794 RKAL |
1366 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan, |
1367 | unsigned long flags) | |
ac3cd20d | 1368 | { |
b201c111 | 1369 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1370 | |
1371 | if (txd) { | |
1372 | dma_async_tx_descriptor_init(&txd->tx, &plchan->chan); | |
c0428794 | 1373 | txd->tx.flags = flags; |
ac3cd20d RKAL |
1374 | txd->tx.tx_submit = pl08x_tx_submit; |
1375 | INIT_LIST_HEAD(&txd->node); | |
b7f69d9d | 1376 | INIT_LIST_HEAD(&txd->dsg_list); |
4983a04f RKAL |
1377 | |
1378 | /* Always enable error and terminal interrupts */ | |
1379 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1380 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1381 | } |
1382 | return txd; | |
1383 | } | |
1384 | ||
e8689e63 LW |
1385 | /* |
1386 | * Initialize a descriptor to be used by memcpy submit | |
1387 | */ | |
1388 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1389 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1390 | size_t len, unsigned long flags) | |
1391 | { | |
1392 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1393 | struct pl08x_driver_data *pl08x = plchan->host; | |
1394 | struct pl08x_txd *txd; | |
b7f69d9d | 1395 | struct pl08x_sg *dsg; |
e8689e63 LW |
1396 | int ret; |
1397 | ||
c0428794 | 1398 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1399 | if (!txd) { |
1400 | dev_err(&pl08x->adev->dev, | |
1401 | "%s no memory for descriptor\n", __func__); | |
1402 | return NULL; | |
1403 | } | |
1404 | ||
b7f69d9d VK |
1405 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); |
1406 | if (!dsg) { | |
1407 | pl08x_free_txd(pl08x, txd); | |
1408 | dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n", | |
1409 | __func__); | |
1410 | return NULL; | |
1411 | } | |
1412 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1413 | ||
92d2fd61 | 1414 | txd->direction = DMA_MEM_TO_MEM; |
b7f69d9d VK |
1415 | dsg->src_addr = src; |
1416 | dsg->dst_addr = dest; | |
1417 | dsg->len = len; | |
e8689e63 LW |
1418 | |
1419 | /* Set platform data for m2m */ | |
4983a04f | 1420 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
c7da9a56 RKAL |
1421 | txd->cctl = pl08x->pd->memcpy_channel.cctl & |
1422 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); | |
4983a04f | 1423 | |
e8689e63 | 1424 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1425 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1426 | |
c7da9a56 | 1427 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1428 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1429 | pl08x->mem_buses); | |
e8689e63 | 1430 | |
e8689e63 LW |
1431 | ret = pl08x_prep_channel_resources(plchan, txd); |
1432 | if (ret) | |
1433 | return NULL; | |
e8689e63 LW |
1434 | |
1435 | return &txd->tx; | |
1436 | } | |
1437 | ||
3e2a037c | 1438 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 | 1439 | struct dma_chan *chan, struct scatterlist *sgl, |
db8196df | 1440 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1441 | unsigned long flags, void *context) |
e8689e63 LW |
1442 | { |
1443 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1444 | struct pl08x_driver_data *pl08x = plchan->host; | |
1445 | struct pl08x_txd *txd; | |
b7f69d9d VK |
1446 | struct pl08x_sg *dsg; |
1447 | struct scatterlist *sg; | |
1448 | dma_addr_t slave_addr; | |
0a235657 | 1449 | int ret, tmp; |
409ec8db RK |
1450 | u8 src_buses, dst_buses; |
1451 | u32 cctl; | |
e8689e63 | 1452 | |
e8689e63 | 1453 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", |
fdaf9c4b | 1454 | __func__, sg_dma_len(sgl), plchan->name); |
e8689e63 | 1455 | |
c0428794 | 1456 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1457 | if (!txd) { |
1458 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1459 | return NULL; | |
1460 | } | |
1461 | ||
e8689e63 LW |
1462 | if (direction != plchan->runtime_direction) |
1463 | dev_err(&pl08x->adev->dev, "%s DMA setup does not match " | |
1464 | "the direction configured for the PrimeCell\n", | |
1465 | __func__); | |
1466 | ||
1467 | /* | |
1468 | * Set up addresses, the PrimeCell configured address | |
1469 | * will take precedence since this may configure the | |
1470 | * channel target address dynamically at runtime. | |
1471 | */ | |
1472 | txd->direction = direction; | |
c7da9a56 | 1473 | |
db8196df | 1474 | if (direction == DMA_MEM_TO_DEV) { |
409ec8db | 1475 | cctl = plchan->dst_cctl | PL080_CONTROL_SRC_INCR; |
ed91c13d | 1476 | slave_addr = plchan->cfg.dst_addr; |
409ec8db RK |
1477 | src_buses = pl08x->mem_buses; |
1478 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1479 | } else if (direction == DMA_DEV_TO_MEM) { |
409ec8db | 1480 | cctl = plchan->src_cctl | PL080_CONTROL_DST_INCR; |
ed91c13d | 1481 | slave_addr = plchan->cfg.src_addr; |
409ec8db RK |
1482 | src_buses = plchan->cd->periph_buses; |
1483 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1484 | } else { |
b7f69d9d | 1485 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1486 | dev_err(&pl08x->adev->dev, |
1487 | "%s direction unsupported\n", __func__); | |
1488 | return NULL; | |
1489 | } | |
e8689e63 | 1490 | |
409ec8db RK |
1491 | txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); |
1492 | ||
95442b22 | 1493 | if (plchan->cfg.device_fc) |
db8196df | 1494 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1495 | PL080_FLOW_PER2MEM_PER; |
1496 | else | |
db8196df | 1497 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1498 | PL080_FLOW_PER2MEM; |
1499 | ||
1500 | txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1501 | ||
b7f69d9d VK |
1502 | for_each_sg(sgl, sg, sg_len, tmp) { |
1503 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1504 | if (!dsg) { | |
1505 | pl08x_free_txd(pl08x, txd); | |
1506 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
1507 | __func__); | |
1508 | return NULL; | |
1509 | } | |
1510 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1511 | ||
1512 | dsg->len = sg_dma_len(sg); | |
db8196df | 1513 | if (direction == DMA_MEM_TO_DEV) { |
cbb796cc | 1514 | dsg->src_addr = sg_dma_address(sg); |
b7f69d9d VK |
1515 | dsg->dst_addr = slave_addr; |
1516 | } else { | |
1517 | dsg->src_addr = slave_addr; | |
cbb796cc | 1518 | dsg->dst_addr = sg_dma_address(sg); |
b7f69d9d VK |
1519 | } |
1520 | } | |
1521 | ||
e8689e63 LW |
1522 | ret = pl08x_prep_channel_resources(plchan, txd); |
1523 | if (ret) | |
1524 | return NULL; | |
e8689e63 LW |
1525 | |
1526 | return &txd->tx; | |
1527 | } | |
1528 | ||
1529 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1530 | unsigned long arg) | |
1531 | { | |
1532 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1533 | struct pl08x_driver_data *pl08x = plchan->host; | |
1534 | unsigned long flags; | |
1535 | int ret = 0; | |
1536 | ||
1537 | /* Controls applicable to inactive channels */ | |
1538 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1539 | return dma_set_runtime_config(chan, |
1540 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1541 | } |
1542 | ||
1543 | /* | |
1544 | * Anything succeeds on channels with no physical allocation and | |
1545 | * no queued transfers. | |
1546 | */ | |
1547 | spin_lock_irqsave(&plchan->lock, flags); | |
1548 | if (!plchan->phychan && !plchan->at) { | |
1549 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1550 | return 0; | |
1551 | } | |
1552 | ||
1553 | switch (cmd) { | |
1554 | case DMA_TERMINATE_ALL: | |
1555 | plchan->state = PL08X_CHAN_IDLE; | |
1556 | ||
1557 | if (plchan->phychan) { | |
fb526210 | 1558 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); |
e8689e63 LW |
1559 | |
1560 | /* | |
1561 | * Mark physical channel as free and free any slave | |
1562 | * signal | |
1563 | */ | |
8c8cc2b1 | 1564 | release_phy_channel(plchan); |
88c08a3f | 1565 | plchan->phychan_hold = 0; |
e8689e63 | 1566 | } |
e8689e63 LW |
1567 | /* Dequeue jobs and free LLIs */ |
1568 | if (plchan->at) { | |
1569 | pl08x_free_txd(pl08x, plchan->at); | |
1570 | plchan->at = NULL; | |
1571 | } | |
1572 | /* Dequeue jobs not yet fired as well */ | |
1573 | pl08x_free_txd_list(pl08x, plchan); | |
1574 | break; | |
1575 | case DMA_PAUSE: | |
1576 | pl08x_pause_phy_chan(plchan->phychan); | |
1577 | plchan->state = PL08X_CHAN_PAUSED; | |
1578 | break; | |
1579 | case DMA_RESUME: | |
1580 | pl08x_resume_phy_chan(plchan->phychan); | |
1581 | plchan->state = PL08X_CHAN_RUNNING; | |
1582 | break; | |
1583 | default: | |
1584 | /* Unknown command */ | |
1585 | ret = -ENXIO; | |
1586 | break; | |
1587 | } | |
1588 | ||
1589 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1590 | ||
1591 | return ret; | |
1592 | } | |
1593 | ||
1594 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1595 | { | |
7703eac9 | 1596 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
1597 | char *name = chan_id; |
1598 | ||
7703eac9 RKAL |
1599 | /* Reject channels for devices not bound to this driver */ |
1600 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
1601 | return false; | |
1602 | ||
1603 | plchan = to_pl08x_chan(chan); | |
1604 | ||
e8689e63 LW |
1605 | /* Check that the channel is not taken! */ |
1606 | if (!strcmp(plchan->name, name)) | |
1607 | return true; | |
1608 | ||
1609 | return false; | |
1610 | } | |
1611 | ||
1612 | /* | |
1613 | * Just check that the device is there and active | |
94ae8522 RKAL |
1614 | * TODO: turn this bit on/off depending on the number of physical channels |
1615 | * actually used, if it is zero... well shut it off. That will save some | |
1616 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1617 | */ |
1618 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1619 | { | |
affa115e LW |
1620 | /* The Nomadik variant does not have the config register */ |
1621 | if (pl08x->vd->nomadik) | |
1622 | return; | |
48a59ef3 | 1623 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
1624 | } |
1625 | ||
3d992e1a RKAL |
1626 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1627 | { | |
1628 | struct device *dev = txd->tx.chan->device->dev; | |
b7f69d9d | 1629 | struct pl08x_sg *dsg; |
3d992e1a RKAL |
1630 | |
1631 | if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
1632 | if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
b7f69d9d VK |
1633 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1634 | dma_unmap_single(dev, dsg->src_addr, dsg->len, | |
1635 | DMA_TO_DEVICE); | |
1636 | else { | |
1637 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1638 | dma_unmap_page(dev, dsg->src_addr, dsg->len, | |
1639 | DMA_TO_DEVICE); | |
1640 | } | |
3d992e1a RKAL |
1641 | } |
1642 | if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
1643 | if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
b7f69d9d VK |
1644 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1645 | dma_unmap_single(dev, dsg->dst_addr, dsg->len, | |
1646 | DMA_FROM_DEVICE); | |
3d992e1a | 1647 | else |
b7f69d9d VK |
1648 | list_for_each_entry(dsg, &txd->dsg_list, node) |
1649 | dma_unmap_page(dev, dsg->dst_addr, dsg->len, | |
1650 | DMA_FROM_DEVICE); | |
3d992e1a RKAL |
1651 | } |
1652 | } | |
1653 | ||
e8689e63 LW |
1654 | static void pl08x_tasklet(unsigned long data) |
1655 | { | |
1656 | struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; | |
e8689e63 | 1657 | struct pl08x_driver_data *pl08x = plchan->host; |
858c21c0 | 1658 | struct pl08x_txd *txd; |
bf072af4 | 1659 | unsigned long flags; |
e8689e63 | 1660 | |
bf072af4 | 1661 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1662 | |
858c21c0 RKAL |
1663 | txd = plchan->at; |
1664 | plchan->at = NULL; | |
e8689e63 | 1665 | |
858c21c0 | 1666 | if (txd) { |
94ae8522 | 1667 | /* Update last completed */ |
f7fbce07 | 1668 | dma_cookie_complete(&txd->tx); |
e8689e63 | 1669 | } |
8087aacd | 1670 | |
94ae8522 | 1671 | /* If a new descriptor is queued, set it up plchan->at is NULL here */ |
15c17232 | 1672 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 LW |
1673 | struct pl08x_txd *next; |
1674 | ||
15c17232 | 1675 | next = list_first_entry(&plchan->pend_list, |
e8689e63 LW |
1676 | struct pl08x_txd, |
1677 | node); | |
1678 | list_del(&next->node); | |
c885bee4 RKAL |
1679 | |
1680 | pl08x_start_txd(plchan, next); | |
8087aacd RKAL |
1681 | } else if (plchan->phychan_hold) { |
1682 | /* | |
1683 | * This channel is still in use - we have a new txd being | |
1684 | * prepared and will soon be queued. Don't give up the | |
1685 | * physical channel. | |
1686 | */ | |
e8689e63 LW |
1687 | } else { |
1688 | struct pl08x_dma_chan *waiting = NULL; | |
1689 | ||
1690 | /* | |
1691 | * No more jobs, so free up the physical channel | |
1692 | * Free any allocated signal on slave transfers too | |
1693 | */ | |
8c8cc2b1 | 1694 | release_phy_channel(plchan); |
e8689e63 LW |
1695 | plchan->state = PL08X_CHAN_IDLE; |
1696 | ||
1697 | /* | |
94ae8522 RKAL |
1698 | * And NOW before anyone else can grab that free:d up |
1699 | * physical channel, see if there is some memcpy pending | |
1700 | * that seriously needs to start because of being stacked | |
1701 | * up while we were choking the physical channels with data. | |
e8689e63 LW |
1702 | */ |
1703 | list_for_each_entry(waiting, &pl08x->memcpy.channels, | |
1704 | chan.device_node) { | |
3e27ee84 VK |
1705 | if (waiting->state == PL08X_CHAN_WAITING && |
1706 | waiting->waiting != NULL) { | |
e8689e63 LW |
1707 | int ret; |
1708 | ||
1709 | /* This should REALLY not fail now */ | |
1710 | ret = prep_phy_channel(waiting, | |
1711 | waiting->waiting); | |
1712 | BUG_ON(ret); | |
8087aacd | 1713 | waiting->phychan_hold--; |
e8689e63 LW |
1714 | waiting->state = PL08X_CHAN_RUNNING; |
1715 | waiting->waiting = NULL; | |
1716 | pl08x_issue_pending(&waiting->chan); | |
1717 | break; | |
1718 | } | |
1719 | } | |
1720 | } | |
1721 | ||
bf072af4 | 1722 | spin_unlock_irqrestore(&plchan->lock, flags); |
858c21c0 | 1723 | |
3d992e1a RKAL |
1724 | if (txd) { |
1725 | dma_async_tx_callback callback = txd->tx.callback; | |
1726 | void *callback_param = txd->tx.callback_param; | |
1727 | ||
1728 | /* Don't try to unmap buffers on slave channels */ | |
1729 | if (!plchan->slave) | |
1730 | pl08x_unmap_buffers(txd); | |
1731 | ||
1732 | /* Free the descriptor */ | |
1733 | spin_lock_irqsave(&plchan->lock, flags); | |
1734 | pl08x_free_txd(pl08x, txd); | |
1735 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1736 | ||
1737 | /* Callback to signal completion */ | |
1738 | if (callback) | |
1739 | callback(callback_param); | |
1740 | } | |
e8689e63 LW |
1741 | } |
1742 | ||
1743 | static irqreturn_t pl08x_irq(int irq, void *dev) | |
1744 | { | |
1745 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
1746 | u32 mask = 0, err, tc, i; |
1747 | ||
1748 | /* check & clear - ERR & TC interrupts */ | |
1749 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
1750 | if (err) { | |
1751 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
1752 | __func__, err); | |
1753 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 1754 | } |
d29bf019 | 1755 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
1756 | if (tc) |
1757 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
1758 | ||
1759 | if (!err && !tc) | |
1760 | return IRQ_NONE; | |
1761 | ||
e8689e63 | 1762 | for (i = 0; i < pl08x->vd->channels; i++) { |
28da2836 | 1763 | if (((1 << i) & err) || ((1 << i) & tc)) { |
e8689e63 LW |
1764 | /* Locate physical channel */ |
1765 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1766 | struct pl08x_dma_chan *plchan = phychan->serving; | |
1767 | ||
28da2836 VK |
1768 | if (!plchan) { |
1769 | dev_err(&pl08x->adev->dev, | |
1770 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
1771 | __func__, i); | |
1772 | continue; | |
1773 | } | |
1774 | ||
e8689e63 LW |
1775 | /* Schedule tasklet on this channel */ |
1776 | tasklet_schedule(&plchan->tasklet); | |
e8689e63 LW |
1777 | mask |= (1 << i); |
1778 | } | |
1779 | } | |
e8689e63 LW |
1780 | |
1781 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1782 | } | |
1783 | ||
121c8476 RKAL |
1784 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1785 | { | |
1786 | u32 cctl = pl08x_cctl(chan->cd->cctl); | |
1787 | ||
1788 | chan->slave = true; | |
1789 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
1790 | chan->cfg.src_addr = chan->cd->addr; |
1791 | chan->cfg.dst_addr = chan->cd->addr; | |
409ec8db RK |
1792 | chan->src_cctl = cctl; |
1793 | chan->dst_cctl = cctl; | |
121c8476 RKAL |
1794 | } |
1795 | ||
e8689e63 LW |
1796 | /* |
1797 | * Initialise the DMAC memcpy/slave channels. | |
1798 | * Make a local wrapper to hold required data | |
1799 | */ | |
1800 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1801 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1802 | { |
1803 | struct pl08x_dma_chan *chan; | |
1804 | int i; | |
1805 | ||
1806 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1807 | |
e8689e63 LW |
1808 | /* |
1809 | * Register as many many memcpy as we have physical channels, | |
1810 | * we won't always be able to use all but the code will have | |
1811 | * to cope with that situation. | |
1812 | */ | |
1813 | for (i = 0; i < channels; i++) { | |
b201c111 | 1814 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1815 | if (!chan) { |
1816 | dev_err(&pl08x->adev->dev, | |
1817 | "%s no memory for channel\n", __func__); | |
1818 | return -ENOMEM; | |
1819 | } | |
1820 | ||
1821 | chan->host = pl08x; | |
1822 | chan->state = PL08X_CHAN_IDLE; | |
1823 | ||
1824 | if (slave) { | |
e8689e63 | 1825 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1826 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1827 | } else { |
1828 | chan->cd = &pl08x->pd->memcpy_channel; | |
1829 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1830 | if (!chan->name) { | |
1831 | kfree(chan); | |
1832 | return -ENOMEM; | |
1833 | } | |
1834 | } | |
175a5e61 | 1835 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1836 | "initialize virtual channel \"%s\"\n", |
1837 | chan->name); | |
1838 | ||
1839 | chan->chan.device = dmadev; | |
d3ee98cd | 1840 | dma_cookie_init(&chan->chan); |
e8689e63 LW |
1841 | |
1842 | spin_lock_init(&chan->lock); | |
15c17232 | 1843 | INIT_LIST_HEAD(&chan->pend_list); |
e8689e63 LW |
1844 | tasklet_init(&chan->tasklet, pl08x_tasklet, |
1845 | (unsigned long) chan); | |
1846 | ||
1847 | list_add_tail(&chan->chan.device_node, &dmadev->channels); | |
1848 | } | |
1849 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1850 | i, slave ? "slave" : "memcpy"); | |
1851 | return i; | |
1852 | } | |
1853 | ||
1854 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1855 | { | |
1856 | struct pl08x_dma_chan *chan = NULL; | |
1857 | struct pl08x_dma_chan *next; | |
1858 | ||
1859 | list_for_each_entry_safe(chan, | |
1860 | next, &dmadev->channels, chan.device_node) { | |
1861 | list_del(&chan->chan.device_node); | |
1862 | kfree(chan); | |
1863 | } | |
1864 | } | |
1865 | ||
1866 | #ifdef CONFIG_DEBUG_FS | |
1867 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1868 | { | |
1869 | switch (state) { | |
1870 | case PL08X_CHAN_IDLE: | |
1871 | return "idle"; | |
1872 | case PL08X_CHAN_RUNNING: | |
1873 | return "running"; | |
1874 | case PL08X_CHAN_PAUSED: | |
1875 | return "paused"; | |
1876 | case PL08X_CHAN_WAITING: | |
1877 | return "waiting"; | |
1878 | default: | |
1879 | break; | |
1880 | } | |
1881 | return "UNKNOWN STATE"; | |
1882 | } | |
1883 | ||
1884 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1885 | { | |
1886 | struct pl08x_driver_data *pl08x = s->private; | |
1887 | struct pl08x_dma_chan *chan; | |
1888 | struct pl08x_phy_chan *ch; | |
1889 | unsigned long flags; | |
1890 | int i; | |
1891 | ||
1892 | seq_printf(s, "PL08x physical channels:\n"); | |
1893 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1894 | seq_printf(s, "--------\t-----\n"); | |
1895 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1896 | struct pl08x_dma_chan *virt_chan; | |
1897 | ||
1898 | ch = &pl08x->phy_chans[i]; | |
1899 | ||
1900 | spin_lock_irqsave(&ch->lock, flags); | |
1901 | virt_chan = ch->serving; | |
1902 | ||
affa115e LW |
1903 | seq_printf(s, "%d\t\t%s%s\n", |
1904 | ch->id, | |
1905 | virt_chan ? virt_chan->name : "(none)", | |
1906 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
1907 | |
1908 | spin_unlock_irqrestore(&ch->lock, flags); | |
1909 | } | |
1910 | ||
1911 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1912 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1913 | seq_printf(s, "--------\t------\n"); | |
1914 | list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) { | |
3e2a037c | 1915 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1916 | pl08x_state_str(chan->state)); |
1917 | } | |
1918 | ||
1919 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1920 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1921 | seq_printf(s, "--------\t------\n"); | |
1922 | list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) { | |
3e2a037c | 1923 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1924 | pl08x_state_str(chan->state)); |
1925 | } | |
1926 | ||
1927 | return 0; | |
1928 | } | |
1929 | ||
1930 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1931 | { | |
1932 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1933 | } | |
1934 | ||
1935 | static const struct file_operations pl08x_debugfs_operations = { | |
1936 | .open = pl08x_debugfs_open, | |
1937 | .read = seq_read, | |
1938 | .llseek = seq_lseek, | |
1939 | .release = single_release, | |
1940 | }; | |
1941 | ||
1942 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1943 | { | |
1944 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1945 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1946 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1947 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1948 | } |
1949 | ||
1950 | #else | |
1951 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1952 | { | |
1953 | } | |
1954 | #endif | |
1955 | ||
aa25afad | 1956 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1957 | { |
1958 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1959 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1960 | int ret = 0; |
1961 | int i; | |
1962 | ||
1963 | ret = amba_request_regions(adev, NULL); | |
1964 | if (ret) | |
1965 | return ret; | |
1966 | ||
1967 | /* Create the driver state holder */ | |
b201c111 | 1968 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1969 | if (!pl08x) { |
1970 | ret = -ENOMEM; | |
1971 | goto out_no_pl08x; | |
1972 | } | |
1973 | ||
1974 | /* Initialize memcpy engine */ | |
1975 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1976 | pl08x->memcpy.dev = &adev->dev; | |
1977 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1978 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1979 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1980 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1981 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1982 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1983 | pl08x->memcpy.device_control = pl08x_control; | |
1984 | ||
1985 | /* Initialize slave engine */ | |
1986 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1987 | pl08x->slave.dev = &adev->dev; | |
1988 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1989 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1990 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1991 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1992 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1993 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1994 | pl08x->slave.device_control = pl08x_control; | |
1995 | ||
1996 | /* Get the platform data */ | |
1997 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1998 | if (!pl08x->pd) { | |
1999 | dev_err(&adev->dev, "no platform data supplied\n"); | |
2000 | goto out_no_platdata; | |
2001 | } | |
2002 | ||
2003 | /* Assign useful pointers to the driver state */ | |
2004 | pl08x->adev = adev; | |
2005 | pl08x->vd = vd; | |
2006 | ||
30749cb4 RKAL |
2007 | /* By default, AHB1 only. If dualmaster, from platform */ |
2008 | pl08x->lli_buses = PL08X_AHB1; | |
2009 | pl08x->mem_buses = PL08X_AHB1; | |
2010 | if (pl08x->vd->dualmaster) { | |
2011 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
2012 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
2013 | } | |
2014 | ||
e8689e63 LW |
2015 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
2016 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
2017 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
2018 | if (!pl08x->pool) { | |
2019 | ret = -ENOMEM; | |
2020 | goto out_no_lli_pool; | |
2021 | } | |
2022 | ||
e8689e63 LW |
2023 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
2024 | if (!pl08x->base) { | |
2025 | ret = -ENOMEM; | |
2026 | goto out_no_ioremap; | |
2027 | } | |
2028 | ||
2029 | /* Turn on the PL08x */ | |
2030 | pl08x_ensure_on(pl08x); | |
2031 | ||
94ae8522 | 2032 | /* Attach the interrupt handler */ |
e8689e63 LW |
2033 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
2034 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
2035 | ||
2036 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 2037 | DRIVER_NAME, pl08x); |
e8689e63 LW |
2038 | if (ret) { |
2039 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
2040 | __func__, adev->irq[0]); | |
2041 | goto out_no_irq; | |
2042 | } | |
2043 | ||
2044 | /* Initialize physical channels */ | |
affa115e | 2045 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
2046 | GFP_KERNEL); |
2047 | if (!pl08x->phy_chans) { | |
2048 | dev_err(&adev->dev, "%s failed to allocate " | |
2049 | "physical channel holders\n", | |
2050 | __func__); | |
2051 | goto out_no_phychans; | |
2052 | } | |
2053 | ||
2054 | for (i = 0; i < vd->channels; i++) { | |
2055 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
2056 | ||
2057 | ch->id = i; | |
2058 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
2059 | spin_lock_init(&ch->lock); | |
e8689e63 | 2060 | ch->signal = -1; |
affa115e LW |
2061 | |
2062 | /* | |
2063 | * Nomadik variants can have channels that are locked | |
2064 | * down for the secure world only. Lock up these channels | |
2065 | * by perpetually serving a dummy virtual channel. | |
2066 | */ | |
2067 | if (vd->nomadik) { | |
2068 | u32 val; | |
2069 | ||
2070 | val = readl(ch->base + PL080_CH_CONFIG); | |
2071 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { | |
2072 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
2073 | ch->locked = true; | |
2074 | } | |
2075 | } | |
2076 | ||
175a5e61 VK |
2077 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
2078 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
2079 | } |
2080 | ||
2081 | /* Register as many memcpy channels as there are physical channels */ | |
2082 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
2083 | pl08x->vd->channels, false); | |
2084 | if (ret <= 0) { | |
2085 | dev_warn(&pl08x->adev->dev, | |
2086 | "%s failed to enumerate memcpy channels - %d\n", | |
2087 | __func__, ret); | |
2088 | goto out_no_memcpy; | |
2089 | } | |
2090 | pl08x->memcpy.chancnt = ret; | |
2091 | ||
2092 | /* Register slave channels */ | |
2093 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 2094 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
2095 | if (ret <= 0) { |
2096 | dev_warn(&pl08x->adev->dev, | |
2097 | "%s failed to enumerate slave channels - %d\n", | |
2098 | __func__, ret); | |
2099 | goto out_no_slave; | |
2100 | } | |
2101 | pl08x->slave.chancnt = ret; | |
2102 | ||
2103 | ret = dma_async_device_register(&pl08x->memcpy); | |
2104 | if (ret) { | |
2105 | dev_warn(&pl08x->adev->dev, | |
2106 | "%s failed to register memcpy as an async device - %d\n", | |
2107 | __func__, ret); | |
2108 | goto out_no_memcpy_reg; | |
2109 | } | |
2110 | ||
2111 | ret = dma_async_device_register(&pl08x->slave); | |
2112 | if (ret) { | |
2113 | dev_warn(&pl08x->adev->dev, | |
2114 | "%s failed to register slave as an async device - %d\n", | |
2115 | __func__, ret); | |
2116 | goto out_no_slave_reg; | |
2117 | } | |
2118 | ||
2119 | amba_set_drvdata(adev, pl08x); | |
2120 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
2121 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
2122 | amba_part(adev), amba_rev(adev), | |
2123 | (unsigned long long)adev->res.start, adev->irq[0]); | |
b7b6018b | 2124 | |
e8689e63 LW |
2125 | return 0; |
2126 | ||
2127 | out_no_slave_reg: | |
2128 | dma_async_device_unregister(&pl08x->memcpy); | |
2129 | out_no_memcpy_reg: | |
2130 | pl08x_free_virtual_channels(&pl08x->slave); | |
2131 | out_no_slave: | |
2132 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2133 | out_no_memcpy: | |
2134 | kfree(pl08x->phy_chans); | |
2135 | out_no_phychans: | |
2136 | free_irq(adev->irq[0], pl08x); | |
2137 | out_no_irq: | |
2138 | iounmap(pl08x->base); | |
2139 | out_no_ioremap: | |
2140 | dma_pool_destroy(pl08x->pool); | |
2141 | out_no_lli_pool: | |
2142 | out_no_platdata: | |
2143 | kfree(pl08x); | |
2144 | out_no_pl08x: | |
2145 | amba_release_regions(adev); | |
2146 | return ret; | |
2147 | } | |
2148 | ||
2149 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2150 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
2151 | .channels = 8, |
2152 | .dualmaster = true, | |
2153 | }; | |
2154 | ||
affa115e LW |
2155 | static struct vendor_data vendor_nomadik = { |
2156 | .channels = 8, | |
2157 | .dualmaster = true, | |
2158 | .nomadik = true, | |
2159 | }; | |
2160 | ||
e8689e63 | 2161 | static struct vendor_data vendor_pl081 = { |
e8689e63 LW |
2162 | .channels = 2, |
2163 | .dualmaster = false, | |
2164 | }; | |
2165 | ||
2166 | static struct amba_id pl08x_ids[] = { | |
2167 | /* PL080 */ | |
2168 | { | |
2169 | .id = 0x00041080, | |
2170 | .mask = 0x000fffff, | |
2171 | .data = &vendor_pl080, | |
2172 | }, | |
2173 | /* PL081 */ | |
2174 | { | |
2175 | .id = 0x00041081, | |
2176 | .mask = 0x000fffff, | |
2177 | .data = &vendor_pl081, | |
2178 | }, | |
2179 | /* Nomadik 8815 PL080 variant */ | |
2180 | { | |
affa115e | 2181 | .id = 0x00280080, |
e8689e63 | 2182 | .mask = 0x00ffffff, |
affa115e | 2183 | .data = &vendor_nomadik, |
e8689e63 LW |
2184 | }, |
2185 | { 0, 0 }, | |
2186 | }; | |
2187 | ||
037566df DM |
2188 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
2189 | ||
e8689e63 LW |
2190 | static struct amba_driver pl08x_amba_driver = { |
2191 | .drv.name = DRIVER_NAME, | |
2192 | .id_table = pl08x_ids, | |
2193 | .probe = pl08x_probe, | |
2194 | }; | |
2195 | ||
2196 | static int __init pl08x_init(void) | |
2197 | { | |
2198 | int retval; | |
2199 | retval = amba_driver_register(&pl08x_amba_driver); | |
2200 | if (retval) | |
2201 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2202 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2203 | retval); |
2204 | return retval; | |
2205 | } | |
2206 | subsys_initcall(pl08x_init); |