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4ffda636 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e8689e63 LW |
2 | /* |
3 | * Copyright (c) 2006 ARM Ltd. | |
4 | * Copyright (c) 2010 ST-Ericsson SA | |
1e1cfc72 | 5 | * Copyirght (c) 2017 Linaro Ltd. |
e8689e63 LW |
6 | * |
7 | * Author: Peter Pearse <peter.pearse@arm.com> | |
1e1cfc72 | 8 | * Author: Linus Walleij <linus.walleij@linaro.org> |
e8689e63 | 9 | * |
e8689e63 | 10 | * Documentation: ARM DDI 0196G == PL080 |
94ae8522 | 11 | * Documentation: ARM DDI 0218E == PL081 |
da1b6c05 | 12 | * Documentation: S3C6410 User's Manual == PL080S |
e8689e63 | 13 | * |
94ae8522 RKAL |
14 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
15 | * channel. | |
e8689e63 LW |
16 | * |
17 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
18 | * has only two channels. So on these DMA controllers the number of channels | |
19 | * and the number of incoming DMA signals are two totally different things. | |
20 | * It is usually not possible to theoretically handle all physical signals, | |
21 | * so a multiplexing scheme with possible denial of use is necessary. | |
22 | * | |
23 | * The PL080 has a dual bus master, PL081 has a single master. | |
24 | * | |
da1b6c05 TF |
25 | * PL080S is a version modified by Samsung and used in S3C64xx SoCs. |
26 | * It differs in following aspects: | |
27 | * - CH_CONFIG register at different offset, | |
28 | * - separate CH_CONTROL2 register for transfer size, | |
29 | * - bigger maximum transfer size, | |
30 | * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word, | |
31 | * - no support for peripheral flow control. | |
32 | * | |
e8689e63 LW |
33 | * Memory to peripheral transfer may be visualized as |
34 | * Get data from memory to DMAC | |
35 | * Until no data left | |
36 | * On burst request from peripheral | |
37 | * Destination burst from DMAC to peripheral | |
38 | * Clear burst request | |
39 | * Raise terminal count interrupt | |
40 | * | |
41 | * For peripherals with a FIFO: | |
42 | * Source burst size == half the depth of the peripheral FIFO | |
43 | * Destination burst size == the depth of the peripheral FIFO | |
44 | * | |
45 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
46 | * signals, the DMA controller will simply facilitate its AHB master.) | |
47 | * | |
48 | * ASSUMES default (little) endianness for DMA transfers | |
49 | * | |
9dc2c200 RKAL |
50 | * The PL08x has two flow control settings: |
51 | * - DMAC flow control: the transfer size defines the number of transfers | |
52 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
53 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
54 | * to both the BREQ and SREQ signals (contrary to documented), | |
55 | * transferring data if either is active. The LBREQ and LSREQ signals | |
56 | * are ignored. | |
57 | * | |
58 | * - Peripheral flow control: the transfer size is ignored (and should be | |
59 | * zero). The data is transferred from the current LLI entry, until | |
60 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
da1b6c05 | 61 | * will then move to the next LLI entry. Unsupported by PL080S. |
e8689e63 | 62 | */ |
730404ac | 63 | #include <linux/amba/bus.h> |
e8689e63 LW |
64 | #include <linux/amba/pl08x.h> |
65 | #include <linux/debugfs.h> | |
0c38d701 VK |
66 | #include <linux/delay.h> |
67 | #include <linux/device.h> | |
68 | #include <linux/dmaengine.h> | |
69 | #include <linux/dmapool.h> | |
8516f52f | 70 | #include <linux/dma-mapping.h> |
6d05c9fa | 71 | #include <linux/export.h> |
0c38d701 VK |
72 | #include <linux/init.h> |
73 | #include <linux/interrupt.h> | |
74 | #include <linux/module.h> | |
aa4734da LW |
75 | #include <linux/of.h> |
76 | #include <linux/of_dma.h> | |
b7b6018b | 77 | #include <linux/pm_runtime.h> |
e8689e63 | 78 | #include <linux/seq_file.h> |
0c38d701 | 79 | #include <linux/slab.h> |
3a95b9fb | 80 | #include <linux/amba/pl080.h> |
e8689e63 | 81 | |
d2ebfb33 | 82 | #include "dmaengine.h" |
01d8dc64 | 83 | #include "virt-dma.h" |
d2ebfb33 | 84 | |
e8689e63 LW |
85 | #define DRIVER_NAME "pl08xdmac" |
86 | ||
ea524c7e MB |
87 | #define PL80X_DMA_BUSWIDTHS \ |
88 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
89 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
90 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
91 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | |
92 | ||
7703eac9 | 93 | static struct amba_driver pl08x_amba_driver; |
b23f204c | 94 | struct pl08x_driver_data; |
7703eac9 | 95 | |
e8689e63 | 96 | /** |
94ae8522 | 97 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
da7cbd20 | 98 | * @config_offset: offset to the configuration register |
e8689e63 | 99 | * @channels: the number of channels available in this variant |
f9cd4761 | 100 | * @signals: the number of request signals available from the hardware |
94ae8522 | 101 | * @dualmaster: whether this version supports dual AHB masters or not. |
1e1cfc72 LW |
102 | * @nomadik: whether this variant is a ST Microelectronics Nomadik, where the |
103 | * channels have Nomadik security extension bits that need to be checked | |
104 | * for permission before use and some registers are missing | |
105 | * @pl080s: whether this variant is a Samsung PL080S, which has separate | |
106 | * register and LLI word for transfer size. | |
107 | * @ftdmac020: whether this variant is a Faraday Technology FTDMAC020 | |
f9cd4761 LW |
108 | * @max_transfer_size: the maximum single element transfer size for this |
109 | * PL08x variant. | |
e8689e63 LW |
110 | */ |
111 | struct vendor_data { | |
d86ccea7 | 112 | u8 config_offset; |
e8689e63 | 113 | u8 channels; |
f9cd4761 | 114 | u8 signals; |
e8689e63 | 115 | bool dualmaster; |
affa115e | 116 | bool nomadik; |
da1b6c05 | 117 | bool pl080s; |
1e1cfc72 | 118 | bool ftdmac020; |
5110e51d | 119 | u32 max_transfer_size; |
e8689e63 LW |
120 | }; |
121 | ||
b23f204c RK |
122 | /** |
123 | * struct pl08x_bus_data - information of source or destination | |
124 | * busses for a transfer | |
125 | * @addr: current address | |
126 | * @maxwidth: the maximum width of a transfer on this bus | |
127 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | |
128 | */ | |
129 | struct pl08x_bus_data { | |
130 | dma_addr_t addr; | |
131 | u8 maxwidth; | |
132 | u8 buswidth; | |
133 | }; | |
134 | ||
1c38b289 AP |
135 | #define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth) |
136 | ||
b23f204c RK |
137 | /** |
138 | * struct pl08x_phy_chan - holder for the physical channels | |
139 | * @id: physical index to this channel | |
da7cbd20 LW |
140 | * @base: memory base address for this physical channel |
141 | * @reg_config: configuration address for this physical channel | |
1e1cfc72 LW |
142 | * @reg_control: control address for this physical channel |
143 | * @reg_src: transfer source address register | |
144 | * @reg_dst: transfer destination address register | |
145 | * @reg_lli: transfer LLI address register | |
146 | * @reg_busy: if the variant has a special per-channel busy register, | |
147 | * this contains a pointer to it | |
b23f204c | 148 | * @lock: a lock to use when altering an instance of this struct |
b23f204c RK |
149 | * @serving: the virtual channel currently being served by this physical |
150 | * channel | |
ad0de2ac RK |
151 | * @locked: channel unavailable for the system, e.g. dedicated to secure |
152 | * world | |
1e1cfc72 LW |
153 | * @ftdmac020: channel is on a FTDMAC020 |
154 | * @pl080s: channel is on a PL08s | |
b23f204c RK |
155 | */ |
156 | struct pl08x_phy_chan { | |
157 | unsigned int id; | |
158 | void __iomem *base; | |
d86ccea7 | 159 | void __iomem *reg_config; |
1e1cfc72 LW |
160 | void __iomem *reg_control; |
161 | void __iomem *reg_src; | |
162 | void __iomem *reg_dst; | |
163 | void __iomem *reg_lli; | |
164 | void __iomem *reg_busy; | |
b23f204c | 165 | spinlock_t lock; |
b23f204c | 166 | struct pl08x_dma_chan *serving; |
ad0de2ac | 167 | bool locked; |
1e1cfc72 LW |
168 | bool ftdmac020; |
169 | bool pl080s; | |
b23f204c RK |
170 | }; |
171 | ||
172 | /** | |
173 | * struct pl08x_sg - structure containing data per sg | |
174 | * @src_addr: src address of sg | |
175 | * @dst_addr: dst address of sg | |
176 | * @len: transfer len in bytes | |
177 | * @node: node for txd's dsg_list | |
178 | */ | |
179 | struct pl08x_sg { | |
180 | dma_addr_t src_addr; | |
181 | dma_addr_t dst_addr; | |
182 | size_t len; | |
183 | struct list_head node; | |
184 | }; | |
185 | ||
186 | /** | |
187 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | |
01d8dc64 | 188 | * @vd: virtual DMA descriptor |
b23f204c | 189 | * @dsg_list: list of children sg's |
b23f204c RK |
190 | * @llis_bus: DMA memory address (physical) start for the LLIs |
191 | * @llis_va: virtual memory address start for the LLIs | |
192 | * @cctl: control reg values for current txd | |
193 | * @ccfg: config reg values for current txd | |
18536134 RK |
194 | * @done: this marks completed descriptors, which should not have their |
195 | * mux released. | |
3b24c20b | 196 | * @cyclic: indicate cyclic transfers |
b23f204c RK |
197 | */ |
198 | struct pl08x_txd { | |
01d8dc64 | 199 | struct virt_dma_desc vd; |
b23f204c | 200 | struct list_head dsg_list; |
b23f204c | 201 | dma_addr_t llis_bus; |
ba6785ff | 202 | u32 *llis_va; |
b23f204c RK |
203 | /* Default cctl value for LLIs */ |
204 | u32 cctl; | |
205 | /* | |
206 | * Settings to be put into the physical channel when we | |
207 | * trigger this txd. Other registers are in llis_va[0]. | |
208 | */ | |
209 | u32 ccfg; | |
18536134 | 210 | bool done; |
3b24c20b | 211 | bool cyclic; |
b23f204c RK |
212 | }; |
213 | ||
214 | /** | |
8ee1bdc5 | 215 | * enum pl08x_dma_chan_state - holds the PL08x specific virtual channel |
b23f204c RK |
216 | * states |
217 | * @PL08X_CHAN_IDLE: the channel is idle | |
218 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | |
219 | * channel and is running a transfer on it | |
220 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | |
221 | * channel, but the transfer is currently paused | |
222 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | |
223 | * channel to become available (only pertains to memcpy channels) | |
224 | */ | |
225 | enum pl08x_dma_chan_state { | |
226 | PL08X_CHAN_IDLE, | |
227 | PL08X_CHAN_RUNNING, | |
228 | PL08X_CHAN_PAUSED, | |
229 | PL08X_CHAN_WAITING, | |
230 | }; | |
231 | ||
232 | /** | |
233 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | |
01d8dc64 | 234 | * @vc: wrappped virtual channel |
b23f204c | 235 | * @phychan: the physical channel utilized by this channel, if there is one |
b23f204c RK |
236 | * @name: name of channel |
237 | * @cd: channel platform data | |
da7cbd20 | 238 | * @cfg: slave configuration |
b23f204c | 239 | * @at: active transaction on this channel |
b23f204c RK |
240 | * @host: a pointer to the host (internal use) |
241 | * @state: whether the channel is idle, paused, running etc | |
242 | * @slave: whether this channel is a device (slave) or for memcpy | |
ad0de2ac | 243 | * @signal: the physical DMA request signal which this channel is using |
5e2479bd | 244 | * @mux_use: count of descriptors using this DMA request signal setting |
2ff25c1c | 245 | * @waiting_at: time in jiffies when this channel moved to waiting state |
b23f204c RK |
246 | */ |
247 | struct pl08x_dma_chan { | |
01d8dc64 | 248 | struct virt_dma_chan vc; |
b23f204c | 249 | struct pl08x_phy_chan *phychan; |
550ec36f | 250 | const char *name; |
f9cd4761 | 251 | struct pl08x_channel_data *cd; |
ed91c13d | 252 | struct dma_slave_config cfg; |
b23f204c | 253 | struct pl08x_txd *at; |
b23f204c RK |
254 | struct pl08x_driver_data *host; |
255 | enum pl08x_dma_chan_state state; | |
256 | bool slave; | |
ad0de2ac | 257 | int signal; |
5e2479bd | 258 | unsigned mux_use; |
2ff25c1c | 259 | unsigned long waiting_at; |
b23f204c RK |
260 | }; |
261 | ||
e8689e63 LW |
262 | /** |
263 | * struct pl08x_driver_data - the local state holder for the PL08x | |
ebe9b300 | 264 | * @slave: optional slave engine for this instance |
e8689e63 | 265 | * @memcpy: memcpy engine for this instance |
ebe9b300 | 266 | * @has_slave: the PL08x has a slave engine (routed signals) |
e8689e63 LW |
267 | * @base: virtual memory base (remapped) for the PL08x |
268 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
269 | * @vd: vendor data for this PL08x variant | |
270 | * @pd: platform data passed in from the platform/machine | |
271 | * @phy_chans: array of data for the physical channels | |
272 | * @pool: a pool for the LLI descriptors | |
3e27ee84 VK |
273 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
274 | * fetches | |
30749cb4 | 275 | * @mem_buses: set to indicate memory transfers on AHB2. |
da7cbd20 | 276 | * @lli_words: how many words are used in each LLI item for this variant |
e8689e63 LW |
277 | */ |
278 | struct pl08x_driver_data { | |
279 | struct dma_device slave; | |
280 | struct dma_device memcpy; | |
ebe9b300 | 281 | bool has_slave; |
e8689e63 LW |
282 | void __iomem *base; |
283 | struct amba_device *adev; | |
f96ca9ec | 284 | const struct vendor_data *vd; |
e8689e63 LW |
285 | struct pl08x_platform_data *pd; |
286 | struct pl08x_phy_chan *phy_chans; | |
287 | struct dma_pool *pool; | |
30749cb4 RKAL |
288 | u8 lli_buses; |
289 | u8 mem_buses; | |
ba6785ff | 290 | u8 lli_words; |
e8689e63 LW |
291 | }; |
292 | ||
293 | /* | |
294 | * PL08X specific defines | |
295 | */ | |
296 | ||
ba6785ff TF |
297 | /* The order of words in an LLI. */ |
298 | #define PL080_LLI_SRC 0 | |
299 | #define PL080_LLI_DST 1 | |
300 | #define PL080_LLI_LLI 2 | |
301 | #define PL080_LLI_CCTL 3 | |
da1b6c05 | 302 | #define PL080S_LLI_CCTL2 4 |
ba6785ff TF |
303 | |
304 | /* Total words in an LLI. */ | |
305 | #define PL080_LLI_WORDS 4 | |
da1b6c05 | 306 | #define PL080S_LLI_WORDS 8 |
e8689e63 | 307 | |
ba6785ff TF |
308 | /* |
309 | * Number of LLIs in each LLI buffer allocated for one transfer | |
310 | * (maximum times we call dma_pool_alloc on this pool without freeing) | |
311 | */ | |
312 | #define MAX_NUM_TSFR_LLIS 512 | |
e8689e63 LW |
313 | #define PL08X_ALIGN 8 |
314 | ||
315 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
316 | { | |
01d8dc64 | 317 | return container_of(chan, struct pl08x_dma_chan, vc.chan); |
e8689e63 LW |
318 | } |
319 | ||
501e67e8 RKAL |
320 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
321 | { | |
01d8dc64 | 322 | return container_of(tx, struct pl08x_txd, vd.tx); |
501e67e8 RKAL |
323 | } |
324 | ||
6b16c8b1 RK |
325 | /* |
326 | * Mux handling. | |
327 | * | |
328 | * This gives us the DMA request input to the PL08x primecell which the | |
329 | * peripheral described by the channel data will be routed to, possibly | |
330 | * via a board/SoC specific external MUX. One important point to note | |
331 | * here is that this does not depend on the physical channel. | |
332 | */ | |
ad0de2ac | 333 | static int pl08x_request_mux(struct pl08x_dma_chan *plchan) |
6b16c8b1 RK |
334 | { |
335 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
336 | int ret; | |
337 | ||
d7cabeed MB |
338 | if (plchan->mux_use++ == 0 && pd->get_xfer_signal) { |
339 | ret = pd->get_xfer_signal(plchan->cd); | |
5e2479bd RK |
340 | if (ret < 0) { |
341 | plchan->mux_use = 0; | |
6b16c8b1 | 342 | return ret; |
5e2479bd | 343 | } |
6b16c8b1 | 344 | |
ad0de2ac | 345 | plchan->signal = ret; |
6b16c8b1 RK |
346 | } |
347 | return 0; | |
348 | } | |
349 | ||
350 | static void pl08x_release_mux(struct pl08x_dma_chan *plchan) | |
351 | { | |
352 | const struct pl08x_platform_data *pd = plchan->host->pd; | |
353 | ||
5e2479bd RK |
354 | if (plchan->signal >= 0) { |
355 | WARN_ON(plchan->mux_use == 0); | |
356 | ||
d7cabeed MB |
357 | if (--plchan->mux_use == 0 && pd->put_xfer_signal) { |
358 | pd->put_xfer_signal(plchan->cd, plchan->signal); | |
5e2479bd RK |
359 | plchan->signal = -1; |
360 | } | |
6b16c8b1 RK |
361 | } |
362 | } | |
363 | ||
e8689e63 LW |
364 | /* |
365 | * Physical channel handling | |
366 | */ | |
367 | ||
368 | /* Whether a certain channel is busy or not */ | |
369 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
370 | { | |
371 | unsigned int val; | |
372 | ||
1e1cfc72 LW |
373 | /* If we have a special busy register, take a shortcut */ |
374 | if (ch->reg_busy) { | |
375 | val = readl(ch->reg_busy); | |
376 | return !!(val & BIT(ch->id)); | |
377 | } | |
d86ccea7 | 378 | val = readl(ch->reg_config); |
e8689e63 LW |
379 | return val & PL080_CONFIG_ACTIVE; |
380 | } | |
381 | ||
1e1cfc72 LW |
382 | /* |
383 | * pl08x_write_lli() - Write an LLI into the DMA controller. | |
384 | * | |
385 | * The PL08x derivatives support linked lists, but the first item of the | |
386 | * list containing the source, destination, control word and next LLI is | |
387 | * ignored. Instead the driver has to write those values directly into the | |
388 | * SRC, DST, LLI and control registers. On FTDMAC020 also the SIZE | |
389 | * register need to be set up for the first transfer. | |
390 | */ | |
ba6785ff TF |
391 | static void pl08x_write_lli(struct pl08x_driver_data *pl08x, |
392 | struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg) | |
393 | { | |
da1b6c05 TF |
394 | if (pl08x->vd->pl080s) |
395 | dev_vdbg(&pl08x->adev->dev, | |
396 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
397 | "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n", | |
398 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
399 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], | |
400 | lli[PL080S_LLI_CCTL2], ccfg); | |
401 | else | |
402 | dev_vdbg(&pl08x->adev->dev, | |
403 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
404 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", | |
405 | phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST], | |
406 | lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg); | |
ba6785ff | 407 | |
1e1cfc72 LW |
408 | writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src); |
409 | writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst); | |
410 | writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli); | |
ba6785ff | 411 | |
1e1cfc72 LW |
412 | /* |
413 | * The FTMAC020 has a different layout in the CCTL word of the LLI | |
414 | * and the CCTL register which is split in CSR and SIZE registers. | |
415 | * Convert the LLI item CCTL into the proper values to write into | |
416 | * the CSR and SIZE registers. | |
417 | */ | |
418 | if (phychan->ftdmac020) { | |
419 | u32 llictl = lli[PL080_LLI_CCTL]; | |
420 | u32 val = 0; | |
421 | ||
422 | /* Write the transfer size (12 bits) to the size register */ | |
423 | writel_relaxed(llictl & FTDMAC020_LLI_TRANSFER_SIZE_MASK, | |
424 | phychan->base + FTDMAC020_CH_SIZE); | |
425 | /* | |
426 | * Then write the control bits 28..16 to the control register | |
427 | * by shuffleing the bits around to where they are in the | |
428 | * main register. The mapping is as follows: | |
429 | * Bit 28: TC_MSK - mask on all except last LLI | |
430 | * Bit 27..25: SRC_WIDTH | |
431 | * Bit 24..22: DST_WIDTH | |
432 | * Bit 21..20: SRCAD_CTRL | |
433 | * Bit 19..17: DSTAD_CTRL | |
434 | * Bit 17: SRC_SEL | |
435 | * Bit 16: DST_SEL | |
436 | */ | |
437 | if (llictl & FTDMAC020_LLI_TC_MSK) | |
438 | val |= FTDMAC020_CH_CSR_TC_MSK; | |
439 | val |= ((llictl & FTDMAC020_LLI_SRC_WIDTH_MSK) >> | |
440 | (FTDMAC020_LLI_SRC_WIDTH_SHIFT - | |
441 | FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT)); | |
442 | val |= ((llictl & FTDMAC020_LLI_DST_WIDTH_MSK) >> | |
443 | (FTDMAC020_LLI_DST_WIDTH_SHIFT - | |
444 | FTDMAC020_CH_CSR_DST_WIDTH_SHIFT)); | |
445 | val |= ((llictl & FTDMAC020_LLI_SRCAD_CTL_MSK) >> | |
446 | (FTDMAC020_LLI_SRCAD_CTL_SHIFT - | |
447 | FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT)); | |
448 | val |= ((llictl & FTDMAC020_LLI_DSTAD_CTL_MSK) >> | |
449 | (FTDMAC020_LLI_DSTAD_CTL_SHIFT - | |
450 | FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT)); | |
451 | if (llictl & FTDMAC020_LLI_SRC_SEL) | |
452 | val |= FTDMAC020_CH_CSR_SRC_SEL; | |
453 | if (llictl & FTDMAC020_LLI_DST_SEL) | |
454 | val |= FTDMAC020_CH_CSR_DST_SEL; | |
455 | ||
456 | /* | |
457 | * Set up the bits that exist in the CSR but are not | |
458 | * part the LLI, i.e. only gets written to the control | |
459 | * register right here. | |
460 | * | |
461 | * FIXME: do not just handle memcpy, also handle slave DMA. | |
462 | */ | |
463 | switch (pl08x->pd->memcpy_burst_size) { | |
464 | default: | |
465 | case PL08X_BURST_SZ_1: | |
466 | val |= PL080_BSIZE_1 << | |
467 | FTDMAC020_CH_CSR_SRC_SIZE_SHIFT; | |
468 | break; | |
469 | case PL08X_BURST_SZ_4: | |
470 | val |= PL080_BSIZE_4 << | |
471 | FTDMAC020_CH_CSR_SRC_SIZE_SHIFT; | |
472 | break; | |
473 | case PL08X_BURST_SZ_8: | |
474 | val |= PL080_BSIZE_8 << | |
475 | FTDMAC020_CH_CSR_SRC_SIZE_SHIFT; | |
476 | break; | |
477 | case PL08X_BURST_SZ_16: | |
478 | val |= PL080_BSIZE_16 << | |
479 | FTDMAC020_CH_CSR_SRC_SIZE_SHIFT; | |
480 | break; | |
481 | case PL08X_BURST_SZ_32: | |
482 | val |= PL080_BSIZE_32 << | |
483 | FTDMAC020_CH_CSR_SRC_SIZE_SHIFT; | |
484 | break; | |
485 | case PL08X_BURST_SZ_64: | |
486 | val |= PL080_BSIZE_64 << | |
487 | FTDMAC020_CH_CSR_SRC_SIZE_SHIFT; | |
488 | break; | |
489 | case PL08X_BURST_SZ_128: | |
490 | val |= PL080_BSIZE_128 << | |
491 | FTDMAC020_CH_CSR_SRC_SIZE_SHIFT; | |
492 | break; | |
493 | case PL08X_BURST_SZ_256: | |
494 | val |= PL080_BSIZE_256 << | |
495 | FTDMAC020_CH_CSR_SRC_SIZE_SHIFT; | |
496 | break; | |
497 | } | |
498 | ||
499 | /* Protection flags */ | |
500 | if (pl08x->pd->memcpy_prot_buff) | |
501 | val |= FTDMAC020_CH_CSR_PROT2; | |
502 | if (pl08x->pd->memcpy_prot_cache) | |
503 | val |= FTDMAC020_CH_CSR_PROT3; | |
504 | /* We are the kernel, so we are in privileged mode */ | |
505 | val |= FTDMAC020_CH_CSR_PROT1; | |
506 | ||
507 | writel_relaxed(val, phychan->reg_control); | |
508 | } else { | |
509 | /* Bits are just identical */ | |
510 | writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control); | |
511 | } | |
512 | ||
513 | /* Second control word on the PL080s */ | |
da1b6c05 TF |
514 | if (pl08x->vd->pl080s) |
515 | writel_relaxed(lli[PL080S_LLI_CCTL2], | |
516 | phychan->base + PL080S_CH_CONTROL2); | |
517 | ||
ba6785ff TF |
518 | writel(ccfg, phychan->reg_config); |
519 | } | |
520 | ||
e8689e63 LW |
521 | /* |
522 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 523 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
524 | * been set when the LLIs were constructed. Poke them into the hardware |
525 | * and start the transfer. | |
e8689e63 | 526 | */ |
eab82533 | 527 | static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) |
e8689e63 | 528 | { |
c885bee4 | 529 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 530 | struct pl08x_phy_chan *phychan = plchan->phychan; |
879f127b RK |
531 | struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc); |
532 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
09b3c323 | 533 | u32 val; |
c885bee4 | 534 | |
879f127b | 535 | list_del(&txd->vd.node); |
eab82533 | 536 | |
c885bee4 | 537 | plchan->at = txd; |
e8689e63 | 538 | |
c885bee4 RKAL |
539 | /* Wait for channel inactive */ |
540 | while (pl08x_phy_channel_busy(phychan)) | |
541 | cpu_relax(); | |
e8689e63 | 542 | |
ba6785ff | 543 | pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg); |
c885bee4 RKAL |
544 | |
545 | /* Enable the DMA channel */ | |
546 | /* Do not access config register until channel shows as disabled */ | |
ded091fe | 547 | while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id)) |
19386b32 | 548 | cpu_relax(); |
e8689e63 | 549 | |
c885bee4 | 550 | /* Do not access config register until channel shows as inactive */ |
1e1cfc72 LW |
551 | if (phychan->ftdmac020) { |
552 | val = readl(phychan->reg_config); | |
553 | while (val & FTDMAC020_CH_CFG_BUSY) | |
554 | val = readl(phychan->reg_config); | |
555 | ||
556 | val = readl(phychan->reg_control); | |
557 | while (val & FTDMAC020_CH_CSR_EN) | |
558 | val = readl(phychan->reg_control); | |
559 | ||
560 | writel(val | FTDMAC020_CH_CSR_EN, | |
561 | phychan->reg_control); | |
562 | } else { | |
d86ccea7 | 563 | val = readl(phychan->reg_config); |
1e1cfc72 LW |
564 | while ((val & PL080_CONFIG_ACTIVE) || |
565 | (val & PL080_CONFIG_ENABLE)) | |
566 | val = readl(phychan->reg_config); | |
e8689e63 | 567 | |
1e1cfc72 LW |
568 | writel(val | PL080_CONFIG_ENABLE, phychan->reg_config); |
569 | } | |
e8689e63 LW |
570 | } |
571 | ||
572 | /* | |
81796616 | 573 | * Pause the channel by setting the HALT bit. |
e8689e63 | 574 | * |
81796616 RKAL |
575 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
576 | * the FIFO can only drain if the peripheral is still requesting data. | |
577 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 578 | * |
81796616 RKAL |
579 | * For P->M transfers, disable the peripheral first to stop it filling |
580 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
581 | */ |
582 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
583 | { | |
584 | u32 val; | |
81796616 | 585 | int timeout; |
e8689e63 | 586 | |
1e1cfc72 LW |
587 | if (ch->ftdmac020) { |
588 | /* Use the enable bit on the FTDMAC020 */ | |
589 | val = readl(ch->reg_control); | |
590 | val &= ~FTDMAC020_CH_CSR_EN; | |
591 | writel(val, ch->reg_control); | |
592 | return; | |
593 | } | |
594 | ||
e8689e63 | 595 | /* Set the HALT bit and wait for the FIFO to drain */ |
d86ccea7 | 596 | val = readl(ch->reg_config); |
e8689e63 | 597 | val |= PL080_CONFIG_HALT; |
d86ccea7 | 598 | writel(val, ch->reg_config); |
e8689e63 LW |
599 | |
600 | /* Wait for channel inactive */ | |
81796616 RKAL |
601 | for (timeout = 1000; timeout; timeout--) { |
602 | if (!pl08x_phy_channel_busy(ch)) | |
603 | break; | |
604 | udelay(1); | |
605 | } | |
606 | if (pl08x_phy_channel_busy(ch)) | |
607 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
608 | } |
609 | ||
610 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
611 | { | |
612 | u32 val; | |
613 | ||
1e1cfc72 LW |
614 | /* Use the enable bit on the FTDMAC020 */ |
615 | if (ch->ftdmac020) { | |
616 | val = readl(ch->reg_control); | |
617 | val |= FTDMAC020_CH_CSR_EN; | |
618 | writel(val, ch->reg_control); | |
619 | return; | |
620 | } | |
621 | ||
e8689e63 | 622 | /* Clear the HALT bit */ |
d86ccea7 | 623 | val = readl(ch->reg_config); |
e8689e63 | 624 | val &= ~PL080_CONFIG_HALT; |
d86ccea7 | 625 | writel(val, ch->reg_config); |
e8689e63 LW |
626 | } |
627 | ||
fb526210 RKAL |
628 | /* |
629 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
630 | * clears any pending interrupt status. This should not be used for | |
631 | * an on-going transfer, but as a method of shutting down a channel | |
632 | * (eg, when it's no longer used) or terminating a transfer. | |
633 | */ | |
634 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
635 | struct pl08x_phy_chan *ch) | |
e8689e63 | 636 | { |
1e1cfc72 LW |
637 | u32 val; |
638 | ||
639 | /* The layout for the FTDMAC020 is different */ | |
640 | if (ch->ftdmac020) { | |
641 | /* Disable all interrupts */ | |
642 | val = readl(ch->reg_config); | |
643 | val |= (FTDMAC020_CH_CFG_INT_ABT_MASK | | |
644 | FTDMAC020_CH_CFG_INT_ERR_MASK | | |
645 | FTDMAC020_CH_CFG_INT_TC_MASK); | |
646 | writel(val, ch->reg_config); | |
647 | ||
648 | /* Abort and disable channel */ | |
649 | val = readl(ch->reg_control); | |
650 | val &= ~FTDMAC020_CH_CSR_EN; | |
651 | val |= FTDMAC020_CH_CSR_ABT; | |
652 | writel(val, ch->reg_control); | |
653 | ||
654 | /* Clear ABT and ERR interrupt flags */ | |
655 | writel(BIT(ch->id) | BIT(ch->id + 16), | |
656 | pl08x->base + PL080_ERR_CLEAR); | |
657 | writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR); | |
e8689e63 | 658 | |
1e1cfc72 LW |
659 | return; |
660 | } | |
661 | ||
662 | val = readl(ch->reg_config); | |
fb526210 | 663 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
5835aa86 | 664 | PL080_CONFIG_TC_IRQ_MASK); |
d86ccea7 | 665 | writel(val, ch->reg_config); |
fb526210 | 666 | |
ded091fe LW |
667 | writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR); |
668 | writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
669 | } |
670 | ||
1e1cfc72 | 671 | static u32 get_bytes_in_phy_channel(struct pl08x_phy_chan *ch) |
e8689e63 | 672 | { |
1e1cfc72 LW |
673 | u32 val; |
674 | u32 bytes; | |
675 | ||
676 | if (ch->ftdmac020) { | |
677 | bytes = readl(ch->base + FTDMAC020_CH_SIZE); | |
678 | ||
679 | val = readl(ch->reg_control); | |
680 | val &= FTDMAC020_CH_CSR_SRC_WIDTH_MSK; | |
681 | val >>= FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT; | |
682 | } else if (ch->pl080s) { | |
683 | val = readl(ch->base + PL080S_CH_CONTROL2); | |
684 | bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK; | |
e8689e63 | 685 | |
1e1cfc72 LW |
686 | val = readl(ch->reg_control); |
687 | val &= PL080_CONTROL_SWIDTH_MASK; | |
688 | val >>= PL080_CONTROL_SWIDTH_SHIFT; | |
689 | } else { | |
690 | /* Plain PL08x */ | |
691 | val = readl(ch->reg_control); | |
692 | bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
693 | ||
694 | val &= PL080_CONTROL_SWIDTH_MASK; | |
695 | val >>= PL080_CONTROL_SWIDTH_SHIFT; | |
696 | } | |
f3287a52 | 697 | |
1e1cfc72 | 698 | switch (val) { |
e8689e63 LW |
699 | case PL080_WIDTH_8BIT: |
700 | break; | |
701 | case PL080_WIDTH_16BIT: | |
702 | bytes *= 2; | |
703 | break; | |
704 | case PL080_WIDTH_32BIT: | |
705 | bytes *= 4; | |
706 | break; | |
707 | } | |
708 | return bytes; | |
709 | } | |
710 | ||
1e1cfc72 | 711 | static u32 get_bytes_in_lli(struct pl08x_phy_chan *ch, const u32 *llis_va) |
da1b6c05 | 712 | { |
1e1cfc72 LW |
713 | u32 val; |
714 | u32 bytes; | |
715 | ||
716 | if (ch->ftdmac020) { | |
717 | val = llis_va[PL080_LLI_CCTL]; | |
718 | bytes = val & FTDMAC020_LLI_TRANSFER_SIZE_MASK; | |
719 | ||
720 | val = llis_va[PL080_LLI_CCTL]; | |
721 | val &= FTDMAC020_LLI_SRC_WIDTH_MSK; | |
722 | val >>= FTDMAC020_LLI_SRC_WIDTH_SHIFT; | |
723 | } else if (ch->pl080s) { | |
724 | val = llis_va[PL080S_LLI_CCTL2]; | |
725 | bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK; | |
726 | ||
727 | val = llis_va[PL080_LLI_CCTL]; | |
728 | val &= PL080_CONTROL_SWIDTH_MASK; | |
729 | val >>= PL080_CONTROL_SWIDTH_SHIFT; | |
730 | } else { | |
731 | /* Plain PL08x */ | |
732 | val = llis_va[PL080_LLI_CCTL]; | |
733 | bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
da1b6c05 | 734 | |
1e1cfc72 LW |
735 | val &= PL080_CONTROL_SWIDTH_MASK; |
736 | val >>= PL080_CONTROL_SWIDTH_SHIFT; | |
737 | } | |
f3287a52 | 738 | |
1e1cfc72 | 739 | switch (val) { |
e8689e63 LW |
740 | case PL080_WIDTH_8BIT: |
741 | break; | |
742 | case PL080_WIDTH_16BIT: | |
743 | bytes *= 2; | |
744 | break; | |
745 | case PL080_WIDTH_32BIT: | |
746 | bytes *= 4; | |
747 | break; | |
748 | } | |
749 | return bytes; | |
750 | } | |
751 | ||
752 | /* The channel should be paused when calling this */ | |
753 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
754 | { | |
ba6785ff TF |
755 | struct pl08x_driver_data *pl08x = plchan->host; |
756 | const u32 *llis_va, *llis_va_limit; | |
e8689e63 | 757 | struct pl08x_phy_chan *ch; |
68a7faa2 | 758 | dma_addr_t llis_bus; |
e8689e63 | 759 | struct pl08x_txd *txd; |
ba6785ff | 760 | u32 llis_max_words; |
68a7faa2 | 761 | size_t bytes; |
68a7faa2 | 762 | u32 clli; |
e8689e63 | 763 | |
e8689e63 LW |
764 | ch = plchan->phychan; |
765 | txd = plchan->at; | |
766 | ||
68a7faa2 TF |
767 | if (!ch || !txd) |
768 | return 0; | |
769 | ||
e8689e63 | 770 | /* |
db9f136a RKAL |
771 | * Follow the LLIs to get the number of remaining |
772 | * bytes in the currently active transaction. | |
e8689e63 | 773 | */ |
1e1cfc72 | 774 | clli = readl(ch->reg_lli) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 775 | |
68a7faa2 | 776 | /* First get the remaining bytes in the active transfer */ |
1e1cfc72 | 777 | bytes = get_bytes_in_phy_channel(ch); |
e8689e63 | 778 | |
68a7faa2 TF |
779 | if (!clli) |
780 | return bytes; | |
db9f136a | 781 | |
68a7faa2 TF |
782 | llis_va = txd->llis_va; |
783 | llis_bus = txd->llis_bus; | |
e8689e63 | 784 | |
ba6785ff | 785 | llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS; |
68a7faa2 | 786 | BUG_ON(clli < llis_bus || clli >= llis_bus + |
ba6785ff | 787 | sizeof(u32) * llis_max_words); |
db9f136a | 788 | |
68a7faa2 TF |
789 | /* |
790 | * Locate the next LLI - as this is an array, | |
791 | * it's simple maths to find. | |
792 | */ | |
ba6785ff | 793 | llis_va += (clli - llis_bus) / sizeof(u32); |
e8689e63 | 794 | |
ba6785ff TF |
795 | llis_va_limit = llis_va + llis_max_words; |
796 | ||
797 | for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) { | |
1e1cfc72 | 798 | bytes += get_bytes_in_lli(ch, llis_va); |
68a7faa2 TF |
799 | |
800 | /* | |
3b24c20b | 801 | * A LLI pointer going backward terminates the LLI list |
68a7faa2 | 802 | */ |
3b24c20b | 803 | if (llis_va[PL080_LLI_LLI] <= clli) |
68a7faa2 | 804 | break; |
e8689e63 LW |
805 | } |
806 | ||
e8689e63 LW |
807 | return bytes; |
808 | } | |
809 | ||
810 | /* | |
811 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
812 | * |
813 | * Try to locate a physical channel to be used for this transfer. If all | |
814 | * are taken return NULL and the requester will have to cope by using | |
815 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
816 | */ |
817 | static struct pl08x_phy_chan * | |
818 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
819 | struct pl08x_dma_chan *virt_chan) | |
820 | { | |
821 | struct pl08x_phy_chan *ch = NULL; | |
822 | unsigned long flags; | |
823 | int i; | |
824 | ||
e8689e63 LW |
825 | for (i = 0; i < pl08x->vd->channels; i++) { |
826 | ch = &pl08x->phy_chans[i]; | |
827 | ||
828 | spin_lock_irqsave(&ch->lock, flags); | |
829 | ||
affa115e | 830 | if (!ch->locked && !ch->serving) { |
e8689e63 | 831 | ch->serving = virt_chan; |
e8689e63 LW |
832 | spin_unlock_irqrestore(&ch->lock, flags); |
833 | break; | |
834 | } | |
835 | ||
836 | spin_unlock_irqrestore(&ch->lock, flags); | |
837 | } | |
838 | ||
839 | if (i == pl08x->vd->channels) { | |
840 | /* No physical channel available, cope with it */ | |
841 | return NULL; | |
842 | } | |
843 | ||
844 | return ch; | |
845 | } | |
846 | ||
a5a488db | 847 | /* Mark the physical channel as free. Note, this write is atomic. */ |
e8689e63 LW |
848 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, |
849 | struct pl08x_phy_chan *ch) | |
850 | { | |
a5a488db RK |
851 | ch->serving = NULL; |
852 | } | |
e8689e63 | 853 | |
a5a488db RK |
854 | /* |
855 | * Try to allocate a physical channel. When successful, assign it to | |
856 | * this virtual channel, and initiate the next descriptor. The | |
857 | * virtual channel lock must be held at this point. | |
858 | */ | |
859 | static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) | |
860 | { | |
861 | struct pl08x_driver_data *pl08x = plchan->host; | |
862 | struct pl08x_phy_chan *ch; | |
fb526210 | 863 | |
a5a488db RK |
864 | ch = pl08x_get_phy_channel(pl08x, plchan); |
865 | if (!ch) { | |
866 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
867 | plchan->state = PL08X_CHAN_WAITING; | |
2ff25c1c | 868 | plchan->waiting_at = jiffies; |
a5a488db RK |
869 | return; |
870 | } | |
e8689e63 | 871 | |
a5a488db RK |
872 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n", |
873 | ch->id, plchan->name); | |
874 | ||
875 | plchan->phychan = ch; | |
876 | plchan->state = PL08X_CHAN_RUNNING; | |
877 | pl08x_start_next_txd(plchan); | |
878 | } | |
879 | ||
880 | static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch, | |
881 | struct pl08x_dma_chan *plchan) | |
882 | { | |
883 | struct pl08x_driver_data *pl08x = plchan->host; | |
884 | ||
885 | dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n", | |
886 | ch->id, plchan->name); | |
887 | ||
888 | /* | |
889 | * We do this without taking the lock; we're really only concerned | |
890 | * about whether this pointer is NULL or not, and we're guaranteed | |
891 | * that this will only be called when it _already_ is non-NULL. | |
892 | */ | |
893 | ch->serving = plchan; | |
894 | plchan->phychan = ch; | |
895 | plchan->state = PL08X_CHAN_RUNNING; | |
896 | pl08x_start_next_txd(plchan); | |
897 | } | |
898 | ||
899 | /* | |
900 | * Free a physical DMA channel, potentially reallocating it to another | |
901 | * virtual channel if we have any pending. | |
902 | */ | |
903 | static void pl08x_phy_free(struct pl08x_dma_chan *plchan) | |
904 | { | |
905 | struct pl08x_driver_data *pl08x = plchan->host; | |
906 | struct pl08x_dma_chan *p, *next; | |
2ff25c1c | 907 | unsigned long waiting_at; |
a5a488db RK |
908 | retry: |
909 | next = NULL; | |
2ff25c1c | 910 | waiting_at = jiffies; |
a5a488db | 911 | |
2ff25c1c JNG |
912 | /* |
913 | * Find a waiting virtual channel for the next transfer. | |
914 | * To be fair, time when each channel reached waiting state is compared | |
915 | * to select channel that is waiting for the longest time. | |
916 | */ | |
01d8dc64 | 917 | list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node) |
2ff25c1c JNG |
918 | if (p->state == PL08X_CHAN_WAITING && |
919 | p->waiting_at <= waiting_at) { | |
a5a488db | 920 | next = p; |
2ff25c1c | 921 | waiting_at = p->waiting_at; |
a5a488db RK |
922 | } |
923 | ||
ebe9b300 | 924 | if (!next && pl08x->has_slave) { |
01d8dc64 | 925 | list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node) |
2ff25c1c JNG |
926 | if (p->state == PL08X_CHAN_WAITING && |
927 | p->waiting_at <= waiting_at) { | |
a5a488db | 928 | next = p; |
2ff25c1c | 929 | waiting_at = p->waiting_at; |
a5a488db RK |
930 | } |
931 | } | |
932 | ||
933 | /* Ensure that the physical channel is stopped */ | |
934 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); | |
935 | ||
936 | if (next) { | |
937 | bool success; | |
938 | ||
939 | /* | |
940 | * Eww. We know this isn't going to deadlock | |
941 | * but lockdep probably doesn't. | |
942 | */ | |
083be28a | 943 | spin_lock(&next->vc.lock); |
a5a488db RK |
944 | /* Re-check the state now that we have the lock */ |
945 | success = next->state == PL08X_CHAN_WAITING; | |
946 | if (success) | |
947 | pl08x_phy_reassign_start(plchan->phychan, next); | |
083be28a | 948 | spin_unlock(&next->vc.lock); |
a5a488db RK |
949 | |
950 | /* If the state changed, try to find another channel */ | |
951 | if (!success) | |
952 | goto retry; | |
953 | } else { | |
954 | /* No more jobs, so free up the physical channel */ | |
955 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
956 | } | |
957 | ||
958 | plchan->phychan = NULL; | |
959 | plchan->state = PL08X_CHAN_IDLE; | |
e8689e63 LW |
960 | } |
961 | ||
962 | /* | |
963 | * LLI handling | |
964 | */ | |
965 | ||
1e1cfc72 LW |
966 | static inline unsigned int |
967 | pl08x_get_bytes_for_lli(struct pl08x_driver_data *pl08x, | |
968 | u32 cctl, | |
969 | bool source) | |
e8689e63 | 970 | { |
1e1cfc72 LW |
971 | u32 val; |
972 | ||
973 | if (pl08x->vd->ftdmac020) { | |
974 | if (source) | |
975 | val = (cctl & FTDMAC020_LLI_SRC_WIDTH_MSK) >> | |
976 | FTDMAC020_LLI_SRC_WIDTH_SHIFT; | |
977 | else | |
978 | val = (cctl & FTDMAC020_LLI_DST_WIDTH_MSK) >> | |
979 | FTDMAC020_LLI_DST_WIDTH_SHIFT; | |
980 | } else { | |
981 | if (source) | |
982 | val = (cctl & PL080_CONTROL_SWIDTH_MASK) >> | |
983 | PL080_CONTROL_SWIDTH_SHIFT; | |
984 | else | |
985 | val = (cctl & PL080_CONTROL_DWIDTH_MASK) >> | |
986 | PL080_CONTROL_DWIDTH_SHIFT; | |
987 | } | |
988 | ||
989 | switch (val) { | |
e8689e63 LW |
990 | case PL080_WIDTH_8BIT: |
991 | return 1; | |
992 | case PL080_WIDTH_16BIT: | |
993 | return 2; | |
994 | case PL080_WIDTH_32BIT: | |
995 | return 4; | |
996 | default: | |
997 | break; | |
998 | } | |
999 | BUG(); | |
1000 | return 0; | |
1001 | } | |
1002 | ||
1e1cfc72 LW |
1003 | static inline u32 pl08x_lli_control_bits(struct pl08x_driver_data *pl08x, |
1004 | u32 cctl, | |
1005 | u8 srcwidth, u8 dstwidth, | |
1006 | size_t tsize) | |
e8689e63 LW |
1007 | { |
1008 | u32 retbits = cctl; | |
1009 | ||
1e1cfc72 LW |
1010 | /* |
1011 | * Remove all src, dst and transfer size bits, then set the | |
1012 | * width and size according to the parameters. The bit offsets | |
1013 | * are different in the FTDMAC020 so we need to accound for this. | |
1014 | */ | |
1015 | if (pl08x->vd->ftdmac020) { | |
1016 | retbits &= ~FTDMAC020_LLI_DST_WIDTH_MSK; | |
1017 | retbits &= ~FTDMAC020_LLI_SRC_WIDTH_MSK; | |
1018 | retbits &= ~FTDMAC020_LLI_TRANSFER_SIZE_MASK; | |
1019 | ||
1020 | switch (srcwidth) { | |
1021 | case 1: | |
1022 | retbits |= PL080_WIDTH_8BIT << | |
1023 | FTDMAC020_LLI_SRC_WIDTH_SHIFT; | |
1024 | break; | |
1025 | case 2: | |
1026 | retbits |= PL080_WIDTH_16BIT << | |
1027 | FTDMAC020_LLI_SRC_WIDTH_SHIFT; | |
1028 | break; | |
1029 | case 4: | |
1030 | retbits |= PL080_WIDTH_32BIT << | |
1031 | FTDMAC020_LLI_SRC_WIDTH_SHIFT; | |
1032 | break; | |
1033 | default: | |
1034 | BUG(); | |
1035 | break; | |
1036 | } | |
e8689e63 | 1037 | |
1e1cfc72 LW |
1038 | switch (dstwidth) { |
1039 | case 1: | |
1040 | retbits |= PL080_WIDTH_8BIT << | |
1041 | FTDMAC020_LLI_DST_WIDTH_SHIFT; | |
1042 | break; | |
1043 | case 2: | |
1044 | retbits |= PL080_WIDTH_16BIT << | |
1045 | FTDMAC020_LLI_DST_WIDTH_SHIFT; | |
1046 | break; | |
1047 | case 4: | |
1048 | retbits |= PL080_WIDTH_32BIT << | |
1049 | FTDMAC020_LLI_DST_WIDTH_SHIFT; | |
1050 | break; | |
1051 | default: | |
1052 | BUG(); | |
1053 | break; | |
1054 | } | |
e8689e63 | 1055 | |
1e1cfc72 LW |
1056 | tsize &= FTDMAC020_LLI_TRANSFER_SIZE_MASK; |
1057 | retbits |= tsize << FTDMAC020_LLI_TRANSFER_SIZE_SHIFT; | |
1058 | } else { | |
1059 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; | |
1060 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
1061 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
1062 | ||
1063 | switch (srcwidth) { | |
1064 | case 1: | |
1065 | retbits |= PL080_WIDTH_8BIT << | |
1066 | PL080_CONTROL_SWIDTH_SHIFT; | |
1067 | break; | |
1068 | case 2: | |
1069 | retbits |= PL080_WIDTH_16BIT << | |
1070 | PL080_CONTROL_SWIDTH_SHIFT; | |
1071 | break; | |
1072 | case 4: | |
1073 | retbits |= PL080_WIDTH_32BIT << | |
1074 | PL080_CONTROL_SWIDTH_SHIFT; | |
1075 | break; | |
1076 | default: | |
1077 | BUG(); | |
1078 | break; | |
1079 | } | |
1080 | ||
1081 | switch (dstwidth) { | |
1082 | case 1: | |
1083 | retbits |= PL080_WIDTH_8BIT << | |
1084 | PL080_CONTROL_DWIDTH_SHIFT; | |
1085 | break; | |
1086 | case 2: | |
1087 | retbits |= PL080_WIDTH_16BIT << | |
1088 | PL080_CONTROL_DWIDTH_SHIFT; | |
1089 | break; | |
1090 | case 4: | |
1091 | retbits |= PL080_WIDTH_32BIT << | |
1092 | PL080_CONTROL_DWIDTH_SHIFT; | |
1093 | break; | |
1094 | default: | |
1095 | BUG(); | |
1096 | break; | |
1097 | } | |
1098 | ||
1099 | tsize &= PL080_CONTROL_TRANSFER_SIZE_MASK; | |
1100 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
e8689e63 LW |
1101 | } |
1102 | ||
e8689e63 LW |
1103 | return retbits; |
1104 | } | |
1105 | ||
542361f8 RKAL |
1106 | struct pl08x_lli_build_data { |
1107 | struct pl08x_txd *txd; | |
542361f8 RKAL |
1108 | struct pl08x_bus_data srcbus; |
1109 | struct pl08x_bus_data dstbus; | |
1110 | size_t remainder; | |
25c94f7f | 1111 | u32 lli_bus; |
542361f8 RKAL |
1112 | }; |
1113 | ||
e8689e63 | 1114 | /* |
0532e6fc VK |
1115 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
1116 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
1117 | * masters address with width requirements of transfer (by sending few byte by | |
1118 | * byte data), slave is still not aligned, then its width will be reduced to | |
1119 | * BYTE. | |
1120 | * - prefers the destination bus if both available | |
036f05fd | 1121 | * - prefers bus with fixed address (i.e. peripheral) |
e8689e63 | 1122 | */ |
1e1cfc72 LW |
1123 | static void pl08x_choose_master_bus(struct pl08x_driver_data *pl08x, |
1124 | struct pl08x_lli_build_data *bd, | |
1125 | struct pl08x_bus_data **mbus, | |
1126 | struct pl08x_bus_data **sbus, | |
1127 | u32 cctl) | |
e8689e63 | 1128 | { |
1e1cfc72 LW |
1129 | bool dst_incr; |
1130 | bool src_incr; | |
1131 | ||
1132 | /* | |
1133 | * The FTDMAC020 only supports memory-to-memory transfer, so | |
1134 | * source and destination always increase. | |
1135 | */ | |
1136 | if (pl08x->vd->ftdmac020) { | |
1137 | dst_incr = true; | |
1138 | src_incr = true; | |
1139 | } else { | |
1140 | dst_incr = !!(cctl & PL080_CONTROL_DST_INCR); | |
1141 | src_incr = !!(cctl & PL080_CONTROL_SRC_INCR); | |
1142 | } | |
1143 | ||
1144 | /* | |
1145 | * If either bus is not advancing, i.e. it is a peripheral, that | |
1146 | * one becomes master | |
1147 | */ | |
1148 | if (!dst_incr) { | |
542361f8 RKAL |
1149 | *mbus = &bd->dstbus; |
1150 | *sbus = &bd->srcbus; | |
1e1cfc72 | 1151 | } else if (!src_incr) { |
036f05fd VK |
1152 | *mbus = &bd->srcbus; |
1153 | *sbus = &bd->dstbus; | |
e8689e63 | 1154 | } else { |
036f05fd | 1155 | if (bd->dstbus.buswidth >= bd->srcbus.buswidth) { |
542361f8 RKAL |
1156 | *mbus = &bd->dstbus; |
1157 | *sbus = &bd->srcbus; | |
036f05fd | 1158 | } else { |
542361f8 RKAL |
1159 | *mbus = &bd->srcbus; |
1160 | *sbus = &bd->dstbus; | |
e8689e63 LW |
1161 | } |
1162 | } | |
1163 | } | |
1164 | ||
1165 | /* | |
94ae8522 | 1166 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 1167 | */ |
ba6785ff TF |
1168 | static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x, |
1169 | struct pl08x_lli_build_data *bd, | |
da1b6c05 | 1170 | int num_llis, int len, u32 cctl, u32 cctl2) |
e8689e63 | 1171 | { |
ba6785ff TF |
1172 | u32 offset = num_llis * pl08x->lli_words; |
1173 | u32 *llis_va = bd->txd->llis_va + offset; | |
542361f8 | 1174 | dma_addr_t llis_bus = bd->txd->llis_bus; |
e8689e63 LW |
1175 | |
1176 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
1177 | ||
ba6785ff TF |
1178 | /* Advance the offset to next LLI. */ |
1179 | offset += pl08x->lli_words; | |
1180 | ||
1181 | llis_va[PL080_LLI_SRC] = bd->srcbus.addr; | |
1182 | llis_va[PL080_LLI_DST] = bd->dstbus.addr; | |
1183 | llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset); | |
1184 | llis_va[PL080_LLI_LLI] |= bd->lli_bus; | |
1185 | llis_va[PL080_LLI_CCTL] = cctl; | |
da1b6c05 TF |
1186 | if (pl08x->vd->pl080s) |
1187 | llis_va[PL080S_LLI_CCTL2] = cctl2; | |
e8689e63 | 1188 | |
1e1cfc72 LW |
1189 | if (pl08x->vd->ftdmac020) { |
1190 | /* FIXME: only memcpy so far so both increase */ | |
542361f8 | 1191 | bd->srcbus.addr += len; |
542361f8 | 1192 | bd->dstbus.addr += len; |
1e1cfc72 LW |
1193 | } else { |
1194 | if (cctl & PL080_CONTROL_SRC_INCR) | |
1195 | bd->srcbus.addr += len; | |
1196 | if (cctl & PL080_CONTROL_DST_INCR) | |
1197 | bd->dstbus.addr += len; | |
1198 | } | |
e8689e63 | 1199 | |
542361f8 | 1200 | BUG_ON(bd->remainder < len); |
cace6585 | 1201 | |
542361f8 | 1202 | bd->remainder -= len; |
e8689e63 LW |
1203 | } |
1204 | ||
ba6785ff TF |
1205 | static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x, |
1206 | struct pl08x_lli_build_data *bd, u32 *cctl, u32 len, | |
1207 | int num_llis, size_t *total_bytes) | |
e8689e63 | 1208 | { |
1e1cfc72 | 1209 | *cctl = pl08x_lli_control_bits(pl08x, *cctl, 1, 1, len); |
da1b6c05 | 1210 | pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len); |
03af500f | 1211 | (*total_bytes) += len; |
e8689e63 LW |
1212 | } |
1213 | ||
1e1cfc72 | 1214 | #if 1 |
48924e42 TF |
1215 | static void pl08x_dump_lli(struct pl08x_driver_data *pl08x, |
1216 | const u32 *llis_va, int num_llis) | |
1217 | { | |
1218 | int i; | |
1219 | ||
da1b6c05 | 1220 | if (pl08x->vd->pl080s) { |
48924e42 | 1221 | dev_vdbg(&pl08x->adev->dev, |
da1b6c05 TF |
1222 | "%-3s %-9s %-10s %-10s %-10s %-10s %s\n", |
1223 | "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2"); | |
1224 | for (i = 0; i < num_llis; i++) { | |
1225 | dev_vdbg(&pl08x->adev->dev, | |
1226 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1227 | i, llis_va, llis_va[PL080_LLI_SRC], | |
1228 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
1229 | llis_va[PL080_LLI_CCTL], | |
1230 | llis_va[PL080S_LLI_CCTL2]); | |
1231 | llis_va += pl08x->lli_words; | |
1232 | } | |
1233 | } else { | |
1234 | dev_vdbg(&pl08x->adev->dev, | |
1235 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
1236 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
1237 | for (i = 0; i < num_llis; i++) { | |
1238 | dev_vdbg(&pl08x->adev->dev, | |
1239 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1240 | i, llis_va, llis_va[PL080_LLI_SRC], | |
1241 | llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI], | |
1242 | llis_va[PL080_LLI_CCTL]); | |
1243 | llis_va += pl08x->lli_words; | |
1244 | } | |
48924e42 TF |
1245 | } |
1246 | } | |
1247 | #else | |
1248 | static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x, | |
1249 | const u32 *llis_va, int num_llis) {} | |
1250 | #endif | |
1251 | ||
e8689e63 LW |
1252 | /* |
1253 | * This fills in the table of LLIs for the transfer descriptor | |
1254 | * Note that we assume we never have to change the burst sizes | |
1255 | * Return 0 for error | |
1256 | */ | |
1257 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
1258 | struct pl08x_txd *txd) | |
1259 | { | |
e8689e63 | 1260 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 1261 | struct pl08x_lli_build_data bd; |
e8689e63 | 1262 | int num_llis = 0; |
03af500f | 1263 | u32 cctl, early_bytes = 0; |
b7f69d9d | 1264 | size_t max_bytes_per_lli, total_bytes; |
ba6785ff | 1265 | u32 *llis_va, *last_lli; |
b7f69d9d | 1266 | struct pl08x_sg *dsg; |
e8689e63 | 1267 | |
3e27ee84 | 1268 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
1269 | if (!txd->llis_va) { |
1270 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
1271 | return 0; | |
1272 | } | |
1273 | ||
542361f8 | 1274 | bd.txd = txd; |
25c94f7f | 1275 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
b7f69d9d | 1276 | cctl = txd->cctl; |
542361f8 | 1277 | |
e8689e63 | 1278 | /* Find maximum width of the source bus */ |
1e1cfc72 | 1279 | bd.srcbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, true); |
e8689e63 LW |
1280 | |
1281 | /* Find maximum width of the destination bus */ | |
1e1cfc72 | 1282 | bd.dstbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, false); |
e8689e63 | 1283 | |
b7f69d9d VK |
1284 | list_for_each_entry(dsg, &txd->dsg_list, node) { |
1285 | total_bytes = 0; | |
1286 | cctl = txd->cctl; | |
e8689e63 | 1287 | |
b7f69d9d VK |
1288 | bd.srcbus.addr = dsg->src_addr; |
1289 | bd.dstbus.addr = dsg->dst_addr; | |
1290 | bd.remainder = dsg->len; | |
1291 | bd.srcbus.buswidth = bd.srcbus.maxwidth; | |
1292 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 | 1293 | |
1e1cfc72 | 1294 | pl08x_choose_master_bus(pl08x, &bd, &mbus, &sbus, cctl); |
e8689e63 | 1295 | |
b90ca063 AP |
1296 | dev_vdbg(&pl08x->adev->dev, |
1297 | "src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n", | |
1298 | (u64)bd.srcbus.addr, | |
1299 | cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
b7f69d9d | 1300 | bd.srcbus.buswidth, |
b90ca063 AP |
1301 | (u64)bd.dstbus.addr, |
1302 | cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
b7f69d9d VK |
1303 | bd.dstbus.buswidth, |
1304 | bd.remainder); | |
1305 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
1306 | mbus == &bd.srcbus ? "src" : "dst", | |
1307 | sbus == &bd.srcbus ? "src" : "dst"); | |
fc74eb79 | 1308 | |
b7f69d9d VK |
1309 | /* |
1310 | * Zero length is only allowed if all these requirements are | |
1311 | * met: | |
1312 | * - flow controller is peripheral. | |
1313 | * - src.addr is aligned to src.width | |
1314 | * - dst.addr is aligned to dst.width | |
1315 | * | |
1316 | * sg_len == 1 should be true, as there can be two cases here: | |
1317 | * | |
1318 | * - Memory addresses are contiguous and are not scattered. | |
1319 | * Here, Only one sg will be passed by user driver, with | |
1320 | * memory address and zero length. We pass this to controller | |
1321 | * and after the transfer it will receive the last burst | |
1322 | * request from peripheral and so transfer finishes. | |
1323 | * | |
1324 | * - Memory addresses are scattered and are not contiguous. | |
1325 | * Here, Obviously as DMA controller doesn't know when a lli's | |
1326 | * transfer gets over, it can't load next lli. So in this | |
1327 | * case, there has to be an assumption that only one lli is | |
1328 | * supported. Thus, we can't have scattered addresses. | |
1329 | */ | |
1330 | if (!bd.remainder) { | |
1e1cfc72 LW |
1331 | u32 fc; |
1332 | ||
1333 | /* FTDMAC020 only does memory-to-memory */ | |
1334 | if (pl08x->vd->ftdmac020) | |
1335 | fc = PL080_FLOW_MEM2MEM; | |
1336 | else | |
1337 | fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> | |
1338 | PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
b7f69d9d | 1339 | if (!((fc >= PL080_FLOW_SRC2DST_DST) && |
0a235657 | 1340 | (fc <= PL080_FLOW_SRC2DST_SRC))) { |
b7f69d9d VK |
1341 | dev_err(&pl08x->adev->dev, "%s sg len can't be zero", |
1342 | __func__); | |
1343 | return 0; | |
1344 | } | |
0a235657 | 1345 | |
1c38b289 AP |
1346 | if (!IS_BUS_ALIGNED(&bd.srcbus) || |
1347 | !IS_BUS_ALIGNED(&bd.dstbus)) { | |
b7f69d9d VK |
1348 | dev_err(&pl08x->adev->dev, |
1349 | "%s src & dst address must be aligned to src" | |
1350 | " & dst width if peripheral is flow controller", | |
1351 | __func__); | |
1352 | return 0; | |
1353 | } | |
03af500f | 1354 | |
1e1cfc72 LW |
1355 | cctl = pl08x_lli_control_bits(pl08x, cctl, |
1356 | bd.srcbus.buswidth, bd.dstbus.buswidth, | |
1357 | 0); | |
ba6785ff | 1358 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
da1b6c05 | 1359 | 0, cctl, 0); |
b7f69d9d VK |
1360 | break; |
1361 | } | |
e8689e63 LW |
1362 | |
1363 | /* | |
b7f69d9d VK |
1364 | * Send byte by byte for following cases |
1365 | * - Less than a bus width available | |
1366 | * - until master bus is aligned | |
e8689e63 | 1367 | */ |
b7f69d9d VK |
1368 | if (bd.remainder < mbus->buswidth) |
1369 | early_bytes = bd.remainder; | |
1c38b289 AP |
1370 | else if (!IS_BUS_ALIGNED(mbus)) { |
1371 | early_bytes = mbus->buswidth - | |
1372 | (mbus->addr & (mbus->buswidth - 1)); | |
b7f69d9d VK |
1373 | if ((bd.remainder - early_bytes) < mbus->buswidth) |
1374 | early_bytes = bd.remainder; | |
1375 | } | |
e8689e63 | 1376 | |
b7f69d9d VK |
1377 | if (early_bytes) { |
1378 | dev_vdbg(&pl08x->adev->dev, | |
6fc8ae78 | 1379 | "%s byte width LLIs (remain 0x%08zx)\n", |
b7f69d9d | 1380 | __func__, bd.remainder); |
ba6785ff TF |
1381 | prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, |
1382 | num_llis++, &total_bytes); | |
e8689e63 LW |
1383 | } |
1384 | ||
b7f69d9d VK |
1385 | if (bd.remainder) { |
1386 | /* | |
1387 | * Master now aligned | |
1388 | * - if slave is not then we must set its width down | |
1389 | */ | |
1c38b289 | 1390 | if (!IS_BUS_ALIGNED(sbus)) { |
b7f69d9d VK |
1391 | dev_dbg(&pl08x->adev->dev, |
1392 | "%s set down bus width to one byte\n", | |
1393 | __func__); | |
fa6a940b | 1394 | |
b7f69d9d VK |
1395 | sbus->buswidth = 1; |
1396 | } | |
e8689e63 LW |
1397 | |
1398 | /* | |
b7f69d9d VK |
1399 | * Bytes transferred = tsize * src width, not |
1400 | * MIN(buswidths) | |
e8689e63 | 1401 | */ |
b7f69d9d | 1402 | max_bytes_per_lli = bd.srcbus.buswidth * |
5110e51d | 1403 | pl08x->vd->max_transfer_size; |
b7f69d9d VK |
1404 | dev_vdbg(&pl08x->adev->dev, |
1405 | "%s max bytes per lli = %zu\n", | |
1406 | __func__, max_bytes_per_lli); | |
e8689e63 LW |
1407 | |
1408 | /* | |
b7f69d9d VK |
1409 | * Make largest possible LLIs until less than one bus |
1410 | * width left | |
e8689e63 | 1411 | */ |
b7f69d9d VK |
1412 | while (bd.remainder > (mbus->buswidth - 1)) { |
1413 | size_t lli_len, tsize, width; | |
e8689e63 | 1414 | |
b7f69d9d VK |
1415 | /* |
1416 | * If enough left try to send max possible, | |
1417 | * otherwise try to send the remainder | |
1418 | */ | |
1419 | lli_len = min(bd.remainder, max_bytes_per_lli); | |
16a2e7d3 | 1420 | |
b7f69d9d VK |
1421 | /* |
1422 | * Check against maximum bus alignment: | |
1423 | * Calculate actual transfer size in relation to | |
1424 | * bus width an get a maximum remainder of the | |
1425 | * highest bus width - 1 | |
1426 | */ | |
1427 | width = max(mbus->buswidth, sbus->buswidth); | |
1428 | lli_len = (lli_len / width) * width; | |
1429 | tsize = lli_len / bd.srcbus.buswidth; | |
1430 | ||
1431 | dev_vdbg(&pl08x->adev->dev, | |
1432 | "%s fill lli with single lli chunk of " | |
1433 | "size 0x%08zx (remainder 0x%08zx)\n", | |
1434 | __func__, lli_len, bd.remainder); | |
1435 | ||
1e1cfc72 LW |
1436 | cctl = pl08x_lli_control_bits(pl08x, cctl, |
1437 | bd.srcbus.buswidth, bd.dstbus.buswidth, | |
1438 | tsize); | |
ba6785ff | 1439 | pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++, |
da1b6c05 | 1440 | lli_len, cctl, tsize); |
b7f69d9d VK |
1441 | total_bytes += lli_len; |
1442 | } | |
e8689e63 | 1443 | |
b7f69d9d VK |
1444 | /* |
1445 | * Send any odd bytes | |
1446 | */ | |
1447 | if (bd.remainder) { | |
1448 | dev_vdbg(&pl08x->adev->dev, | |
1449 | "%s align with boundary, send odd bytes (remain %zu)\n", | |
1450 | __func__, bd.remainder); | |
ba6785ff TF |
1451 | prep_byte_width_lli(pl08x, &bd, &cctl, |
1452 | bd.remainder, num_llis++, &total_bytes); | |
b7f69d9d | 1453 | } |
e8689e63 | 1454 | } |
16a2e7d3 | 1455 | |
b7f69d9d VK |
1456 | if (total_bytes != dsg->len) { |
1457 | dev_err(&pl08x->adev->dev, | |
1458 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", | |
1459 | __func__, total_bytes, dsg->len); | |
1460 | return 0; | |
1461 | } | |
e8689e63 | 1462 | |
b7f69d9d VK |
1463 | if (num_llis >= MAX_NUM_TSFR_LLIS) { |
1464 | dev_err(&pl08x->adev->dev, | |
1465 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
ba6785ff | 1466 | __func__, MAX_NUM_TSFR_LLIS); |
b7f69d9d VK |
1467 | return 0; |
1468 | } | |
e8689e63 | 1469 | } |
b58b6b5b RKAL |
1470 | |
1471 | llis_va = txd->llis_va; | |
ba6785ff | 1472 | last_lli = llis_va + (num_llis - 1) * pl08x->lli_words; |
e8689e63 | 1473 | |
3b24c20b AB |
1474 | if (txd->cyclic) { |
1475 | /* Link back to the first LLI. */ | |
1476 | last_lli[PL080_LLI_LLI] = txd->llis_bus | bd.lli_bus; | |
1477 | } else { | |
1478 | /* The final LLI terminates the LLI. */ | |
1479 | last_lli[PL080_LLI_LLI] = 0; | |
1480 | /* The final LLI element shall also fire an interrupt. */ | |
1e1cfc72 LW |
1481 | if (pl08x->vd->ftdmac020) |
1482 | last_lli[PL080_LLI_CCTL] &= ~FTDMAC020_LLI_TC_MSK; | |
1483 | else | |
1484 | last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN; | |
e8689e63 | 1485 | } |
e8689e63 | 1486 | |
48924e42 | 1487 | pl08x_dump_lli(pl08x, llis_va, num_llis); |
e8689e63 LW |
1488 | |
1489 | return num_llis; | |
1490 | } | |
1491 | ||
e8689e63 LW |
1492 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, |
1493 | struct pl08x_txd *txd) | |
1494 | { | |
b7f69d9d VK |
1495 | struct pl08x_sg *dsg, *_dsg; |
1496 | ||
c1205646 VK |
1497 | if (txd->llis_va) |
1498 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); | |
e8689e63 | 1499 | |
b7f69d9d VK |
1500 | list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) { |
1501 | list_del(&dsg->node); | |
1502 | kfree(dsg); | |
1503 | } | |
1504 | ||
e8689e63 LW |
1505 | kfree(txd); |
1506 | } | |
1507 | ||
18536134 RK |
1508 | static void pl08x_desc_free(struct virt_dma_desc *vd) |
1509 | { | |
1510 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1511 | struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan); | |
18536134 | 1512 | |
89116bf9 | 1513 | dma_descriptor_unmap(&vd->tx); |
18536134 RK |
1514 | if (!txd->done) |
1515 | pl08x_release_mux(plchan); | |
1516 | ||
18536134 | 1517 | pl08x_free_txd(plchan->host, txd); |
18536134 RK |
1518 | } |
1519 | ||
e8689e63 LW |
1520 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, |
1521 | struct pl08x_dma_chan *plchan) | |
1522 | { | |
ea160561 | 1523 | LIST_HEAD(head); |
e8689e63 | 1524 | |
879f127b | 1525 | vchan_get_all_descriptors(&plchan->vc, &head); |
91998261 | 1526 | vchan_dma_desc_free_list(&plchan->vc, &head); |
e8689e63 LW |
1527 | } |
1528 | ||
1529 | /* | |
1530 | * The DMA ENGINE API | |
1531 | */ | |
e8689e63 LW |
1532 | static void pl08x_free_chan_resources(struct dma_chan *chan) |
1533 | { | |
a068682c RK |
1534 | /* Ensure all queued descriptors are freed */ |
1535 | vchan_free_chan_resources(to_virt_chan(chan)); | |
e8689e63 LW |
1536 | } |
1537 | ||
e8689e63 LW |
1538 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( |
1539 | struct dma_chan *chan, unsigned long flags) | |
1540 | { | |
1541 | struct dma_async_tx_descriptor *retval = NULL; | |
1542 | ||
1543 | return retval; | |
1544 | } | |
1545 | ||
1546 | /* | |
94ae8522 RKAL |
1547 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1548 | * If slaves are relying on interrupts to signal completion this function | |
1549 | * must not be called with interrupts disabled. | |
e8689e63 | 1550 | */ |
3e27ee84 VK |
1551 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1552 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1553 | { |
1554 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
06e885b7 RK |
1555 | struct virt_dma_desc *vd; |
1556 | unsigned long flags; | |
e8689e63 | 1557 | enum dma_status ret; |
06e885b7 | 1558 | size_t bytes = 0; |
e8689e63 | 1559 | |
96a2af41 | 1560 | ret = dma_cookie_status(chan, cookie, txstate); |
0996e895 | 1561 | if (ret == DMA_COMPLETE) |
e8689e63 | 1562 | return ret; |
e8689e63 | 1563 | |
06e885b7 RK |
1564 | /* |
1565 | * There's no point calculating the residue if there's | |
1566 | * no txstate to store the value. | |
1567 | */ | |
1568 | if (!txstate) { | |
1569 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1570 | ret = DMA_PAUSED; | |
1571 | return ret; | |
1572 | } | |
1573 | ||
1574 | spin_lock_irqsave(&plchan->vc.lock, flags); | |
1575 | ret = dma_cookie_status(chan, cookie, txstate); | |
0996e895 | 1576 | if (ret != DMA_COMPLETE) { |
06e885b7 RK |
1577 | vd = vchan_find_desc(&plchan->vc, cookie); |
1578 | if (vd) { | |
1579 | /* On the issued list, so hasn't been processed yet */ | |
1580 | struct pl08x_txd *txd = to_pl08x_txd(&vd->tx); | |
1581 | struct pl08x_sg *dsg; | |
1582 | ||
1583 | list_for_each_entry(dsg, &txd->dsg_list, node) | |
1584 | bytes += dsg->len; | |
1585 | } else { | |
1586 | bytes = pl08x_getbytes_chan(plchan); | |
1587 | } | |
1588 | } | |
1589 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
1590 | ||
e8689e63 LW |
1591 | /* |
1592 | * This cookie not complete yet | |
96a2af41 | 1593 | * Get number of bytes left in the active transactions and queue |
e8689e63 | 1594 | */ |
06e885b7 | 1595 | dma_set_residue(txstate, bytes); |
e8689e63 | 1596 | |
06e885b7 RK |
1597 | if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS) |
1598 | ret = DMA_PAUSED; | |
e8689e63 LW |
1599 | |
1600 | /* Whether waiting or running, we're in progress */ | |
06e885b7 | 1601 | return ret; |
e8689e63 LW |
1602 | } |
1603 | ||
1604 | /* PrimeCell DMA extension */ | |
1605 | struct burst_table { | |
760596c6 | 1606 | u32 burstwords; |
e8689e63 LW |
1607 | u32 reg; |
1608 | }; | |
1609 | ||
1610 | static const struct burst_table burst_sizes[] = { | |
1611 | { | |
1612 | .burstwords = 256, | |
760596c6 | 1613 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1614 | }, |
1615 | { | |
1616 | .burstwords = 128, | |
760596c6 | 1617 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1618 | }, |
1619 | { | |
1620 | .burstwords = 64, | |
760596c6 | 1621 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1622 | }, |
1623 | { | |
1624 | .burstwords = 32, | |
760596c6 | 1625 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1626 | }, |
1627 | { | |
1628 | .burstwords = 16, | |
760596c6 | 1629 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1630 | }, |
1631 | { | |
1632 | .burstwords = 8, | |
760596c6 | 1633 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1634 | }, |
1635 | { | |
1636 | .burstwords = 4, | |
760596c6 | 1637 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1638 | }, |
1639 | { | |
760596c6 RKAL |
1640 | .burstwords = 0, |
1641 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1642 | }, |
1643 | }; | |
1644 | ||
121c8476 RKAL |
1645 | /* |
1646 | * Given the source and destination available bus masks, select which | |
1647 | * will be routed to each port. We try to have source and destination | |
1648 | * on separate ports, but always respect the allowable settings. | |
1649 | */ | |
1e1cfc72 | 1650 | static u32 pl08x_select_bus(bool ftdmac020, u8 src, u8 dst) |
121c8476 RKAL |
1651 | { |
1652 | u32 cctl = 0; | |
1e1cfc72 LW |
1653 | u32 dst_ahb2; |
1654 | u32 src_ahb2; | |
1655 | ||
1656 | /* The FTDMAC020 use different bits to indicate src/dst bus */ | |
1657 | if (ftdmac020) { | |
1658 | dst_ahb2 = FTDMAC020_LLI_DST_SEL; | |
1659 | src_ahb2 = FTDMAC020_LLI_SRC_SEL; | |
1660 | } else { | |
1661 | dst_ahb2 = PL080_CONTROL_DST_AHB2; | |
1662 | src_ahb2 = PL080_CONTROL_SRC_AHB2; | |
1663 | } | |
121c8476 RKAL |
1664 | |
1665 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1e1cfc72 | 1666 | cctl |= dst_ahb2; |
121c8476 | 1667 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) |
1e1cfc72 | 1668 | cctl |= src_ahb2; |
121c8476 RKAL |
1669 | |
1670 | return cctl; | |
1671 | } | |
1672 | ||
f14c426c RKAL |
1673 | static u32 pl08x_cctl(u32 cctl) |
1674 | { | |
1675 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1676 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1677 | PL080_CONTROL_PROT_MASK); | |
1678 | ||
1679 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1680 | return cctl | PL080_CONTROL_PROT_SYS; | |
1681 | } | |
1682 | ||
aa88cdaa RKAL |
1683 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1684 | { | |
1685 | switch (width) { | |
1686 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1687 | return PL080_WIDTH_8BIT; | |
1688 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1689 | return PL080_WIDTH_16BIT; | |
1690 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1691 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1692 | default: |
1693 | return ~0; | |
aa88cdaa | 1694 | } |
aa88cdaa RKAL |
1695 | } |
1696 | ||
760596c6 RKAL |
1697 | static u32 pl08x_burst(u32 maxburst) |
1698 | { | |
1699 | int i; | |
1700 | ||
1701 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1702 | if (burst_sizes[i].burstwords <= maxburst) | |
1703 | break; | |
1704 | ||
1705 | return burst_sizes[i].reg; | |
1706 | } | |
1707 | ||
9862ba17 RK |
1708 | static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan, |
1709 | enum dma_slave_buswidth addr_width, u32 maxburst) | |
1710 | { | |
1711 | u32 width, burst, cctl = 0; | |
1712 | ||
1713 | width = pl08x_width(addr_width); | |
1714 | if (width == ~0) | |
1715 | return ~0; | |
1716 | ||
1717 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; | |
1718 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1719 | ||
1720 | /* | |
1721 | * If this channel will only request single transfers, set this | |
1722 | * down to ONE element. Also select one element if no maxburst | |
1723 | * is specified. | |
1724 | */ | |
1725 | if (plchan->cd->single) | |
1726 | maxburst = 1; | |
1727 | ||
1728 | burst = pl08x_burst(maxburst); | |
1729 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1730 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
1731 | ||
1732 | return pl08x_cctl(cctl); | |
1733 | } | |
1734 | ||
e8689e63 LW |
1735 | /* |
1736 | * Slave transactions callback to the slave device to allow | |
1737 | * synchronization of slave DMA signals with the DMAC enable | |
1738 | */ | |
1739 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1740 | { | |
1741 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1742 | unsigned long flags; |
1743 | ||
083be28a | 1744 | spin_lock_irqsave(&plchan->vc.lock, flags); |
879f127b | 1745 | if (vchan_issue_pending(&plchan->vc)) { |
a5a488db RK |
1746 | if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING) |
1747 | pl08x_phy_alloc_and_start(plchan); | |
e8689e63 | 1748 | } |
083be28a | 1749 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
1750 | } |
1751 | ||
879f127b | 1752 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan) |
ac3cd20d | 1753 | { |
b201c111 | 1754 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d | 1755 | |
1e1cfc72 | 1756 | if (txd) |
b7f69d9d | 1757 | INIT_LIST_HEAD(&txd->dsg_list); |
ac3cd20d RKAL |
1758 | return txd; |
1759 | } | |
1760 | ||
1e1cfc72 | 1761 | static u32 pl08x_memcpy_cctl(struct pl08x_driver_data *pl08x) |
e8689e63 | 1762 | { |
4166a56a | 1763 | u32 cctl = 0; |
4166a56a LW |
1764 | |
1765 | /* Conjure cctl */ | |
1766 | switch (pl08x->pd->memcpy_burst_size) { | |
1767 | default: | |
1768 | dev_err(&pl08x->adev->dev, | |
1769 | "illegal burst size for memcpy, set to 1\n"); | |
1770 | /* Fall through */ | |
1771 | case PL08X_BURST_SZ_1: | |
1772 | cctl |= PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT | | |
1773 | PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT; | |
1774 | break; | |
1775 | case PL08X_BURST_SZ_4: | |
1776 | cctl |= PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT | | |
1777 | PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT; | |
1778 | break; | |
1779 | case PL08X_BURST_SZ_8: | |
1780 | cctl |= PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT | | |
1781 | PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT; | |
1782 | break; | |
1783 | case PL08X_BURST_SZ_16: | |
1784 | cctl |= PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | | |
1785 | PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT; | |
1786 | break; | |
1787 | case PL08X_BURST_SZ_32: | |
1788 | cctl |= PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT | | |
1789 | PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT; | |
1790 | break; | |
1791 | case PL08X_BURST_SZ_64: | |
1792 | cctl |= PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT | | |
1793 | PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT; | |
1794 | break; | |
1795 | case PL08X_BURST_SZ_128: | |
1796 | cctl |= PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT | | |
1797 | PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT; | |
1798 | break; | |
1799 | case PL08X_BURST_SZ_256: | |
1800 | cctl |= PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT | | |
1801 | PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT; | |
1802 | break; | |
1803 | } | |
1804 | ||
1805 | switch (pl08x->pd->memcpy_bus_width) { | |
1806 | default: | |
1807 | dev_err(&pl08x->adev->dev, | |
1808 | "illegal bus width for memcpy, set to 8 bits\n"); | |
1809 | /* Fall through */ | |
1810 | case PL08X_BUS_WIDTH_8_BITS: | |
1811 | cctl |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT | | |
1812 | PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
1813 | break; | |
1814 | case PL08X_BUS_WIDTH_16_BITS: | |
1815 | cctl |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT | | |
1816 | PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
1817 | break; | |
1818 | case PL08X_BUS_WIDTH_32_BITS: | |
1819 | cctl |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | | |
1820 | PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
1821 | break; | |
1822 | } | |
1823 | ||
1824 | /* Protection flags */ | |
1825 | if (pl08x->pd->memcpy_prot_buff) | |
1826 | cctl |= PL080_CONTROL_PROT_BUFF; | |
1827 | if (pl08x->pd->memcpy_prot_cache) | |
1828 | cctl |= PL080_CONTROL_PROT_CACHE; | |
1829 | ||
1830 | /* We are the kernel, so we are in privileged mode */ | |
1831 | cctl |= PL080_CONTROL_PROT_SYS; | |
4983a04f | 1832 | |
e8689e63 | 1833 | /* Both to be incremented or the code will break */ |
4166a56a | 1834 | cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1835 | |
c7da9a56 | 1836 | if (pl08x->vd->dualmaster) |
1e1cfc72 LW |
1837 | cctl |= pl08x_select_bus(false, |
1838 | pl08x->mem_buses, | |
1839 | pl08x->mem_buses); | |
1840 | ||
1841 | return cctl; | |
1842 | } | |
1843 | ||
1844 | static u32 pl08x_ftdmac020_memcpy_cctl(struct pl08x_driver_data *pl08x) | |
1845 | { | |
1846 | u32 cctl = 0; | |
1847 | ||
1848 | /* Conjure cctl */ | |
1849 | switch (pl08x->pd->memcpy_bus_width) { | |
1850 | default: | |
1851 | dev_err(&pl08x->adev->dev, | |
1852 | "illegal bus width for memcpy, set to 8 bits\n"); | |
1853 | /* Fall through */ | |
1854 | case PL08X_BUS_WIDTH_8_BITS: | |
1855 | cctl |= PL080_WIDTH_8BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT | | |
1856 | PL080_WIDTH_8BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT; | |
1857 | break; | |
1858 | case PL08X_BUS_WIDTH_16_BITS: | |
1859 | cctl |= PL080_WIDTH_16BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT | | |
1860 | PL080_WIDTH_16BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT; | |
1861 | break; | |
1862 | case PL08X_BUS_WIDTH_32_BITS: | |
1863 | cctl |= PL080_WIDTH_32BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT | | |
1864 | PL080_WIDTH_32BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT; | |
1865 | break; | |
1866 | } | |
1867 | ||
1868 | /* | |
1869 | * By default mask the TC IRQ on all LLIs, it will be unmasked on | |
1870 | * the last LLI item by other code. | |
1871 | */ | |
1872 | cctl |= FTDMAC020_LLI_TC_MSK; | |
1873 | ||
1874 | /* | |
1875 | * Both to be incremented so leave bits FTDMAC020_LLI_SRCAD_CTL | |
1876 | * and FTDMAC020_LLI_DSTAD_CTL as zero | |
1877 | */ | |
1878 | if (pl08x->vd->dualmaster) | |
1879 | cctl |= pl08x_select_bus(true, | |
1880 | pl08x->mem_buses, | |
4166a56a LW |
1881 | pl08x->mem_buses); |
1882 | ||
1e1cfc72 LW |
1883 | return cctl; |
1884 | } | |
1885 | ||
1886 | /* | |
1887 | * Initialize a descriptor to be used by memcpy submit | |
1888 | */ | |
1889 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1890 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1891 | size_t len, unsigned long flags) | |
1892 | { | |
1893 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1894 | struct pl08x_driver_data *pl08x = plchan->host; | |
1895 | struct pl08x_txd *txd; | |
1896 | struct pl08x_sg *dsg; | |
1897 | int ret; | |
1898 | ||
1899 | txd = pl08x_get_txd(plchan); | |
1900 | if (!txd) { | |
1901 | dev_err(&pl08x->adev->dev, | |
1902 | "%s no memory for descriptor\n", __func__); | |
1903 | return NULL; | |
1904 | } | |
1905 | ||
1906 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
1907 | if (!dsg) { | |
1908 | pl08x_free_txd(pl08x, txd); | |
1909 | return NULL; | |
1910 | } | |
1911 | list_add_tail(&dsg->node, &txd->dsg_list); | |
1912 | ||
1913 | dsg->src_addr = src; | |
1914 | dsg->dst_addr = dest; | |
1915 | dsg->len = len; | |
1916 | if (pl08x->vd->ftdmac020) { | |
1917 | /* Writing CCFG zero ENABLES all interrupts */ | |
1918 | txd->ccfg = 0; | |
1919 | txd->cctl = pl08x_ftdmac020_memcpy_cctl(pl08x); | |
1920 | } else { | |
1921 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1922 | PL080_CONFIG_TC_IRQ_MASK | | |
1923 | PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
1924 | txd->cctl = pl08x_memcpy_cctl(pl08x); | |
1925 | } | |
e8689e63 | 1926 | |
aa4afb75 RK |
1927 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
1928 | if (!ret) { | |
1929 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 1930 | return NULL; |
aa4afb75 | 1931 | } |
e8689e63 | 1932 | |
879f127b | 1933 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
1934 | } |
1935 | ||
3b24c20b AB |
1936 | static struct pl08x_txd *pl08x_init_txd( |
1937 | struct dma_chan *chan, | |
1938 | enum dma_transfer_direction direction, | |
1939 | dma_addr_t *slave_addr) | |
e8689e63 LW |
1940 | { |
1941 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1942 | struct pl08x_driver_data *pl08x = plchan->host; | |
1943 | struct pl08x_txd *txd; | |
dc8d5f8d | 1944 | enum dma_slave_buswidth addr_width; |
0a235657 | 1945 | int ret, tmp; |
409ec8db | 1946 | u8 src_buses, dst_buses; |
dc8d5f8d | 1947 | u32 maxburst, cctl; |
e8689e63 | 1948 | |
879f127b | 1949 | txd = pl08x_get_txd(plchan); |
e8689e63 LW |
1950 | if (!txd) { |
1951 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1952 | return NULL; | |
1953 | } | |
1954 | ||
e8689e63 LW |
1955 | /* |
1956 | * Set up addresses, the PrimeCell configured address | |
1957 | * will take precedence since this may configure the | |
1958 | * channel target address dynamically at runtime. | |
1959 | */ | |
db8196df | 1960 | if (direction == DMA_MEM_TO_DEV) { |
dc8d5f8d | 1961 | cctl = PL080_CONTROL_SRC_INCR; |
3b24c20b | 1962 | *slave_addr = plchan->cfg.dst_addr; |
dc8d5f8d RK |
1963 | addr_width = plchan->cfg.dst_addr_width; |
1964 | maxburst = plchan->cfg.dst_maxburst; | |
409ec8db RK |
1965 | src_buses = pl08x->mem_buses; |
1966 | dst_buses = plchan->cd->periph_buses; | |
db8196df | 1967 | } else if (direction == DMA_DEV_TO_MEM) { |
dc8d5f8d | 1968 | cctl = PL080_CONTROL_DST_INCR; |
3b24c20b | 1969 | *slave_addr = plchan->cfg.src_addr; |
dc8d5f8d RK |
1970 | addr_width = plchan->cfg.src_addr_width; |
1971 | maxburst = plchan->cfg.src_maxburst; | |
409ec8db RK |
1972 | src_buses = plchan->cd->periph_buses; |
1973 | dst_buses = pl08x->mem_buses; | |
e8689e63 | 1974 | } else { |
b7f69d9d | 1975 | pl08x_free_txd(pl08x, txd); |
e8689e63 LW |
1976 | dev_err(&pl08x->adev->dev, |
1977 | "%s direction unsupported\n", __func__); | |
1978 | return NULL; | |
1979 | } | |
e8689e63 | 1980 | |
dc8d5f8d | 1981 | cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); |
800d683e RK |
1982 | if (cctl == ~0) { |
1983 | pl08x_free_txd(pl08x, txd); | |
1984 | dev_err(&pl08x->adev->dev, | |
1985 | "DMA slave configuration botched?\n"); | |
1986 | return NULL; | |
1987 | } | |
1988 | ||
1e1cfc72 | 1989 | txd->cctl = cctl | pl08x_select_bus(false, src_buses, dst_buses); |
409ec8db | 1990 | |
95442b22 | 1991 | if (plchan->cfg.device_fc) |
db8196df | 1992 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER : |
0a235657 VK |
1993 | PL080_FLOW_PER2MEM_PER; |
1994 | else | |
db8196df | 1995 | tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER : |
0a235657 VK |
1996 | PL080_FLOW_PER2MEM; |
1997 | ||
1e1cfc72 LW |
1998 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | |
1999 | PL080_CONFIG_TC_IRQ_MASK | | |
2000 | tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; | |
0a235657 | 2001 | |
c48d4963 RK |
2002 | ret = pl08x_request_mux(plchan); |
2003 | if (ret < 0) { | |
2004 | pl08x_free_txd(pl08x, txd); | |
2005 | dev_dbg(&pl08x->adev->dev, | |
2006 | "unable to mux for transfer on %s due to platform restrictions\n", | |
2007 | plchan->name); | |
2008 | return NULL; | |
2009 | } | |
2010 | ||
2011 | dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n", | |
2012 | plchan->signal, plchan->name); | |
2013 | ||
2014 | /* Assign the flow control signal to this channel */ | |
2015 | if (direction == DMA_MEM_TO_DEV) | |
2016 | txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
2017 | else | |
2018 | txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
2019 | ||
3b24c20b AB |
2020 | return txd; |
2021 | } | |
2022 | ||
2023 | static int pl08x_tx_add_sg(struct pl08x_txd *txd, | |
2024 | enum dma_transfer_direction direction, | |
2025 | dma_addr_t slave_addr, | |
2026 | dma_addr_t buf_addr, | |
2027 | unsigned int len) | |
2028 | { | |
2029 | struct pl08x_sg *dsg; | |
2030 | ||
2031 | dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT); | |
2032 | if (!dsg) | |
2033 | return -ENOMEM; | |
2034 | ||
2035 | list_add_tail(&dsg->node, &txd->dsg_list); | |
2036 | ||
2037 | dsg->len = len; | |
2038 | if (direction == DMA_MEM_TO_DEV) { | |
2039 | dsg->src_addr = buf_addr; | |
2040 | dsg->dst_addr = slave_addr; | |
2041 | } else { | |
2042 | dsg->src_addr = slave_addr; | |
2043 | dsg->dst_addr = buf_addr; | |
2044 | } | |
2045 | ||
2046 | return 0; | |
2047 | } | |
2048 | ||
2049 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( | |
2050 | struct dma_chan *chan, struct scatterlist *sgl, | |
2051 | unsigned int sg_len, enum dma_transfer_direction direction, | |
2052 | unsigned long flags, void *context) | |
2053 | { | |
2054 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
2055 | struct pl08x_driver_data *pl08x = plchan->host; | |
2056 | struct pl08x_txd *txd; | |
2057 | struct scatterlist *sg; | |
2058 | int ret, tmp; | |
2059 | dma_addr_t slave_addr; | |
2060 | ||
2061 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", | |
2062 | __func__, sg_dma_len(sgl), plchan->name); | |
2063 | ||
2064 | txd = pl08x_init_txd(chan, direction, &slave_addr); | |
2065 | if (!txd) | |
2066 | return NULL; | |
2067 | ||
b7f69d9d | 2068 | for_each_sg(sgl, sg, sg_len, tmp) { |
3b24c20b AB |
2069 | ret = pl08x_tx_add_sg(txd, direction, slave_addr, |
2070 | sg_dma_address(sg), | |
2071 | sg_dma_len(sg)); | |
2072 | if (ret) { | |
c48d4963 | 2073 | pl08x_release_mux(plchan); |
b7f69d9d VK |
2074 | pl08x_free_txd(pl08x, txd); |
2075 | dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n", | |
2076 | __func__); | |
2077 | return NULL; | |
2078 | } | |
3b24c20b | 2079 | } |
b7f69d9d | 2080 | |
3b24c20b AB |
2081 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
2082 | if (!ret) { | |
2083 | pl08x_release_mux(plchan); | |
2084 | pl08x_free_txd(pl08x, txd); | |
2085 | return NULL; | |
2086 | } | |
2087 | ||
2088 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); | |
2089 | } | |
2090 | ||
2091 | static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic( | |
2092 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
2093 | size_t period_len, enum dma_transfer_direction direction, | |
31c1e5a1 | 2094 | unsigned long flags) |
3b24c20b AB |
2095 | { |
2096 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
2097 | struct pl08x_driver_data *pl08x = plchan->host; | |
2098 | struct pl08x_txd *txd; | |
2099 | int ret, tmp; | |
2100 | dma_addr_t slave_addr; | |
2101 | ||
2102 | dev_dbg(&pl08x->adev->dev, | |
6fc8ae78 | 2103 | "%s prepare cyclic transaction of %zd/%zd bytes %s %s\n", |
3b24c20b AB |
2104 | __func__, period_len, buf_len, |
2105 | direction == DMA_MEM_TO_DEV ? "to" : "from", | |
2106 | plchan->name); | |
2107 | ||
2108 | txd = pl08x_init_txd(chan, direction, &slave_addr); | |
2109 | if (!txd) | |
2110 | return NULL; | |
2111 | ||
2112 | txd->cyclic = true; | |
2113 | txd->cctl |= PL080_CONTROL_TC_IRQ_EN; | |
2114 | for (tmp = 0; tmp < buf_len; tmp += period_len) { | |
2115 | ret = pl08x_tx_add_sg(txd, direction, slave_addr, | |
2116 | buf_addr + tmp, period_len); | |
2117 | if (ret) { | |
2118 | pl08x_release_mux(plchan); | |
2119 | pl08x_free_txd(pl08x, txd); | |
2120 | return NULL; | |
b7f69d9d VK |
2121 | } |
2122 | } | |
2123 | ||
aa4afb75 RK |
2124 | ret = pl08x_fill_llis_for_desc(plchan->host, txd); |
2125 | if (!ret) { | |
2126 | pl08x_release_mux(plchan); | |
2127 | pl08x_free_txd(pl08x, txd); | |
e8689e63 | 2128 | return NULL; |
aa4afb75 | 2129 | } |
e8689e63 | 2130 | |
879f127b | 2131 | return vchan_tx_prep(&plchan->vc, &txd->vd, flags); |
e8689e63 LW |
2132 | } |
2133 | ||
bcd1b0b9 MR |
2134 | static int pl08x_config(struct dma_chan *chan, |
2135 | struct dma_slave_config *config) | |
2136 | { | |
2137 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
2138 | struct pl08x_driver_data *pl08x = plchan->host; | |
2139 | ||
2140 | if (!plchan->slave) | |
2141 | return -EINVAL; | |
2142 | ||
2143 | /* Reject definitely invalid configurations */ | |
2144 | if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
2145 | config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2146 | return -EINVAL; | |
2147 | ||
2148 | if (config->device_fc && pl08x->vd->pl080s) { | |
2149 | dev_err(&pl08x->adev->dev, | |
2150 | "%s: PL080S does not support peripheral flow control\n", | |
2151 | __func__); | |
2152 | return -EINVAL; | |
2153 | } | |
2154 | ||
2155 | plchan->cfg = *config; | |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
2160 | static int pl08x_terminate_all(struct dma_chan *chan) | |
e8689e63 LW |
2161 | { |
2162 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
2163 | struct pl08x_driver_data *pl08x = plchan->host; | |
2164 | unsigned long flags; | |
e8689e63 | 2165 | |
bcd1b0b9 MR |
2166 | spin_lock_irqsave(&plchan->vc.lock, flags); |
2167 | if (!plchan->phychan && !plchan->at) { | |
2168 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
2169 | return 0; | |
e8689e63 LW |
2170 | } |
2171 | ||
bcd1b0b9 MR |
2172 | plchan->state = PL08X_CHAN_IDLE; |
2173 | ||
2174 | if (plchan->phychan) { | |
2175 | /* | |
2176 | * Mark physical channel as free and free any slave | |
2177 | * signal | |
2178 | */ | |
2179 | pl08x_phy_free(plchan); | |
2180 | } | |
2181 | /* Dequeue jobs and free LLIs */ | |
2182 | if (plchan->at) { | |
47d71bc7 | 2183 | vchan_terminate_vdesc(&plchan->at->vd); |
bcd1b0b9 MR |
2184 | plchan->at = NULL; |
2185 | } | |
2186 | /* Dequeue jobs not yet fired as well */ | |
2187 | pl08x_free_txd_list(pl08x, plchan); | |
2188 | ||
2189 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
2190 | ||
2191 | return 0; | |
2192 | } | |
2193 | ||
47d71bc7 PU |
2194 | static void pl08x_synchronize(struct dma_chan *chan) |
2195 | { | |
2196 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
2197 | ||
2198 | vchan_synchronize(&plchan->vc); | |
2199 | } | |
2200 | ||
bcd1b0b9 MR |
2201 | static int pl08x_pause(struct dma_chan *chan) |
2202 | { | |
2203 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
2204 | unsigned long flags; | |
2205 | ||
e8689e63 LW |
2206 | /* |
2207 | * Anything succeeds on channels with no physical allocation and | |
2208 | * no queued transfers. | |
2209 | */ | |
083be28a | 2210 | spin_lock_irqsave(&plchan->vc.lock, flags); |
e8689e63 | 2211 | if (!plchan->phychan && !plchan->at) { |
083be28a | 2212 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 LW |
2213 | return 0; |
2214 | } | |
2215 | ||
bcd1b0b9 MR |
2216 | pl08x_pause_phy_chan(plchan->phychan); |
2217 | plchan->state = PL08X_CHAN_PAUSED; | |
e8689e63 | 2218 | |
bcd1b0b9 MR |
2219 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
2220 | ||
2221 | return 0; | |
2222 | } | |
2223 | ||
2224 | static int pl08x_resume(struct dma_chan *chan) | |
2225 | { | |
2226 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
2227 | unsigned long flags; | |
2228 | ||
2229 | /* | |
2230 | * Anything succeeds on channels with no physical allocation and | |
2231 | * no queued transfers. | |
2232 | */ | |
2233 | spin_lock_irqsave(&plchan->vc.lock, flags); | |
2234 | if (!plchan->phychan && !plchan->at) { | |
2235 | spin_unlock_irqrestore(&plchan->vc.lock, flags); | |
2236 | return 0; | |
e8689e63 LW |
2237 | } |
2238 | ||
bcd1b0b9 MR |
2239 | pl08x_resume_phy_chan(plchan->phychan); |
2240 | plchan->state = PL08X_CHAN_RUNNING; | |
2241 | ||
083be28a | 2242 | spin_unlock_irqrestore(&plchan->vc.lock, flags); |
e8689e63 | 2243 | |
bcd1b0b9 | 2244 | return 0; |
e8689e63 LW |
2245 | } |
2246 | ||
2247 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
2248 | { | |
7703eac9 | 2249 | struct pl08x_dma_chan *plchan; |
e8689e63 LW |
2250 | char *name = chan_id; |
2251 | ||
7703eac9 RKAL |
2252 | /* Reject channels for devices not bound to this driver */ |
2253 | if (chan->device->dev->driver != &pl08x_amba_driver.drv) | |
2254 | return false; | |
2255 | ||
2256 | plchan = to_pl08x_chan(chan); | |
2257 | ||
e8689e63 LW |
2258 | /* Check that the channel is not taken! */ |
2259 | if (!strcmp(plchan->name, name)) | |
2260 | return true; | |
2261 | ||
2262 | return false; | |
2263 | } | |
6d05c9fa | 2264 | EXPORT_SYMBOL_GPL(pl08x_filter_id); |
e8689e63 | 2265 | |
da6f8ca1 SN |
2266 | static bool pl08x_filter_fn(struct dma_chan *chan, void *chan_id) |
2267 | { | |
2268 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
2269 | ||
2270 | return plchan->cd == chan_id; | |
2271 | } | |
2272 | ||
e8689e63 LW |
2273 | /* |
2274 | * Just check that the device is there and active | |
94ae8522 RKAL |
2275 | * TODO: turn this bit on/off depending on the number of physical channels |
2276 | * actually used, if it is zero... well shut it off. That will save some | |
2277 | * power. Cut the clock at the same time. | |
e8689e63 LW |
2278 | */ |
2279 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
2280 | { | |
affa115e LW |
2281 | /* The Nomadik variant does not have the config register */ |
2282 | if (pl08x->vd->nomadik) | |
2283 | return; | |
1e1cfc72 LW |
2284 | /* The FTDMAC020 variant does this in another register */ |
2285 | if (pl08x->vd->ftdmac020) { | |
2286 | writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR); | |
2287 | return; | |
2288 | } | |
48a59ef3 | 2289 | writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); |
e8689e63 LW |
2290 | } |
2291 | ||
e8689e63 LW |
2292 | static irqreturn_t pl08x_irq(int irq, void *dev) |
2293 | { | |
2294 | struct pl08x_driver_data *pl08x = dev; | |
28da2836 VK |
2295 | u32 mask = 0, err, tc, i; |
2296 | ||
2297 | /* check & clear - ERR & TC interrupts */ | |
2298 | err = readl(pl08x->base + PL080_ERR_STATUS); | |
2299 | if (err) { | |
2300 | dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n", | |
2301 | __func__, err); | |
2302 | writel(err, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 | 2303 | } |
d29bf019 | 2304 | tc = readl(pl08x->base + PL080_TC_STATUS); |
28da2836 VK |
2305 | if (tc) |
2306 | writel(tc, pl08x->base + PL080_TC_CLEAR); | |
2307 | ||
2308 | if (!err && !tc) | |
2309 | return IRQ_NONE; | |
2310 | ||
e8689e63 | 2311 | for (i = 0; i < pl08x->vd->channels; i++) { |
ded091fe | 2312 | if ((BIT(i) & err) || (BIT(i) & tc)) { |
e8689e63 LW |
2313 | /* Locate physical channel */ |
2314 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
2315 | struct pl08x_dma_chan *plchan = phychan->serving; | |
a936e793 | 2316 | struct pl08x_txd *tx; |
e8689e63 | 2317 | |
28da2836 VK |
2318 | if (!plchan) { |
2319 | dev_err(&pl08x->adev->dev, | |
2320 | "%s Error TC interrupt on unused channel: 0x%08x\n", | |
2321 | __func__, i); | |
2322 | continue; | |
2323 | } | |
2324 | ||
083be28a | 2325 | spin_lock(&plchan->vc.lock); |
a936e793 | 2326 | tx = plchan->at; |
3b24c20b AB |
2327 | if (tx && tx->cyclic) { |
2328 | vchan_cyclic_callback(&tx->vd); | |
2329 | } else if (tx) { | |
a936e793 | 2330 | plchan->at = NULL; |
c48d4963 RK |
2331 | /* |
2332 | * This descriptor is done, release its mux | |
2333 | * reservation. | |
2334 | */ | |
2335 | pl08x_release_mux(plchan); | |
18536134 RK |
2336 | tx->done = true; |
2337 | vchan_cookie_complete(&tx->vd); | |
c33b644c | 2338 | |
a5a488db RK |
2339 | /* |
2340 | * And start the next descriptor (if any), | |
2341 | * otherwise free this channel. | |
2342 | */ | |
879f127b | 2343 | if (vchan_next_desc(&plchan->vc)) |
c33b644c | 2344 | pl08x_start_next_txd(plchan); |
a5a488db RK |
2345 | else |
2346 | pl08x_phy_free(plchan); | |
a936e793 | 2347 | } |
083be28a | 2348 | spin_unlock(&plchan->vc.lock); |
a936e793 | 2349 | |
ded091fe | 2350 | mask |= BIT(i); |
e8689e63 LW |
2351 | } |
2352 | } | |
e8689e63 LW |
2353 | |
2354 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
2355 | } | |
2356 | ||
121c8476 RKAL |
2357 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
2358 | { | |
121c8476 RKAL |
2359 | chan->slave = true; |
2360 | chan->name = chan->cd->bus_id; | |
ed91c13d RK |
2361 | chan->cfg.src_addr = chan->cd->addr; |
2362 | chan->cfg.dst_addr = chan->cd->addr; | |
121c8476 RKAL |
2363 | } |
2364 | ||
e8689e63 LW |
2365 | /* |
2366 | * Initialise the DMAC memcpy/slave channels. | |
2367 | * Make a local wrapper to hold required data | |
2368 | */ | |
2369 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 2370 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
2371 | { |
2372 | struct pl08x_dma_chan *chan; | |
2373 | int i; | |
2374 | ||
2375 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 2376 | |
e8689e63 LW |
2377 | /* |
2378 | * Register as many many memcpy as we have physical channels, | |
2379 | * we won't always be able to use all but the code will have | |
2380 | * to cope with that situation. | |
2381 | */ | |
2382 | for (i = 0; i < channels; i++) { | |
b201c111 | 2383 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
aef94fea | 2384 | if (!chan) |
e8689e63 | 2385 | return -ENOMEM; |
e8689e63 LW |
2386 | |
2387 | chan->host = pl08x; | |
2388 | chan->state = PL08X_CHAN_IDLE; | |
ad0de2ac | 2389 | chan->signal = -1; |
e8689e63 LW |
2390 | |
2391 | if (slave) { | |
e8689e63 | 2392 | chan->cd = &pl08x->pd->slave_channels[i]; |
f9cd4761 LW |
2393 | /* |
2394 | * Some implementations have muxed signals, whereas some | |
2395 | * use a mux in front of the signals and need dynamic | |
2396 | * assignment of signals. | |
2397 | */ | |
2398 | chan->signal = i; | |
121c8476 | 2399 | pl08x_dma_slave_init(chan); |
e8689e63 | 2400 | } else { |
4166a56a LW |
2401 | chan->cd = kzalloc(sizeof(*chan->cd), GFP_KERNEL); |
2402 | if (!chan->cd) { | |
2403 | kfree(chan); | |
2404 | return -ENOMEM; | |
2405 | } | |
2406 | chan->cd->bus_id = "memcpy"; | |
2407 | chan->cd->periph_buses = pl08x->pd->mem_buses; | |
e8689e63 LW |
2408 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); |
2409 | if (!chan->name) { | |
4166a56a | 2410 | kfree(chan->cd); |
e8689e63 LW |
2411 | kfree(chan); |
2412 | return -ENOMEM; | |
2413 | } | |
2414 | } | |
175a5e61 | 2415 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
2416 | "initialize virtual channel \"%s\"\n", |
2417 | chan->name); | |
2418 | ||
18536134 | 2419 | chan->vc.desc_free = pl08x_desc_free; |
083be28a | 2420 | vchan_init(&chan->vc, dmadev); |
e8689e63 LW |
2421 | } |
2422 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
2423 | i, slave ? "slave" : "memcpy"); | |
2424 | return i; | |
2425 | } | |
2426 | ||
2427 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
2428 | { | |
2429 | struct pl08x_dma_chan *chan = NULL; | |
2430 | struct pl08x_dma_chan *next; | |
2431 | ||
2432 | list_for_each_entry_safe(chan, | |
01d8dc64 RK |
2433 | next, &dmadev->channels, vc.chan.device_node) { |
2434 | list_del(&chan->vc.chan.device_node); | |
e8689e63 LW |
2435 | kfree(chan); |
2436 | } | |
2437 | } | |
2438 | ||
2439 | #ifdef CONFIG_DEBUG_FS | |
2440 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
2441 | { | |
2442 | switch (state) { | |
2443 | case PL08X_CHAN_IDLE: | |
2444 | return "idle"; | |
2445 | case PL08X_CHAN_RUNNING: | |
2446 | return "running"; | |
2447 | case PL08X_CHAN_PAUSED: | |
2448 | return "paused"; | |
2449 | case PL08X_CHAN_WAITING: | |
2450 | return "waiting"; | |
2451 | default: | |
2452 | break; | |
2453 | } | |
2454 | return "UNKNOWN STATE"; | |
2455 | } | |
2456 | ||
2457 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
2458 | { | |
2459 | struct pl08x_driver_data *pl08x = s->private; | |
2460 | struct pl08x_dma_chan *chan; | |
2461 | struct pl08x_phy_chan *ch; | |
2462 | unsigned long flags; | |
2463 | int i; | |
2464 | ||
2465 | seq_printf(s, "PL08x physical channels:\n"); | |
2466 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
2467 | seq_printf(s, "--------\t-----\n"); | |
2468 | for (i = 0; i < pl08x->vd->channels; i++) { | |
2469 | struct pl08x_dma_chan *virt_chan; | |
2470 | ||
2471 | ch = &pl08x->phy_chans[i]; | |
2472 | ||
2473 | spin_lock_irqsave(&ch->lock, flags); | |
2474 | virt_chan = ch->serving; | |
2475 | ||
affa115e LW |
2476 | seq_printf(s, "%d\t\t%s%s\n", |
2477 | ch->id, | |
2478 | virt_chan ? virt_chan->name : "(none)", | |
2479 | ch->locked ? " LOCKED" : ""); | |
e8689e63 LW |
2480 | |
2481 | spin_unlock_irqrestore(&ch->lock, flags); | |
2482 | } | |
2483 | ||
2484 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
2485 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
2486 | seq_printf(s, "--------\t------\n"); | |
01d8dc64 | 2487 | list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) { |
3e2a037c | 2488 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
2489 | pl08x_state_str(chan->state)); |
2490 | } | |
2491 | ||
ebe9b300 LW |
2492 | if (pl08x->has_slave) { |
2493 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
2494 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
2495 | seq_printf(s, "--------\t------\n"); | |
2496 | list_for_each_entry(chan, &pl08x->slave.channels, | |
2497 | vc.chan.device_node) { | |
2498 | seq_printf(s, "%s\t\t%s\n", chan->name, | |
2499 | pl08x_state_str(chan->state)); | |
2500 | } | |
e8689e63 LW |
2501 | } |
2502 | ||
2503 | return 0; | |
2504 | } | |
2505 | ||
8e1897bc | 2506 | DEFINE_SHOW_ATTRIBUTE(pl08x_debugfs); |
e8689e63 LW |
2507 | |
2508 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
2509 | { | |
2510 | /* Expose a simple debugfs interface to view all clocks */ | |
718745f8 GKH |
2511 | debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO, |
2512 | NULL, pl08x, &pl08x_debugfs_fops); | |
e8689e63 LW |
2513 | } |
2514 | ||
2515 | #else | |
2516 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
2517 | { | |
2518 | } | |
2519 | #endif | |
2520 | ||
aa4734da LW |
2521 | #ifdef CONFIG_OF |
2522 | static struct dma_chan *pl08x_find_chan_id(struct pl08x_driver_data *pl08x, | |
2523 | u32 id) | |
2524 | { | |
2525 | struct pl08x_dma_chan *chan; | |
2526 | ||
ebe9b300 LW |
2527 | /* Trying to get a slave channel from something with no slave support */ |
2528 | if (!pl08x->has_slave) | |
2529 | return NULL; | |
2530 | ||
aa4734da LW |
2531 | list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) { |
2532 | if (chan->signal == id) | |
2533 | return &chan->vc.chan; | |
2534 | } | |
2535 | ||
2536 | return NULL; | |
2537 | } | |
2538 | ||
2539 | static struct dma_chan *pl08x_of_xlate(struct of_phandle_args *dma_spec, | |
2540 | struct of_dma *ofdma) | |
2541 | { | |
2542 | struct pl08x_driver_data *pl08x = ofdma->of_dma_data; | |
aa4734da | 2543 | struct dma_chan *dma_chan; |
f9cd4761 | 2544 | struct pl08x_dma_chan *plchan; |
aa4734da LW |
2545 | |
2546 | if (!pl08x) | |
2547 | return NULL; | |
2548 | ||
f9cd4761 LW |
2549 | if (dma_spec->args_count != 2) { |
2550 | dev_err(&pl08x->adev->dev, | |
2551 | "DMA channel translation requires two cells\n"); | |
aa4734da | 2552 | return NULL; |
f9cd4761 | 2553 | } |
aa4734da LW |
2554 | |
2555 | dma_chan = pl08x_find_chan_id(pl08x, dma_spec->args[0]); | |
f9cd4761 LW |
2556 | if (!dma_chan) { |
2557 | dev_err(&pl08x->adev->dev, | |
2558 | "DMA slave channel not found\n"); | |
aa4734da | 2559 | return NULL; |
f9cd4761 | 2560 | } |
aa4734da | 2561 | |
f9cd4761 LW |
2562 | plchan = to_pl08x_chan(dma_chan); |
2563 | dev_dbg(&pl08x->adev->dev, | |
2564 | "translated channel for signal %d\n", | |
2565 | dma_spec->args[0]); | |
aa4734da | 2566 | |
f9cd4761 LW |
2567 | /* Augment channel data for applicable AHB buses */ |
2568 | plchan->cd->periph_buses = dma_spec->args[1]; | |
2569 | return dma_get_slave_channel(dma_chan); | |
aa4734da LW |
2570 | } |
2571 | ||
2572 | static int pl08x_of_probe(struct amba_device *adev, | |
2573 | struct pl08x_driver_data *pl08x, | |
2574 | struct device_node *np) | |
2575 | { | |
2576 | struct pl08x_platform_data *pd; | |
f9cd4761 | 2577 | struct pl08x_channel_data *chanp = NULL; |
aa4734da LW |
2578 | u32 val; |
2579 | int ret; | |
f9cd4761 | 2580 | int i; |
aa4734da LW |
2581 | |
2582 | pd = devm_kzalloc(&adev->dev, sizeof(*pd), GFP_KERNEL); | |
2583 | if (!pd) | |
2584 | return -ENOMEM; | |
2585 | ||
2586 | /* Eligible bus masters for fetching LLIs */ | |
2587 | if (of_property_read_bool(np, "lli-bus-interface-ahb1")) | |
2588 | pd->lli_buses |= PL08X_AHB1; | |
2589 | if (of_property_read_bool(np, "lli-bus-interface-ahb2")) | |
2590 | pd->lli_buses |= PL08X_AHB2; | |
2591 | if (!pd->lli_buses) { | |
2592 | dev_info(&adev->dev, "no bus masters for LLIs stated, assume all\n"); | |
2593 | pd->lli_buses |= PL08X_AHB1 | PL08X_AHB2; | |
2594 | } | |
2595 | ||
2596 | /* Eligible bus masters for memory access */ | |
2597 | if (of_property_read_bool(np, "mem-bus-interface-ahb1")) | |
2598 | pd->mem_buses |= PL08X_AHB1; | |
2599 | if (of_property_read_bool(np, "mem-bus-interface-ahb2")) | |
2600 | pd->mem_buses |= PL08X_AHB2; | |
2601 | if (!pd->mem_buses) { | |
2602 | dev_info(&adev->dev, "no bus masters for memory stated, assume all\n"); | |
2603 | pd->mem_buses |= PL08X_AHB1 | PL08X_AHB2; | |
2604 | } | |
2605 | ||
2606 | /* Parse the memcpy channel properties */ | |
2607 | ret = of_property_read_u32(np, "memcpy-burst-size", &val); | |
2608 | if (ret) { | |
2609 | dev_info(&adev->dev, "no memcpy burst size specified, using 1 byte\n"); | |
2610 | val = 1; | |
2611 | } | |
2612 | switch (val) { | |
2613 | default: | |
2614 | dev_err(&adev->dev, "illegal burst size for memcpy, set to 1\n"); | |
2615 | /* Fall through */ | |
2616 | case 1: | |
4166a56a | 2617 | pd->memcpy_burst_size = PL08X_BURST_SZ_1; |
aa4734da LW |
2618 | break; |
2619 | case 4: | |
4166a56a | 2620 | pd->memcpy_burst_size = PL08X_BURST_SZ_4; |
aa4734da LW |
2621 | break; |
2622 | case 8: | |
4166a56a | 2623 | pd->memcpy_burst_size = PL08X_BURST_SZ_8; |
aa4734da LW |
2624 | break; |
2625 | case 16: | |
4166a56a | 2626 | pd->memcpy_burst_size = PL08X_BURST_SZ_16; |
aa4734da LW |
2627 | break; |
2628 | case 32: | |
4166a56a | 2629 | pd->memcpy_burst_size = PL08X_BURST_SZ_32; |
aa4734da LW |
2630 | break; |
2631 | case 64: | |
4166a56a | 2632 | pd->memcpy_burst_size = PL08X_BURST_SZ_64; |
aa4734da LW |
2633 | break; |
2634 | case 128: | |
4166a56a | 2635 | pd->memcpy_burst_size = PL08X_BURST_SZ_128; |
aa4734da LW |
2636 | break; |
2637 | case 256: | |
4166a56a | 2638 | pd->memcpy_burst_size = PL08X_BURST_SZ_256; |
aa4734da LW |
2639 | break; |
2640 | } | |
2641 | ||
2642 | ret = of_property_read_u32(np, "memcpy-bus-width", &val); | |
2643 | if (ret) { | |
2644 | dev_info(&adev->dev, "no memcpy bus width specified, using 8 bits\n"); | |
2645 | val = 8; | |
2646 | } | |
2647 | switch (val) { | |
2648 | default: | |
2649 | dev_err(&adev->dev, "illegal bus width for memcpy, set to 8 bits\n"); | |
2650 | /* Fall through */ | |
2651 | case 8: | |
4166a56a | 2652 | pd->memcpy_bus_width = PL08X_BUS_WIDTH_8_BITS; |
aa4734da LW |
2653 | break; |
2654 | case 16: | |
4166a56a | 2655 | pd->memcpy_bus_width = PL08X_BUS_WIDTH_16_BITS; |
aa4734da LW |
2656 | break; |
2657 | case 32: | |
4166a56a | 2658 | pd->memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS; |
aa4734da LW |
2659 | break; |
2660 | } | |
2661 | ||
f9cd4761 LW |
2662 | /* |
2663 | * Allocate channel data for all possible slave channels (one | |
2664 | * for each possible signal), channels will then be allocated | |
2665 | * for a device and have it's AHB interfaces set up at | |
2666 | * translation time. | |
2667 | */ | |
ebe9b300 LW |
2668 | if (pl08x->vd->signals) { |
2669 | chanp = devm_kcalloc(&adev->dev, | |
2670 | pl08x->vd->signals, | |
2671 | sizeof(struct pl08x_channel_data), | |
2672 | GFP_KERNEL); | |
2673 | if (!chanp) | |
2674 | return -ENOMEM; | |
f9cd4761 | 2675 | |
ebe9b300 LW |
2676 | pd->slave_channels = chanp; |
2677 | for (i = 0; i < pl08x->vd->signals; i++) { | |
2678 | /* | |
2679 | * chanp->periph_buses will be assigned at translation | |
2680 | */ | |
2681 | chanp->bus_id = kasprintf(GFP_KERNEL, "slave%d", i); | |
2682 | chanp++; | |
2683 | } | |
2684 | pd->num_slave_channels = pl08x->vd->signals; | |
f9cd4761 | 2685 | } |
f9cd4761 | 2686 | |
aa4734da LW |
2687 | pl08x->pd = pd; |
2688 | ||
2689 | return of_dma_controller_register(adev->dev.of_node, pl08x_of_xlate, | |
2690 | pl08x); | |
2691 | } | |
2692 | #else | |
2693 | static inline int pl08x_of_probe(struct amba_device *adev, | |
2694 | struct pl08x_driver_data *pl08x, | |
2695 | struct device_node *np) | |
2696 | { | |
2697 | return -EINVAL; | |
2698 | } | |
2699 | #endif | |
2700 | ||
aa25afad | 2701 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
2702 | { |
2703 | struct pl08x_driver_data *pl08x; | |
1e1cfc72 | 2704 | struct vendor_data *vd = id->data; |
aa4734da | 2705 | struct device_node *np = adev->dev.of_node; |
ba6785ff | 2706 | u32 tsfr_size; |
e8689e63 LW |
2707 | int ret = 0; |
2708 | int i; | |
2709 | ||
2710 | ret = amba_request_regions(adev, NULL); | |
2711 | if (ret) | |
2712 | return ret; | |
2713 | ||
de1a2419 RK |
2714 | /* Ensure that we can do DMA */ |
2715 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); | |
2716 | if (ret) | |
2717 | goto out_no_pl08x; | |
2718 | ||
e8689e63 | 2719 | /* Create the driver state holder */ |
b201c111 | 2720 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
2721 | if (!pl08x) { |
2722 | ret = -ENOMEM; | |
2723 | goto out_no_pl08x; | |
2724 | } | |
2725 | ||
f9cd4761 LW |
2726 | /* Assign useful pointers to the driver state */ |
2727 | pl08x->adev = adev; | |
2728 | pl08x->vd = vd; | |
2729 | ||
1e1cfc72 LW |
2730 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); |
2731 | if (!pl08x->base) { | |
2732 | ret = -ENOMEM; | |
2733 | goto out_no_ioremap; | |
2734 | } | |
2735 | ||
2736 | if (vd->ftdmac020) { | |
2737 | u32 val; | |
2738 | ||
2739 | val = readl(pl08x->base + FTDMAC020_REVISION); | |
2740 | dev_info(&pl08x->adev->dev, "FTDMAC020 %d.%d rel %d\n", | |
2741 | (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); | |
2742 | val = readl(pl08x->base + FTDMAC020_FEATURE); | |
2743 | dev_info(&pl08x->adev->dev, "FTDMAC020 %d channels, " | |
2744 | "%s built-in bridge, %s, %s linked lists\n", | |
2745 | (val >> 12) & 0x0f, | |
2746 | (val & BIT(10)) ? "no" : "has", | |
2747 | (val & BIT(9)) ? "AHB0 and AHB1" : "AHB0", | |
2748 | (val & BIT(8)) ? "supports" : "does not support"); | |
2749 | ||
2750 | /* Vendor data from feature register */ | |
2751 | if (!(val & BIT(8))) | |
2752 | dev_warn(&pl08x->adev->dev, | |
2753 | "linked lists not supported, required\n"); | |
2754 | vd->channels = (val >> 12) & 0x0f; | |
2755 | vd->dualmaster = !!(val & BIT(9)); | |
2756 | } | |
2757 | ||
e8689e63 LW |
2758 | /* Initialize memcpy engine */ |
2759 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
2760 | pl08x->memcpy.dev = &adev->dev; | |
e8689e63 LW |
2761 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; |
2762 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
2763 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
2764 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
2765 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
bcd1b0b9 MR |
2766 | pl08x->memcpy.device_config = pl08x_config; |
2767 | pl08x->memcpy.device_pause = pl08x_pause; | |
2768 | pl08x->memcpy.device_resume = pl08x_resume; | |
2769 | pl08x->memcpy.device_terminate_all = pl08x_terminate_all; | |
47d71bc7 | 2770 | pl08x->memcpy.device_synchronize = pl08x_synchronize; |
ea524c7e MB |
2771 | pl08x->memcpy.src_addr_widths = PL80X_DMA_BUSWIDTHS; |
2772 | pl08x->memcpy.dst_addr_widths = PL80X_DMA_BUSWIDTHS; | |
2773 | pl08x->memcpy.directions = BIT(DMA_MEM_TO_MEM); | |
2774 | pl08x->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; | |
1e1cfc72 LW |
2775 | if (vd->ftdmac020) |
2776 | pl08x->memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES; | |
2777 | ||
e8689e63 | 2778 | |
ebe9b300 LW |
2779 | /* |
2780 | * Initialize slave engine, if the block has no signals, that means | |
2781 | * we have no slave support. | |
2782 | */ | |
2783 | if (vd->signals) { | |
2784 | pl08x->has_slave = true; | |
2785 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
2786 | dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask); | |
2787 | pl08x->slave.dev = &adev->dev; | |
2788 | pl08x->slave.device_free_chan_resources = | |
2789 | pl08x_free_chan_resources; | |
2790 | pl08x->slave.device_prep_dma_interrupt = | |
2791 | pl08x_prep_dma_interrupt; | |
2792 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
2793 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
2794 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
2795 | pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic; | |
2796 | pl08x->slave.device_config = pl08x_config; | |
2797 | pl08x->slave.device_pause = pl08x_pause; | |
2798 | pl08x->slave.device_resume = pl08x_resume; | |
2799 | pl08x->slave.device_terminate_all = pl08x_terminate_all; | |
47d71bc7 | 2800 | pl08x->slave.device_synchronize = pl08x_synchronize; |
ebe9b300 LW |
2801 | pl08x->slave.src_addr_widths = PL80X_DMA_BUSWIDTHS; |
2802 | pl08x->slave.dst_addr_widths = PL80X_DMA_BUSWIDTHS; | |
2803 | pl08x->slave.directions = | |
2804 | BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
2805 | pl08x->slave.residue_granularity = | |
2806 | DMA_RESIDUE_GRANULARITY_SEGMENT; | |
2807 | } | |
e8689e63 LW |
2808 | |
2809 | /* Get the platform data */ | |
2810 | pl08x->pd = dev_get_platdata(&adev->dev); | |
2811 | if (!pl08x->pd) { | |
aa4734da LW |
2812 | if (np) { |
2813 | ret = pl08x_of_probe(adev, pl08x, np); | |
2814 | if (ret) | |
2815 | goto out_no_platdata; | |
2816 | } else { | |
2817 | dev_err(&adev->dev, "no platform data supplied\n"); | |
2818 | ret = -EINVAL; | |
2819 | goto out_no_platdata; | |
2820 | } | |
da6f8ca1 SN |
2821 | } else { |
2822 | pl08x->slave.filter.map = pl08x->pd->slave_map; | |
2823 | pl08x->slave.filter.mapcnt = pl08x->pd->slave_map_len; | |
2824 | pl08x->slave.filter.fn = pl08x_filter_fn; | |
e8689e63 LW |
2825 | } |
2826 | ||
30749cb4 RKAL |
2827 | /* By default, AHB1 only. If dualmaster, from platform */ |
2828 | pl08x->lli_buses = PL08X_AHB1; | |
2829 | pl08x->mem_buses = PL08X_AHB1; | |
2830 | if (pl08x->vd->dualmaster) { | |
2831 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
2832 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
2833 | } | |
2834 | ||
da1b6c05 TF |
2835 | if (vd->pl080s) |
2836 | pl08x->lli_words = PL080S_LLI_WORDS; | |
2837 | else | |
2838 | pl08x->lli_words = PL080_LLI_WORDS; | |
ba6785ff TF |
2839 | tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32); |
2840 | ||
e8689e63 LW |
2841 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
2842 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
ba6785ff | 2843 | tsfr_size, PL08X_ALIGN, 0); |
e8689e63 LW |
2844 | if (!pl08x->pool) { |
2845 | ret = -ENOMEM; | |
2846 | goto out_no_lli_pool; | |
2847 | } | |
2848 | ||
e8689e63 LW |
2849 | /* Turn on the PL08x */ |
2850 | pl08x_ensure_on(pl08x); | |
2851 | ||
1e1cfc72 LW |
2852 | /* Clear any pending interrupts */ |
2853 | if (vd->ftdmac020) | |
2854 | /* This variant has error IRQs in bits 16-19 */ | |
2855 | writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR); | |
2856 | else | |
2857 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); | |
e8689e63 LW |
2858 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); |
2859 | ||
1e1cfc72 | 2860 | /* Attach the interrupt handler */ |
174b537a | 2861 | ret = request_irq(adev->irq[0], pl08x_irq, 0, DRIVER_NAME, pl08x); |
e8689e63 LW |
2862 | if (ret) { |
2863 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
2864 | __func__, adev->irq[0]); | |
2865 | goto out_no_irq; | |
2866 | } | |
2867 | ||
2868 | /* Initialize physical channels */ | |
affa115e | 2869 | pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
2870 | GFP_KERNEL); |
2871 | if (!pl08x->phy_chans) { | |
983d7beb | 2872 | ret = -ENOMEM; |
e8689e63 LW |
2873 | goto out_no_phychans; |
2874 | } | |
2875 | ||
2876 | for (i = 0; i < vd->channels; i++) { | |
2877 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
2878 | ||
2879 | ch->id = i; | |
2880 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
1e1cfc72 LW |
2881 | if (vd->ftdmac020) { |
2882 | /* FTDMA020 has a special channel busy register */ | |
2883 | ch->reg_busy = ch->base + FTDMAC020_CH_BUSY; | |
2884 | ch->reg_config = ch->base + FTDMAC020_CH_CFG; | |
2885 | ch->reg_control = ch->base + FTDMAC020_CH_CSR; | |
2886 | ch->reg_src = ch->base + FTDMAC020_CH_SRC_ADDR; | |
2887 | ch->reg_dst = ch->base + FTDMAC020_CH_DST_ADDR; | |
2888 | ch->reg_lli = ch->base + FTDMAC020_CH_LLP; | |
2889 | ch->ftdmac020 = true; | |
2890 | } else { | |
2891 | ch->reg_config = ch->base + vd->config_offset; | |
2892 | ch->reg_control = ch->base + PL080_CH_CONTROL; | |
2893 | ch->reg_src = ch->base + PL080_CH_SRC_ADDR; | |
2894 | ch->reg_dst = ch->base + PL080_CH_DST_ADDR; | |
2895 | ch->reg_lli = ch->base + PL080_CH_LLI; | |
2896 | } | |
2897 | if (vd->pl080s) | |
2898 | ch->pl080s = true; | |
2899 | ||
e8689e63 | 2900 | spin_lock_init(&ch->lock); |
affa115e LW |
2901 | |
2902 | /* | |
2903 | * Nomadik variants can have channels that are locked | |
2904 | * down for the secure world only. Lock up these channels | |
2905 | * by perpetually serving a dummy virtual channel. | |
2906 | */ | |
2907 | if (vd->nomadik) { | |
2908 | u32 val; | |
2909 | ||
d86ccea7 | 2910 | val = readl(ch->reg_config); |
affa115e LW |
2911 | if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { |
2912 | dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); | |
2913 | ch->locked = true; | |
2914 | } | |
2915 | } | |
2916 | ||
175a5e61 VK |
2917 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
2918 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
2919 | } |
2920 | ||
2921 | /* Register as many memcpy channels as there are physical channels */ | |
2922 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
2923 | pl08x->vd->channels, false); | |
2924 | if (ret <= 0) { | |
2925 | dev_warn(&pl08x->adev->dev, | |
2926 | "%s failed to enumerate memcpy channels - %d\n", | |
2927 | __func__, ret); | |
2928 | goto out_no_memcpy; | |
2929 | } | |
e8689e63 LW |
2930 | |
2931 | /* Register slave channels */ | |
ebe9b300 LW |
2932 | if (pl08x->has_slave) { |
2933 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
2934 | pl08x->pd->num_slave_channels, true); | |
2935 | if (ret < 0) { | |
2936 | dev_warn(&pl08x->adev->dev, | |
2937 | "%s failed to enumerate slave channels - %d\n", | |
2938 | __func__, ret); | |
2939 | goto out_no_slave; | |
2940 | } | |
e8689e63 | 2941 | } |
e8689e63 LW |
2942 | |
2943 | ret = dma_async_device_register(&pl08x->memcpy); | |
2944 | if (ret) { | |
2945 | dev_warn(&pl08x->adev->dev, | |
2946 | "%s failed to register memcpy as an async device - %d\n", | |
2947 | __func__, ret); | |
2948 | goto out_no_memcpy_reg; | |
2949 | } | |
2950 | ||
ebe9b300 LW |
2951 | if (pl08x->has_slave) { |
2952 | ret = dma_async_device_register(&pl08x->slave); | |
2953 | if (ret) { | |
2954 | dev_warn(&pl08x->adev->dev, | |
e8689e63 LW |
2955 | "%s failed to register slave as an async device - %d\n", |
2956 | __func__, ret); | |
ebe9b300 LW |
2957 | goto out_no_slave_reg; |
2958 | } | |
e8689e63 LW |
2959 | } |
2960 | ||
2961 | amba_set_drvdata(adev, pl08x); | |
2962 | init_pl08x_debugfs(pl08x); | |
da1b6c05 TF |
2963 | dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n", |
2964 | amba_part(adev), pl08x->vd->pl080s ? "s" : "", amba_rev(adev), | |
b05cd8f4 | 2965 | (unsigned long long)adev->res.start, adev->irq[0]); |
b7b6018b | 2966 | |
e8689e63 LW |
2967 | return 0; |
2968 | ||
2969 | out_no_slave_reg: | |
2970 | dma_async_device_unregister(&pl08x->memcpy); | |
2971 | out_no_memcpy_reg: | |
ebe9b300 LW |
2972 | if (pl08x->has_slave) |
2973 | pl08x_free_virtual_channels(&pl08x->slave); | |
e8689e63 LW |
2974 | out_no_slave: |
2975 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2976 | out_no_memcpy: | |
2977 | kfree(pl08x->phy_chans); | |
2978 | out_no_phychans: | |
2979 | free_irq(adev->irq[0], pl08x); | |
2980 | out_no_irq: | |
e8689e63 LW |
2981 | dma_pool_destroy(pl08x->pool); |
2982 | out_no_lli_pool: | |
2983 | out_no_platdata: | |
1e1cfc72 LW |
2984 | iounmap(pl08x->base); |
2985 | out_no_ioremap: | |
e8689e63 LW |
2986 | kfree(pl08x); |
2987 | out_no_pl08x: | |
2988 | amba_release_regions(adev); | |
2989 | return ret; | |
2990 | } | |
2991 | ||
2992 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2993 | static struct vendor_data vendor_pl080 = { | |
d86ccea7 | 2994 | .config_offset = PL080_CH_CONFIG, |
e8689e63 | 2995 | .channels = 8, |
f9cd4761 | 2996 | .signals = 16, |
e8689e63 | 2997 | .dualmaster = true, |
5110e51d | 2998 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
e8689e63 LW |
2999 | }; |
3000 | ||
affa115e | 3001 | static struct vendor_data vendor_nomadik = { |
d86ccea7 | 3002 | .config_offset = PL080_CH_CONFIG, |
affa115e | 3003 | .channels = 8, |
f9cd4761 | 3004 | .signals = 32, |
affa115e LW |
3005 | .dualmaster = true, |
3006 | .nomadik = true, | |
5110e51d | 3007 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
affa115e LW |
3008 | }; |
3009 | ||
da1b6c05 TF |
3010 | static struct vendor_data vendor_pl080s = { |
3011 | .config_offset = PL080S_CH_CONFIG, | |
3012 | .channels = 8, | |
f9cd4761 | 3013 | .signals = 32, |
da1b6c05 | 3014 | .pl080s = true, |
5110e51d | 3015 | .max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK, |
affa115e LW |
3016 | }; |
3017 | ||
e8689e63 | 3018 | static struct vendor_data vendor_pl081 = { |
d86ccea7 | 3019 | .config_offset = PL080_CH_CONFIG, |
e8689e63 | 3020 | .channels = 2, |
f9cd4761 | 3021 | .signals = 16, |
e8689e63 | 3022 | .dualmaster = false, |
5110e51d | 3023 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, |
e8689e63 LW |
3024 | }; |
3025 | ||
1e1cfc72 LW |
3026 | static struct vendor_data vendor_ftdmac020 = { |
3027 | .config_offset = PL080_CH_CONFIG, | |
3028 | .ftdmac020 = true, | |
3029 | .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK, | |
3030 | }; | |
3031 | ||
b80fa121 | 3032 | static const struct amba_id pl08x_ids[] = { |
da1b6c05 TF |
3033 | /* Samsung PL080S variant */ |
3034 | { | |
3035 | .id = 0x0a141080, | |
3036 | .mask = 0xffffffff, | |
3037 | .data = &vendor_pl080s, | |
3038 | }, | |
e8689e63 LW |
3039 | /* PL080 */ |
3040 | { | |
3041 | .id = 0x00041080, | |
3042 | .mask = 0x000fffff, | |
3043 | .data = &vendor_pl080, | |
3044 | }, | |
3045 | /* PL081 */ | |
3046 | { | |
3047 | .id = 0x00041081, | |
3048 | .mask = 0x000fffff, | |
3049 | .data = &vendor_pl081, | |
3050 | }, | |
3051 | /* Nomadik 8815 PL080 variant */ | |
3052 | { | |
affa115e | 3053 | .id = 0x00280080, |
e8689e63 | 3054 | .mask = 0x00ffffff, |
affa115e | 3055 | .data = &vendor_nomadik, |
e8689e63 | 3056 | }, |
1e1cfc72 LW |
3057 | /* Faraday Technology FTDMAC020 */ |
3058 | { | |
3059 | .id = 0x0003b080, | |
3060 | .mask = 0x000fffff, | |
3061 | .data = &vendor_ftdmac020, | |
3062 | }, | |
e8689e63 LW |
3063 | { 0, 0 }, |
3064 | }; | |
3065 | ||
037566df DM |
3066 | MODULE_DEVICE_TABLE(amba, pl08x_ids); |
3067 | ||
e8689e63 LW |
3068 | static struct amba_driver pl08x_amba_driver = { |
3069 | .drv.name = DRIVER_NAME, | |
3070 | .id_table = pl08x_ids, | |
3071 | .probe = pl08x_probe, | |
3072 | }; | |
3073 | ||
3074 | static int __init pl08x_init(void) | |
3075 | { | |
3076 | int retval; | |
3077 | retval = amba_driver_register(&pl08x_amba_driver); | |
3078 | if (retval) | |
3079 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 3080 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
3081 | retval); |
3082 | return retval; | |
3083 | } | |
3084 | subsys_initcall(pl08x_init); |