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6234f380 TV |
1 | /* |
2 | * A devfreq driver for NVIDIA Tegra SoCs | |
3 | * | |
4 | * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved. | |
5 | * Copyright (C) 2014 Google, Inc | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/cpufreq.h> | |
23 | #include <linux/devfreq.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/module.h> | |
ac316725 | 27 | #include <linux/mod_devicetable.h> |
6234f380 TV |
28 | #include <linux/platform_device.h> |
29 | #include <linux/pm_opp.h> | |
30 | #include <linux/reset.h> | |
31 | ||
32 | #include "governor.h" | |
33 | ||
34 | #define ACTMON_GLB_STATUS 0x0 | |
35 | #define ACTMON_GLB_PERIOD_CTRL 0x4 | |
36 | ||
37 | #define ACTMON_DEV_CTRL 0x0 | |
38 | #define ACTMON_DEV_CTRL_K_VAL_SHIFT 10 | |
39 | #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18) | |
40 | #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20) | |
41 | #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21) | |
42 | #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT 23 | |
43 | #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT 26 | |
44 | #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29) | |
45 | #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30) | |
46 | #define ACTMON_DEV_CTRL_ENB BIT(31) | |
47 | ||
48 | #define ACTMON_DEV_UPPER_WMARK 0x4 | |
49 | #define ACTMON_DEV_LOWER_WMARK 0x8 | |
50 | #define ACTMON_DEV_INIT_AVG 0xc | |
51 | #define ACTMON_DEV_AVG_UPPER_WMARK 0x10 | |
52 | #define ACTMON_DEV_AVG_LOWER_WMARK 0x14 | |
53 | #define ACTMON_DEV_COUNT_WEIGHT 0x18 | |
54 | #define ACTMON_DEV_AVG_COUNT 0x20 | |
55 | #define ACTMON_DEV_INTR_STATUS 0x24 | |
56 | ||
57 | #define ACTMON_INTR_STATUS_CLEAR 0xffffffff | |
58 | ||
59 | #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31) | |
60 | #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30) | |
61 | ||
62 | #define ACTMON_ABOVE_WMARK_WINDOW 1 | |
63 | #define ACTMON_BELOW_WMARK_WINDOW 3 | |
64 | #define ACTMON_BOOST_FREQ_STEP 16000 | |
65 | ||
11573e91 TV |
66 | /* |
67 | * Activity counter is incremented every 256 memory transactions, and each | |
6234f380 TV |
68 | * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is |
69 | * 4 * 256 = 1024. | |
70 | */ | |
71 | #define ACTMON_COUNT_WEIGHT 0x400 | |
72 | ||
73 | /* | |
74 | * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which | |
75 | * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128 | |
76 | */ | |
77 | #define ACTMON_AVERAGE_WINDOW_LOG2 6 | |
78 | #define ACTMON_SAMPLING_PERIOD 12 /* ms */ | |
79 | #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */ | |
80 | ||
81 | #define KHZ 1000 | |
82 | ||
83 | /* Assume that the bus is saturated if the utilization is 25% */ | |
84 | #define BUS_SATURATION_RATIO 25 | |
85 | ||
86 | /** | |
87 | * struct tegra_devfreq_device_config - configuration specific to an ACTMON | |
88 | * device | |
89 | * | |
11573e91 | 90 | * Coefficients and thresholds are percentages unless otherwise noted |
6234f380 TV |
91 | */ |
92 | struct tegra_devfreq_device_config { | |
93 | u32 offset; | |
94 | u32 irq_mask; | |
95 | ||
11573e91 | 96 | /* Factors applied to boost_freq every consecutive watermark breach */ |
6234f380 TV |
97 | unsigned int boost_up_coeff; |
98 | unsigned int boost_down_coeff; | |
11573e91 TV |
99 | |
100 | /* Define the watermark bounds when applied to the current avg */ | |
6234f380 TV |
101 | unsigned int boost_up_threshold; |
102 | unsigned int boost_down_threshold; | |
11573e91 TV |
103 | |
104 | /* | |
105 | * Threshold of activity (cycles) below which the CPU frequency isn't | |
106 | * to be taken into account. This is to avoid increasing the EMC | |
107 | * frequency when the CPU is very busy but not accessing the bus often. | |
108 | */ | |
6234f380 TV |
109 | u32 avg_dependency_threshold; |
110 | }; | |
111 | ||
112 | enum tegra_actmon_device { | |
113 | MCALL = 0, | |
114 | MCCPU, | |
115 | }; | |
116 | ||
117 | static struct tegra_devfreq_device_config actmon_device_configs[] = { | |
118 | { | |
11573e91 | 119 | /* MCALL: All memory accesses (including from the CPUs) */ |
6234f380 TV |
120 | .offset = 0x1c0, |
121 | .irq_mask = 1 << 26, | |
122 | .boost_up_coeff = 200, | |
123 | .boost_down_coeff = 50, | |
124 | .boost_up_threshold = 60, | |
125 | .boost_down_threshold = 40, | |
126 | }, | |
127 | { | |
11573e91 | 128 | /* MCCPU: memory accesses from the CPUs */ |
6234f380 TV |
129 | .offset = 0x200, |
130 | .irq_mask = 1 << 25, | |
131 | .boost_up_coeff = 800, | |
132 | .boost_down_coeff = 90, | |
133 | .boost_up_threshold = 27, | |
134 | .boost_down_threshold = 10, | |
135 | .avg_dependency_threshold = 50000, | |
136 | }, | |
137 | }; | |
138 | ||
139 | /** | |
140 | * struct tegra_devfreq_device - state specific to an ACTMON device | |
141 | * | |
142 | * Frequencies are in kHz. | |
143 | */ | |
144 | struct tegra_devfreq_device { | |
145 | const struct tegra_devfreq_device_config *config; | |
11573e91 TV |
146 | void __iomem *regs; |
147 | spinlock_t lock; | |
6234f380 | 148 | |
11573e91 TV |
149 | /* Average event count sampled in the last interrupt */ |
150 | u32 avg_count; | |
6234f380 | 151 | |
11573e91 TV |
152 | /* |
153 | * Extra frequency to increase the target by due to consecutive | |
154 | * watermark breaches. | |
155 | */ | |
156 | unsigned long boost_freq; | |
157 | ||
158 | /* Optimal frequency calculated from the stats for this device */ | |
159 | unsigned long target_freq; | |
6234f380 TV |
160 | }; |
161 | ||
162 | struct tegra_devfreq { | |
163 | struct devfreq *devfreq; | |
164 | ||
6234f380 TV |
165 | struct reset_control *reset; |
166 | struct clk *clock; | |
167 | void __iomem *regs; | |
168 | ||
6234f380 TV |
169 | struct clk *emc_clock; |
170 | unsigned long max_freq; | |
171 | unsigned long cur_freq; | |
172 | struct notifier_block rate_change_nb; | |
173 | ||
174 | struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)]; | |
175 | }; | |
176 | ||
177 | struct tegra_actmon_emc_ratio { | |
178 | unsigned long cpu_freq; | |
179 | unsigned long emc_freq; | |
180 | }; | |
181 | ||
182 | static struct tegra_actmon_emc_ratio actmon_emc_ratios[] = { | |
183 | { 1400000, ULONG_MAX }, | |
184 | { 1200000, 750000 }, | |
185 | { 1100000, 600000 }, | |
186 | { 1000000, 500000 }, | |
187 | { 800000, 375000 }, | |
188 | { 500000, 200000 }, | |
189 | { 250000, 100000 }, | |
190 | }; | |
191 | ||
11573e91 TV |
192 | static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset) |
193 | { | |
194 | return readl(tegra->regs + offset); | |
195 | } | |
196 | ||
197 | static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset) | |
198 | { | |
199 | writel(val, tegra->regs + offset); | |
200 | } | |
201 | ||
202 | static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset) | |
203 | { | |
204 | return readl(dev->regs + offset); | |
205 | } | |
206 | ||
207 | static void device_writel(struct tegra_devfreq_device *dev, u32 val, | |
208 | u32 offset) | |
209 | { | |
210 | writel(val, dev->regs + offset); | |
211 | } | |
212 | ||
6234f380 TV |
213 | static unsigned long do_percent(unsigned long val, unsigned int pct) |
214 | { | |
215 | return val * pct / 100; | |
216 | } | |
217 | ||
11573e91 TV |
218 | static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra, |
219 | struct tegra_devfreq_device *dev) | |
6234f380 TV |
220 | { |
221 | u32 avg = dev->avg_count; | |
11573e91 TV |
222 | u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; |
223 | u32 band = avg_band_freq * ACTMON_SAMPLING_PERIOD; | |
224 | ||
225 | device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK); | |
6234f380 | 226 | |
11573e91 TV |
227 | avg = max(dev->avg_count, band); |
228 | device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK); | |
6234f380 TV |
229 | } |
230 | ||
231 | static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra, | |
232 | struct tegra_devfreq_device *dev) | |
233 | { | |
234 | u32 val = tegra->cur_freq * ACTMON_SAMPLING_PERIOD; | |
235 | ||
11573e91 TV |
236 | device_writel(dev, do_percent(val, dev->config->boost_up_threshold), |
237 | ACTMON_DEV_UPPER_WMARK); | |
6234f380 | 238 | |
11573e91 TV |
239 | device_writel(dev, do_percent(val, dev->config->boost_down_threshold), |
240 | ACTMON_DEV_LOWER_WMARK); | |
6234f380 TV |
241 | } |
242 | ||
243 | static void actmon_write_barrier(struct tegra_devfreq *tegra) | |
244 | { | |
245 | /* ensure the update has reached the ACTMON */ | |
246 | wmb(); | |
11573e91 | 247 | actmon_readl(tegra, ACTMON_GLB_STATUS); |
6234f380 TV |
248 | } |
249 | ||
11573e91 TV |
250 | static void actmon_isr_device(struct tegra_devfreq *tegra, |
251 | struct tegra_devfreq_device *dev) | |
6234f380 | 252 | { |
6234f380 | 253 | unsigned long flags; |
11573e91 | 254 | u32 intr_status, dev_ctrl; |
6234f380 | 255 | |
11573e91 | 256 | spin_lock_irqsave(&dev->lock, flags); |
6234f380 | 257 | |
11573e91 TV |
258 | dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT); |
259 | tegra_devfreq_update_avg_wmark(tegra, dev); | |
6234f380 | 260 | |
11573e91 TV |
261 | intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS); |
262 | dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL); | |
6234f380 | 263 | |
11573e91 | 264 | if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) { |
6234f380 TV |
265 | /* |
266 | * new_boost = min(old_boost * up_coef + step, max_freq) | |
267 | */ | |
268 | dev->boost_freq = do_percent(dev->boost_freq, | |
269 | dev->config->boost_up_coeff); | |
270 | dev->boost_freq += ACTMON_BOOST_FREQ_STEP; | |
6234f380 | 271 | |
11573e91 TV |
272 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
273 | ||
274 | if (dev->boost_freq >= tegra->max_freq) | |
275 | dev->boost_freq = tegra->max_freq; | |
276 | else | |
277 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
278 | } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) { | |
6234f380 TV |
279 | /* |
280 | * new_boost = old_boost * down_coef | |
281 | * or 0 if (old_boost * down_coef < step / 2) | |
282 | */ | |
283 | dev->boost_freq = do_percent(dev->boost_freq, | |
284 | dev->config->boost_down_coeff); | |
11573e91 TV |
285 | |
286 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
287 | ||
288 | if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1)) | |
6234f380 | 289 | dev->boost_freq = 0; |
11573e91 TV |
290 | else |
291 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
6234f380 TV |
292 | } |
293 | ||
294 | if (dev->config->avg_dependency_threshold) { | |
6234f380 | 295 | if (dev->avg_count >= dev->config->avg_dependency_threshold) |
11573e91 | 296 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
6234f380 | 297 | else if (dev->boost_freq == 0) |
11573e91 | 298 | dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
6234f380 TV |
299 | } |
300 | ||
11573e91 TV |
301 | device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL); |
302 | ||
303 | device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); | |
6234f380 TV |
304 | |
305 | actmon_write_barrier(tegra); | |
306 | ||
11573e91 TV |
307 | spin_unlock_irqrestore(&dev->lock, flags); |
308 | } | |
6234f380 | 309 | |
11573e91 TV |
310 | static irqreturn_t actmon_isr(int irq, void *data) |
311 | { | |
312 | struct tegra_devfreq *tegra = data; | |
313 | bool handled = false; | |
314 | unsigned int i; | |
315 | u32 val; | |
316 | ||
317 | val = actmon_readl(tegra, ACTMON_GLB_STATUS); | |
318 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
319 | if (val & tegra->devices[i].config->irq_mask) { | |
320 | actmon_isr_device(tegra, tegra->devices + i); | |
321 | handled = true; | |
322 | } | |
323 | } | |
324 | ||
325 | return handled ? IRQ_WAKE_THREAD : IRQ_NONE; | |
6234f380 TV |
326 | } |
327 | ||
328 | static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra, | |
329 | unsigned long cpu_freq) | |
330 | { | |
331 | unsigned int i; | |
332 | struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios; | |
333 | ||
334 | for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) { | |
335 | if (cpu_freq >= ratio->cpu_freq) { | |
336 | if (ratio->emc_freq >= tegra->max_freq) | |
337 | return tegra->max_freq; | |
338 | else | |
339 | return ratio->emc_freq; | |
340 | } | |
341 | } | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static void actmon_update_target(struct tegra_devfreq *tegra, | |
347 | struct tegra_devfreq_device *dev) | |
348 | { | |
349 | unsigned long cpu_freq = 0; | |
350 | unsigned long static_cpu_emc_freq = 0; | |
351 | unsigned int avg_sustain_coef; | |
352 | unsigned long flags; | |
353 | ||
354 | if (dev->config->avg_dependency_threshold) { | |
355 | cpu_freq = cpufreq_get(0); | |
356 | static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq); | |
357 | } | |
358 | ||
11573e91 | 359 | spin_lock_irqsave(&dev->lock, flags); |
6234f380 TV |
360 | |
361 | dev->target_freq = dev->avg_count / ACTMON_SAMPLING_PERIOD; | |
362 | avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold; | |
363 | dev->target_freq = do_percent(dev->target_freq, avg_sustain_coef); | |
364 | dev->target_freq += dev->boost_freq; | |
365 | ||
366 | if (dev->avg_count >= dev->config->avg_dependency_threshold) | |
367 | dev->target_freq = max(dev->target_freq, static_cpu_emc_freq); | |
368 | ||
11573e91 | 369 | spin_unlock_irqrestore(&dev->lock, flags); |
6234f380 TV |
370 | } |
371 | ||
372 | static irqreturn_t actmon_thread_isr(int irq, void *data) | |
373 | { | |
374 | struct tegra_devfreq *tegra = data; | |
375 | ||
376 | mutex_lock(&tegra->devfreq->lock); | |
377 | update_devfreq(tegra->devfreq); | |
378 | mutex_unlock(&tegra->devfreq->lock); | |
379 | ||
380 | return IRQ_HANDLED; | |
381 | } | |
382 | ||
383 | static int tegra_actmon_rate_notify_cb(struct notifier_block *nb, | |
384 | unsigned long action, void *ptr) | |
385 | { | |
386 | struct clk_notifier_data *data = ptr; | |
11573e91 TV |
387 | struct tegra_devfreq *tegra; |
388 | struct tegra_devfreq_device *dev; | |
6234f380 TV |
389 | unsigned int i; |
390 | unsigned long flags; | |
391 | ||
11573e91 TV |
392 | if (action != POST_RATE_CHANGE) |
393 | return NOTIFY_OK; | |
6234f380 | 394 | |
11573e91 | 395 | tegra = container_of(nb, struct tegra_devfreq, rate_change_nb); |
6234f380 | 396 | |
11573e91 | 397 | tegra->cur_freq = data->new_rate / KHZ; |
6234f380 | 398 | |
11573e91 TV |
399 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { |
400 | dev = &tegra->devices[i]; | |
401 | ||
402 | spin_lock_irqsave(&dev->lock, flags); | |
403 | tegra_devfreq_update_wmark(tegra, dev); | |
404 | spin_unlock_irqrestore(&dev->lock, flags); | |
405 | } | |
6234f380 | 406 | |
11573e91 | 407 | actmon_write_barrier(tegra); |
6234f380 TV |
408 | |
409 | return NOTIFY_OK; | |
410 | } | |
411 | ||
11573e91 | 412 | static void tegra_actmon_enable_interrupts(struct tegra_devfreq *tegra) |
6234f380 | 413 | { |
11573e91 | 414 | struct tegra_devfreq_device *dev; |
6234f380 | 415 | u32 val; |
11573e91 | 416 | unsigned int i; |
6234f380 | 417 | |
11573e91 TV |
418 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { |
419 | dev = &tegra->devices[i]; | |
6234f380 | 420 | |
11573e91 TV |
421 | val = device_readl(dev, ACTMON_DEV_CTRL); |
422 | val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN; | |
423 | val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN; | |
424 | val |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
425 | val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
6234f380 | 426 | |
11573e91 TV |
427 | device_writel(dev, val, ACTMON_DEV_CTRL); |
428 | } | |
6234f380 TV |
429 | |
430 | actmon_write_barrier(tegra); | |
431 | } | |
432 | ||
11573e91 | 433 | static void tegra_actmon_disable_interrupts(struct tegra_devfreq *tegra) |
6234f380 | 434 | { |
11573e91 | 435 | struct tegra_devfreq_device *dev; |
6234f380 | 436 | u32 val; |
11573e91 | 437 | unsigned int i; |
6234f380 TV |
438 | |
439 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
11573e91 | 440 | dev = &tegra->devices[i]; |
6234f380 | 441 | |
11573e91 TV |
442 | val = device_readl(dev, ACTMON_DEV_CTRL); |
443 | val &= ~ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN; | |
444 | val &= ~ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN; | |
445 | val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
446 | val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
6234f380 | 447 | |
11573e91 | 448 | device_writel(dev, val, ACTMON_DEV_CTRL); |
6234f380 TV |
449 | } |
450 | ||
11573e91 | 451 | actmon_write_barrier(tegra); |
6234f380 TV |
452 | } |
453 | ||
11573e91 TV |
454 | static void tegra_actmon_configure_device(struct tegra_devfreq *tegra, |
455 | struct tegra_devfreq_device *dev) | |
6234f380 | 456 | { |
11573e91 | 457 | u32 val = 0; |
6234f380 | 458 | |
11573e91 | 459 | dev->target_freq = tegra->cur_freq; |
6234f380 | 460 | |
11573e91 TV |
461 | dev->avg_count = tegra->cur_freq * ACTMON_SAMPLING_PERIOD; |
462 | device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG); | |
6234f380 | 463 | |
11573e91 TV |
464 | tegra_devfreq_update_avg_wmark(tegra, dev); |
465 | tegra_devfreq_update_wmark(tegra, dev); | |
6234f380 | 466 | |
11573e91 TV |
467 | device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT); |
468 | device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); | |
469 | ||
470 | val |= ACTMON_DEV_CTRL_ENB_PERIODIC; | |
471 | val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1) | |
472 | << ACTMON_DEV_CTRL_K_VAL_SHIFT; | |
473 | val |= (ACTMON_BELOW_WMARK_WINDOW - 1) | |
474 | << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT; | |
475 | val |= (ACTMON_ABOVE_WMARK_WINDOW - 1) | |
476 | << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT; | |
477 | val |= ACTMON_DEV_CTRL_ENB; | |
478 | ||
479 | device_writel(dev, val, ACTMON_DEV_CTRL); | |
480 | ||
481 | actmon_write_barrier(tegra); | |
6234f380 TV |
482 | } |
483 | ||
484 | static int tegra_devfreq_target(struct device *dev, unsigned long *freq, | |
485 | u32 flags) | |
486 | { | |
11573e91 | 487 | struct tegra_devfreq *tegra = dev_get_drvdata(dev); |
6234f380 TV |
488 | struct dev_pm_opp *opp; |
489 | unsigned long rate = *freq * KHZ; | |
490 | ||
6234f380 TV |
491 | opp = devfreq_recommended_opp(dev, &rate, flags); |
492 | if (IS_ERR(opp)) { | |
6234f380 TV |
493 | dev_err(dev, "Failed to find opp for %lu KHz\n", *freq); |
494 | return PTR_ERR(opp); | |
495 | } | |
496 | rate = dev_pm_opp_get_freq(opp); | |
8a31d9d9 | 497 | dev_pm_opp_put(opp); |
6234f380 | 498 | |
c70eea73 TV |
499 | clk_set_min_rate(tegra->emc_clock, rate); |
500 | clk_set_rate(tegra->emc_clock, 0); | |
6234f380 | 501 | |
dbb0c7c4 TV |
502 | *freq = rate; |
503 | ||
6234f380 TV |
504 | return 0; |
505 | } | |
506 | ||
507 | static int tegra_devfreq_get_dev_status(struct device *dev, | |
508 | struct devfreq_dev_status *stat) | |
509 | { | |
11573e91 | 510 | struct tegra_devfreq *tegra = dev_get_drvdata(dev); |
6234f380 TV |
511 | struct tegra_devfreq_device *actmon_dev; |
512 | ||
6234f380 TV |
513 | stat->current_frequency = tegra->cur_freq; |
514 | ||
515 | /* To be used by the tegra governor */ | |
516 | stat->private_data = tegra; | |
517 | ||
518 | /* The below are to be used by the other governors */ | |
519 | ||
520 | actmon_dev = &tegra->devices[MCALL]; | |
521 | ||
522 | /* Number of cycles spent on memory access */ | |
11573e91 | 523 | stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT); |
6234f380 TV |
524 | |
525 | /* The bus can be considered to be saturated way before 100% */ | |
526 | stat->busy_time *= 100 / BUS_SATURATION_RATIO; | |
527 | ||
528 | /* Number of cycles in a sampling period */ | |
529 | stat->total_time = ACTMON_SAMPLING_PERIOD * tegra->cur_freq; | |
530 | ||
11573e91 TV |
531 | stat->busy_time = min(stat->busy_time, stat->total_time); |
532 | ||
6234f380 TV |
533 | return 0; |
534 | } | |
535 | ||
11573e91 TV |
536 | static struct devfreq_dev_profile tegra_devfreq_profile = { |
537 | .polling_ms = 0, | |
538 | .target = tegra_devfreq_target, | |
539 | .get_dev_status = tegra_devfreq_get_dev_status, | |
540 | }; | |
541 | ||
542 | static int tegra_governor_get_target(struct devfreq *devfreq, | |
543 | unsigned long *freq) | |
6234f380 | 544 | { |
14de3903 | 545 | struct devfreq_dev_status *stat; |
6234f380 TV |
546 | struct tegra_devfreq *tegra; |
547 | struct tegra_devfreq_device *dev; | |
548 | unsigned long target_freq = 0; | |
549 | unsigned int i; | |
550 | int err; | |
551 | ||
14de3903 | 552 | err = devfreq_update_stats(devfreq); |
6234f380 TV |
553 | if (err) |
554 | return err; | |
555 | ||
14de3903 MH |
556 | stat = &devfreq->last_status; |
557 | ||
558 | tegra = stat->private_data; | |
6234f380 TV |
559 | |
560 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
561 | dev = &tegra->devices[i]; | |
562 | ||
563 | actmon_update_target(tegra, dev); | |
564 | ||
565 | target_freq = max(target_freq, dev->target_freq); | |
566 | } | |
567 | ||
568 | *freq = target_freq; | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
11573e91 TV |
573 | static int tegra_governor_event_handler(struct devfreq *devfreq, |
574 | unsigned int event, void *data) | |
6234f380 | 575 | { |
11573e91 TV |
576 | struct tegra_devfreq *tegra; |
577 | int ret = 0; | |
578 | ||
579 | tegra = dev_get_drvdata(devfreq->dev.parent); | |
580 | ||
581 | switch (event) { | |
582 | case DEVFREQ_GOV_START: | |
11573e91 | 583 | devfreq_monitor_start(devfreq); |
34ed5040 | 584 | tegra_actmon_enable_interrupts(tegra); |
11573e91 TV |
585 | break; |
586 | ||
587 | case DEVFREQ_GOV_STOP: | |
588 | tegra_actmon_disable_interrupts(tegra); | |
589 | devfreq_monitor_stop(devfreq); | |
590 | break; | |
591 | ||
592 | case DEVFREQ_GOV_SUSPEND: | |
593 | tegra_actmon_disable_interrupts(tegra); | |
594 | devfreq_monitor_suspend(devfreq); | |
595 | break; | |
596 | ||
597 | case DEVFREQ_GOV_RESUME: | |
11573e91 | 598 | devfreq_monitor_resume(devfreq); |
34ed5040 | 599 | tegra_actmon_enable_interrupts(tegra); |
11573e91 TV |
600 | break; |
601 | } | |
602 | ||
603 | return ret; | |
6234f380 TV |
604 | } |
605 | ||
606 | static struct devfreq_governor tegra_devfreq_governor = { | |
11573e91 TV |
607 | .name = "tegra_actmon", |
608 | .get_target_freq = tegra_governor_get_target, | |
609 | .event_handler = tegra_governor_event_handler, | |
6234f380 TV |
610 | }; |
611 | ||
6234f380 TV |
612 | static int tegra_devfreq_probe(struct platform_device *pdev) |
613 | { | |
614 | struct tegra_devfreq *tegra; | |
615 | struct tegra_devfreq_device *dev; | |
616 | struct resource *res; | |
6234f380 | 617 | unsigned int i; |
5d498b46 | 618 | unsigned long rate; |
6234f380 TV |
619 | int irq; |
620 | int err; | |
621 | ||
622 | tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); | |
623 | if (!tegra) | |
624 | return -ENOMEM; | |
625 | ||
6234f380 | 626 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
6234f380 TV |
627 | |
628 | tegra->regs = devm_ioremap_resource(&pdev->dev, res); | |
11573e91 | 629 | if (IS_ERR(tegra->regs)) |
6234f380 | 630 | return PTR_ERR(tegra->regs); |
6234f380 TV |
631 | |
632 | tegra->reset = devm_reset_control_get(&pdev->dev, "actmon"); | |
633 | if (IS_ERR(tegra->reset)) { | |
634 | dev_err(&pdev->dev, "Failed to get reset\n"); | |
635 | return PTR_ERR(tegra->reset); | |
636 | } | |
637 | ||
638 | tegra->clock = devm_clk_get(&pdev->dev, "actmon"); | |
639 | if (IS_ERR(tegra->clock)) { | |
640 | dev_err(&pdev->dev, "Failed to get actmon clock\n"); | |
641 | return PTR_ERR(tegra->clock); | |
642 | } | |
643 | ||
644 | tegra->emc_clock = devm_clk_get(&pdev->dev, "emc"); | |
645 | if (IS_ERR(tegra->emc_clock)) { | |
646 | dev_err(&pdev->dev, "Failed to get emc clock\n"); | |
647 | return PTR_ERR(tegra->emc_clock); | |
648 | } | |
649 | ||
c70eea73 TV |
650 | clk_set_rate(tegra->emc_clock, ULONG_MAX); |
651 | ||
6234f380 TV |
652 | tegra->rate_change_nb.notifier_call = tegra_actmon_rate_notify_cb; |
653 | err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb); | |
654 | if (err) { | |
655 | dev_err(&pdev->dev, | |
656 | "Failed to register rate change notifier\n"); | |
657 | return err; | |
658 | } | |
659 | ||
660 | reset_control_assert(tegra->reset); | |
661 | ||
662 | err = clk_prepare_enable(tegra->clock); | |
663 | if (err) { | |
11573e91 TV |
664 | dev_err(&pdev->dev, |
665 | "Failed to prepare and enable ACTMON clock\n"); | |
6234f380 TV |
666 | return err; |
667 | } | |
668 | ||
669 | reset_control_deassert(tegra->reset); | |
670 | ||
c70eea73 | 671 | tegra->max_freq = clk_round_rate(tegra->emc_clock, ULONG_MAX) / KHZ; |
6234f380 TV |
672 | tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ; |
673 | ||
11573e91 TV |
674 | actmon_writel(tegra, ACTMON_SAMPLING_PERIOD - 1, |
675 | ACTMON_GLB_PERIOD_CTRL); | |
6234f380 TV |
676 | |
677 | for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) { | |
678 | dev = tegra->devices + i; | |
679 | dev->config = actmon_device_configs + i; | |
680 | dev->regs = tegra->regs + dev->config->offset; | |
11573e91 | 681 | spin_lock_init(&dev->lock); |
6234f380 | 682 | |
11573e91 | 683 | tegra_actmon_configure_device(tegra, dev); |
6234f380 TV |
684 | } |
685 | ||
5d498b46 TV |
686 | for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) { |
687 | rate = clk_round_rate(tegra->emc_clock, rate); | |
688 | dev_pm_opp_add(&pdev->dev, rate, 0); | |
689 | } | |
690 | ||
11573e91 | 691 | irq = platform_get_irq(pdev, 0); |
9e578b37 GS |
692 | if (irq < 0) { |
693 | dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq); | |
694 | return irq; | |
6234f380 TV |
695 | } |
696 | ||
2da19b1a TV |
697 | platform_set_drvdata(pdev, tegra); |
698 | ||
6234f380 TV |
699 | err = devm_request_threaded_irq(&pdev->dev, irq, actmon_isr, |
700 | actmon_thread_isr, IRQF_SHARED, | |
701 | "tegra-devfreq", tegra); | |
702 | if (err) { | |
703 | dev_err(&pdev->dev, "Interrupt request failed\n"); | |
704 | return err; | |
705 | } | |
706 | ||
11573e91 TV |
707 | tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock); |
708 | tegra->devfreq = devm_devfreq_add_device(&pdev->dev, | |
709 | &tegra_devfreq_profile, | |
710 | "tegra_actmon", | |
711 | NULL); | |
712 | ||
6234f380 TV |
713 | return 0; |
714 | } | |
715 | ||
716 | static int tegra_devfreq_remove(struct platform_device *pdev) | |
717 | { | |
718 | struct tegra_devfreq *tegra = platform_get_drvdata(pdev); | |
11573e91 TV |
719 | int irq = platform_get_irq(pdev, 0); |
720 | u32 val; | |
721 | unsigned int i; | |
722 | ||
723 | for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) { | |
724 | val = device_readl(&tegra->devices[i], ACTMON_DEV_CTRL); | |
725 | val &= ~ACTMON_DEV_CTRL_ENB; | |
726 | device_writel(&tegra->devices[i], val, ACTMON_DEV_CTRL); | |
727 | } | |
728 | ||
729 | actmon_write_barrier(tegra); | |
730 | ||
731 | devm_free_irq(&pdev->dev, irq, tegra); | |
6234f380 TV |
732 | |
733 | clk_notifier_unregister(tegra->emc_clock, &tegra->rate_change_nb); | |
734 | ||
735 | clk_disable_unprepare(tegra->clock); | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
11573e91 | 740 | static const struct of_device_id tegra_devfreq_of_match[] = { |
6234f380 TV |
741 | { .compatible = "nvidia,tegra124-actmon" }, |
742 | { }, | |
743 | }; | |
744 | ||
11573e91 TV |
745 | MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match); |
746 | ||
6234f380 TV |
747 | static struct platform_driver tegra_devfreq_driver = { |
748 | .probe = tegra_devfreq_probe, | |
749 | .remove = tegra_devfreq_remove, | |
750 | .driver = { | |
11573e91 | 751 | .name = "tegra-devfreq", |
6234f380 | 752 | .of_match_table = tegra_devfreq_of_match, |
6234f380 TV |
753 | }, |
754 | }; | |
358b615f TV |
755 | |
756 | static int __init tegra_devfreq_init(void) | |
757 | { | |
758 | int ret = 0; | |
759 | ||
760 | ret = devfreq_add_governor(&tegra_devfreq_governor); | |
761 | if (ret) { | |
762 | pr_err("%s: failed to add governor: %d\n", __func__, ret); | |
763 | return ret; | |
764 | } | |
765 | ||
766 | ret = platform_driver_register(&tegra_devfreq_driver); | |
767 | if (ret) | |
768 | devfreq_remove_governor(&tegra_devfreq_governor); | |
769 | ||
770 | return ret; | |
771 | } | |
772 | module_init(tegra_devfreq_init) | |
773 | ||
774 | static void __exit tegra_devfreq_exit(void) | |
775 | { | |
776 | int ret = 0; | |
777 | ||
778 | platform_driver_unregister(&tegra_devfreq_driver); | |
779 | ||
780 | ret = devfreq_remove_governor(&tegra_devfreq_governor); | |
781 | if (ret) | |
782 | pr_err("%s: failed to remove governor: %d\n", __func__, ret); | |
783 | } | |
784 | module_exit(tegra_devfreq_exit) | |
6234f380 | 785 | |
11573e91 | 786 | MODULE_LICENSE("GPL v2"); |
6234f380 TV |
787 | MODULE_DESCRIPTION("Tegra devfreq driver"); |
788 | MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>"); |