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9952f691 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6234f380 TV |
2 | /* |
3 | * A devfreq driver for NVIDIA Tegra SoCs | |
4 | * | |
5 | * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved. | |
6 | * Copyright (C) 2014 Google, Inc | |
6234f380 TV |
7 | */ |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/cpufreq.h> | |
11 | #include <linux/devfreq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/module.h> | |
ac316725 | 15 | #include <linux/mod_devicetable.h> |
6234f380 TV |
16 | #include <linux/platform_device.h> |
17 | #include <linux/pm_opp.h> | |
18 | #include <linux/reset.h> | |
19 | ||
20 | #include "governor.h" | |
21 | ||
22 | #define ACTMON_GLB_STATUS 0x0 | |
23 | #define ACTMON_GLB_PERIOD_CTRL 0x4 | |
24 | ||
25 | #define ACTMON_DEV_CTRL 0x0 | |
26 | #define ACTMON_DEV_CTRL_K_VAL_SHIFT 10 | |
27 | #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18) | |
28 | #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20) | |
29 | #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21) | |
30 | #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT 23 | |
31 | #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT 26 | |
32 | #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29) | |
33 | #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30) | |
34 | #define ACTMON_DEV_CTRL_ENB BIT(31) | |
35 | ||
36 | #define ACTMON_DEV_UPPER_WMARK 0x4 | |
37 | #define ACTMON_DEV_LOWER_WMARK 0x8 | |
38 | #define ACTMON_DEV_INIT_AVG 0xc | |
39 | #define ACTMON_DEV_AVG_UPPER_WMARK 0x10 | |
40 | #define ACTMON_DEV_AVG_LOWER_WMARK 0x14 | |
41 | #define ACTMON_DEV_COUNT_WEIGHT 0x18 | |
42 | #define ACTMON_DEV_AVG_COUNT 0x20 | |
43 | #define ACTMON_DEV_INTR_STATUS 0x24 | |
44 | ||
45 | #define ACTMON_INTR_STATUS_CLEAR 0xffffffff | |
46 | ||
47 | #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31) | |
48 | #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30) | |
49 | ||
50 | #define ACTMON_ABOVE_WMARK_WINDOW 1 | |
51 | #define ACTMON_BELOW_WMARK_WINDOW 3 | |
52 | #define ACTMON_BOOST_FREQ_STEP 16000 | |
53 | ||
11573e91 TV |
54 | /* |
55 | * Activity counter is incremented every 256 memory transactions, and each | |
6234f380 TV |
56 | * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is |
57 | * 4 * 256 = 1024. | |
58 | */ | |
59 | #define ACTMON_COUNT_WEIGHT 0x400 | |
60 | ||
61 | /* | |
62 | * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which | |
63 | * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128 | |
64 | */ | |
65 | #define ACTMON_AVERAGE_WINDOW_LOG2 6 | |
66 | #define ACTMON_SAMPLING_PERIOD 12 /* ms */ | |
67 | #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */ | |
68 | ||
69 | #define KHZ 1000 | |
70 | ||
71 | /* Assume that the bus is saturated if the utilization is 25% */ | |
72 | #define BUS_SATURATION_RATIO 25 | |
73 | ||
74 | /** | |
75 | * struct tegra_devfreq_device_config - configuration specific to an ACTMON | |
76 | * device | |
77 | * | |
11573e91 | 78 | * Coefficients and thresholds are percentages unless otherwise noted |
6234f380 TV |
79 | */ |
80 | struct tegra_devfreq_device_config { | |
81 | u32 offset; | |
82 | u32 irq_mask; | |
83 | ||
11573e91 | 84 | /* Factors applied to boost_freq every consecutive watermark breach */ |
6234f380 TV |
85 | unsigned int boost_up_coeff; |
86 | unsigned int boost_down_coeff; | |
11573e91 TV |
87 | |
88 | /* Define the watermark bounds when applied to the current avg */ | |
6234f380 TV |
89 | unsigned int boost_up_threshold; |
90 | unsigned int boost_down_threshold; | |
11573e91 TV |
91 | |
92 | /* | |
93 | * Threshold of activity (cycles) below which the CPU frequency isn't | |
94 | * to be taken into account. This is to avoid increasing the EMC | |
95 | * frequency when the CPU is very busy but not accessing the bus often. | |
96 | */ | |
6234f380 TV |
97 | u32 avg_dependency_threshold; |
98 | }; | |
99 | ||
100 | enum tegra_actmon_device { | |
101 | MCALL = 0, | |
102 | MCCPU, | |
103 | }; | |
104 | ||
105 | static struct tegra_devfreq_device_config actmon_device_configs[] = { | |
106 | { | |
11573e91 | 107 | /* MCALL: All memory accesses (including from the CPUs) */ |
6234f380 TV |
108 | .offset = 0x1c0, |
109 | .irq_mask = 1 << 26, | |
110 | .boost_up_coeff = 200, | |
111 | .boost_down_coeff = 50, | |
112 | .boost_up_threshold = 60, | |
113 | .boost_down_threshold = 40, | |
114 | }, | |
115 | { | |
11573e91 | 116 | /* MCCPU: memory accesses from the CPUs */ |
6234f380 TV |
117 | .offset = 0x200, |
118 | .irq_mask = 1 << 25, | |
119 | .boost_up_coeff = 800, | |
120 | .boost_down_coeff = 90, | |
121 | .boost_up_threshold = 27, | |
122 | .boost_down_threshold = 10, | |
123 | .avg_dependency_threshold = 50000, | |
124 | }, | |
125 | }; | |
126 | ||
127 | /** | |
128 | * struct tegra_devfreq_device - state specific to an ACTMON device | |
129 | * | |
130 | * Frequencies are in kHz. | |
131 | */ | |
132 | struct tegra_devfreq_device { | |
133 | const struct tegra_devfreq_device_config *config; | |
11573e91 TV |
134 | void __iomem *regs; |
135 | spinlock_t lock; | |
6234f380 | 136 | |
11573e91 TV |
137 | /* Average event count sampled in the last interrupt */ |
138 | u32 avg_count; | |
6234f380 | 139 | |
11573e91 TV |
140 | /* |
141 | * Extra frequency to increase the target by due to consecutive | |
142 | * watermark breaches. | |
143 | */ | |
144 | unsigned long boost_freq; | |
145 | ||
146 | /* Optimal frequency calculated from the stats for this device */ | |
147 | unsigned long target_freq; | |
6234f380 TV |
148 | }; |
149 | ||
150 | struct tegra_devfreq { | |
151 | struct devfreq *devfreq; | |
152 | ||
6234f380 TV |
153 | struct reset_control *reset; |
154 | struct clk *clock; | |
155 | void __iomem *regs; | |
156 | ||
6234f380 TV |
157 | struct clk *emc_clock; |
158 | unsigned long max_freq; | |
159 | unsigned long cur_freq; | |
160 | struct notifier_block rate_change_nb; | |
161 | ||
162 | struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)]; | |
163 | }; | |
164 | ||
165 | struct tegra_actmon_emc_ratio { | |
166 | unsigned long cpu_freq; | |
167 | unsigned long emc_freq; | |
168 | }; | |
169 | ||
170 | static struct tegra_actmon_emc_ratio actmon_emc_ratios[] = { | |
171 | { 1400000, ULONG_MAX }, | |
172 | { 1200000, 750000 }, | |
173 | { 1100000, 600000 }, | |
174 | { 1000000, 500000 }, | |
175 | { 800000, 375000 }, | |
176 | { 500000, 200000 }, | |
177 | { 250000, 100000 }, | |
178 | }; | |
179 | ||
11573e91 TV |
180 | static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset) |
181 | { | |
182 | return readl(tegra->regs + offset); | |
183 | } | |
184 | ||
185 | static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset) | |
186 | { | |
187 | writel(val, tegra->regs + offset); | |
188 | } | |
189 | ||
190 | static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset) | |
191 | { | |
192 | return readl(dev->regs + offset); | |
193 | } | |
194 | ||
195 | static void device_writel(struct tegra_devfreq_device *dev, u32 val, | |
196 | u32 offset) | |
197 | { | |
198 | writel(val, dev->regs + offset); | |
199 | } | |
200 | ||
6234f380 TV |
201 | static unsigned long do_percent(unsigned long val, unsigned int pct) |
202 | { | |
203 | return val * pct / 100; | |
204 | } | |
205 | ||
11573e91 TV |
206 | static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra, |
207 | struct tegra_devfreq_device *dev) | |
6234f380 TV |
208 | { |
209 | u32 avg = dev->avg_count; | |
11573e91 TV |
210 | u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; |
211 | u32 band = avg_band_freq * ACTMON_SAMPLING_PERIOD; | |
212 | ||
213 | device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK); | |
6234f380 | 214 | |
11573e91 TV |
215 | avg = max(dev->avg_count, band); |
216 | device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK); | |
6234f380 TV |
217 | } |
218 | ||
219 | static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra, | |
220 | struct tegra_devfreq_device *dev) | |
221 | { | |
222 | u32 val = tegra->cur_freq * ACTMON_SAMPLING_PERIOD; | |
223 | ||
11573e91 TV |
224 | device_writel(dev, do_percent(val, dev->config->boost_up_threshold), |
225 | ACTMON_DEV_UPPER_WMARK); | |
6234f380 | 226 | |
11573e91 TV |
227 | device_writel(dev, do_percent(val, dev->config->boost_down_threshold), |
228 | ACTMON_DEV_LOWER_WMARK); | |
6234f380 TV |
229 | } |
230 | ||
231 | static void actmon_write_barrier(struct tegra_devfreq *tegra) | |
232 | { | |
233 | /* ensure the update has reached the ACTMON */ | |
234 | wmb(); | |
11573e91 | 235 | actmon_readl(tegra, ACTMON_GLB_STATUS); |
6234f380 TV |
236 | } |
237 | ||
11573e91 TV |
238 | static void actmon_isr_device(struct tegra_devfreq *tegra, |
239 | struct tegra_devfreq_device *dev) | |
6234f380 | 240 | { |
6234f380 | 241 | unsigned long flags; |
11573e91 | 242 | u32 intr_status, dev_ctrl; |
6234f380 | 243 | |
11573e91 | 244 | spin_lock_irqsave(&dev->lock, flags); |
6234f380 | 245 | |
11573e91 TV |
246 | dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT); |
247 | tegra_devfreq_update_avg_wmark(tegra, dev); | |
6234f380 | 248 | |
11573e91 TV |
249 | intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS); |
250 | dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL); | |
6234f380 | 251 | |
11573e91 | 252 | if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) { |
6234f380 TV |
253 | /* |
254 | * new_boost = min(old_boost * up_coef + step, max_freq) | |
255 | */ | |
256 | dev->boost_freq = do_percent(dev->boost_freq, | |
257 | dev->config->boost_up_coeff); | |
258 | dev->boost_freq += ACTMON_BOOST_FREQ_STEP; | |
6234f380 | 259 | |
11573e91 TV |
260 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
261 | ||
262 | if (dev->boost_freq >= tegra->max_freq) | |
263 | dev->boost_freq = tegra->max_freq; | |
264 | else | |
265 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
266 | } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) { | |
6234f380 TV |
267 | /* |
268 | * new_boost = old_boost * down_coef | |
269 | * or 0 if (old_boost * down_coef < step / 2) | |
270 | */ | |
271 | dev->boost_freq = do_percent(dev->boost_freq, | |
272 | dev->config->boost_down_coeff); | |
11573e91 TV |
273 | |
274 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
275 | ||
276 | if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1)) | |
6234f380 | 277 | dev->boost_freq = 0; |
11573e91 TV |
278 | else |
279 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
6234f380 TV |
280 | } |
281 | ||
282 | if (dev->config->avg_dependency_threshold) { | |
6234f380 | 283 | if (dev->avg_count >= dev->config->avg_dependency_threshold) |
11573e91 | 284 | dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
6234f380 | 285 | else if (dev->boost_freq == 0) |
11573e91 | 286 | dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; |
6234f380 TV |
287 | } |
288 | ||
11573e91 TV |
289 | device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL); |
290 | ||
291 | device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); | |
6234f380 TV |
292 | |
293 | actmon_write_barrier(tegra); | |
294 | ||
11573e91 TV |
295 | spin_unlock_irqrestore(&dev->lock, flags); |
296 | } | |
6234f380 | 297 | |
11573e91 TV |
298 | static irqreturn_t actmon_isr(int irq, void *data) |
299 | { | |
300 | struct tegra_devfreq *tegra = data; | |
301 | bool handled = false; | |
302 | unsigned int i; | |
303 | u32 val; | |
304 | ||
305 | val = actmon_readl(tegra, ACTMON_GLB_STATUS); | |
306 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
307 | if (val & tegra->devices[i].config->irq_mask) { | |
308 | actmon_isr_device(tegra, tegra->devices + i); | |
309 | handled = true; | |
310 | } | |
311 | } | |
312 | ||
313 | return handled ? IRQ_WAKE_THREAD : IRQ_NONE; | |
6234f380 TV |
314 | } |
315 | ||
316 | static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra, | |
317 | unsigned long cpu_freq) | |
318 | { | |
319 | unsigned int i; | |
320 | struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios; | |
321 | ||
322 | for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) { | |
323 | if (cpu_freq >= ratio->cpu_freq) { | |
324 | if (ratio->emc_freq >= tegra->max_freq) | |
325 | return tegra->max_freq; | |
326 | else | |
327 | return ratio->emc_freq; | |
328 | } | |
329 | } | |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | static void actmon_update_target(struct tegra_devfreq *tegra, | |
335 | struct tegra_devfreq_device *dev) | |
336 | { | |
337 | unsigned long cpu_freq = 0; | |
338 | unsigned long static_cpu_emc_freq = 0; | |
339 | unsigned int avg_sustain_coef; | |
340 | unsigned long flags; | |
341 | ||
342 | if (dev->config->avg_dependency_threshold) { | |
343 | cpu_freq = cpufreq_get(0); | |
344 | static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq); | |
345 | } | |
346 | ||
11573e91 | 347 | spin_lock_irqsave(&dev->lock, flags); |
6234f380 TV |
348 | |
349 | dev->target_freq = dev->avg_count / ACTMON_SAMPLING_PERIOD; | |
350 | avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold; | |
351 | dev->target_freq = do_percent(dev->target_freq, avg_sustain_coef); | |
352 | dev->target_freq += dev->boost_freq; | |
353 | ||
354 | if (dev->avg_count >= dev->config->avg_dependency_threshold) | |
355 | dev->target_freq = max(dev->target_freq, static_cpu_emc_freq); | |
356 | ||
11573e91 | 357 | spin_unlock_irqrestore(&dev->lock, flags); |
6234f380 TV |
358 | } |
359 | ||
360 | static irqreturn_t actmon_thread_isr(int irq, void *data) | |
361 | { | |
362 | struct tegra_devfreq *tegra = data; | |
363 | ||
364 | mutex_lock(&tegra->devfreq->lock); | |
365 | update_devfreq(tegra->devfreq); | |
366 | mutex_unlock(&tegra->devfreq->lock); | |
367 | ||
368 | return IRQ_HANDLED; | |
369 | } | |
370 | ||
371 | static int tegra_actmon_rate_notify_cb(struct notifier_block *nb, | |
372 | unsigned long action, void *ptr) | |
373 | { | |
374 | struct clk_notifier_data *data = ptr; | |
11573e91 TV |
375 | struct tegra_devfreq *tegra; |
376 | struct tegra_devfreq_device *dev; | |
6234f380 TV |
377 | unsigned int i; |
378 | unsigned long flags; | |
379 | ||
11573e91 TV |
380 | if (action != POST_RATE_CHANGE) |
381 | return NOTIFY_OK; | |
6234f380 | 382 | |
11573e91 | 383 | tegra = container_of(nb, struct tegra_devfreq, rate_change_nb); |
6234f380 | 384 | |
11573e91 | 385 | tegra->cur_freq = data->new_rate / KHZ; |
6234f380 | 386 | |
11573e91 TV |
387 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { |
388 | dev = &tegra->devices[i]; | |
389 | ||
390 | spin_lock_irqsave(&dev->lock, flags); | |
391 | tegra_devfreq_update_wmark(tegra, dev); | |
392 | spin_unlock_irqrestore(&dev->lock, flags); | |
393 | } | |
6234f380 | 394 | |
11573e91 | 395 | actmon_write_barrier(tegra); |
6234f380 TV |
396 | |
397 | return NOTIFY_OK; | |
398 | } | |
399 | ||
11573e91 | 400 | static void tegra_actmon_enable_interrupts(struct tegra_devfreq *tegra) |
6234f380 | 401 | { |
11573e91 | 402 | struct tegra_devfreq_device *dev; |
6234f380 | 403 | u32 val; |
11573e91 | 404 | unsigned int i; |
6234f380 | 405 | |
11573e91 TV |
406 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { |
407 | dev = &tegra->devices[i]; | |
6234f380 | 408 | |
11573e91 TV |
409 | val = device_readl(dev, ACTMON_DEV_CTRL); |
410 | val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN; | |
411 | val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN; | |
412 | val |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
413 | val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
6234f380 | 414 | |
11573e91 TV |
415 | device_writel(dev, val, ACTMON_DEV_CTRL); |
416 | } | |
6234f380 TV |
417 | |
418 | actmon_write_barrier(tegra); | |
419 | } | |
420 | ||
11573e91 | 421 | static void tegra_actmon_disable_interrupts(struct tegra_devfreq *tegra) |
6234f380 | 422 | { |
11573e91 | 423 | struct tegra_devfreq_device *dev; |
6234f380 | 424 | u32 val; |
11573e91 | 425 | unsigned int i; |
6234f380 TV |
426 | |
427 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
11573e91 | 428 | dev = &tegra->devices[i]; |
6234f380 | 429 | |
11573e91 TV |
430 | val = device_readl(dev, ACTMON_DEV_CTRL); |
431 | val &= ~ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN; | |
432 | val &= ~ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN; | |
433 | val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN; | |
434 | val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN; | |
6234f380 | 435 | |
11573e91 | 436 | device_writel(dev, val, ACTMON_DEV_CTRL); |
6234f380 TV |
437 | } |
438 | ||
11573e91 | 439 | actmon_write_barrier(tegra); |
6234f380 TV |
440 | } |
441 | ||
11573e91 TV |
442 | static void tegra_actmon_configure_device(struct tegra_devfreq *tegra, |
443 | struct tegra_devfreq_device *dev) | |
6234f380 | 444 | { |
11573e91 | 445 | u32 val = 0; |
6234f380 | 446 | |
11573e91 | 447 | dev->target_freq = tegra->cur_freq; |
6234f380 | 448 | |
11573e91 TV |
449 | dev->avg_count = tegra->cur_freq * ACTMON_SAMPLING_PERIOD; |
450 | device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG); | |
6234f380 | 451 | |
11573e91 TV |
452 | tegra_devfreq_update_avg_wmark(tegra, dev); |
453 | tegra_devfreq_update_wmark(tegra, dev); | |
6234f380 | 454 | |
11573e91 TV |
455 | device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT); |
456 | device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); | |
457 | ||
458 | val |= ACTMON_DEV_CTRL_ENB_PERIODIC; | |
459 | val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1) | |
460 | << ACTMON_DEV_CTRL_K_VAL_SHIFT; | |
461 | val |= (ACTMON_BELOW_WMARK_WINDOW - 1) | |
462 | << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT; | |
463 | val |= (ACTMON_ABOVE_WMARK_WINDOW - 1) | |
464 | << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT; | |
465 | val |= ACTMON_DEV_CTRL_ENB; | |
466 | ||
467 | device_writel(dev, val, ACTMON_DEV_CTRL); | |
468 | ||
469 | actmon_write_barrier(tegra); | |
6234f380 TV |
470 | } |
471 | ||
472 | static int tegra_devfreq_target(struct device *dev, unsigned long *freq, | |
473 | u32 flags) | |
474 | { | |
11573e91 | 475 | struct tegra_devfreq *tegra = dev_get_drvdata(dev); |
6234f380 TV |
476 | struct dev_pm_opp *opp; |
477 | unsigned long rate = *freq * KHZ; | |
478 | ||
6234f380 TV |
479 | opp = devfreq_recommended_opp(dev, &rate, flags); |
480 | if (IS_ERR(opp)) { | |
6234f380 TV |
481 | dev_err(dev, "Failed to find opp for %lu KHz\n", *freq); |
482 | return PTR_ERR(opp); | |
483 | } | |
484 | rate = dev_pm_opp_get_freq(opp); | |
8a31d9d9 | 485 | dev_pm_opp_put(opp); |
6234f380 | 486 | |
c70eea73 TV |
487 | clk_set_min_rate(tegra->emc_clock, rate); |
488 | clk_set_rate(tegra->emc_clock, 0); | |
6234f380 | 489 | |
dbb0c7c4 TV |
490 | *freq = rate; |
491 | ||
6234f380 TV |
492 | return 0; |
493 | } | |
494 | ||
495 | static int tegra_devfreq_get_dev_status(struct device *dev, | |
496 | struct devfreq_dev_status *stat) | |
497 | { | |
11573e91 | 498 | struct tegra_devfreq *tegra = dev_get_drvdata(dev); |
6234f380 TV |
499 | struct tegra_devfreq_device *actmon_dev; |
500 | ||
6234f380 TV |
501 | stat->current_frequency = tegra->cur_freq; |
502 | ||
503 | /* To be used by the tegra governor */ | |
504 | stat->private_data = tegra; | |
505 | ||
506 | /* The below are to be used by the other governors */ | |
507 | ||
508 | actmon_dev = &tegra->devices[MCALL]; | |
509 | ||
510 | /* Number of cycles spent on memory access */ | |
11573e91 | 511 | stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT); |
6234f380 TV |
512 | |
513 | /* The bus can be considered to be saturated way before 100% */ | |
514 | stat->busy_time *= 100 / BUS_SATURATION_RATIO; | |
515 | ||
516 | /* Number of cycles in a sampling period */ | |
517 | stat->total_time = ACTMON_SAMPLING_PERIOD * tegra->cur_freq; | |
518 | ||
11573e91 TV |
519 | stat->busy_time = min(stat->busy_time, stat->total_time); |
520 | ||
6234f380 TV |
521 | return 0; |
522 | } | |
523 | ||
11573e91 TV |
524 | static struct devfreq_dev_profile tegra_devfreq_profile = { |
525 | .polling_ms = 0, | |
526 | .target = tegra_devfreq_target, | |
527 | .get_dev_status = tegra_devfreq_get_dev_status, | |
528 | }; | |
529 | ||
530 | static int tegra_governor_get_target(struct devfreq *devfreq, | |
531 | unsigned long *freq) | |
6234f380 | 532 | { |
14de3903 | 533 | struct devfreq_dev_status *stat; |
6234f380 TV |
534 | struct tegra_devfreq *tegra; |
535 | struct tegra_devfreq_device *dev; | |
536 | unsigned long target_freq = 0; | |
537 | unsigned int i; | |
538 | int err; | |
539 | ||
14de3903 | 540 | err = devfreq_update_stats(devfreq); |
6234f380 TV |
541 | if (err) |
542 | return err; | |
543 | ||
14de3903 MH |
544 | stat = &devfreq->last_status; |
545 | ||
546 | tegra = stat->private_data; | |
6234f380 TV |
547 | |
548 | for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { | |
549 | dev = &tegra->devices[i]; | |
550 | ||
551 | actmon_update_target(tegra, dev); | |
552 | ||
553 | target_freq = max(target_freq, dev->target_freq); | |
554 | } | |
555 | ||
556 | *freq = target_freq; | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
11573e91 TV |
561 | static int tegra_governor_event_handler(struct devfreq *devfreq, |
562 | unsigned int event, void *data) | |
6234f380 | 563 | { |
1d1397c3 | 564 | struct tegra_devfreq *tegra = dev_get_drvdata(devfreq->dev.parent); |
11573e91 TV |
565 | |
566 | switch (event) { | |
567 | case DEVFREQ_GOV_START: | |
11573e91 | 568 | devfreq_monitor_start(devfreq); |
34ed5040 | 569 | tegra_actmon_enable_interrupts(tegra); |
11573e91 TV |
570 | break; |
571 | ||
572 | case DEVFREQ_GOV_STOP: | |
573 | tegra_actmon_disable_interrupts(tegra); | |
574 | devfreq_monitor_stop(devfreq); | |
575 | break; | |
576 | ||
577 | case DEVFREQ_GOV_SUSPEND: | |
578 | tegra_actmon_disable_interrupts(tegra); | |
579 | devfreq_monitor_suspend(devfreq); | |
580 | break; | |
581 | ||
582 | case DEVFREQ_GOV_RESUME: | |
11573e91 | 583 | devfreq_monitor_resume(devfreq); |
34ed5040 | 584 | tegra_actmon_enable_interrupts(tegra); |
11573e91 TV |
585 | break; |
586 | } | |
587 | ||
1d1397c3 | 588 | return 0; |
6234f380 TV |
589 | } |
590 | ||
591 | static struct devfreq_governor tegra_devfreq_governor = { | |
11573e91 TV |
592 | .name = "tegra_actmon", |
593 | .get_target_freq = tegra_governor_get_target, | |
594 | .event_handler = tegra_governor_event_handler, | |
6234f380 TV |
595 | }; |
596 | ||
6234f380 TV |
597 | static int tegra_devfreq_probe(struct platform_device *pdev) |
598 | { | |
599 | struct tegra_devfreq *tegra; | |
600 | struct tegra_devfreq_device *dev; | |
601 | struct resource *res; | |
6234f380 | 602 | unsigned int i; |
5d498b46 | 603 | unsigned long rate; |
6234f380 TV |
604 | int irq; |
605 | int err; | |
606 | ||
607 | tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); | |
608 | if (!tegra) | |
609 | return -ENOMEM; | |
610 | ||
6234f380 | 611 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
6234f380 TV |
612 | |
613 | tegra->regs = devm_ioremap_resource(&pdev->dev, res); | |
11573e91 | 614 | if (IS_ERR(tegra->regs)) |
6234f380 | 615 | return PTR_ERR(tegra->regs); |
6234f380 TV |
616 | |
617 | tegra->reset = devm_reset_control_get(&pdev->dev, "actmon"); | |
618 | if (IS_ERR(tegra->reset)) { | |
619 | dev_err(&pdev->dev, "Failed to get reset\n"); | |
620 | return PTR_ERR(tegra->reset); | |
621 | } | |
622 | ||
623 | tegra->clock = devm_clk_get(&pdev->dev, "actmon"); | |
624 | if (IS_ERR(tegra->clock)) { | |
625 | dev_err(&pdev->dev, "Failed to get actmon clock\n"); | |
626 | return PTR_ERR(tegra->clock); | |
627 | } | |
628 | ||
629 | tegra->emc_clock = devm_clk_get(&pdev->dev, "emc"); | |
630 | if (IS_ERR(tegra->emc_clock)) { | |
631 | dev_err(&pdev->dev, "Failed to get emc clock\n"); | |
632 | return PTR_ERR(tegra->emc_clock); | |
633 | } | |
634 | ||
c70eea73 TV |
635 | clk_set_rate(tegra->emc_clock, ULONG_MAX); |
636 | ||
6234f380 TV |
637 | tegra->rate_change_nb.notifier_call = tegra_actmon_rate_notify_cb; |
638 | err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb); | |
639 | if (err) { | |
640 | dev_err(&pdev->dev, | |
641 | "Failed to register rate change notifier\n"); | |
642 | return err; | |
643 | } | |
644 | ||
645 | reset_control_assert(tegra->reset); | |
646 | ||
647 | err = clk_prepare_enable(tegra->clock); | |
648 | if (err) { | |
11573e91 TV |
649 | dev_err(&pdev->dev, |
650 | "Failed to prepare and enable ACTMON clock\n"); | |
6234f380 TV |
651 | return err; |
652 | } | |
653 | ||
654 | reset_control_deassert(tegra->reset); | |
655 | ||
c70eea73 | 656 | tegra->max_freq = clk_round_rate(tegra->emc_clock, ULONG_MAX) / KHZ; |
6234f380 TV |
657 | tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ; |
658 | ||
11573e91 TV |
659 | actmon_writel(tegra, ACTMON_SAMPLING_PERIOD - 1, |
660 | ACTMON_GLB_PERIOD_CTRL); | |
6234f380 TV |
661 | |
662 | for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) { | |
663 | dev = tegra->devices + i; | |
664 | dev->config = actmon_device_configs + i; | |
665 | dev->regs = tegra->regs + dev->config->offset; | |
11573e91 | 666 | spin_lock_init(&dev->lock); |
6234f380 | 667 | |
11573e91 | 668 | tegra_actmon_configure_device(tegra, dev); |
6234f380 TV |
669 | } |
670 | ||
5d498b46 TV |
671 | for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) { |
672 | rate = clk_round_rate(tegra->emc_clock, rate); | |
673 | dev_pm_opp_add(&pdev->dev, rate, 0); | |
674 | } | |
675 | ||
11573e91 | 676 | irq = platform_get_irq(pdev, 0); |
9e578b37 GS |
677 | if (irq < 0) { |
678 | dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq); | |
679 | return irq; | |
6234f380 TV |
680 | } |
681 | ||
2da19b1a TV |
682 | platform_set_drvdata(pdev, tegra); |
683 | ||
6234f380 TV |
684 | err = devm_request_threaded_irq(&pdev->dev, irq, actmon_isr, |
685 | actmon_thread_isr, IRQF_SHARED, | |
686 | "tegra-devfreq", tegra); | |
687 | if (err) { | |
688 | dev_err(&pdev->dev, "Interrupt request failed\n"); | |
689 | return err; | |
690 | } | |
691 | ||
11573e91 TV |
692 | tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock); |
693 | tegra->devfreq = devm_devfreq_add_device(&pdev->dev, | |
694 | &tegra_devfreq_profile, | |
695 | "tegra_actmon", | |
696 | NULL); | |
697 | ||
6234f380 TV |
698 | return 0; |
699 | } | |
700 | ||
701 | static int tegra_devfreq_remove(struct platform_device *pdev) | |
702 | { | |
703 | struct tegra_devfreq *tegra = platform_get_drvdata(pdev); | |
11573e91 TV |
704 | int irq = platform_get_irq(pdev, 0); |
705 | u32 val; | |
706 | unsigned int i; | |
707 | ||
708 | for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) { | |
709 | val = device_readl(&tegra->devices[i], ACTMON_DEV_CTRL); | |
710 | val &= ~ACTMON_DEV_CTRL_ENB; | |
711 | device_writel(&tegra->devices[i], val, ACTMON_DEV_CTRL); | |
712 | } | |
713 | ||
714 | actmon_write_barrier(tegra); | |
715 | ||
716 | devm_free_irq(&pdev->dev, irq, tegra); | |
6234f380 TV |
717 | |
718 | clk_notifier_unregister(tegra->emc_clock, &tegra->rate_change_nb); | |
719 | ||
720 | clk_disable_unprepare(tegra->clock); | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
11573e91 | 725 | static const struct of_device_id tegra_devfreq_of_match[] = { |
6234f380 TV |
726 | { .compatible = "nvidia,tegra124-actmon" }, |
727 | { }, | |
728 | }; | |
729 | ||
11573e91 TV |
730 | MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match); |
731 | ||
6234f380 TV |
732 | static struct platform_driver tegra_devfreq_driver = { |
733 | .probe = tegra_devfreq_probe, | |
734 | .remove = tegra_devfreq_remove, | |
735 | .driver = { | |
11573e91 | 736 | .name = "tegra-devfreq", |
6234f380 | 737 | .of_match_table = tegra_devfreq_of_match, |
6234f380 TV |
738 | }, |
739 | }; | |
358b615f TV |
740 | |
741 | static int __init tegra_devfreq_init(void) | |
742 | { | |
743 | int ret = 0; | |
744 | ||
745 | ret = devfreq_add_governor(&tegra_devfreq_governor); | |
746 | if (ret) { | |
747 | pr_err("%s: failed to add governor: %d\n", __func__, ret); | |
748 | return ret; | |
749 | } | |
750 | ||
751 | ret = platform_driver_register(&tegra_devfreq_driver); | |
752 | if (ret) | |
753 | devfreq_remove_governor(&tegra_devfreq_governor); | |
754 | ||
755 | return ret; | |
756 | } | |
757 | module_init(tegra_devfreq_init) | |
758 | ||
759 | static void __exit tegra_devfreq_exit(void) | |
760 | { | |
761 | int ret = 0; | |
762 | ||
763 | platform_driver_unregister(&tegra_devfreq_driver); | |
764 | ||
765 | ret = devfreq_remove_governor(&tegra_devfreq_governor); | |
766 | if (ret) | |
767 | pr_err("%s: failed to remove governor: %d\n", __func__, ret); | |
768 | } | |
769 | module_exit(tegra_devfreq_exit) | |
6234f380 | 770 | |
11573e91 | 771 | MODULE_LICENSE("GPL v2"); |
6234f380 TV |
772 | MODULE_DESCRIPTION("Tegra devfreq driver"); |
773 | MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>"); |