[linux-2.6-block.git] / drivers / devfreq / rk3399_dmc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
 * Author: Lin Huang <hl@rock-chips.com>
 */

#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/devfreq.h>
#include <linux/devfreq-event.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/rwsem.h>
#include <linux/suspend.h>

#include <soc/rockchip/rk3399_grf.h>
#include <soc/rockchip/rockchip_sip.h>

struct dram_timing {
	unsigned int ddr3_speed_bin;
	unsigned int pd_idle;
	unsigned int sr_idle;
	unsigned int sr_mc_gate_idle;
	unsigned int srpd_lite_idle;
	unsigned int standby_idle;
	unsigned int auto_pd_dis_freq;
	unsigned int dram_dll_dis_freq;
	unsigned int phy_dll_dis_freq;
	unsigned int ddr3_odt_dis_freq;
	unsigned int ddr3_drv;
	unsigned int ddr3_odt;
	unsigned int phy_ddr3_ca_drv;
	unsigned int phy_ddr3_dq_drv;
	unsigned int phy_ddr3_odt;
	unsigned int lpddr3_odt_dis_freq;
	unsigned int lpddr3_drv;
	unsigned int lpddr3_odt;
	unsigned int phy_lpddr3_ca_drv;
	unsigned int phy_lpddr3_dq_drv;
	unsigned int phy_lpddr3_odt;
	unsigned int lpddr4_odt_dis_freq;
	unsigned int lpddr4_drv;
	unsigned int lpddr4_dq_odt;
	unsigned int lpddr4_ca_odt;
	unsigned int phy_lpddr4_ca_drv;
	unsigned int phy_lpddr4_ck_cs_drv;
	unsigned int phy_lpddr4_dq_drv;
	unsigned int phy_lpddr4_odt;
};

struct rk3399_dmcfreq {
	struct device *dev;
	struct devfreq *devfreq;
	struct devfreq_simple_ondemand_data ondemand_data;
	struct clk *dmc_clk;
	struct devfreq_event_dev *edev;
	struct mutex lock;
	struct dram_timing timing;
	struct regulator *vdd_center;
	struct regmap *regmap_pmu;
	unsigned long rate, target_rate;
	unsigned long volt, target_volt;
	unsigned int odt_dis_freq;
	int odt_pd_arg0, odt_pd_arg1;
};

static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
				 u32 flags)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	struct dev_pm_opp *opp;
	unsigned long old_clk_rate = dmcfreq->rate;
	unsigned long target_volt, target_rate;
	struct arm_smccc_res res;
	bool odt_enable = false;
	int err;

	opp = devfreq_recommended_opp(dev, freq, flags);
	if (IS_ERR(opp))
		return PTR_ERR(opp);

	target_rate = dev_pm_opp_get_freq(opp);
	target_volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	if (dmcfreq->rate == target_rate)
		return 0;

	mutex_lock(&dmcfreq->lock);

	if (dmcfreq->regmap_pmu) {
		if (target_rate >= dmcfreq->odt_dis_freq)
			odt_enable = true;

		/*
		 * This makes a SMC call to the TF-A to set the DDR PD
		 * (power-down) timings and to enable or disable the
		 * ODT (on-die termination) resistors.
		 */
		arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
			      dmcfreq->odt_pd_arg1,
			      ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
			      odt_enable, 0, 0, 0, &res);
	}

	/*
	 * If frequency scaling from low to high, adjust voltage first.
	 * If frequency scaling from high to low, adjust frequency first.
	 */
	if (old_clk_rate < target_rate) {
		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
					    target_volt);
		if (err) {
			dev_err(dev, "Cannot set voltage %lu uV\n",
				target_volt);
			goto out;
		}
	}

	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
	if (err) {
		dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
			err);
		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
				      dmcfreq->volt);
		goto out;
	}

	/*
	 * Check the dpll rate,
	 * There only two result we will get,
	 * 1. Ddr frequency scaling fail, we still get the old rate.
	 * 2. Ddr frequency scaling sucessful, we get the rate we set.
	 */
	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);

	/* If get the incorrect rate, set voltage to old value. */
	if (dmcfreq->rate != target_rate) {
		dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
			target_rate, dmcfreq->rate);
		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
				      dmcfreq->volt);
		goto out;
	} else if (old_clk_rate > target_rate)
		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
					    target_volt);
	if (err)
		dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);

	dmcfreq->rate = target_rate;
	dmcfreq->volt = target_volt;

out:
	mutex_unlock(&dmcfreq->lock);
	return err;
}

static int rk3399_dmcfreq_get_dev_status(struct device *dev,
					 struct devfreq_dev_status *stat)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	struct devfreq_event_data edata;
	int ret = 0;

	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
	if (ret < 0)
		return ret;

	stat->current_frequency = dmcfreq->rate;
	stat->busy_time = edata.load_count;
	stat->total_time = edata.total_count;

	return ret;
}

static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);

	*freq = dmcfreq->rate;

	return 0;
}

static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
	.polling_ms	= 200,
	.target		= rk3399_dmcfreq_target,
	.get_dev_status	= rk3399_dmcfreq_get_dev_status,
	.get_cur_freq	= rk3399_dmcfreq_get_cur_freq,
};

static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	int ret = 0;

	ret = devfreq_event_disable_edev(dmcfreq->edev);
	if (ret < 0) {
		dev_err(dev, "failed to disable the devfreq-event devices\n");
		return ret;
	}

	ret = devfreq_suspend_device(dmcfreq->devfreq);
	if (ret < 0) {
		dev_err(dev, "failed to suspend the devfreq devices\n");
		return ret;
	}

	return 0;
}

static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	int ret = 0;

	ret = devfreq_event_enable_edev(dmcfreq->edev);
	if (ret < 0) {
		dev_err(dev, "failed to enable the devfreq-event devices\n");
		return ret;
	}

	ret = devfreq_resume_device(dmcfreq->devfreq);
	if (ret < 0) {
		dev_err(dev, "failed to resume the devfreq devices\n");
		return ret;
	}
	return ret;
}

static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
			 rk3399_dmcfreq_resume);

static int of_get_ddr_timings(struct dram_timing *timing,
			      struct device_node *np)
{
	int ret = 0;

	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
				   &timing->ddr3_speed_bin);
	ret |= of_property_read_u32(np, "rockchip,pd_idle",
				    &timing->pd_idle);
	ret |= of_property_read_u32(np, "rockchip,sr_idle",
				    &timing->sr_idle);
	ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
				    &timing->sr_mc_gate_idle);
	ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
				    &timing->srpd_lite_idle);
	ret |= of_property_read_u32(np, "rockchip,standby_idle",
				    &timing->standby_idle);
	ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
				    &timing->auto_pd_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
				    &timing->dram_dll_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
				    &timing->phy_dll_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
				    &timing->ddr3_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
				    &timing->ddr3_drv);
	ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
				    &timing->ddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
				    &timing->phy_ddr3_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
				    &timing->phy_ddr3_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
				    &timing->phy_ddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
				    &timing->lpddr3_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
				    &timing->lpddr3_drv);
	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
				    &timing->lpddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
				    &timing->phy_lpddr3_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
				    &timing->phy_lpddr3_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
				    &timing->phy_lpddr3_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
				    &timing->lpddr4_odt_dis_freq);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
				    &timing->lpddr4_drv);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
				    &timing->lpddr4_dq_odt);
	ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
				    &timing->lpddr4_ca_odt);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
				    &timing->phy_lpddr4_ca_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
				    &timing->phy_lpddr4_ck_cs_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
				    &timing->phy_lpddr4_dq_drv);
	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
				    &timing->phy_lpddr4_odt);

	return ret;
}

static int rk3399_dmcfreq_probe(struct platform_device *pdev)
{
	struct arm_smccc_res res;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node, *node;
	struct rk3399_dmcfreq *data;
	int ret, index, size;
	uint32_t *timing;
	struct dev_pm_opp *opp;
	u32 ddr_type;
	u32 val;

	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	mutex_init(&data->lock);

	data->vdd_center = devm_regulator_get(dev, "center");
	if (IS_ERR(data->vdd_center))
		return dev_err_probe(dev, PTR_ERR(data->vdd_center),
				     "Cannot get the regulator \"center\"\n");

	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
	if (IS_ERR(data->dmc_clk))
		return dev_err_probe(dev, PTR_ERR(data->dmc_clk),
				     "Cannot get the clk dmc_clk\n");

	data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
	if (IS_ERR(data->edev))
		return -EPROBE_DEFER;

	ret = devfreq_event_enable_edev(data->edev);
	if (ret < 0) {
		dev_err(dev, "failed to enable devfreq-event devices\n");
		return ret;
	}

	/*
	 * Get dram timing and pass it to arm trust firmware,
	 * the dram driver in arm trust firmware will get these
	 * timing and to do dram initial.
	 */
	if (!of_get_ddr_timings(&data->timing, np)) {
		timing = &data->timing.ddr3_speed_bin;
		size = sizeof(struct dram_timing) / 4;
		for (index = 0; index < size; index++) {
			arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
				      ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
				      0, 0, 0, 0, &res);
			if (res.a0) {
				dev_err(dev, "Failed to set dram param: %ld\n",
					res.a0);
				ret = -EINVAL;
				goto err_edev;
			}
		}
	}

	node = of_parse_phandle(np, "rockchip,pmu", 0);
	if (!node)
		goto no_pmu;

	data->regmap_pmu = syscon_node_to_regmap(node);
	of_node_put(node);
	if (IS_ERR(data->regmap_pmu)) {
		ret = PTR_ERR(data->regmap_pmu);
		goto err_edev;
	}

	regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
	ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
		    RK3399_PMUGRF_DDRTYPE_MASK;

	switch (ddr_type) {
	case RK3399_PMUGRF_DDRTYPE_DDR3:
		data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
		break;
	case RK3399_PMUGRF_DDRTYPE_LPDDR3:
		data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
		break;
	case RK3399_PMUGRF_DDRTYPE_LPDDR4:
		data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
		break;
	default:
		ret = -EINVAL;
		goto err_edev;
	}

no_pmu:
	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
		      ROCKCHIP_SIP_CONFIG_DRAM_INIT,
		      0, 0, 0, 0, &res);

	/*
	 * In TF-A there is a platform SIP call to set the PD (power-down)
	 * timings and to enable or disable the ODT (on-die termination).
	 * This call needs three arguments as follows:
	 *
	 * arg0:
	 *     bit[0-7]   : sr_idle
	 *     bit[8-15]  : sr_mc_gate_idle
	 *     bit[16-31] : standby idle
	 * arg1:
	 *     bit[0-11]  : pd_idle
	 *     bit[16-27] : srpd_lite_idle
	 * arg2:
	 *     bit[0]     : odt enable
	 */
	data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
			    ((data->timing.sr_mc_gate_idle & 0xff) << 8) |
			    ((data->timing.standby_idle & 0xffff) << 16);
	data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
			    ((data->timing.srpd_lite_idle & 0xfff) << 16);

	/*
	 * We add a devfreq driver to our parent since it has a device tree node
	 * with operating points.
	 */
	if (dev_pm_opp_of_add_table(dev)) {
		dev_err(dev, "Invalid operating-points in device tree.\n");
		ret = -EINVAL;
		goto err_edev;
	}

	of_property_read_u32(np, "upthreshold",
			     &data->ondemand_data.upthreshold);
	of_property_read_u32(np, "downdifferential",
			     &data->ondemand_data.downdifferential);

	data->rate = clk_get_rate(data->dmc_clk);

	opp = devfreq_recommended_opp(dev, &data->rate, 0);
	if (IS_ERR(opp)) {
		ret = PTR_ERR(opp);
		goto err_free_opp;
	}

	data->rate = dev_pm_opp_get_freq(opp);
	data->volt = dev_pm_opp_get_voltage(opp);
	dev_pm_opp_put(opp);

	rk3399_devfreq_dmc_profile.initial_freq = data->rate;

	data->devfreq = devm_devfreq_add_device(dev,
					   &rk3399_devfreq_dmc_profile,
					   DEVFREQ_GOV_SIMPLE_ONDEMAND,
					   &data->ondemand_data);
	if (IS_ERR(data->devfreq)) {
		ret = PTR_ERR(data->devfreq);
		goto err_free_opp;
	}

	devm_devfreq_register_opp_notifier(dev, data->devfreq);

	data->dev = dev;
	platform_set_drvdata(pdev, data);

	return 0;

err_free_opp:
	dev_pm_opp_of_remove_table(&pdev->dev);
err_edev:
	devfreq_event_disable_edev(data->edev);

	return ret;
}

static int rk3399_dmcfreq_remove(struct platform_device *pdev)
{
	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);

	/*
	 * Before remove the opp table we need to unregister the opp notifier.
	 */
	devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
	dev_pm_opp_of_remove_table(dmcfreq->dev);

	return 0;
}

static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
	{ .compatible = "rockchip,rk3399-dmc" },
	{ },
};
MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);

static struct platform_driver rk3399_dmcfreq_driver = {
	.probe	= rk3399_dmcfreq_probe,
	.remove = rk3399_dmcfreq_remove,
	.driver = {
		.name	= "rk3399-dmc-freq",
		.pm	= &rk3399_dmcfreq_pm,
		.of_match_table = rk3399dmc_devfreq_of_match,
	},
};
module_platform_driver(rk3399_dmcfreq_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
Commit	Line	Data
2025cf9e	1	// SPDX-License-Identifier: GPL-2.0-only
5a893e31 LH	2	/*
	3	* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
	4	* Author: Lin Huang <hl@rock-chips.com>
5a893e31 LH	5	*/
	6
	7	#include <linux/arm-smccc.h>
	8	#include <linux/clk.h>
	9	#include <linux/delay.h>
	10	#include <linux/devfreq.h>
	11	#include <linux/devfreq-event.h>
	12	#include <linux/interrupt.h>
9173c5ce	13	#include <linux/mfd/syscon.h>
5a893e31 LH	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/pm_opp.h>
9173c5ce	18	#include <linux/regmap.h>
5a893e31 LH	19	#include <linux/regulator/consumer.h>
	20	#include <linux/rwsem.h>
	21	#include <linux/suspend.h>
	22
9173c5ce	23	#include <soc/rockchip/rk3399_grf.h>
5a893e31 LH	24	#include <soc/rockchip/rockchip_sip.h>
	25
	26	struct dram_timing {
	27	unsigned int ddr3_speed_bin;
	28	unsigned int pd_idle;
	29	unsigned int sr_idle;
	30	unsigned int sr_mc_gate_idle;
	31	unsigned int srpd_lite_idle;
	32	unsigned int standby_idle;
	33	unsigned int auto_pd_dis_freq;
	34	unsigned int dram_dll_dis_freq;
	35	unsigned int phy_dll_dis_freq;
	36	unsigned int ddr3_odt_dis_freq;
	37	unsigned int ddr3_drv;
	38	unsigned int ddr3_odt;
	39	unsigned int phy_ddr3_ca_drv;
	40	unsigned int phy_ddr3_dq_drv;
	41	unsigned int phy_ddr3_odt;
	42	unsigned int lpddr3_odt_dis_freq;
	43	unsigned int lpddr3_drv;
	44	unsigned int lpddr3_odt;
	45	unsigned int phy_lpddr3_ca_drv;
	46	unsigned int phy_lpddr3_dq_drv;
	47	unsigned int phy_lpddr3_odt;
	48	unsigned int lpddr4_odt_dis_freq;
	49	unsigned int lpddr4_drv;
	50	unsigned int lpddr4_dq_odt;
	51	unsigned int lpddr4_ca_odt;
	52	unsigned int phy_lpddr4_ca_drv;
	53	unsigned int phy_lpddr4_ck_cs_drv;
	54	unsigned int phy_lpddr4_dq_drv;
	55	unsigned int phy_lpddr4_odt;
	56	};
	57
	58	struct rk3399_dmcfreq {
	59	struct device *dev;
	60	struct devfreq *devfreq;
	61	struct devfreq_simple_ondemand_data ondemand_data;
	62	struct clk *dmc_clk;
	63	struct devfreq_event_dev *edev;
	64	struct mutex lock;
	65	struct dram_timing timing;
5a893e31	66	struct regulator *vdd_center;
9173c5ce	67	struct regmap *regmap_pmu;
5a893e31 LH	68	unsigned long rate, target_rate;
5a893e31 LH	69	unsigned long volt, target_volt;
9173c5ce EBS	70	unsigned int odt_dis_freq;
9173c5ce EBS	71	int odt_pd_arg0, odt_pd_arg1;
5a893e31 LH	72	};
	73
	74	static int rk3399_dmcfreq_target(struct device dev, unsigned long freq,
	75	u32 flags)
	76	{
	77	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	78	struct dev_pm_opp *opp;
	79	unsigned long old_clk_rate = dmcfreq->rate;
	80	unsigned long target_volt, target_rate;
9173c5ce EBS	81	struct arm_smccc_res res;
9173c5ce EBS	82	bool odt_enable = false;
5a893e31 LH	83	int err;
5a893e31 LH	84
5a893e31	85	opp = devfreq_recommended_opp(dev, freq, flags);
8a31d9d9	86	if (IS_ERR(opp))
5a893e31	87	return PTR_ERR(opp);
5a893e31 LH	88
	89	target_rate = dev_pm_opp_get_freq(opp);
	90	target_volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	91	dev_pm_opp_put(opp);
5a893e31 LH	92
	93	if (dmcfreq->rate == target_rate)
	94	return 0;
	95
	96	mutex_lock(&dmcfreq->lock);
	97
63ef91f2 MZ	98	if (dmcfreq->regmap_pmu) {
	99	if (target_rate >= dmcfreq->odt_dis_freq)
	100	odt_enable = true;
	101
	102	/*
	103	* This makes a SMC call to the TF-A to set the DDR PD
	104	* (power-down) timings and to enable or disable the
	105	* ODT (on-die termination) resistors.
	106	*/
	107	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
	108	dmcfreq->odt_pd_arg1,
	109	ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
	110	odt_enable, 0, 0, 0, &res);
	111	}
9173c5ce	112
5a893e31 LH	113	/*
	114	* If frequency scaling from low to high, adjust voltage first.
	115	* If frequency scaling from high to low, adjust frequency first.
	116	*/
	117	if (old_clk_rate < target_rate) {
	118	err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
	119	target_volt);
	120	if (err) {
dfa7d764	121	dev_err(dev, "Cannot set voltage %lu uV\n",
5a893e31 LH	122	target_volt);
	123	goto out;
	124	}
	125	}
5a893e31 LH	126
	127	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
	128	if (err) {
dfa7d764 EBS	129	dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
dfa7d764 EBS	130	err);
5a893e31 LH	131	regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
	132	dmcfreq->volt);
	133	goto out;
	134	}
	135
5a893e31 LH	136	/*
	137	* Check the dpll rate,
	138	* There only two result we will get,
	139	* 1. Ddr frequency scaling fail, we still get the old rate.
	140	* 2. Ddr frequency scaling sucessful, we get the rate we set.
	141	*/
	142	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
	143
	144	/* If get the incorrect rate, set voltage to old value. */
	145	if (dmcfreq->rate != target_rate) {
dfa7d764 EBS	146	dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
dfa7d764 EBS	147	target_rate, dmcfreq->rate);
5a893e31 LH	148	regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
	149	dmcfreq->volt);
	150	goto out;
	151	} else if (old_clk_rate > target_rate)
	152	err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
	153	target_volt);
	154	if (err)
dfa7d764	155	dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
5a893e31	156
e37d3508 VK	157	dmcfreq->rate = target_rate;
	158	dmcfreq->volt = target_volt;
	159
5a893e31 LH	160	out:
	161	mutex_unlock(&dmcfreq->lock);
	162	return err;
	163	}
	164
	165	static int rk3399_dmcfreq_get_dev_status(struct device *dev,
	166	struct devfreq_dev_status *stat)
	167	{
	168	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	169	struct devfreq_event_data edata;
	170	int ret = 0;
	171
	172	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
	173	if (ret < 0)
	174	return ret;
	175
	176	stat->current_frequency = dmcfreq->rate;
	177	stat->busy_time = edata.load_count;
	178	stat->total_time = edata.total_count;
	179
	180	return ret;
	181	}
	182
	183	static int rk3399_dmcfreq_get_cur_freq(struct device dev, unsigned long freq)
	184	{
	185	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	186
	187	*freq = dmcfreq->rate;
	188
	189	return 0;
	190	}
	191
	192	static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
	193	.polling_ms = 200,
	194	.target = rk3399_dmcfreq_target,
	195	.get_dev_status = rk3399_dmcfreq_get_dev_status,
	196	.get_cur_freq = rk3399_dmcfreq_get_cur_freq,
	197	};
	198
	199	static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
	200	{
	201	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	202	int ret = 0;
	203
	204	ret = devfreq_event_disable_edev(dmcfreq->edev);
	205	if (ret < 0) {
	206	dev_err(dev, "failed to disable the devfreq-event devices\n");
	207	return ret;
	208	}
	209
	210	ret = devfreq_suspend_device(dmcfreq->devfreq);
	211	if (ret < 0) {
	212	dev_err(dev, "failed to suspend the devfreq devices\n");
	213	return ret;
	214	}
	215
	216	return 0;
	217	}
	218
	219	static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
	220	{
	221	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
	222	int ret = 0;
	223
224	ret = devfreq_event_enable_edev(dmcfreq->edev);
225	if (ret < 0) {
226	dev_err(dev, "failed to enable the devfreq-event devices\n");
227	return ret;
228	}
229
230	ret = devfreq_resume_device(dmcfreq->devfreq);
231	if (ret < 0) {
232	dev_err(dev, "failed to resume the devfreq devices\n");
233	return ret;
234	}
235	return ret;
236	}
237
238	static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
239	rk3399_dmcfreq_resume);
240
5a893e31 LH	241	static int of_get_ddr_timings(struct dram_timing *timing,
	242	struct device_node *np)
	243	{
	244	int ret = 0;
	245
	246	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
	247	&timing->ddr3_speed_bin);
	248	ret \|= of_property_read_u32(np, "rockchip,pd_idle",
	249	&timing->pd_idle);
	250	ret \|= of_property_read_u32(np, "rockchip,sr_idle",
	251	&timing->sr_idle);
	252	ret \|= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
	253	&timing->sr_mc_gate_idle);
	254	ret \|= of_property_read_u32(np, "rockchip,srpd_lite_idle",
	255	&timing->srpd_lite_idle);
	256	ret \|= of_property_read_u32(np, "rockchip,standby_idle",
	257	&timing->standby_idle);
	258	ret \|= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
	259	&timing->auto_pd_dis_freq);
	260	ret \|= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
	261	&timing->dram_dll_dis_freq);
	262	ret \|= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
	263	&timing->phy_dll_dis_freq);
	264	ret \|= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
	265	&timing->ddr3_odt_dis_freq);
	266	ret \|= of_property_read_u32(np, "rockchip,ddr3_drv",
	267	&timing->ddr3_drv);
	268	ret \|= of_property_read_u32(np, "rockchip,ddr3_odt",
	269	&timing->ddr3_odt);
	270	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
	271	&timing->phy_ddr3_ca_drv);
	272	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
	273	&timing->phy_ddr3_dq_drv);
	274	ret \|= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
	275	&timing->phy_ddr3_odt);
	276	ret \|= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
	277	&timing->lpddr3_odt_dis_freq);
	278	ret \|= of_property_read_u32(np, "rockchip,lpddr3_drv",
	279	&timing->lpddr3_drv);
	280	ret \|= of_property_read_u32(np, "rockchip,lpddr3_odt",
	281	&timing->lpddr3_odt);
	282	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
	283	&timing->phy_lpddr3_ca_drv);
	284	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
	285	&timing->phy_lpddr3_dq_drv);
	286	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
	287	&timing->phy_lpddr3_odt);
	288	ret \|= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
	289	&timing->lpddr4_odt_dis_freq);
	290	ret \|= of_property_read_u32(np, "rockchip,lpddr4_drv",
	291	&timing->lpddr4_drv);
	292	ret \|= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
	293	&timing->lpddr4_dq_odt);
	294	ret \|= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
	295	&timing->lpddr4_ca_odt);
	296	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
	297	&timing->phy_lpddr4_ca_drv);
	298	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
	299	&timing->phy_lpddr4_ck_cs_drv);
	300	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
	301	&timing->phy_lpddr4_dq_drv);
	302	ret \|= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
	303	&timing->phy_lpddr4_odt);
	304
305	return ret;
306	}
307
308	static int rk3399_dmcfreq_probe(struct platform_device *pdev)
309	{
310	struct arm_smccc_res res;
311	struct device *dev = &pdev->dev;
9173c5ce	312	struct device_node np = pdev->dev.of_node, node;
5a893e31	313	struct rk3399_dmcfreq *data;
90dd72e1	314	int ret, index, size;
5a893e31 LH	315	uint32_t *timing;
5a893e31 LH	316	struct dev_pm_opp *opp;
9173c5ce EBS	317	u32 ddr_type;
9173c5ce EBS	318	u32 val;
5a893e31	319
5a893e31 LH	320	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
	321	if (!data)
	322	return -ENOMEM;
	323
	324	mutex_init(&data->lock);
	325
	326	data->vdd_center = devm_regulator_get(dev, "center");
fbf821ec KK	327	if (IS_ERR(data->vdd_center))
	328	return dev_err_probe(dev, PTR_ERR(data->vdd_center),
	329	"Cannot get the regulator \"center\"\n");
5a893e31 LH	330
5a893e31 LH	331	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
fbf821ec KK	332	if (IS_ERR(data->dmc_clk))
	333	return dev_err_probe(dev, PTR_ERR(data->dmc_clk),
	334	"Cannot get the clk dmc_clk\n");
5a893e31	335
02bdbf7d	336	data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
5a893e31 LH	337	if (IS_ERR(data->edev))
	338	return -EPROBE_DEFER;
	339
	340	ret = devfreq_event_enable_edev(data->edev);
	341	if (ret < 0) {
	342	dev_err(dev, "failed to enable devfreq-event devices\n");
	343	return ret;
	344	}
	345
	346	/*
	347	* Get dram timing and pass it to arm trust firmware,
0a453aca	348	* the dram driver in arm trust firmware will get these
5a893e31 LH	349	* timing and to do dram initial.
	350	*/
	351	if (!of_get_ddr_timings(&data->timing, np)) {
	352	timing = &data->timing.ddr3_speed_bin;
	353	size = sizeof(struct dram_timing) / 4;
	354	for (index = 0; index < size; index++) {
	355	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
	356	ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
	357	0, 0, 0, 0, &res);
	358	if (res.a0) {
	359	dev_err(dev, "Failed to set dram param: %ld\n",
	360	res.a0);
39a6e473 YL	361	ret = -EINVAL;
39a6e473 YL	362	goto err_edev;
5a893e31 LH	363	}
	364	}
	365	}
	366
9173c5ce	367	node = of_parse_phandle(np, "rockchip,pmu", 0);
63ef91f2 MZ	368	if (!node)
	369	goto no_pmu;
	370
	371	data->regmap_pmu = syscon_node_to_regmap(node);
	372	of_node_put(node);
	373	if (IS_ERR(data->regmap_pmu)) {
	374	ret = PTR_ERR(data->regmap_pmu);
	375	goto err_edev;
9173c5ce EBS	376	}
	377
	378	regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
	379	ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
	380	RK3399_PMUGRF_DDRTYPE_MASK;
	381
	382	switch (ddr_type) {
	383	case RK3399_PMUGRF_DDRTYPE_DDR3:
	384	data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
	385	break;
	386	case RK3399_PMUGRF_DDRTYPE_LPDDR3:
	387	data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
	388	break;
	389	case RK3399_PMUGRF_DDRTYPE_LPDDR4:
	390	data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
	391	break;
	392	default:
39a6e473 YL	393	ret = -EINVAL;
39a6e473 YL	394	goto err_edev;
fc1745c0	395	}
9173c5ce	396
63ef91f2	397	no_pmu:
5a893e31 LH	398	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
	399	ROCKCHIP_SIP_CONFIG_DRAM_INIT,
	400	0, 0, 0, 0, &res);
	401
9173c5ce EBS	402	/*
	403	* In TF-A there is a platform SIP call to set the PD (power-down)
	404	* timings and to enable or disable the ODT (on-die termination).
	405	* This call needs three arguments as follows:
	406	*
	407	* arg0:
	408	* bit[0-7] : sr_idle
	409	* bit[8-15] : sr_mc_gate_idle
	410	* bit[16-31] : standby idle
	411	* arg1:
	412	* bit[0-11] : pd_idle
	413	* bit[16-27] : srpd_lite_idle
	414	* arg2:
	415	* bit[0] : odt enable
	416	*/
	417	data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) \|
	418	((data->timing.sr_mc_gate_idle & 0xff) << 8) \|
	419	((data->timing.standby_idle & 0xffff) << 16);
	420	data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) \|
	421	((data->timing.srpd_lite_idle & 0xfff) << 16);
	422
5a893e31 LH	423	/*
	424	* We add a devfreq driver to our parent since it has a device tree node
	425	* with operating points.
	426	*/
	427	if (dev_pm_opp_of_add_table(dev)) {
	428	dev_err(dev, "Invalid operating-points in device tree.\n");
39a6e473 YL	429	ret = -EINVAL;
39a6e473 YL	430	goto err_edev;
5a893e31 LH	431	}
	432
	433	of_property_read_u32(np, "upthreshold",
	434	&data->ondemand_data.upthreshold);
	435	of_property_read_u32(np, "downdifferential",
	436	&data->ondemand_data.downdifferential);
	437
	438	data->rate = clk_get_rate(data->dmc_clk);
	439
5a893e31	440	opp = devfreq_recommended_opp(dev, &data->rate, 0);
d6e98f3e EBS	441	if (IS_ERR(opp)) {
	442	ret = PTR_ERR(opp);
	443	goto err_free_opp;
	444	}
8a31d9d9	445
e37d3508 VK	446	data->rate = dev_pm_opp_get_freq(opp);
e37d3508 VK	447	data->volt = dev_pm_opp_get_voltage(opp);
8a31d9d9	448	dev_pm_opp_put(opp);
5a893e31 LH	449
	450	rk3399_devfreq_dmc_profile.initial_freq = data->rate;
	451
927b75a6	452	data->devfreq = devm_devfreq_add_device(dev,
5a893e31	453	&rk3399_devfreq_dmc_profile,
aa7c352f	454	DEVFREQ_GOV_SIMPLE_ONDEMAND,
5a893e31	455	&data->ondemand_data);
d6e98f3e EBS	456	if (IS_ERR(data->devfreq)) {
	457	ret = PTR_ERR(data->devfreq);
	458	goto err_free_opp;
	459	}
	460
5a893e31 LH	461	devm_devfreq_register_opp_notifier(dev, data->devfreq);
	462
	463	data->dev = dev;
	464	platform_set_drvdata(pdev, data);
	465
d6e98f3e EBS	466	return 0;
	467
	468	err_free_opp:
	469	dev_pm_opp_of_remove_table(&pdev->dev);
39a6e473 YL	470	err_edev:
	471	devfreq_event_disable_edev(data->edev);
	472
d6e98f3e EBS	473	return ret;
	474	}
	475
	476	static int rk3399_dmcfreq_remove(struct platform_device *pdev)
	477	{
	478	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
	479
	480	/*
	481	* Before remove the opp table we need to unregister the opp notifier.
	482	*/
	483	devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
	484	dev_pm_opp_of_remove_table(dmcfreq->dev);
	485
5a893e31 LH	486	return 0;
	487	}
	488
5a893e31 LH	489	static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
	490	{ .compatible = "rockchip,rk3399-dmc" },
	491	{ },
	492	};
2f3f1a26	493	MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
5a893e31 LH	494
	495	static struct platform_driver rk3399_dmcfreq_driver = {
	496	.probe = rk3399_dmcfreq_probe,
d6e98f3e	497	.remove = rk3399_dmcfreq_remove,
5a893e31 LH	498	.driver = {
	499	.name = "rk3399-dmc-freq",
	500	.pm = &rk3399_dmcfreq_pm,
	501	.of_match_table = rk3399dmc_devfreq_of_match,
	502	},
	503	};
	504	module_platform_driver(rk3399_dmcfreq_driver);
	505
	506	MODULE_LICENSE("GPL v2");
	507	MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
	508	MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");