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09d09e04 DW |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* Copyright(c) 2023 Intel Corporation. All rights reserved. */ | |
3 | #include <linux/module.h> | |
4 | #include <linux/dax.h> | |
5 | ||
6 | #include "../cxl/cxl.h" | |
7 | #include "bus.h" | |
8 | ||
9 | static int cxl_dax_region_probe(struct device *dev) | |
10 | { | |
11 | struct cxl_dax_region *cxlr_dax = to_cxl_dax_region(dev); | |
12 | int nid = phys_to_target_node(cxlr_dax->hpa_range.start); | |
13 | struct cxl_region *cxlr = cxlr_dax->cxlr; | |
14 | struct dax_region *dax_region; | |
15 | struct dev_dax_data data; | |
09d09e04 DW |
16 | |
17 | if (nid == NUMA_NO_NODE) | |
18 | nid = memory_add_physaddr_to_nid(cxlr_dax->hpa_range.start); | |
19 | ||
20 | dax_region = alloc_dax_region(dev, cxlr->id, &cxlr_dax->hpa_range, nid, | |
21 | PMD_SIZE, IORESOURCE_DAX_KMEM); | |
22 | if (!dax_region) | |
23 | return -ENOMEM; | |
24 | ||
25 | data = (struct dev_dax_data) { | |
26 | .dax_region = dax_region, | |
27 | .id = -1, | |
28 | .size = range_len(&cxlr_dax->hpa_range), | |
4eca0ef4 | 29 | .memmap_on_memory = true, |
09d09e04 | 30 | }; |
09d09e04 | 31 | |
2532f416 | 32 | return PTR_ERR_OR_ZERO(devm_create_dev_dax(&data)); |
09d09e04 DW |
33 | } |
34 | ||
35 | static struct cxl_driver cxl_dax_region_driver = { | |
36 | .name = "cxl_dax_region", | |
37 | .probe = cxl_dax_region_probe, | |
38 | .id = CXL_DEVICE_DAX_REGION, | |
39 | .drv = { | |
40 | .suppress_bind_attrs = true, | |
41 | }, | |
42 | }; | |
43 | ||
44 | module_cxl_driver(cxl_dax_region_driver); | |
45 | MODULE_ALIAS_CXL(CXL_DEVICE_DAX_REGION); | |
46 | MODULE_LICENSE("GPL"); | |
47 | MODULE_AUTHOR("Intel Corporation"); | |
48 | MODULE_IMPORT_NS(CXL); |