[linux-block.git] / drivers / cxl / port.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
#include <linux/device.h>
#include <linux/module.h>
#include <linux/slab.h>

#include "cxlmem.h"
#include "cxlpci.h"

/**
 * DOC: cxl port
 *
 * The port driver enumerates dport via PCI and scans for HDM
 * (Host-managed-Device-Memory) decoder resources via the
 * @component_reg_phys value passed in by the agent that registered the
 * port. All descendant ports of a CXL root port (described by platform
 * firmware) are managed in this drivers context. Each driver instance
 * is responsible for tearing down the driver context of immediate
 * descendant ports. The locking for this is validated by
 * CONFIG_PROVE_CXL_LOCKING.
 *
 * The primary service this driver provides is presenting APIs to other
 * drivers to utilize the decoders, and indicating to userspace (via bind
 * status) the connectivity of the CXL.mem protocol throughout the
 * PCIe topology.
 */

static void schedule_detach(void *cxlmd)
{
	schedule_cxl_memdev_detach(cxlmd);
}

static int cxl_switch_port_probe(struct cxl_port *port)
{
	struct cxl_hdm *cxlhdm;
	int rc;

	rc = devm_cxl_port_enumerate_dports(port);
	if (rc < 0)
		return rc;

	if (rc == 1)
		return devm_cxl_add_passthrough_decoder(port);

	cxlhdm = devm_cxl_setup_hdm(port);
	if (IS_ERR(cxlhdm))
		return PTR_ERR(cxlhdm);

	return devm_cxl_enumerate_decoders(cxlhdm);
}

static int cxl_endpoint_port_probe(struct cxl_port *port)
{
	struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
	struct cxl_dev_state *cxlds = cxlmd->cxlds;
	struct cxl_hdm *cxlhdm;
	int rc;

	cxlhdm = devm_cxl_setup_hdm(port);
	if (IS_ERR(cxlhdm))
		return PTR_ERR(cxlhdm);

	/* Cache the data early to ensure is_visible() works */
	read_cdat_data(port);

	get_device(&cxlmd->dev);
	rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd);
	if (rc)
		return rc;

	rc = cxl_hdm_decode_init(cxlds, cxlhdm);
	if (rc)
		return rc;

	rc = cxl_await_media_ready(cxlds);
	if (rc) {
		dev_err(&port->dev, "Media not active (%d)\n", rc);
		return rc;
	}

	return devm_cxl_enumerate_decoders(cxlhdm);
}

static int cxl_port_probe(struct device *dev)
{
	struct cxl_port *port = to_cxl_port(dev);

	if (is_cxl_endpoint(port))
		return cxl_endpoint_port_probe(port);
	return cxl_switch_port_probe(port);
}

static ssize_t CDAT_read(struct file *filp, struct kobject *kobj,
			 struct bin_attribute *bin_attr, char *buf,
			 loff_t offset, size_t count)
{
	struct device *dev = kobj_to_dev(kobj);
	struct cxl_port *port = to_cxl_port(dev);

	if (!port->cdat_available)
		return -ENXIO;

	if (!port->cdat.table)
		return 0;

	return memory_read_from_buffer(buf, count, &offset,
				       port->cdat.table,
				       port->cdat.length);
}

static BIN_ATTR_ADMIN_RO(CDAT, 0);

static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
					    struct bin_attribute *attr, int i)
{
	struct device *dev = kobj_to_dev(kobj);
	struct cxl_port *port = to_cxl_port(dev);

	if ((attr == &bin_attr_CDAT) && port->cdat_available)
		return attr->attr.mode;

	return 0;
}

static struct bin_attribute *cxl_cdat_bin_attributes[] = {
	&bin_attr_CDAT,
	NULL,
};

static struct attribute_group cxl_cdat_attribute_group = {
	.bin_attrs = cxl_cdat_bin_attributes,
	.is_bin_visible = cxl_port_bin_attr_is_visible,
};

static const struct attribute_group *cxl_port_attribute_groups[] = {
	&cxl_cdat_attribute_group,
	NULL,
};

static struct cxl_driver cxl_port_driver = {
	.name = "cxl_port",
	.probe = cxl_port_probe,
	.id = CXL_DEVICE_PORT,
	.drv = {
		.dev_groups = cxl_port_attribute_groups,
	},
};

module_cxl_driver(cxl_port_driver);
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(CXL);
MODULE_ALIAS_CXL(CXL_DEVICE_PORT);
Commit	Line	Data
54cdbf84 BW	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
	3	#include <linux/device.h>
	4	#include <linux/module.h>
	5	#include <linux/slab.h>
	6
	7	#include "cxlmem.h"
	8	#include "cxlpci.h"
	9
	10	/**
	11	* DOC: cxl port
	12	*
	13	* The port driver enumerates dport via PCI and scans for HDM
	14	* (Host-managed-Device-Memory) decoder resources via the
	15	* @component_reg_phys value passed in by the agent that registered the
	16	* port. All descendant ports of a CXL root port (described by platform
	17	* firmware) are managed in this drivers context. Each driver instance
	18	* is responsible for tearing down the driver context of immediate
	19	* descendant ports. The locking for this is validated by
	20	* CONFIG_PROVE_CXL_LOCKING.
	21	*
	22	* The primary service this driver provides is presenting APIs to other
	23	* drivers to utilize the decoders, and indicating to userspace (via bind
	24	* status) the connectivity of the CXL.mem protocol throughout the
	25	* PCIe topology.
	26	*/
	27
8dd2bc0f BW	28	static void schedule_detach(void *cxlmd)
	29	{
	30	schedule_cxl_memdev_detach(cxlmd);
	31	}
	32
32ce3f18	33	static int cxl_switch_port_probe(struct cxl_port *port)
54cdbf84	34	{
54cdbf84 BW	35	struct cxl_hdm *cxlhdm;
	36	int rc;
	37
32ce3f18 DW	38	rc = devm_cxl_port_enumerate_dports(port);
	39	if (rc < 0)
	40	return rc;
fcfbc93c	41
32ce3f18 DW	42	if (rc == 1)
32ce3f18 DW	43	return devm_cxl_add_passthrough_decoder(port);
fcfbc93c DW	44
	45	cxlhdm = devm_cxl_setup_hdm(port);
	46	if (IS_ERR(cxlhdm))
	47	return PTR_ERR(cxlhdm);
	48
32ce3f18 DW	49	return devm_cxl_enumerate_decoders(cxlhdm);
32ce3f18 DW	50	}
8dd2bc0f	51
32ce3f18 DW	52	static int cxl_endpoint_port_probe(struct cxl_port *port)
	53	{
	54	struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
	55	struct cxl_dev_state *cxlds = cxlmd->cxlds;
	56	struct cxl_hdm *cxlhdm;
	57	int rc;
c9700604	58
32ce3f18 DW	59	cxlhdm = devm_cxl_setup_hdm(port);
	60	if (IS_ERR(cxlhdm))
	61	return PTR_ERR(cxlhdm);
5e5f4ad5	62
32ce3f18 DW	63	/* Cache the data early to ensure is_visible() works */
32ce3f18 DW	64	read_cdat_data(port);
5e5f4ad5	65
32ce3f18 DW	66	get_device(&cxlmd->dev);
	67	rc = devm_add_action_or_reset(&port->dev, schedule_detach, cxlmd);
	68	if (rc)
	69	return rc;
8dd2bc0f	70
32ce3f18 DW	71	rc = cxl_hdm_decode_init(cxlds, cxlhdm);
	72	if (rc)
	73	return rc;
	74
	75	rc = cxl_await_media_ready(cxlds);
54cdbf84	76	if (rc) {
32ce3f18	77	dev_err(&port->dev, "Media not active (%d)\n", rc);
54cdbf84 BW	78	return rc;
	79	}
	80
32ce3f18 DW	81	return devm_cxl_enumerate_decoders(cxlhdm);
	82	}
	83
	84	static int cxl_port_probe(struct device *dev)
	85	{
	86	struct cxl_port *port = to_cxl_port(dev);
	87
	88	if (is_cxl_endpoint(port))
	89	return cxl_endpoint_port_probe(port);
	90	return cxl_switch_port_probe(port);
54cdbf84 BW	91	}
54cdbf84 BW	92
c9700604 IW	93	static ssize_t CDAT_read(struct file filp, struct kobject kobj,
	94	struct bin_attribute bin_attr, char buf,
	95	loff_t offset, size_t count)
	96	{
	97	struct device *dev = kobj_to_dev(kobj);
	98	struct cxl_port *port = to_cxl_port(dev);
	99
	100	if (!port->cdat_available)
	101	return -ENXIO;
	102
	103	if (!port->cdat.table)
	104	return 0;
	105
	106	return memory_read_from_buffer(buf, count, &offset,
	107	port->cdat.table,
	108	port->cdat.length);
	109	}
	110
	111	static BIN_ATTR_ADMIN_RO(CDAT, 0);
	112
	113	static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
	114	struct bin_attribute *attr, int i)
	115	{
	116	struct device *dev = kobj_to_dev(kobj);
	117	struct cxl_port *port = to_cxl_port(dev);
	118
	119	if ((attr == &bin_attr_CDAT) && port->cdat_available)
	120	return attr->attr.mode;
	121
	122	return 0;
	123	}
	124
	125	static struct bin_attribute *cxl_cdat_bin_attributes[] = {
	126	&bin_attr_CDAT,
	127	NULL,
	128	};
	129
	130	static struct attribute_group cxl_cdat_attribute_group = {
	131	.bin_attrs = cxl_cdat_bin_attributes,
	132	.is_bin_visible = cxl_port_bin_attr_is_visible,
	133	};
	134
	135	static const struct attribute_group *cxl_port_attribute_groups[] = {
	136	&cxl_cdat_attribute_group,
	137	NULL,
	138	};
	139
54cdbf84 BW	140	static struct cxl_driver cxl_port_driver = {
	141	.name = "cxl_port",
	142	.probe = cxl_port_probe,
	143	.id = CXL_DEVICE_PORT,
c9700604 IW	144	.drv = {
	145	.dev_groups = cxl_port_attribute_groups,
	146	},
54cdbf84 BW	147	};
	148
	149	module_cxl_driver(cxl_port_driver);
	150	MODULE_LICENSE("GPL v2");
	151	MODULE_IMPORT_NS(CXL);
	152	MODULE_ALIAS_CXL(CXL_DEVICE_PORT);