projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 4cdadfd5 DW |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ | |
| 3 | #ifndef __CXL_PCI_H__ | |
| 4 | #define __CXL_PCI_H__ | |
| 54cdbf84 | 5 | #include <linux/pci.h> |
| af9cae9f | 6 | #include "cxl.h" |
| 4cdadfd5 DW |
7 | |
| 8 | #define CXL_MEMORY_PROGIF 0x10 | |
| 9 | ||
| 10 | /* | |
| 11 | * See section 8.1 Configuration Space Registers in the CXL 2.0 | |
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12 | * Specification. Names are taken straight from the specification with "CXL" and |
| 13 | * "DVSEC" redundancies removed. When obvious, abbreviations may be used. | |
| 4cdadfd5 | 14 | */ |
| 8adaf747 | 15 | #define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) |
| 4cdadfd5 | 16 | #define PCI_DVSEC_VENDOR_ID_CXL 0x1E98 |
| 4cdadfd5 | 17 | |
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18 | /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ |
| 19 | #define CXL_DVSEC_PCIE_DEVICE 0 | |
| 8adaf747 | 20 | |
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21 | /* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ |
| 22 | #define CXL_DVSEC_FUNCTION_MAP 2 | |
| 23 | ||
| 24 | /* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ | |
| 25 | #define CXL_DVSEC_PORT_EXTENSIONS 3 | |
| 26 | ||
| 27 | /* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ | |
| 28 | #define CXL_DVSEC_PORT_GPF 4 | |
| 29 | ||
| 30 | /* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ | |
| 31 | #define CXL_DVSEC_DEVICE_GPF 5 | |
| 32 | ||
| 33 | /* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ | |
| 34 | #define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 | |
| 35 | ||
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36 | /* CXL 2.0 8.1.9: Register Locator DVSEC */ |
| 37 | #define CXL_DVSEC_REG_LOCATOR 8 | |
| 38 | #define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC | |
| 39 | #define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0) | |
| 40 | #define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8) | |
| 41 | #define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16) | |
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42 | |
| 43 | /* Register Block Identifier (RBI) */ | |
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44 | enum cxl_regloc_type { |
| 45 | CXL_REGLOC_RBI_EMPTY = 0, | |
| 46 | CXL_REGLOC_RBI_COMPONENT, | |
| 47 | CXL_REGLOC_RBI_VIRT, | |
| 48 | CXL_REGLOC_RBI_MEMDEV, | |
| 49 | CXL_REGLOC_RBI_TYPES | |
| 50 | }; | |
| 8adaf747 | 51 | |
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52 | static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev, |
| 53 | struct cxl_register_map *map) | |
| 54 | { | |
| 55 | if (map->block_offset == U64_MAX) | |
| 56 | return CXL_RESOURCE_NONE; | |
| 57 | ||
| 58 | return pci_resource_start(pdev, map->barno) + map->block_offset; | |
| 59 | } | |
| 60 | ||
| 98d2d3a2 | 61 | int devm_cxl_port_enumerate_dports(struct device *host, struct cxl_port *port); |
| 4cdadfd5 | 62 | #endif /* __CXL_PCI_H__ */ |