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1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ | |
3 | #ifndef __CXL_PCI_H__ | |
4 | #define __CXL_PCI_H__ | |
54cdbf84 | 5 | #include <linux/pci.h> |
af9cae9f | 6 | #include "cxl.h" |
4cdadfd5 DW |
7 | |
8 | #define CXL_MEMORY_PROGIF 0x10 | |
9 | ||
10 | /* | |
11 | * See section 8.1 Configuration Space Registers in the CXL 2.0 | |
46c6ad27 BW |
12 | * Specification. Names are taken straight from the specification with "CXL" and |
13 | * "DVSEC" redundancies removed. When obvious, abbreviations may be used. | |
4cdadfd5 | 14 | */ |
8adaf747 | 15 | #define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) |
4cdadfd5 | 16 | #define PCI_DVSEC_VENDOR_ID_CXL 0x1E98 |
4cdadfd5 | 17 | |
46c6ad27 BW |
18 | /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ |
19 | #define CXL_DVSEC_PCIE_DEVICE 0 | |
560f7855 BW |
20 | #define CXL_DVSEC_CAP_OFFSET 0xA |
21 | #define CXL_DVSEC_MEM_CAPABLE BIT(2) | |
22 | #define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4) | |
23 | #define CXL_DVSEC_CTRL_OFFSET 0xC | |
24 | #define CXL_DVSEC_MEM_ENABLE BIT(2) | |
25 | #define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) | |
26 | #define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) | |
27 | #define CXL_DVSEC_MEM_INFO_VALID BIT(0) | |
28 | #define CXL_DVSEC_MEM_ACTIVE BIT(1) | |
29 | #define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28) | |
30 | #define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) | |
31 | #define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) | |
32 | #define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28) | |
8adaf747 | 33 | |
ce17ad0d DJ |
34 | #define CXL_DVSEC_RANGE_MAX 2 |
35 | ||
8baa787b BW |
36 | /* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ |
37 | #define CXL_DVSEC_FUNCTION_MAP 2 | |
38 | ||
39 | /* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ | |
40 | #define CXL_DVSEC_PORT_EXTENSIONS 3 | |
41 | ||
42 | /* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ | |
43 | #define CXL_DVSEC_PORT_GPF 4 | |
44 | ||
45 | /* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ | |
46 | #define CXL_DVSEC_DEVICE_GPF 5 | |
47 | ||
48 | /* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ | |
49 | #define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 | |
50 | ||
46c6ad27 BW |
51 | /* CXL 2.0 8.1.9: Register Locator DVSEC */ |
52 | #define CXL_DVSEC_REG_LOCATOR 8 | |
53 | #define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC | |
54 | #define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0) | |
55 | #define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8) | |
56 | #define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16) | |
8adaf747 | 57 | |
a49aa814 DB |
58 | /* |
59 | * NOTE: Currently all the functions which are enabled for CXL require their | |
60 | * vectors to be in the first 16. Use this as the default max. | |
61 | */ | |
62 | #define CXL_PCI_DEFAULT_MAX_VECTORS 16 | |
63 | ||
8adaf747 | 64 | /* Register Block Identifier (RBI) */ |
cdcce47c BW |
65 | enum cxl_regloc_type { |
66 | CXL_REGLOC_RBI_EMPTY = 0, | |
67 | CXL_REGLOC_RBI_COMPONENT, | |
68 | CXL_REGLOC_RBI_VIRT, | |
69 | CXL_REGLOC_RBI_MEMDEV, | |
1ad3f701 | 70 | CXL_REGLOC_RBI_PMU, |
cdcce47c BW |
71 | CXL_REGLOC_RBI_TYPES |
72 | }; | |
8adaf747 | 73 | |
b56faef2 LW |
74 | struct cdat_header { |
75 | __le32 length; | |
76 | u8 revision; | |
77 | u8 checksum; | |
78 | u8 reserved[6]; | |
79 | __le32 sequence; | |
80 | } __packed; | |
81 | ||
82 | struct cdat_entry_header { | |
83 | u8 type; | |
84 | u8 reserved; | |
85 | __le16 length; | |
86 | } __packed; | |
87 | ||
664bf115 | 88 | int devm_cxl_port_enumerate_dports(struct cxl_port *port); |
14d78874 | 89 | struct cxl_dev_state; |
59c3368b DJ |
90 | int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, |
91 | struct cxl_endpoint_dvsec_info *info); | |
c9700604 | 92 | void read_cdat_data(struct cxl_port *port); |
4a20bc3e DW |
93 | void cxl_cor_error_detected(struct pci_dev *pdev); |
94 | pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, | |
95 | pci_channel_state_t state); | |
4cdadfd5 | 96 | #endif /* __CXL_PCI_H__ */ |