[linux-block.git] / drivers / cxl / cxlmem.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright(c) 2020-2021 Intel Corporation. */
#ifndef __CXL_MEM_H__
#define __CXL_MEM_H__
#include <uapi/linux/cxl_mem.h>
#include <linux/cdev.h>
#include <linux/uuid.h>
#include "cxl.h"

/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
#define CXLMDEV_STATUS_OFFSET 0x0
#define   CXLMDEV_DEV_FATAL BIT(0)
#define   CXLMDEV_FW_HALT BIT(1)
#define   CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
#define     CXLMDEV_MS_NOT_READY 0
#define     CXLMDEV_MS_READY 1
#define     CXLMDEV_MS_ERROR 2
#define     CXLMDEV_MS_DISABLED 3
#define CXLMDEV_READY(status)                                                  \
	(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) ==                \
	 CXLMDEV_MS_READY)
#define   CXLMDEV_MBOX_IF_READY BIT(4)
#define   CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
#define     CXLMDEV_RESET_NEEDED_NOT 0
#define     CXLMDEV_RESET_NEEDED_COLD 1
#define     CXLMDEV_RESET_NEEDED_WARM 2
#define     CXLMDEV_RESET_NEEDED_HOT 3
#define     CXLMDEV_RESET_NEEDED_CXL 4
#define CXLMDEV_RESET_NEEDED(status)                                           \
	(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) !=                       \
	 CXLMDEV_RESET_NEEDED_NOT)

/**
 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
 * @dev: driver core device object
 * @cdev: char dev core object for ioctl operations
 * @cxlds: The device state backing this device
 * @detach_work: active memdev lost a port in its ancestry
 * @cxl_nvb: coordinate removal of @cxl_nvd if present
 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
 * @id: id number of this memdev instance.
 */
struct cxl_memdev {
	struct device dev;
	struct cdev cdev;
	struct cxl_dev_state *cxlds;
	struct work_struct detach_work;
	struct cxl_nvdimm_bridge *cxl_nvb;
	struct cxl_nvdimm *cxl_nvd;
	int id;
};

static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
{
	return container_of(dev, struct cxl_memdev, dev);
}

static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
{
	return to_cxl_port(cxled->cxld.dev.parent);
}

static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
{
	return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
}

static inline struct cxl_memdev *
cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
{
	struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);

	return to_cxl_memdev(port->uport);
}

bool is_cxl_memdev(struct device *dev);
static inline bool is_cxl_endpoint(struct cxl_port *port)
{
	return is_cxl_memdev(port->uport);
}

struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);

static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
					 struct cxl_memdev *cxlmd)
{
	if (!port)
		return NULL;

	return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
}

/**
 * struct cxl_mbox_cmd - A command to be submitted to hardware.
 * @opcode: (input) The command set and command submitted to hardware.
 * @payload_in: (input) Pointer to the input payload.
 * @payload_out: (output) Pointer to the output payload. Must be allocated by
 *		 the caller.
 * @size_in: (input) Number of bytes to load from @payload_in.
 * @size_out: (input) Max number of bytes loaded into @payload_out.
 *            (output) Number of bytes generated by the device. For fixed size
 *            outputs commands this is always expected to be deterministic. For
 *            variable sized output commands, it tells the exact number of bytes
 *            written.
 * @min_out: (input) internal command output payload size validation
 * @return_code: (output) Error code returned from hardware.
 *
 * This is the primary mechanism used to send commands to the hardware.
 * All the fields except @payload_* correspond exactly to the fields described in
 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
 * @payload_out are written to, and read from the Command Payload Registers
 * defined in CXL 2.0 8.2.8.4.8.
 */
struct cxl_mbox_cmd {
	u16 opcode;
	void *payload_in;
	void *payload_out;
	size_t size_in;
	size_t size_out;
	size_t min_out;
	u16 return_code;
};

/*
 * Per CXL 2.0 Section 8.2.8.4.5.1
 */
#define CMD_CMD_RC_TABLE							\
	C(SUCCESS, 0, NULL),							\
	C(BACKGROUND, -ENXIO, "background cmd started successfully"),           \
	C(INPUT, -ENXIO, "cmd input was invalid"),				\
	C(UNSUPPORTED, -ENXIO, "cmd is not supported"),				\
	C(INTERNAL, -ENXIO, "internal device error"),				\
	C(RETRY, -ENXIO, "temporary error, retry once"),			\
	C(BUSY, -ENXIO, "ongoing background operation"),			\
	C(MEDIADISABLED, -ENXIO, "media access is disabled"),			\
	C(FWINPROGRESS, -ENXIO,	"one FW package can be transferred at a time"), \
	C(FWOOO, -ENXIO, "FW package content was transferred out of order"),    \
	C(FWAUTH, -ENXIO, "FW package authentication failed"),			\
	C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"),  \
	C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"),         \
	C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"),		\
	C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"),     \
	C(PADDR, -ENXIO, "physical address specified is invalid"),		\
	C(POISONLMT, -ENXIO, "poison injection limit has been reached"),        \
	C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"),		\
	C(ABORT, -ENXIO, "background cmd was aborted by device"),               \
	C(SECURITY, -ENXIO, "not valid in the current security state"),         \
	C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"),   \
	C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
	C(PAYLOADLEN, -ENXIO, "invalid payload length")

#undef C
#define C(a, b, c) CXL_MBOX_CMD_RC_##a
enum  { CMD_CMD_RC_TABLE };
#undef C
#define C(a, b, c) { b, c }
struct cxl_mbox_cmd_rc {
	int err;
	const char *desc;
};

static const
struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
#undef C

static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
{
	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
}

static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
{
	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
}

/*
 * CXL 2.0 - Memory capacity multiplier
 * See Section 8.2.9.5
 *
 * Volatile, Persistent, and Partition capacities are specified to be in
 * multiples of 256MB - define a multiplier to convert to/from bytes.
 */
#define CXL_CAPACITY_MULTIPLIER SZ_256M

/**
 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
 * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
 * @ranges: Number of active HDM ranges this device uses.
 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
 */
struct cxl_endpoint_dvsec_info {
	bool mem_enabled;
	int ranges;
	struct range dvsec_range[2];
};

/**
 * struct cxl_event_state - Event log driver state
 *
 * @event_buf: Buffer to receive event data
 * @event_log_lock: Serialize event_buf and log use
 */
struct cxl_event_state {
	struct cxl_get_event_payload *buf;
	struct mutex log_lock;
};

/**
 * struct cxl_dev_state - The driver device state
 *
 * cxl_dev_state represents the CXL driver/device state.  It provides an
 * interface to mailbox commands as well as some cached data about the device.
 * Currently only memory devices are represented.
 *
 * @dev: The device associated with this CXL state
 * @cxlmd: The device representing the CXL.mem capabilities of @dev
 * @regs: Parsed register blocks
 * @cxl_dvsec: Offset to the PCIe device DVSEC
 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
 * @payload_size: Size of space for payload
 *                (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
 * @lsa_size: Size of Label Storage Area
 *                (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
 * @mbox_mutex: Mutex to synchronize mailbox access.
 * @firmware_version: Firmware version for the memory device.
 * @enabled_cmds: Hardware commands found enabled in CEL.
 * @exclusive_cmds: Commands that are kernel-internal only
 * @dpa_res: Overall DPA resource tree for the device
 * @pmem_res: Active Persistent memory capacity configuration
 * @ram_res: Active Volatile memory capacity configuration
 * @total_bytes: sum of all possible capacities
 * @volatile_only_bytes: hard volatile capacity
 * @persistent_only_bytes: hard persistent capacity
 * @partition_align_bytes: alignment size for partition-able capacity
 * @active_volatile_bytes: sum of hard + soft volatile
 * @active_persistent_bytes: sum of hard + soft persistent
 * @next_volatile_bytes: volatile capacity change pending device reset
 * @next_persistent_bytes: persistent capacity change pending device reset
 * @component_reg_phys: register base of component registers
 * @info: Cached DVSEC information about the device.
 * @serial: PCIe Device Serial Number
 * @doe_mbs: PCI DOE mailbox array
 * @mbox_send: @dev specific transport for transmitting mailbox commands
 *
 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
 * details on capacity parameters.
 */
struct cxl_dev_state {
	struct device *dev;
	struct cxl_memdev *cxlmd;

	struct cxl_regs regs;
	int cxl_dvsec;

	bool rcd;
	size_t payload_size;
	size_t lsa_size;
	struct mutex mbox_mutex; /* Protects device mailbox and firmware */
	char firmware_version[0x10];
	DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
	DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);

	struct resource dpa_res;
	struct resource pmem_res;
	struct resource ram_res;
	u64 total_bytes;
	u64 volatile_only_bytes;
	u64 persistent_only_bytes;
	u64 partition_align_bytes;

	u64 active_volatile_bytes;
	u64 active_persistent_bytes;
	u64 next_volatile_bytes;
	u64 next_persistent_bytes;

	resource_size_t component_reg_phys;
	u64 serial;

	struct xarray doe_mbs;

	struct cxl_event_state event;

	int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
};

enum cxl_opcode {
	CXL_MBOX_OP_INVALID		= 0x0000,
	CXL_MBOX_OP_RAW			= CXL_MBOX_OP_INVALID,
	CXL_MBOX_OP_GET_EVENT_RECORD	= 0x0100,
	CXL_MBOX_OP_CLEAR_EVENT_RECORD	= 0x0101,
	CXL_MBOX_OP_GET_FW_INFO		= 0x0200,
	CXL_MBOX_OP_ACTIVATE_FW		= 0x0202,
	CXL_MBOX_OP_GET_SUPPORTED_LOGS	= 0x0400,
	CXL_MBOX_OP_GET_LOG		= 0x0401,
	CXL_MBOX_OP_IDENTIFY		= 0x4000,
	CXL_MBOX_OP_GET_PARTITION_INFO	= 0x4100,
	CXL_MBOX_OP_SET_PARTITION_INFO	= 0x4101,
	CXL_MBOX_OP_GET_LSA		= 0x4102,
	CXL_MBOX_OP_SET_LSA		= 0x4103,
	CXL_MBOX_OP_GET_HEALTH_INFO	= 0x4200,
	CXL_MBOX_OP_GET_ALERT_CONFIG	= 0x4201,
	CXL_MBOX_OP_SET_ALERT_CONFIG	= 0x4202,
	CXL_MBOX_OP_GET_SHUTDOWN_STATE	= 0x4203,
	CXL_MBOX_OP_SET_SHUTDOWN_STATE	= 0x4204,
	CXL_MBOX_OP_GET_POISON		= 0x4300,
	CXL_MBOX_OP_INJECT_POISON	= 0x4301,
	CXL_MBOX_OP_CLEAR_POISON	= 0x4302,
	CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS	= 0x4303,
	CXL_MBOX_OP_SCAN_MEDIA		= 0x4304,
	CXL_MBOX_OP_GET_SCAN_MEDIA	= 0x4305,
	CXL_MBOX_OP_GET_SECURITY_STATE	= 0x4500,
	CXL_MBOX_OP_SET_PASSPHRASE	= 0x4501,
	CXL_MBOX_OP_DISABLE_PASSPHRASE	= 0x4502,
	CXL_MBOX_OP_UNLOCK		= 0x4503,
	CXL_MBOX_OP_FREEZE_SECURITY	= 0x4504,
	CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE	= 0x4505,
	CXL_MBOX_OP_MAX			= 0x10000
};

#define DEFINE_CXL_CEL_UUID                                                    \
	UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62,     \
		  0x3b, 0x3f, 0x17)

#define DEFINE_CXL_VENDOR_DEBUG_UUID                                           \
	UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19,     \
		  0x40, 0x3d, 0x86)

struct cxl_mbox_get_supported_logs {
	__le16 entries;
	u8 rsvd[6];
	struct cxl_gsl_entry {
		uuid_t uuid;
		__le32 size;
	} __packed entry[];
}  __packed;

struct cxl_cel_entry {
	__le16 opcode;
	__le16 effect;
} __packed;

struct cxl_mbox_get_log {
	uuid_t uuid;
	__le32 offset;
	__le32 length;
} __packed;

/* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
struct cxl_mbox_identify {
	char fw_revision[0x10];
	__le64 total_capacity;
	__le64 volatile_capacity;
	__le64 persistent_capacity;
	__le64 partition_align;
	__le16 info_event_log_size;
	__le16 warning_event_log_size;
	__le16 failure_event_log_size;
	__le16 fatal_event_log_size;
	__le32 lsa_size;
	u8 poison_list_max_mer[3];
	__le16 inject_poison_limit;
	u8 poison_caps;
	u8 qos_telemetry_caps;
} __packed;

/*
 * Common Event Record Format
 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
 */
struct cxl_event_record_hdr {
	uuid_t id;
	u8 length;
	u8 flags[3];
	__le16 handle;
	__le16 related_handle;
	__le64 timestamp;
	u8 maint_op_class;
	u8 reserved[15];
} __packed;

#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
struct cxl_event_record_raw {
	struct cxl_event_record_hdr hdr;
	u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
} __packed;

/*
 * Get Event Records output payload
 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
 */
#define CXL_GET_EVENT_FLAG_OVERFLOW		BIT(0)
#define CXL_GET_EVENT_FLAG_MORE_RECORDS		BIT(1)
struct cxl_get_event_payload {
	u8 flags;
	u8 reserved1;
	__le16 overflow_err_count;
	__le64 first_overflow_timestamp;
	__le64 last_overflow_timestamp;
	__le16 record_count;
	u8 reserved2[10];
	struct cxl_event_record_raw records[];
} __packed;

/*
 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
 */
enum cxl_event_log_type {
	CXL_EVENT_TYPE_INFO = 0x00,
	CXL_EVENT_TYPE_WARN,
	CXL_EVENT_TYPE_FAIL,
	CXL_EVENT_TYPE_FATAL,
	CXL_EVENT_TYPE_MAX
};

/*
 * Clear Event Records input payload
 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
 */
struct cxl_mbox_clear_event_payload {
	u8 event_log;		/* enum cxl_event_log_type */
	u8 clear_flags;
	u8 nr_recs;
	u8 reserved[3];
	__le16 handles[];
} __packed;
#define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX

struct cxl_mbox_get_partition_info {
	__le64 active_volatile_cap;
	__le64 active_persistent_cap;
	__le64 next_volatile_cap;
	__le64 next_persistent_cap;
} __packed;

struct cxl_mbox_get_lsa {
	__le32 offset;
	__le32 length;
} __packed;

struct cxl_mbox_set_lsa {
	__le32 offset;
	__le32 reserved;
	u8 data[];
} __packed;

struct cxl_mbox_set_partition_info {
	__le64 volatile_capacity;
	u8 flags;
} __packed;

#define  CXL_SET_PARTITION_IMMEDIATE_FLAG	BIT(0)

/**
 * struct cxl_mem_command - Driver representation of a memory device command
 * @info: Command information as it exists for the UAPI
 * @opcode: The actual bits used for the mailbox protocol
 * @flags: Set of flags effecting driver behavior.
 *
 *  * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
 *    will be enabled by the driver regardless of what hardware may have
 *    advertised.
 *
 * The cxl_mem_command is the driver's internal representation of commands that
 * are supported by the driver. Some of these commands may not be supported by
 * the hardware. The driver will use @info to validate the fields passed in by
 * the user then submit the @opcode to the hardware.
 *
 * See struct cxl_command_info.
 */
struct cxl_mem_command {
	struct cxl_command_info info;
	enum cxl_opcode opcode;
	u32 flags;
#define CXL_CMD_FLAG_NONE 0
#define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
};

#define CXL_PMEM_SEC_STATE_USER_PASS_SET	0x01
#define CXL_PMEM_SEC_STATE_MASTER_PASS_SET	0x02
#define CXL_PMEM_SEC_STATE_LOCKED		0x04
#define CXL_PMEM_SEC_STATE_FROZEN		0x08
#define CXL_PMEM_SEC_STATE_USER_PLIMIT		0x10
#define CXL_PMEM_SEC_STATE_MASTER_PLIMIT	0x20

/* set passphrase input payload */
struct cxl_set_pass {
	u8 type;
	u8 reserved[31];
	/* CXL field using NVDIMM define, same length */
	u8 old_pass[NVDIMM_PASSPHRASE_LEN];
	u8 new_pass[NVDIMM_PASSPHRASE_LEN];
} __packed;

/* disable passphrase input payload */
struct cxl_disable_pass {
	u8 type;
	u8 reserved[31];
	u8 pass[NVDIMM_PASSPHRASE_LEN];
} __packed;

/* passphrase secure erase payload */
struct cxl_pass_erase {
	u8 type;
	u8 reserved[31];
	u8 pass[NVDIMM_PASSPHRASE_LEN];
} __packed;

enum {
	CXL_PMEM_SEC_PASS_MASTER = 0,
	CXL_PMEM_SEC_PASS_USER,
};

int cxl_internal_send_cmd(struct cxl_dev_state *cxlds,
			  struct cxl_mbox_cmd *cmd);
int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
int cxl_await_media_ready(struct cxl_dev_state *cxlds);
int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
struct cxl_dev_state *cxl_dev_state_create(struct device *dev);
void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
void cxl_mem_get_event_records(struct cxl_dev_state *cxlds, u32 status);
#ifdef CONFIG_CXL_SUSPEND
void cxl_mem_active_inc(void);
void cxl_mem_active_dec(void);
#else
static inline void cxl_mem_active_inc(void)
{
}
static inline void cxl_mem_active_dec(void)
{
}
#endif

struct cxl_hdm {
	struct cxl_component_regs regs;
	unsigned int decoder_count;
	unsigned int target_count;
	unsigned int interleave_mask;
	struct cxl_port *port;
};

struct seq_file;
struct dentry *cxl_debugfs_create_dir(const char *dir);
void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
#endif /* __CXL_MEM_H__ */
Commit	Line	Data
5f50d6b2 DW	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/* Copyright(c) 2020-2021 Intel Corporation. */
	3	#ifndef __CXL_MEM_H__
	4	#define __CXL_MEM_H__
4faf31b4	5	#include <uapi/linux/cxl_mem.h>
21083f51	6	#include <linux/cdev.h>
6ebe28f9	7	#include <linux/uuid.h>
21083f51	8	#include "cxl.h"
5f50d6b2 DW	9
	10	/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
	11	#define CXLMDEV_STATUS_OFFSET 0x0
	12	#define CXLMDEV_DEV_FATAL BIT(0)
	13	#define CXLMDEV_FW_HALT BIT(1)
	14	#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
	15	#define CXLMDEV_MS_NOT_READY 0
	16	#define CXLMDEV_MS_READY 1
	17	#define CXLMDEV_MS_ERROR 2
	18	#define CXLMDEV_MS_DISABLED 3
	19	#define CXLMDEV_READY(status) \
	20	(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
	21	CXLMDEV_MS_READY)
	22	#define CXLMDEV_MBOX_IF_READY BIT(4)
	23	#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
	24	#define CXLMDEV_RESET_NEEDED_NOT 0
	25	#define CXLMDEV_RESET_NEEDED_COLD 1
	26	#define CXLMDEV_RESET_NEEDED_WARM 2
	27	#define CXLMDEV_RESET_NEEDED_HOT 3
	28	#define CXLMDEV_RESET_NEEDED_CXL 4
	29	#define CXLMDEV_RESET_NEEDED(status) \
	30	(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
	31	CXLMDEV_RESET_NEEDED_NOT)
	32
5f50d6b2 DW	33	/**
	34	* struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
	35	* @dev: driver core device object
	36	* @cdev: char dev core object for ioctl operations
5e2411ae	37	* @cxlds: The device state backing this device
8dd2bc0f	38	* @detach_work: active memdev lost a port in its ancestry
f17b558d DW	39	* @cxl_nvb: coordinate removal of @cxl_nvd if present
f17b558d DW	40	* @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
5f50d6b2 DW	41	* @id: id number of this memdev instance.
	42	*/
	43	struct cxl_memdev {
	44	struct device dev;
	45	struct cdev cdev;
5e2411ae	46	struct cxl_dev_state *cxlds;
8dd2bc0f	47	struct work_struct detach_work;
f17b558d DW	48	struct cxl_nvdimm_bridge *cxl_nvb;
f17b558d DW	49	struct cxl_nvdimm *cxl_nvd;
5f50d6b2 DW	50	int id;
	51	};
	52
3d135db5 BW	53	static inline struct cxl_memdev to_cxl_memdev(struct device dev)
	54	{
	55	return container_of(dev, struct cxl_memdev, dev);
	56	}
	57
9c57cde0 DW	58	static inline struct cxl_port cxled_to_port(struct cxl_endpoint_decoder cxled)
	59	{
	60	return to_cxl_port(cxled->cxld.dev.parent);
	61	}
	62
384e624b DW	63	static inline struct cxl_port cxlrd_to_port(struct cxl_root_decoder cxlrd)
	64	{
	65	return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
	66	}
	67
9c57cde0 DW	68	static inline struct cxl_memdev *
	69	cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
	70	{
	71	struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
	72
	73	return to_cxl_memdev(port->uport);
	74	}
	75
8dd2bc0f BW	76	bool is_cxl_memdev(struct device *dev);
	77	static inline bool is_cxl_endpoint(struct cxl_port *port)
	78	{
	79	return is_cxl_memdev(port->uport);
	80	}
	81
5e2411ae	82	struct cxl_memdev devm_cxl_add_memdev(struct cxl_dev_state cxlds);
3d135db5	83
7592d935 DW	84	static inline struct cxl_ep cxl_ep_load(struct cxl_port port,
	85	struct cxl_memdev *cxlmd)
	86	{
	87	if (!port)
	88	return NULL;
	89
	90	return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
	91	}
	92
b64955a9 DW	93	/**
	94	* struct cxl_mbox_cmd - A command to be submitted to hardware.
	95	* @opcode: (input) The command set and command submitted to hardware.
	96	* @payload_in: (input) Pointer to the input payload.
	97	* @payload_out: (output) Pointer to the output payload. Must be allocated by
	98	* the caller.
	99	* @size_in: (input) Number of bytes to load from @payload_in.
	100	* @size_out: (input) Max number of bytes loaded into @payload_out.
	101	* (output) Number of bytes generated by the device. For fixed size
	102	* outputs commands this is always expected to be deterministic. For
	103	* variable sized output commands, it tells the exact number of bytes
	104	* written.
2aeaf663	105	* @min_out: (input) internal command output payload size validation
b64955a9 DW	106	* @return_code: (output) Error code returned from hardware.
	107	*
	108	* This is the primary mechanism used to send commands to the hardware.
	109	* All the fields except @payload_* correspond exactly to the fields described in
	110	* Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
	111	* @payload_out are written to, and read from the Command Payload Registers
	112	* defined in CXL 2.0 8.2.8.4.8.
	113	*/
	114	struct cxl_mbox_cmd {
	115	u16 opcode;
	116	void *payload_in;
	117	void *payload_out;
	118	size_t size_in;
	119	size_t size_out;
2aeaf663	120	size_t min_out;
b64955a9	121	u16 return_code;
b64955a9 DW	122	};
b64955a9 DW	123
92fcc1ab DB	124	/*
	125	* Per CXL 2.0 Section 8.2.8.4.5.1
	126	*/
	127	#define CMD_CMD_RC_TABLE \
	128	C(SUCCESS, 0, NULL), \
	129	C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
	130	C(INPUT, -ENXIO, "cmd input was invalid"), \
	131	C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
	132	C(INTERNAL, -ENXIO, "internal device error"), \
	133	C(RETRY, -ENXIO, "temporary error, retry once"), \
	134	C(BUSY, -ENXIO, "ongoing background operation"), \
	135	C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
	136	C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
	137	C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
	138	C(FWAUTH, -ENXIO, "FW package authentication failed"), \
	139	C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
	140	C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
	141	C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
	142	C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
	143	C(PADDR, -ENXIO, "physical address specified is invalid"), \
	144	C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \
	145	C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
	146	C(ABORT, -ENXIO, "background cmd was aborted by device"), \
	147	C(SECURITY, -ENXIO, "not valid in the current security state"), \
	148	C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
	149	C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
	150	C(PAYLOADLEN, -ENXIO, "invalid payload length")
	151
	152	#undef C
	153	#define C(a, b, c) CXL_MBOX_CMD_RC_##a
	154	enum { CMD_CMD_RC_TABLE };
	155	#undef C
	156	#define C(a, b, c) { b, c }
	157	struct cxl_mbox_cmd_rc {
	158	int err;
	159	const char *desc;
	160	};
	161
	162	static const
	163	struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
	164	#undef C
	165
	166	static inline const char cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd mbox_cmd)
	167	{
	168	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
	169	}
	170
	171	static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
	172	{
	173	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
	174	}
	175
b64955a9 DW	176	/*
	177	* CXL 2.0 - Memory capacity multiplier
	178	* See Section 8.2.9.5
	179	*
	180	* Volatile, Persistent, and Partition capacities are specified to be in
	181	* multiples of 256MB - define a multiplier to convert to/from bytes.
	182	*/
	183	#define CXL_CAPACITY_MULTIPLIER SZ_256M
	184
560f7855 BW	185	/**
	186	* struct cxl_endpoint_dvsec_info - Cached DVSEC info
	187	* @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
	188	* @ranges: Number of active HDM ranges this device uses.
	189	* @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
	190	*/
	191	struct cxl_endpoint_dvsec_info {
	192	bool mem_enabled;
	193	int ranges;
	194	struct range dvsec_range[2];
	195	};
	196
6ebe28f9 IW	197	/**
	198	* struct cxl_event_state - Event log driver state
	199	*
	200	* @event_buf: Buffer to receive event data
	201	* @event_log_lock: Serialize event_buf and log use
	202	*/
	203	struct cxl_event_state {
	204	struct cxl_get_event_payload *buf;
	205	struct mutex log_lock;
	206	};
	207
5f50d6b2	208	/**
5e2411ae IW	209	* struct cxl_dev_state - The driver device state
	210	*
	211	* cxl_dev_state represents the CXL driver/device state. It provides an
	212	* interface to mailbox commands as well as some cached data about the device.
	213	* Currently only memory devices are represented.
	214	*
	215	* @dev: The device associated with this CXL state
2905cb52	216	* @cxlmd: The device representing the CXL.mem capabilities of @dev
8ac75dd6	217	* @regs: Parsed register blocks
06e279e5	218	* @cxl_dvsec: Offset to the PCIe device DVSEC
0a19bfc8	219	* @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
5f50d6b2 DW	220	* @payload_size: Size of space for payload
5f50d6b2 DW	221	* (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
199cf8c3 VV	222	* @lsa_size: Size of Label Storage Area
199cf8c3 VV	223	* (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
5f50d6b2 DW	224	* @mbox_mutex: Mutex to synchronize mailbox access.
	225	* @firmware_version: Firmware version for the memory device.
	226	* @enabled_cmds: Hardware commands found enabled in CEL.
12f3856a	227	* @exclusive_cmds: Commands that are kernel-internal only
d3b75029 DW	228	* @dpa_res: Overall DPA resource tree for the device
	229	* @pmem_res: Active Persistent memory capacity configuration
	230	* @ram_res: Active Volatile memory capacity configuration
13e7749d DW	231	* @total_bytes: sum of all possible capacities
	232	* @volatile_only_bytes: hard volatile capacity
	233	* @persistent_only_bytes: hard persistent capacity
	234	* @partition_align_bytes: alignment size for partition-able capacity
	235	* @active_volatile_bytes: sum of hard + soft volatile
	236	* @active_persistent_bytes: sum of hard + soft persistent
	237	* @next_volatile_bytes: volatile capacity change pending device reset
	238	* @next_persistent_bytes: persistent capacity change pending device reset
4112a08d	239	* @component_reg_phys: register base of component registers
560f7855	240	* @info: Cached DVSEC information about the device.
bcc79ea3	241	* @serial: PCIe Device Serial Number
3eddcc93	242	* @doe_mbs: PCI DOE mailbox array
b64955a9	243	* @mbox_send: @dev specific transport for transmitting mailbox commands
13e7749d DW	244	*
	245	* See section 8.2.9.5.2 Capacity Configuration and Label Storage for
	246	* details on capacity parameters.
5f50d6b2	247	*/
5e2411ae	248	struct cxl_dev_state {
99e222a5	249	struct device *dev;
2905cb52	250	struct cxl_memdev *cxlmd;
5f50d6b2	251
8ac75dd6	252	struct cxl_regs regs;
06e279e5	253	int cxl_dvsec;
5f50d6b2	254
0a19bfc8	255	bool rcd;
5f50d6b2	256	size_t payload_size;
199cf8c3	257	size_t lsa_size;
5f50d6b2 DW	258	struct mutex mbox_mutex; /* Protects device mailbox and firmware */
5f50d6b2 DW	259	char firmware_version[0x10];
ff56ab9e	260	DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
12f3856a	261	DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
5f50d6b2	262
d3b75029 DW	263	struct resource dpa_res;
	264	struct resource pmem_res;
	265	struct resource ram_res;
0b9159d0 IW	266	u64 total_bytes;
	267	u64 volatile_only_bytes;
	268	u64 persistent_only_bytes;
	269	u64 partition_align_bytes;
f847502a IW	270
	271	u64 active_volatile_bytes;
	272	u64 active_persistent_bytes;
	273	u64 next_volatile_bytes;
	274	u64 next_persistent_bytes;
b64955a9	275
4112a08d	276	resource_size_t component_reg_phys;
bcc79ea3	277	u64 serial;
4112a08d	278
3eddcc93 IW	279	struct xarray doe_mbs;
3eddcc93 IW	280
6ebe28f9 IW	281	struct cxl_event_state event;
6ebe28f9 IW	282
5e2411ae	283	int (mbox_send)(struct cxl_dev_state cxlds, struct cxl_mbox_cmd *cmd);
5f50d6b2	284	};
4faf31b4 DW	285
	286	enum cxl_opcode {
	287	CXL_MBOX_OP_INVALID = 0x0000,
	288	CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
6ebe28f9 IW	289	CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100,
6ebe28f9 IW	290	CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101,
4faf31b4 DW	291	CXL_MBOX_OP_GET_FW_INFO = 0x0200,
	292	CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
	293	CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
	294	CXL_MBOX_OP_GET_LOG = 0x0401,
	295	CXL_MBOX_OP_IDENTIFY = 0x4000,
	296	CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
	297	CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
	298	CXL_MBOX_OP_GET_LSA = 0x4102,
	299	CXL_MBOX_OP_SET_LSA = 0x4103,
	300	CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
	301	CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
	302	CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
	303	CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
	304	CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
	305	CXL_MBOX_OP_GET_POISON = 0x4300,
	306	CXL_MBOX_OP_INJECT_POISON = 0x4301,
	307	CXL_MBOX_OP_CLEAR_POISON = 0x4302,
	308	CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
	309	CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
	310	CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
32828115	311	CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
99746940	312	CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
c4ef680d	313	CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
2bb692f7	314	CXL_MBOX_OP_UNLOCK = 0x4503,
a072f7b7	315	CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
3b502e88	316	CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
4faf31b4 DW	317	CXL_MBOX_OP_MAX = 0x10000
	318	};
	319
49be6dd8 DW	320	#define DEFINE_CXL_CEL_UUID \
	321	UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
	322	0x3b, 0x3f, 0x17)
	323
	324	#define DEFINE_CXL_VENDOR_DEBUG_UUID \
	325	UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
	326	0x40, 0x3d, 0x86)
	327
	328	struct cxl_mbox_get_supported_logs {
	329	__le16 entries;
	330	u8 rsvd[6];
	331	struct cxl_gsl_entry {
	332	uuid_t uuid;
	333	__le32 size;
	334	} __packed entry[];
	335	} __packed;
	336
	337	struct cxl_cel_entry {
	338	__le16 opcode;
	339	__le16 effect;
	340	} __packed;
	341
	342	struct cxl_mbox_get_log {
	343	uuid_t uuid;
	344	__le32 offset;
	345	__le32 length;
	346	} __packed;
	347
	348	/* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
	349	struct cxl_mbox_identify {
	350	char fw_revision[0x10];
	351	__le64 total_capacity;
	352	__le64 volatile_capacity;
	353	__le64 persistent_capacity;
	354	__le64 partition_align;
	355	__le16 info_event_log_size;
	356	__le16 warning_event_log_size;
	357	__le16 failure_event_log_size;
	358	__le16 fatal_event_log_size;
	359	__le32 lsa_size;
	360	u8 poison_list_max_mer[3];
	361	__le16 inject_poison_limit;
	362	u8 poison_caps;
	363	u8 qos_telemetry_caps;
	364	} __packed;
	365
6ebe28f9 IW	366	/*
	367	* Common Event Record Format
	368	* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
	369	*/
	370	struct cxl_event_record_hdr {
	371	uuid_t id;
	372	u8 length;
	373	u8 flags[3];
	374	__le16 handle;
	375	__le16 related_handle;
	376	__le64 timestamp;
	377	u8 maint_op_class;
	378	u8 reserved[15];
	379	} __packed;
	380
	381	#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
	382	struct cxl_event_record_raw {
	383	struct cxl_event_record_hdr hdr;
	384	u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
	385	} __packed;
	386
	387	/*
	388	* Get Event Records output payload
	389	* CXL rev 3.0 section 8.2.9.2.2; Table 8-50
	390	*/
	391	#define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
	392	#define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
	393	struct cxl_get_event_payload {
	394	u8 flags;
	395	u8 reserved1;
	396	__le16 overflow_err_count;
	397	__le64 first_overflow_timestamp;
	398	__le64 last_overflow_timestamp;
	399	__le16 record_count;
	400	u8 reserved2[10];
	401	struct cxl_event_record_raw records[];
	402	} __packed;
	403
	404	/*
	405	* CXL rev 3.0 section 8.2.9.2.2; Table 8-49
	406	*/
	407	enum cxl_event_log_type {
	408	CXL_EVENT_TYPE_INFO = 0x00,
	409	CXL_EVENT_TYPE_WARN,
	410	CXL_EVENT_TYPE_FAIL,
	411	CXL_EVENT_TYPE_FATAL,
	412	CXL_EVENT_TYPE_MAX
	413	};
	414
	415	/*
	416	* Clear Event Records input payload
	417	* CXL rev 3.0 section 8.2.9.2.3; Table 8-51
	418	*/
	419	struct cxl_mbox_clear_event_payload {
	420	u8 event_log; /* enum cxl_event_log_type */
	421	u8 clear_flags;
	422	u8 nr_recs;
	423	u8 reserved[3];
	424	__le16 handles[];
	425	} __packed;
	426	#define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
	427
e7ad1bf6 DW	428	struct cxl_mbox_get_partition_info {
	429	__le64 active_volatile_cap;
	430	__le64 active_persistent_cap;
	431	__le64 next_volatile_cap;
	432	__le64 next_persistent_cap;
	433	} __packed;
	434
49be6dd8	435	struct cxl_mbox_get_lsa {
8a664875 AS	436	__le32 offset;
8a664875 AS	437	__le32 length;
49be6dd8 DW	438	} __packed;
	439
	440	struct cxl_mbox_set_lsa {
8a664875 AS	441	__le32 offset;
8a664875 AS	442	__le32 reserved;
49be6dd8 DW	443	u8 data[];
	444	} __packed;
	445
6179045c AS	446	struct cxl_mbox_set_partition_info {
	447	__le64 volatile_capacity;
	448	u8 flags;
	449	} __packed;
	450
	451	#define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
	452
4faf31b4 DW	453	/**
	454	* struct cxl_mem_command - Driver representation of a memory device command
	455	* @info: Command information as it exists for the UAPI
	456	* @opcode: The actual bits used for the mailbox protocol
	457	* @flags: Set of flags effecting driver behavior.
	458	*
	459	* * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
	460	* will be enabled by the driver regardless of what hardware may have
	461	* advertised.
	462	*
	463	* The cxl_mem_command is the driver's internal representation of commands that
	464	* are supported by the driver. Some of these commands may not be supported by
	465	* the hardware. The driver will use @info to validate the fields passed in by
	466	* the user then submit the @opcode to the hardware.
	467	*
	468	* See struct cxl_command_info.
	469	*/
	470	struct cxl_mem_command {
	471	struct cxl_command_info info;
	472	enum cxl_opcode opcode;
	473	u32 flags;
	474	#define CXL_CMD_FLAG_NONE 0
	475	#define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
	476	};
	477
32828115 DJ	478	#define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
	479	#define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
	480	#define CXL_PMEM_SEC_STATE_LOCKED 0x04
	481	#define CXL_PMEM_SEC_STATE_FROZEN 0x08
	482	#define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
	483	#define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
	484
99746940 DJ	485	/* set passphrase input payload */
	486	struct cxl_set_pass {
	487	u8 type;
	488	u8 reserved[31];
	489	/* CXL field using NVDIMM define, same length */
	490	u8 old_pass[NVDIMM_PASSPHRASE_LEN];
	491	u8 new_pass[NVDIMM_PASSPHRASE_LEN];
	492	} __packed;
	493
c4ef680d DJ	494	/* disable passphrase input payload */
	495	struct cxl_disable_pass {
	496	u8 type;
	497	u8 reserved[31];
	498	u8 pass[NVDIMM_PASSPHRASE_LEN];
	499	} __packed;
	500
3b502e88 DJ	501	/* passphrase secure erase payload */
	502	struct cxl_pass_erase {
	503	u8 type;
	504	u8 reserved[31];
	505	u8 pass[NVDIMM_PASSPHRASE_LEN];
	506	} __packed;
	507
99746940 DJ	508	enum {
	509	CXL_PMEM_SEC_PASS_MASTER = 0,
	510	CXL_PMEM_SEC_PASS_USER,
	511	};
	512
5331cdf4 DW	513	int cxl_internal_send_cmd(struct cxl_dev_state *cxlds,
5331cdf4 DW	514	struct cxl_mbox_cmd *cmd);
5e2411ae	515	int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
2e4ba0ec	516	int cxl_await_media_ready(struct cxl_dev_state *cxlds);
5e2411ae IW	517	int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
	518	int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
	519	struct cxl_dev_state cxl_dev_state_create(struct device dev);
	520	void set_exclusive_cxl_commands(struct cxl_dev_state cxlds, unsigned long cmds);
	521	void clear_exclusive_cxl_commands(struct cxl_dev_state cxlds, unsigned long cmds);
6ebe28f9	522	void cxl_mem_get_event_records(struct cxl_dev_state *cxlds, u32 status);
9ea4dcf4 DW	523	#ifdef CONFIG_CXL_SUSPEND
	524	void cxl_mem_active_inc(void);
	525	void cxl_mem_active_dec(void);
	526	#else
	527	static inline void cxl_mem_active_inc(void)
	528	{
	529	}
	530	static inline void cxl_mem_active_dec(void)
	531	{
	532	}
	533	#endif
d17d0540 DW	534
	535	struct cxl_hdm {
	536	struct cxl_component_regs regs;
	537	unsigned int decoder_count;
	538	unsigned int target_count;
	539	unsigned int interleave_mask;
	540	struct cxl_port *port;
	541	};
cc2a4878 DW	542
	543	struct seq_file;
	544	struct dentry cxl_debugfs_create_dir(const char dir);
	545	void cxl_dpa_debug(struct seq_file file, struct cxl_dev_state cxlds);
5f50d6b2	546	#endif /* __CXL_MEM_H__ */