[linux-block.git] / drivers / cxl / cxlmem.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright(c) 2020-2021 Intel Corporation. */
#ifndef __CXL_MEM_H__
#define __CXL_MEM_H__
#include <uapi/linux/cxl_mem.h>
#include <linux/cdev.h>
#include "cxl.h"

/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
#define CXLMDEV_STATUS_OFFSET 0x0
#define   CXLMDEV_DEV_FATAL BIT(0)
#define   CXLMDEV_FW_HALT BIT(1)
#define   CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
#define     CXLMDEV_MS_NOT_READY 0
#define     CXLMDEV_MS_READY 1
#define     CXLMDEV_MS_ERROR 2
#define     CXLMDEV_MS_DISABLED 3
#define CXLMDEV_READY(status)                                                  \
	(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) ==                \
	 CXLMDEV_MS_READY)
#define   CXLMDEV_MBOX_IF_READY BIT(4)
#define   CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
#define     CXLMDEV_RESET_NEEDED_NOT 0
#define     CXLMDEV_RESET_NEEDED_COLD 1
#define     CXLMDEV_RESET_NEEDED_WARM 2
#define     CXLMDEV_RESET_NEEDED_HOT 3
#define     CXLMDEV_RESET_NEEDED_CXL 4
#define CXLMDEV_RESET_NEEDED(status)                                           \
	(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) !=                       \
	 CXLMDEV_RESET_NEEDED_NOT)

/**
 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
 * @dev: driver core device object
 * @cdev: char dev core object for ioctl operations
 * @cxlds: The device state backing this device
 * @detach_work: active memdev lost a port in its ancestry
 * @cxl_nvb: coordinate removal of @cxl_nvd if present
 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
 * @id: id number of this memdev instance.
 */
struct cxl_memdev {
	struct device dev;
	struct cdev cdev;
	struct cxl_dev_state *cxlds;
	struct work_struct detach_work;
	struct cxl_nvdimm_bridge *cxl_nvb;
	struct cxl_nvdimm *cxl_nvd;
	int id;
};

static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
{
	return container_of(dev, struct cxl_memdev, dev);
}

static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
{
	return to_cxl_port(cxled->cxld.dev.parent);
}

static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
{
	return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
}

static inline struct cxl_memdev *
cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
{
	struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);

	return to_cxl_memdev(port->uport);
}

bool is_cxl_memdev(struct device *dev);
static inline bool is_cxl_endpoint(struct cxl_port *port)
{
	return is_cxl_memdev(port->uport);
}

struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);

static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
					 struct cxl_memdev *cxlmd)
{
	if (!port)
		return NULL;

	return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
}

/**
 * struct cxl_mbox_cmd - A command to be submitted to hardware.
 * @opcode: (input) The command set and command submitted to hardware.
 * @payload_in: (input) Pointer to the input payload.
 * @payload_out: (output) Pointer to the output payload. Must be allocated by
 *		 the caller.
 * @size_in: (input) Number of bytes to load from @payload_in.
 * @size_out: (input) Max number of bytes loaded into @payload_out.
 *            (output) Number of bytes generated by the device. For fixed size
 *            outputs commands this is always expected to be deterministic. For
 *            variable sized output commands, it tells the exact number of bytes
 *            written.
 * @return_code: (output) Error code returned from hardware.
 *
 * This is the primary mechanism used to send commands to the hardware.
 * All the fields except @payload_* correspond exactly to the fields described in
 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
 * @payload_out are written to, and read from the Command Payload Registers
 * defined in CXL 2.0 8.2.8.4.8.
 */
struct cxl_mbox_cmd {
	u16 opcode;
	void *payload_in;
	void *payload_out;
	size_t size_in;
	size_t size_out;
	u16 return_code;
};

/*
 * Per CXL 2.0 Section 8.2.8.4.5.1
 */
#define CMD_CMD_RC_TABLE							\
	C(SUCCESS, 0, NULL),							\
	C(BACKGROUND, -ENXIO, "background cmd started successfully"),           \
	C(INPUT, -ENXIO, "cmd input was invalid"),				\
	C(UNSUPPORTED, -ENXIO, "cmd is not supported"),				\
	C(INTERNAL, -ENXIO, "internal device error"),				\
	C(RETRY, -ENXIO, "temporary error, retry once"),			\
	C(BUSY, -ENXIO, "ongoing background operation"),			\
	C(MEDIADISABLED, -ENXIO, "media access is disabled"),			\
	C(FWINPROGRESS, -ENXIO,	"one FW package can be transferred at a time"), \
	C(FWOOO, -ENXIO, "FW package content was transferred out of order"),    \
	C(FWAUTH, -ENXIO, "FW package authentication failed"),			\
	C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"),  \
	C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"),         \
	C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"),		\
	C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"),     \
	C(PADDR, -ENXIO, "physical address specified is invalid"),		\
	C(POISONLMT, -ENXIO, "poison injection limit has been reached"),        \
	C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"),		\
	C(ABORT, -ENXIO, "background cmd was aborted by device"),               \
	C(SECURITY, -ENXIO, "not valid in the current security state"),         \
	C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"),   \
	C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
	C(PAYLOADLEN, -ENXIO, "invalid payload length")

#undef C
#define C(a, b, c) CXL_MBOX_CMD_RC_##a
enum  { CMD_CMD_RC_TABLE };
#undef C
#define C(a, b, c) { b, c }
struct cxl_mbox_cmd_rc {
	int err;
	const char *desc;
};

static const
struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
#undef C

static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
{
	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
}

static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
{
	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
}

/*
 * CXL 2.0 - Memory capacity multiplier
 * See Section 8.2.9.5
 *
 * Volatile, Persistent, and Partition capacities are specified to be in
 * multiples of 256MB - define a multiplier to convert to/from bytes.
 */
#define CXL_CAPACITY_MULTIPLIER SZ_256M

/**
 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
 * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
 * @ranges: Number of active HDM ranges this device uses.
 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
 */
struct cxl_endpoint_dvsec_info {
	bool mem_enabled;
	int ranges;
	struct range dvsec_range[2];
};

/**
 * struct cxl_dev_state - The driver device state
 *
 * cxl_dev_state represents the CXL driver/device state.  It provides an
 * interface to mailbox commands as well as some cached data about the device.
 * Currently only memory devices are represented.
 *
 * @dev: The device associated with this CXL state
 * @cxlmd: The device representing the CXL.mem capabilities of @dev
 * @regs: Parsed register blocks
 * @cxl_dvsec: Offset to the PCIe device DVSEC
 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
 * @payload_size: Size of space for payload
 *                (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
 * @lsa_size: Size of Label Storage Area
 *                (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
 * @mbox_mutex: Mutex to synchronize mailbox access.
 * @firmware_version: Firmware version for the memory device.
 * @enabled_cmds: Hardware commands found enabled in CEL.
 * @exclusive_cmds: Commands that are kernel-internal only
 * @dpa_res: Overall DPA resource tree for the device
 * @pmem_res: Active Persistent memory capacity configuration
 * @ram_res: Active Volatile memory capacity configuration
 * @total_bytes: sum of all possible capacities
 * @volatile_only_bytes: hard volatile capacity
 * @persistent_only_bytes: hard persistent capacity
 * @partition_align_bytes: alignment size for partition-able capacity
 * @active_volatile_bytes: sum of hard + soft volatile
 * @active_persistent_bytes: sum of hard + soft persistent
 * @next_volatile_bytes: volatile capacity change pending device reset
 * @next_persistent_bytes: persistent capacity change pending device reset
 * @component_reg_phys: register base of component registers
 * @info: Cached DVSEC information about the device.
 * @serial: PCIe Device Serial Number
 * @doe_mbs: PCI DOE mailbox array
 * @mbox_send: @dev specific transport for transmitting mailbox commands
 *
 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
 * details on capacity parameters.
 */
struct cxl_dev_state {
	struct device *dev;
	struct cxl_memdev *cxlmd;

	struct cxl_regs regs;
	int cxl_dvsec;

	bool rcd;
	size_t payload_size;
	size_t lsa_size;
	struct mutex mbox_mutex; /* Protects device mailbox and firmware */
	char firmware_version[0x10];
	DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
	DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);

	struct resource dpa_res;
	struct resource pmem_res;
	struct resource ram_res;
	u64 total_bytes;
	u64 volatile_only_bytes;
	u64 persistent_only_bytes;
	u64 partition_align_bytes;

	u64 active_volatile_bytes;
	u64 active_persistent_bytes;
	u64 next_volatile_bytes;
	u64 next_persistent_bytes;

	resource_size_t component_reg_phys;
	u64 serial;

	struct xarray doe_mbs;

	int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
};

enum cxl_opcode {
	CXL_MBOX_OP_INVALID		= 0x0000,
	CXL_MBOX_OP_RAW			= CXL_MBOX_OP_INVALID,
	CXL_MBOX_OP_GET_FW_INFO		= 0x0200,
	CXL_MBOX_OP_ACTIVATE_FW		= 0x0202,
	CXL_MBOX_OP_GET_SUPPORTED_LOGS	= 0x0400,
	CXL_MBOX_OP_GET_LOG		= 0x0401,
	CXL_MBOX_OP_IDENTIFY		= 0x4000,
	CXL_MBOX_OP_GET_PARTITION_INFO	= 0x4100,
	CXL_MBOX_OP_SET_PARTITION_INFO	= 0x4101,
	CXL_MBOX_OP_GET_LSA		= 0x4102,
	CXL_MBOX_OP_SET_LSA		= 0x4103,
	CXL_MBOX_OP_GET_HEALTH_INFO	= 0x4200,
	CXL_MBOX_OP_GET_ALERT_CONFIG	= 0x4201,
	CXL_MBOX_OP_SET_ALERT_CONFIG	= 0x4202,
	CXL_MBOX_OP_GET_SHUTDOWN_STATE	= 0x4203,
	CXL_MBOX_OP_SET_SHUTDOWN_STATE	= 0x4204,
	CXL_MBOX_OP_GET_POISON		= 0x4300,
	CXL_MBOX_OP_INJECT_POISON	= 0x4301,
	CXL_MBOX_OP_CLEAR_POISON	= 0x4302,
	CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS	= 0x4303,
	CXL_MBOX_OP_SCAN_MEDIA		= 0x4304,
	CXL_MBOX_OP_GET_SCAN_MEDIA	= 0x4305,
	CXL_MBOX_OP_GET_SECURITY_STATE	= 0x4500,
	CXL_MBOX_OP_SET_PASSPHRASE	= 0x4501,
	CXL_MBOX_OP_DISABLE_PASSPHRASE	= 0x4502,
	CXL_MBOX_OP_UNLOCK		= 0x4503,
	CXL_MBOX_OP_FREEZE_SECURITY	= 0x4504,
	CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE	= 0x4505,
	CXL_MBOX_OP_MAX			= 0x10000
};

#define DEFINE_CXL_CEL_UUID                                                    \
	UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62,     \
		  0x3b, 0x3f, 0x17)

#define DEFINE_CXL_VENDOR_DEBUG_UUID                                           \
	UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19,     \
		  0x40, 0x3d, 0x86)

struct cxl_mbox_get_supported_logs {
	__le16 entries;
	u8 rsvd[6];
	struct cxl_gsl_entry {
		uuid_t uuid;
		__le32 size;
	} __packed entry[];
}  __packed;

struct cxl_cel_entry {
	__le16 opcode;
	__le16 effect;
} __packed;

struct cxl_mbox_get_log {
	uuid_t uuid;
	__le32 offset;
	__le32 length;
} __packed;

/* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
struct cxl_mbox_identify {
	char fw_revision[0x10];
	__le64 total_capacity;
	__le64 volatile_capacity;
	__le64 persistent_capacity;
	__le64 partition_align;
	__le16 info_event_log_size;
	__le16 warning_event_log_size;
	__le16 failure_event_log_size;
	__le16 fatal_event_log_size;
	__le32 lsa_size;
	u8 poison_list_max_mer[3];
	__le16 inject_poison_limit;
	u8 poison_caps;
	u8 qos_telemetry_caps;
} __packed;

struct cxl_mbox_get_partition_info {
	__le64 active_volatile_cap;
	__le64 active_persistent_cap;
	__le64 next_volatile_cap;
	__le64 next_persistent_cap;
} __packed;

struct cxl_mbox_get_lsa {
	__le32 offset;
	__le32 length;
} __packed;

struct cxl_mbox_set_lsa {
	__le32 offset;
	__le32 reserved;
	u8 data[];
} __packed;

struct cxl_mbox_set_partition_info {
	__le64 volatile_capacity;
	u8 flags;
} __packed;

#define  CXL_SET_PARTITION_IMMEDIATE_FLAG	BIT(0)

/**
 * struct cxl_mem_command - Driver representation of a memory device command
 * @info: Command information as it exists for the UAPI
 * @opcode: The actual bits used for the mailbox protocol
 * @flags: Set of flags effecting driver behavior.
 *
 *  * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
 *    will be enabled by the driver regardless of what hardware may have
 *    advertised.
 *
 * The cxl_mem_command is the driver's internal representation of commands that
 * are supported by the driver. Some of these commands may not be supported by
 * the hardware. The driver will use @info to validate the fields passed in by
 * the user then submit the @opcode to the hardware.
 *
 * See struct cxl_command_info.
 */
struct cxl_mem_command {
	struct cxl_command_info info;
	enum cxl_opcode opcode;
	u32 flags;
#define CXL_CMD_FLAG_NONE 0
#define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
};

#define CXL_PMEM_SEC_STATE_USER_PASS_SET	0x01
#define CXL_PMEM_SEC_STATE_MASTER_PASS_SET	0x02
#define CXL_PMEM_SEC_STATE_LOCKED		0x04
#define CXL_PMEM_SEC_STATE_FROZEN		0x08
#define CXL_PMEM_SEC_STATE_USER_PLIMIT		0x10
#define CXL_PMEM_SEC_STATE_MASTER_PLIMIT	0x20

/* set passphrase input payload */
struct cxl_set_pass {
	u8 type;
	u8 reserved[31];
	/* CXL field using NVDIMM define, same length */
	u8 old_pass[NVDIMM_PASSPHRASE_LEN];
	u8 new_pass[NVDIMM_PASSPHRASE_LEN];
} __packed;

/* disable passphrase input payload */
struct cxl_disable_pass {
	u8 type;
	u8 reserved[31];
	u8 pass[NVDIMM_PASSPHRASE_LEN];
} __packed;

/* passphrase secure erase payload */
struct cxl_pass_erase {
	u8 type;
	u8 reserved[31];
	u8 pass[NVDIMM_PASSPHRASE_LEN];
} __packed;

enum {
	CXL_PMEM_SEC_PASS_MASTER = 0,
	CXL_PMEM_SEC_PASS_USER,
};

int cxl_internal_send_cmd(struct cxl_dev_state *cxlds,
			  struct cxl_mbox_cmd *cmd);
int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
int cxl_await_media_ready(struct cxl_dev_state *cxlds);
int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
struct cxl_dev_state *cxl_dev_state_create(struct device *dev);
void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
#ifdef CONFIG_CXL_SUSPEND
void cxl_mem_active_inc(void);
void cxl_mem_active_dec(void);
#else
static inline void cxl_mem_active_inc(void)
{
}
static inline void cxl_mem_active_dec(void)
{
}
#endif

struct cxl_hdm {
	struct cxl_component_regs regs;
	unsigned int decoder_count;
	unsigned int target_count;
	unsigned int interleave_mask;
	struct cxl_port *port;
};

struct seq_file;
struct dentry *cxl_debugfs_create_dir(const char *dir);
void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
#endif /* __CXL_MEM_H__ */
Commit	Line	Data
5f50d6b2 DW	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/* Copyright(c) 2020-2021 Intel Corporation. */
	3	#ifndef __CXL_MEM_H__
	4	#define __CXL_MEM_H__
4faf31b4	5	#include <uapi/linux/cxl_mem.h>
21083f51 DW	6	#include <linux/cdev.h>
21083f51 DW	7	#include "cxl.h"
5f50d6b2 DW	8
	9	/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
	10	#define CXLMDEV_STATUS_OFFSET 0x0
	11	#define CXLMDEV_DEV_FATAL BIT(0)
	12	#define CXLMDEV_FW_HALT BIT(1)
	13	#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
	14	#define CXLMDEV_MS_NOT_READY 0
	15	#define CXLMDEV_MS_READY 1
	16	#define CXLMDEV_MS_ERROR 2
	17	#define CXLMDEV_MS_DISABLED 3
	18	#define CXLMDEV_READY(status) \
	19	(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
	20	CXLMDEV_MS_READY)
	21	#define CXLMDEV_MBOX_IF_READY BIT(4)
	22	#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
	23	#define CXLMDEV_RESET_NEEDED_NOT 0
	24	#define CXLMDEV_RESET_NEEDED_COLD 1
	25	#define CXLMDEV_RESET_NEEDED_WARM 2
	26	#define CXLMDEV_RESET_NEEDED_HOT 3
	27	#define CXLMDEV_RESET_NEEDED_CXL 4
	28	#define CXLMDEV_RESET_NEEDED(status) \
	29	(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
	30	CXLMDEV_RESET_NEEDED_NOT)
	31
5f50d6b2 DW	32	/**
	33	* struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
	34	* @dev: driver core device object
	35	* @cdev: char dev core object for ioctl operations
5e2411ae	36	* @cxlds: The device state backing this device
8dd2bc0f	37	* @detach_work: active memdev lost a port in its ancestry
f17b558d DW	38	* @cxl_nvb: coordinate removal of @cxl_nvd if present
f17b558d DW	39	* @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
5f50d6b2 DW	40	* @id: id number of this memdev instance.
	41	*/
	42	struct cxl_memdev {
	43	struct device dev;
	44	struct cdev cdev;
5e2411ae	45	struct cxl_dev_state *cxlds;
8dd2bc0f	46	struct work_struct detach_work;
f17b558d DW	47	struct cxl_nvdimm_bridge *cxl_nvb;
f17b558d DW	48	struct cxl_nvdimm *cxl_nvd;
5f50d6b2 DW	49	int id;
	50	};
	51
3d135db5 BW	52	static inline struct cxl_memdev to_cxl_memdev(struct device dev)
	53	{
	54	return container_of(dev, struct cxl_memdev, dev);
	55	}
	56
9c57cde0 DW	57	static inline struct cxl_port cxled_to_port(struct cxl_endpoint_decoder cxled)
	58	{
	59	return to_cxl_port(cxled->cxld.dev.parent);
	60	}
	61
384e624b DW	62	static inline struct cxl_port cxlrd_to_port(struct cxl_root_decoder cxlrd)
	63	{
	64	return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
	65	}
	66
9c57cde0 DW	67	static inline struct cxl_memdev *
	68	cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
	69	{
	70	struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
	71
	72	return to_cxl_memdev(port->uport);
	73	}
	74
8dd2bc0f BW	75	bool is_cxl_memdev(struct device *dev);
	76	static inline bool is_cxl_endpoint(struct cxl_port *port)
	77	{
	78	return is_cxl_memdev(port->uport);
	79	}
	80
5e2411ae	81	struct cxl_memdev devm_cxl_add_memdev(struct cxl_dev_state cxlds);
3d135db5	82
7592d935 DW	83	static inline struct cxl_ep cxl_ep_load(struct cxl_port port,
	84	struct cxl_memdev *cxlmd)
	85	{
	86	if (!port)
	87	return NULL;
	88
	89	return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
	90	}
	91
b64955a9 DW	92	/**
	93	* struct cxl_mbox_cmd - A command to be submitted to hardware.
	94	* @opcode: (input) The command set and command submitted to hardware.
	95	* @payload_in: (input) Pointer to the input payload.
	96	* @payload_out: (output) Pointer to the output payload. Must be allocated by
	97	* the caller.
	98	* @size_in: (input) Number of bytes to load from @payload_in.
	99	* @size_out: (input) Max number of bytes loaded into @payload_out.
	100	* (output) Number of bytes generated by the device. For fixed size
	101	* outputs commands this is always expected to be deterministic. For
	102	* variable sized output commands, it tells the exact number of bytes
	103	* written.
	104	* @return_code: (output) Error code returned from hardware.
	105	*
	106	* This is the primary mechanism used to send commands to the hardware.
	107	* All the fields except @payload_* correspond exactly to the fields described in
	108	* Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
	109	* @payload_out are written to, and read from the Command Payload Registers
	110	* defined in CXL 2.0 8.2.8.4.8.
	111	*/
	112	struct cxl_mbox_cmd {
	113	u16 opcode;
	114	void *payload_in;
	115	void *payload_out;
	116	size_t size_in;
	117	size_t size_out;
	118	u16 return_code;
b64955a9 DW	119	};
b64955a9 DW	120
92fcc1ab DB	121	/*
	122	* Per CXL 2.0 Section 8.2.8.4.5.1
	123	*/
	124	#define CMD_CMD_RC_TABLE \
	125	C(SUCCESS, 0, NULL), \
	126	C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
	127	C(INPUT, -ENXIO, "cmd input was invalid"), \
	128	C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
	129	C(INTERNAL, -ENXIO, "internal device error"), \
	130	C(RETRY, -ENXIO, "temporary error, retry once"), \
	131	C(BUSY, -ENXIO, "ongoing background operation"), \
	132	C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
	133	C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
	134	C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
	135	C(FWAUTH, -ENXIO, "FW package authentication failed"), \
	136	C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
	137	C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
	138	C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
	139	C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
	140	C(PADDR, -ENXIO, "physical address specified is invalid"), \
	141	C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \
	142	C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
	143	C(ABORT, -ENXIO, "background cmd was aborted by device"), \
	144	C(SECURITY, -ENXIO, "not valid in the current security state"), \
	145	C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
	146	C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
	147	C(PAYLOADLEN, -ENXIO, "invalid payload length")
	148
	149	#undef C
	150	#define C(a, b, c) CXL_MBOX_CMD_RC_##a
	151	enum { CMD_CMD_RC_TABLE };
	152	#undef C
	153	#define C(a, b, c) { b, c }
	154	struct cxl_mbox_cmd_rc {
	155	int err;
	156	const char *desc;
	157	};
	158
	159	static const
	160	struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
	161	#undef C
	162
	163	static inline const char cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd mbox_cmd)
	164	{
	165	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
	166	}
	167
	168	static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
	169	{
	170	return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
	171	}
	172
b64955a9 DW	173	/*
	174	* CXL 2.0 - Memory capacity multiplier
	175	* See Section 8.2.9.5
	176	*
	177	* Volatile, Persistent, and Partition capacities are specified to be in
	178	* multiples of 256MB - define a multiplier to convert to/from bytes.
	179	*/
	180	#define CXL_CAPACITY_MULTIPLIER SZ_256M
	181
560f7855 BW	182	/**
	183	* struct cxl_endpoint_dvsec_info - Cached DVSEC info
	184	* @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
	185	* @ranges: Number of active HDM ranges this device uses.
	186	* @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
	187	*/
	188	struct cxl_endpoint_dvsec_info {
	189	bool mem_enabled;
	190	int ranges;
	191	struct range dvsec_range[2];
	192	};
	193
5f50d6b2	194	/**
5e2411ae IW	195	* struct cxl_dev_state - The driver device state
	196	*
	197	* cxl_dev_state represents the CXL driver/device state. It provides an
	198	* interface to mailbox commands as well as some cached data about the device.
	199	* Currently only memory devices are represented.
	200	*
	201	* @dev: The device associated with this CXL state
2905cb52	202	* @cxlmd: The device representing the CXL.mem capabilities of @dev
8ac75dd6	203	* @regs: Parsed register blocks
06e279e5	204	* @cxl_dvsec: Offset to the PCIe device DVSEC
0a19bfc8	205	* @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
5f50d6b2 DW	206	* @payload_size: Size of space for payload
5f50d6b2 DW	207	* (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
199cf8c3 VV	208	* @lsa_size: Size of Label Storage Area
199cf8c3 VV	209	* (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
5f50d6b2 DW	210	* @mbox_mutex: Mutex to synchronize mailbox access.
	211	* @firmware_version: Firmware version for the memory device.
	212	* @enabled_cmds: Hardware commands found enabled in CEL.
12f3856a	213	* @exclusive_cmds: Commands that are kernel-internal only
d3b75029 DW	214	* @dpa_res: Overall DPA resource tree for the device
	215	* @pmem_res: Active Persistent memory capacity configuration
	216	* @ram_res: Active Volatile memory capacity configuration
13e7749d DW	217	* @total_bytes: sum of all possible capacities
	218	* @volatile_only_bytes: hard volatile capacity
	219	* @persistent_only_bytes: hard persistent capacity
	220	* @partition_align_bytes: alignment size for partition-able capacity
	221	* @active_volatile_bytes: sum of hard + soft volatile
	222	* @active_persistent_bytes: sum of hard + soft persistent
	223	* @next_volatile_bytes: volatile capacity change pending device reset
	224	* @next_persistent_bytes: persistent capacity change pending device reset
4112a08d	225	* @component_reg_phys: register base of component registers
560f7855	226	* @info: Cached DVSEC information about the device.
bcc79ea3	227	* @serial: PCIe Device Serial Number
3eddcc93	228	* @doe_mbs: PCI DOE mailbox array
b64955a9	229	* @mbox_send: @dev specific transport for transmitting mailbox commands
13e7749d DW	230	*
	231	* See section 8.2.9.5.2 Capacity Configuration and Label Storage for
	232	* details on capacity parameters.
5f50d6b2	233	*/
5e2411ae	234	struct cxl_dev_state {
99e222a5	235	struct device *dev;
2905cb52	236	struct cxl_memdev *cxlmd;
5f50d6b2	237
8ac75dd6	238	struct cxl_regs regs;
06e279e5	239	int cxl_dvsec;
5f50d6b2	240
0a19bfc8	241	bool rcd;
5f50d6b2	242	size_t payload_size;
199cf8c3	243	size_t lsa_size;
5f50d6b2 DW	244	struct mutex mbox_mutex; /* Protects device mailbox and firmware */
5f50d6b2 DW	245	char firmware_version[0x10];
ff56ab9e	246	DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
12f3856a	247	DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
5f50d6b2	248
d3b75029 DW	249	struct resource dpa_res;
	250	struct resource pmem_res;
	251	struct resource ram_res;
0b9159d0 IW	252	u64 total_bytes;
	253	u64 volatile_only_bytes;
	254	u64 persistent_only_bytes;
	255	u64 partition_align_bytes;
f847502a IW	256
	257	u64 active_volatile_bytes;
	258	u64 active_persistent_bytes;
	259	u64 next_volatile_bytes;
	260	u64 next_persistent_bytes;
b64955a9	261
4112a08d	262	resource_size_t component_reg_phys;
bcc79ea3	263	u64 serial;
4112a08d	264
3eddcc93 IW	265	struct xarray doe_mbs;
3eddcc93 IW	266
5e2411ae	267	int (mbox_send)(struct cxl_dev_state cxlds, struct cxl_mbox_cmd *cmd);
5f50d6b2	268	};
4faf31b4 DW	269
	270	enum cxl_opcode {
	271	CXL_MBOX_OP_INVALID = 0x0000,
	272	CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
	273	CXL_MBOX_OP_GET_FW_INFO = 0x0200,
	274	CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
	275	CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
	276	CXL_MBOX_OP_GET_LOG = 0x0401,
	277	CXL_MBOX_OP_IDENTIFY = 0x4000,
	278	CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
	279	CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
	280	CXL_MBOX_OP_GET_LSA = 0x4102,
	281	CXL_MBOX_OP_SET_LSA = 0x4103,
	282	CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
	283	CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
	284	CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
	285	CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
	286	CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
	287	CXL_MBOX_OP_GET_POISON = 0x4300,
	288	CXL_MBOX_OP_INJECT_POISON = 0x4301,
	289	CXL_MBOX_OP_CLEAR_POISON = 0x4302,
	290	CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
	291	CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
	292	CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
32828115	293	CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
99746940	294	CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
c4ef680d	295	CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
2bb692f7	296	CXL_MBOX_OP_UNLOCK = 0x4503,
a072f7b7	297	CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
3b502e88	298	CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
4faf31b4 DW	299	CXL_MBOX_OP_MAX = 0x10000
	300	};
	301
49be6dd8 DW	302	#define DEFINE_CXL_CEL_UUID \
	303	UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
	304	0x3b, 0x3f, 0x17)
	305
	306	#define DEFINE_CXL_VENDOR_DEBUG_UUID \
	307	UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
	308	0x40, 0x3d, 0x86)
	309
	310	struct cxl_mbox_get_supported_logs {
	311	__le16 entries;
	312	u8 rsvd[6];
	313	struct cxl_gsl_entry {
	314	uuid_t uuid;
	315	__le32 size;
	316	} __packed entry[];
	317	} __packed;
	318
	319	struct cxl_cel_entry {
	320	__le16 opcode;
	321	__le16 effect;
	322	} __packed;
	323
	324	struct cxl_mbox_get_log {
	325	uuid_t uuid;
	326	__le32 offset;
	327	__le32 length;
	328	} __packed;
	329
	330	/* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
	331	struct cxl_mbox_identify {
	332	char fw_revision[0x10];
	333	__le64 total_capacity;
	334	__le64 volatile_capacity;
	335	__le64 persistent_capacity;
	336	__le64 partition_align;
	337	__le16 info_event_log_size;
	338	__le16 warning_event_log_size;
	339	__le16 failure_event_log_size;
	340	__le16 fatal_event_log_size;
	341	__le32 lsa_size;
	342	u8 poison_list_max_mer[3];
	343	__le16 inject_poison_limit;
	344	u8 poison_caps;
	345	u8 qos_telemetry_caps;
	346	} __packed;
	347
e7ad1bf6 DW	348	struct cxl_mbox_get_partition_info {
	349	__le64 active_volatile_cap;
	350	__le64 active_persistent_cap;
	351	__le64 next_volatile_cap;
	352	__le64 next_persistent_cap;
	353	} __packed;
	354
49be6dd8	355	struct cxl_mbox_get_lsa {
8a664875 AS	356	__le32 offset;
8a664875 AS	357	__le32 length;
49be6dd8 DW	358	} __packed;
	359
	360	struct cxl_mbox_set_lsa {
8a664875 AS	361	__le32 offset;
8a664875 AS	362	__le32 reserved;
49be6dd8 DW	363	u8 data[];
	364	} __packed;
	365
6179045c AS	366	struct cxl_mbox_set_partition_info {
	367	__le64 volatile_capacity;
	368	u8 flags;
	369	} __packed;
	370
	371	#define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
	372
4faf31b4 DW	373	/**
	374	* struct cxl_mem_command - Driver representation of a memory device command
	375	* @info: Command information as it exists for the UAPI
	376	* @opcode: The actual bits used for the mailbox protocol
	377	* @flags: Set of flags effecting driver behavior.
	378	*
	379	* * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
	380	* will be enabled by the driver regardless of what hardware may have
	381	* advertised.
	382	*
	383	* The cxl_mem_command is the driver's internal representation of commands that
	384	* are supported by the driver. Some of these commands may not be supported by
	385	* the hardware. The driver will use @info to validate the fields passed in by
	386	* the user then submit the @opcode to the hardware.
	387	*
	388	* See struct cxl_command_info.
	389	*/
	390	struct cxl_mem_command {
	391	struct cxl_command_info info;
	392	enum cxl_opcode opcode;
	393	u32 flags;
	394	#define CXL_CMD_FLAG_NONE 0
	395	#define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
	396	};
	397
32828115 DJ	398	#define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
	399	#define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
	400	#define CXL_PMEM_SEC_STATE_LOCKED 0x04
	401	#define CXL_PMEM_SEC_STATE_FROZEN 0x08
	402	#define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
	403	#define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
	404
99746940 DJ	405	/* set passphrase input payload */
	406	struct cxl_set_pass {
	407	u8 type;
	408	u8 reserved[31];
	409	/* CXL field using NVDIMM define, same length */
	410	u8 old_pass[NVDIMM_PASSPHRASE_LEN];
	411	u8 new_pass[NVDIMM_PASSPHRASE_LEN];
	412	} __packed;
	413
c4ef680d DJ	414	/* disable passphrase input payload */
	415	struct cxl_disable_pass {
	416	u8 type;
	417	u8 reserved[31];
	418	u8 pass[NVDIMM_PASSPHRASE_LEN];
	419	} __packed;
	420
3b502e88 DJ	421	/* passphrase secure erase payload */
	422	struct cxl_pass_erase {
	423	u8 type;
	424	u8 reserved[31];
	425	u8 pass[NVDIMM_PASSPHRASE_LEN];
	426	} __packed;
	427
99746940 DJ	428	enum {
	429	CXL_PMEM_SEC_PASS_MASTER = 0,
	430	CXL_PMEM_SEC_PASS_USER,
	431	};
	432
5331cdf4 DW	433	int cxl_internal_send_cmd(struct cxl_dev_state *cxlds,
5331cdf4 DW	434	struct cxl_mbox_cmd *cmd);
5e2411ae	435	int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
2e4ba0ec	436	int cxl_await_media_ready(struct cxl_dev_state *cxlds);
5e2411ae IW	437	int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
	438	int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
	439	struct cxl_dev_state cxl_dev_state_create(struct device dev);
	440	void set_exclusive_cxl_commands(struct cxl_dev_state cxlds, unsigned long cmds);
	441	void clear_exclusive_cxl_commands(struct cxl_dev_state cxlds, unsigned long cmds);
9ea4dcf4 DW	442	#ifdef CONFIG_CXL_SUSPEND
	443	void cxl_mem_active_inc(void);
	444	void cxl_mem_active_dec(void);
	445	#else
	446	static inline void cxl_mem_active_inc(void)
	447	{
	448	}
	449	static inline void cxl_mem_active_dec(void)
	450	{
	451	}
	452	#endif
d17d0540 DW	453
	454	struct cxl_hdm {
	455	struct cxl_component_regs regs;
	456	unsigned int decoder_count;
	457	unsigned int target_count;
	458	unsigned int interleave_mask;
	459	struct cxl_port *port;
	460	};
cc2a4878 DW	461
	462	struct seq_file;
	463	struct dentry cxl_debugfs_create_dir(const char dir);
	464	void cxl_dpa_debug(struct seq_file file, struct cxl_dev_state cxlds);
5f50d6b2	465	#endif /* __CXL_MEM_H__ */