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8adaf747 BW |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* Copyright(c) 2020 Intel Corporation. */ | |
3 | ||
4 | #ifndef __CXL_H__ | |
5 | #define __CXL_H__ | |
6 | ||
8fdcb170 | 7 | #include <linux/libnvdimm.h> |
8adaf747 BW |
8 | #include <linux/bitfield.h> |
9 | #include <linux/bitops.h> | |
80d10a6c | 10 | #include <linux/log2.h> |
8adaf747 BW |
11 | #include <linux/io.h> |
12 | ||
4812be97 DW |
13 | /** |
14 | * DOC: cxl objects | |
15 | * | |
16 | * The CXL core objects like ports, decoders, and regions are shared | |
17 | * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers | |
18 | * (port-driver, region-driver, nvdimm object-drivers... etc). | |
19 | */ | |
20 | ||
d17d0540 DW |
21 | /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ |
22 | #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K | |
23 | ||
08422378 BW |
24 | /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ |
25 | #define CXL_CM_OFFSET 0x1000 | |
26 | #define CXL_CM_CAP_HDR_OFFSET 0x0 | |
27 | #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) | |
28 | #define CM_CAP_HDR_CAP_ID 1 | |
29 | #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) | |
30 | #define CM_CAP_HDR_CAP_VERSION 1 | |
31 | #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) | |
32 | #define CM_CAP_HDR_CACHE_MEM_VERSION 1 | |
33 | #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) | |
34 | #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) | |
35 | ||
bd09626b | 36 | #define CXL_CM_CAP_CAP_ID_RAS 0x2 |
08422378 BW |
37 | #define CXL_CM_CAP_CAP_ID_HDM 0x5 |
38 | #define CXL_CM_CAP_CAP_HDM_VERSION 1 | |
39 | ||
40 | /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ | |
41 | #define CXL_HDM_DECODER_CAP_OFFSET 0x0 | |
42 | #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) | |
43 | #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) | |
d17d0540 DW |
44 | #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) |
45 | #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) | |
46 | #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 | |
47 | #define CXL_HDM_DECODER_ENABLE BIT(1) | |
48 | #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) | |
49 | #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) | |
50 | #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) | |
51 | #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) | |
52 | #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) | |
53 | #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) | |
54 | #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) | |
55 | #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) | |
56 | #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) | |
57 | #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) | |
176baefb | 58 | #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) |
d17d0540 DW |
59 | #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12) |
60 | #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) | |
61 | #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) | |
9c57cde0 DW |
62 | #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) |
63 | #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) | |
08422378 | 64 | |
3b39fd6c AM |
65 | /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ |
66 | #define CXL_DECODER_MIN_GRANULARITY 256 | |
67 | #define CXL_DECODER_MAX_ENCODED_IG 6 | |
68 | ||
6423035f BW |
69 | static inline int cxl_hdm_decoder_count(u32 cap_hdr) |
70 | { | |
71 | int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); | |
72 | ||
73 | return val ? val * 2 : 1; | |
74 | } | |
75 | ||
419af595 | 76 | /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ |
83351ddb | 77 | static inline int eig_to_granularity(u16 eig, unsigned int *granularity) |
419af595 | 78 | { |
83351ddb | 79 | if (eig > CXL_DECODER_MAX_ENCODED_IG) |
419af595 | 80 | return -EINVAL; |
83351ddb | 81 | *granularity = CXL_DECODER_MIN_GRANULARITY << eig; |
419af595 DW |
82 | return 0; |
83 | } | |
84 | ||
85 | /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ | |
c99b2e8c | 86 | static inline int eiw_to_ways(u8 eiw, unsigned int *ways) |
419af595 | 87 | { |
c99b2e8c | 88 | switch (eiw) { |
419af595 | 89 | case 0 ... 4: |
c99b2e8c | 90 | *ways = 1 << eiw; |
419af595 DW |
91 | break; |
92 | case 8 ... 10: | |
c99b2e8c | 93 | *ways = 3 << (eiw - 8); |
419af595 DW |
94 | break; |
95 | default: | |
96 | return -EINVAL; | |
97 | } | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
83351ddb | 102 | static inline int granularity_to_eig(int granularity, u16 *eig) |
80d10a6c | 103 | { |
83351ddb DJ |
104 | if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || |
105 | !is_power_of_2(granularity)) | |
80d10a6c | 106 | return -EINVAL; |
83351ddb | 107 | *eig = ilog2(granularity) - 8; |
80d10a6c BW |
108 | return 0; |
109 | } | |
110 | ||
c99b2e8c | 111 | static inline int ways_to_eiw(unsigned int ways, u8 *eiw) |
80d10a6c BW |
112 | { |
113 | if (ways > 16) | |
114 | return -EINVAL; | |
115 | if (is_power_of_2(ways)) { | |
c99b2e8c | 116 | *eiw = ilog2(ways); |
80d10a6c BW |
117 | return 0; |
118 | } | |
119 | if (ways % 3) | |
120 | return -EINVAL; | |
121 | ways /= 3; | |
122 | if (!is_power_of_2(ways)) | |
123 | return -EINVAL; | |
c99b2e8c | 124 | *eiw = ilog2(ways) + 8; |
80d10a6c BW |
125 | return 0; |
126 | } | |
127 | ||
bd09626b DW |
128 | /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ |
129 | #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 | |
130 | #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) | |
131 | #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 | |
132 | #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) | |
133 | #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 | |
134 | #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) | |
135 | #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC | |
136 | #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) | |
137 | #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 | |
138 | #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) | |
139 | #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 | |
2905cb52 | 140 | #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) |
bd09626b DW |
141 | #define CXL_RAS_HEADER_LOG_OFFSET 0x18 |
142 | #define CXL_RAS_CAPABILITY_LENGTH 0x58 | |
4a20bc3e DW |
143 | #define CXL_HEADERLOG_SIZE SZ_512 |
144 | #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) | |
bd09626b | 145 | |
8adaf747 BW |
146 | /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ |
147 | #define CXLDEV_CAP_ARRAY_OFFSET 0x0 | |
148 | #define CXLDEV_CAP_ARRAY_CAP_ID 0 | |
149 | #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) | |
150 | #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) | |
151 | /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ | |
152 | #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) | |
153 | /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ | |
154 | #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 | |
155 | #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 | |
156 | #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 | |
157 | #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 | |
158 | ||
159 | /* CXL 2.0 8.2.8.4 Mailbox Registers */ | |
160 | #define CXLDEV_MBOX_CAPS_OFFSET 0x00 | |
161 | #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) | |
162 | #define CXLDEV_MBOX_CTRL_OFFSET 0x04 | |
163 | #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) | |
164 | #define CXLDEV_MBOX_CMD_OFFSET 0x08 | |
165 | #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) | |
166 | #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) | |
167 | #define CXLDEV_MBOX_STATUS_OFFSET 0x10 | |
168 | #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) | |
169 | #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 | |
170 | #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 | |
171 | ||
8ac75dd6 | 172 | /* |
301e68dd KC |
173 | * Using struct_group() allows for per register-block-type helper routines, |
174 | * without requiring block-type agnostic code to include the prefix. | |
8ac75dd6 DW |
175 | */ |
176 | struct cxl_regs { | |
301e68dd KC |
177 | /* |
178 | * Common set of CXL Component register block base pointers | |
179 | * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure | |
bd09626b | 180 | * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure |
301e68dd KC |
181 | */ |
182 | struct_group_tagged(cxl_component_regs, component, | |
183 | void __iomem *hdm_decoder; | |
bd09626b | 184 | void __iomem *ras; |
301e68dd KC |
185 | ); |
186 | /* | |
187 | * Common set of CXL Device register block base pointers | |
188 | * @status: CXL 2.0 8.2.8.3 Device Status Registers | |
189 | * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers | |
190 | * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers | |
191 | */ | |
192 | struct_group_tagged(cxl_device_regs, device_regs, | |
193 | void __iomem *status, *mbox, *memdev; | |
194 | ); | |
8ac75dd6 DW |
195 | }; |
196 | ||
30af9729 IW |
197 | struct cxl_reg_map { |
198 | bool valid; | |
a1554e9c | 199 | int id; |
30af9729 IW |
200 | unsigned long offset; |
201 | unsigned long size; | |
202 | }; | |
203 | ||
08422378 BW |
204 | struct cxl_component_reg_map { |
205 | struct cxl_reg_map hdm_decoder; | |
bd09626b | 206 | struct cxl_reg_map ras; |
08422378 BW |
207 | }; |
208 | ||
30af9729 IW |
209 | struct cxl_device_reg_map { |
210 | struct cxl_reg_map status; | |
211 | struct cxl_reg_map mbox; | |
212 | struct cxl_reg_map memdev; | |
213 | }; | |
214 | ||
a261e9a1 DW |
215 | /** |
216 | * struct cxl_register_map - DVSEC harvested register block mapping parameters | |
217 | * @base: virtual base of the register-block-BAR + @block_offset | |
6c7f4f1e DW |
218 | * @resource: physical resource base of the register block |
219 | * @max_size: maximum mapping size to perform register search | |
a261e9a1 | 220 | * @reg_type: see enum cxl_regloc_type |
a261e9a1 DW |
221 | * @component_map: cxl_reg_map for component registers |
222 | * @device_map: cxl_reg_maps for device registers | |
223 | */ | |
30af9729 | 224 | struct cxl_register_map { |
a261e9a1 | 225 | void __iomem *base; |
6c7f4f1e DW |
226 | resource_size_t resource; |
227 | resource_size_t max_size; | |
30af9729 | 228 | u8 reg_type; |
30af9729 | 229 | union { |
08422378 | 230 | struct cxl_component_reg_map component_map; |
30af9729 IW |
231 | struct cxl_device_reg_map device_map; |
232 | }; | |
233 | }; | |
234 | ||
08422378 BW |
235 | void cxl_probe_component_regs(struct device *dev, void __iomem *base, |
236 | struct cxl_component_reg_map *map); | |
30af9729 IW |
237 | void cxl_probe_device_regs(struct device *dev, void __iomem *base, |
238 | struct cxl_device_reg_map *map); | |
6c7f4f1e | 239 | int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, |
a1554e9c DW |
240 | struct cxl_register_map *map, |
241 | unsigned long map_mask); | |
6c7f4f1e | 242 | int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs, |
30af9729 | 243 | struct cxl_register_map *map); |
399d34eb | 244 | |
303ebc1b BW |
245 | enum cxl_regloc_type; |
246 | int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, | |
247 | struct cxl_register_map *map); | |
248 | ||
d5b1a271 RR |
249 | enum cxl_rcrb { |
250 | CXL_RCRB_DOWNSTREAM, | |
251 | CXL_RCRB_UPSTREAM, | |
252 | }; | |
253 | resource_size_t cxl_rcrb_to_component(struct device *dev, | |
254 | resource_size_t rcrb, | |
255 | enum cxl_rcrb which); | |
256 | ||
4812be97 | 257 | #define CXL_RESOURCE_NONE ((resource_size_t) -1) |
7d4b5ca2 | 258 | #define CXL_TARGET_STRLEN 20 |
4812be97 | 259 | |
40ba17af DW |
260 | /* |
261 | * cxl_decoder flags that define the type of memory / devices this | |
262 | * decoder supports as well as configuration lock status See "CXL 2.0 | |
263 | * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. | |
a32320b7 DW |
264 | * Additionally indicate whether decoder settings were autodetected, |
265 | * user customized. | |
40ba17af DW |
266 | */ |
267 | #define CXL_DECODER_F_RAM BIT(0) | |
268 | #define CXL_DECODER_F_PMEM BIT(1) | |
269 | #define CXL_DECODER_F_TYPE2 BIT(2) | |
270 | #define CXL_DECODER_F_TYPE3 BIT(3) | |
271 | #define CXL_DECODER_F_LOCK BIT(4) | |
d17d0540 DW |
272 | #define CXL_DECODER_F_ENABLE BIT(5) |
273 | #define CXL_DECODER_F_MASK GENMASK(5, 0) | |
40ba17af DW |
274 | |
275 | enum cxl_decoder_type { | |
276 | CXL_DECODER_ACCELERATOR = 2, | |
277 | CXL_DECODER_EXPANDER = 3, | |
278 | }; | |
279 | ||
a5c25802 DW |
280 | /* |
281 | * Current specification goes up to 8, double that seems a reasonable | |
282 | * software max for the foreseeable future | |
283 | */ | |
284 | #define CXL_DECODER_MAX_INTERLEAVE 16 | |
285 | ||
e7748305 | 286 | |
40ba17af | 287 | /** |
e636479e | 288 | * struct cxl_decoder - Common CXL HDM Decoder Attributes |
40ba17af DW |
289 | * @dev: this decoder's device |
290 | * @id: kernel device name id | |
e8b7ea58 | 291 | * @hpa_range: Host physical address range mapped by this decoder |
40ba17af DW |
292 | * @interleave_ways: number of cxl_dports in this decode |
293 | * @interleave_granularity: data stride per dport | |
294 | * @target_type: accelerator vs expander (type2 vs type3) selector | |
b9686e8c | 295 | * @region: currently assigned region for this decoder |
40ba17af | 296 | * @flags: memory type capabilities and locking |
176baefb DW |
297 | * @commit: device/decoder-type specific callback to commit settings to hw |
298 | * @reset: device/decoder-type specific callback to reset hw settings | |
299 | */ | |
40ba17af DW |
300 | struct cxl_decoder { |
301 | struct device dev; | |
302 | int id; | |
e50fe01e | 303 | struct range hpa_range; |
40ba17af DW |
304 | int interleave_ways; |
305 | int interleave_granularity; | |
306 | enum cxl_decoder_type target_type; | |
b9686e8c | 307 | struct cxl_region *region; |
40ba17af | 308 | unsigned long flags; |
176baefb DW |
309 | int (*commit)(struct cxl_decoder *cxld); |
310 | int (*reset)(struct cxl_decoder *cxld); | |
e636479e DW |
311 | }; |
312 | ||
b9686e8c DW |
313 | /* |
314 | * CXL_DECODER_DEAD prevents endpoints from being reattached to regions | |
315 | * while cxld_unregister() is running | |
316 | */ | |
2c866903 DW |
317 | enum cxl_decoder_mode { |
318 | CXL_DECODER_NONE, | |
319 | CXL_DECODER_RAM, | |
320 | CXL_DECODER_PMEM, | |
321 | CXL_DECODER_MIXED, | |
b9686e8c | 322 | CXL_DECODER_DEAD, |
2c866903 DW |
323 | }; |
324 | ||
7d505f98 DW |
325 | static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) |
326 | { | |
327 | static const char * const names[] = { | |
328 | [CXL_DECODER_NONE] = "none", | |
329 | [CXL_DECODER_RAM] = "ram", | |
330 | [CXL_DECODER_PMEM] = "pmem", | |
331 | [CXL_DECODER_MIXED] = "mixed", | |
332 | }; | |
333 | ||
334 | if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) | |
335 | return names[mode]; | |
336 | return "mixed"; | |
337 | } | |
338 | ||
a32320b7 DW |
339 | /* |
340 | * Track whether this decoder is reserved for region autodiscovery, or | |
341 | * free for userspace provisioning. | |
342 | */ | |
343 | enum cxl_decoder_state { | |
344 | CXL_DECODER_STATE_MANUAL, | |
345 | CXL_DECODER_STATE_AUTO, | |
346 | }; | |
347 | ||
3bf65915 DW |
348 | /** |
349 | * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder | |
350 | * @cxld: base cxl_decoder_object | |
351 | * @dpa_res: actively claimed DPA span of this decoder | |
352 | * @skip: offset into @dpa_res where @cxld.hpa_range maps | |
2c866903 | 353 | * @mode: which memory type / access-mode-partition this decoder targets |
a32320b7 | 354 | * @state: autodiscovery state |
b9686e8c | 355 | * @pos: interleave position in @cxld.region |
3bf65915 DW |
356 | */ |
357 | struct cxl_endpoint_decoder { | |
358 | struct cxl_decoder cxld; | |
359 | struct resource *dpa_res; | |
360 | resource_size_t skip; | |
2c866903 | 361 | enum cxl_decoder_mode mode; |
a32320b7 | 362 | enum cxl_decoder_state state; |
b9686e8c | 363 | int pos; |
3bf65915 DW |
364 | }; |
365 | ||
e636479e DW |
366 | /** |
367 | * struct cxl_switch_decoder - Switch specific CXL HDM Decoder | |
368 | * @cxld: base cxl_decoder object | |
369 | * @target_lock: coordinate coherent reads of the target list | |
370 | * @nr_targets: number of elements in @target | |
371 | * @target: active ordered target list in current decoder configuration | |
372 | * | |
373 | * The 'switch' decoder type represents the decoder instances of cxl_port's that | |
374 | * route from the root of a CXL memory decode topology to the endpoints. They | |
375 | * come in two flavors, root-level decoders, statically defined by platform | |
376 | * firmware, and mid-level decoders, where interleave-granularity, | |
377 | * interleave-width, and the target list are mutable. | |
378 | */ | |
379 | struct cxl_switch_decoder { | |
380 | struct cxl_decoder cxld; | |
86c8ea0f | 381 | seqlock_t target_lock; |
be185c29 | 382 | int nr_targets; |
40ba17af DW |
383 | struct cxl_dport *target[]; |
384 | }; | |
385 | ||
f9db85bf AS |
386 | struct cxl_root_decoder; |
387 | typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, | |
388 | int pos); | |
8fdcb170 | 389 | |
0f157c7f DW |
390 | /** |
391 | * struct cxl_root_decoder - Static platform CXL address decoder | |
392 | * @res: host / parent resource for region allocations | |
779dd20c | 393 | * @region_id: region id for next region provisioning event |
6aa41144 | 394 | * @calc_hb: which host bridge covers the n'th position by granularity |
f9db85bf | 395 | * @platform_data: platform specific configuration data |
a32320b7 | 396 | * @range_lock: sync region autodiscovery by address range |
0f157c7f DW |
397 | * @cxlsd: base cxl switch decoder |
398 | */ | |
399 | struct cxl_root_decoder { | |
400 | struct resource *res; | |
779dd20c | 401 | atomic_t region_id; |
f9db85bf AS |
402 | cxl_calc_hb_fn calc_hb; |
403 | void *platform_data; | |
a32320b7 | 404 | struct mutex range_lock; |
0f157c7f DW |
405 | struct cxl_switch_decoder cxlsd; |
406 | }; | |
407 | ||
dd5ba0eb BW |
408 | /* |
409 | * enum cxl_config_state - State machine for region configuration | |
410 | * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely | |
80d10a6c BW |
411 | * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more |
412 | * changes to interleave_ways or interleave_granularity | |
dd5ba0eb BW |
413 | * @CXL_CONFIG_ACTIVE: All targets have been added the region is now |
414 | * active | |
176baefb DW |
415 | * @CXL_CONFIG_RESET_PENDING: see commit_store() |
416 | * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware | |
dd5ba0eb BW |
417 | */ |
418 | enum cxl_config_state { | |
419 | CXL_CONFIG_IDLE, | |
80d10a6c | 420 | CXL_CONFIG_INTERLEAVE_ACTIVE, |
dd5ba0eb | 421 | CXL_CONFIG_ACTIVE, |
176baefb DW |
422 | CXL_CONFIG_RESET_PENDING, |
423 | CXL_CONFIG_COMMIT, | |
dd5ba0eb BW |
424 | }; |
425 | ||
426 | /** | |
427 | * struct cxl_region_params - region settings | |
428 | * @state: allow the driver to lockdown further parameter changes | |
429 | * @uuid: unique id for persistent regions | |
80d10a6c BW |
430 | * @interleave_ways: number of endpoints in the region |
431 | * @interleave_granularity: capacity each endpoint contributes to a stripe | |
23a22cd1 | 432 | * @res: allocated iomem capacity for this region |
038e6eb8 BS |
433 | * @targets: active ordered targets in current decoder configuration |
434 | * @nr_targets: number of targets | |
dd5ba0eb BW |
435 | * |
436 | * State transitions are protected by the cxl_region_rwsem | |
437 | */ | |
438 | struct cxl_region_params { | |
439 | enum cxl_config_state state; | |
440 | uuid_t uuid; | |
80d10a6c BW |
441 | int interleave_ways; |
442 | int interleave_granularity; | |
23a22cd1 | 443 | struct resource *res; |
b9686e8c DW |
444 | struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; |
445 | int nr_targets; | |
dd5ba0eb BW |
446 | }; |
447 | ||
d18bc74a DW |
448 | /* |
449 | * Flag whether this region needs to have its HPA span synchronized with | |
450 | * CPU cache state at region activation time. | |
451 | */ | |
452 | #define CXL_REGION_F_INCOHERENT 0 | |
453 | ||
a32320b7 DW |
454 | /* |
455 | * Indicate whether this region has been assembled by autodetection or | |
456 | * userspace assembly. Prevent endpoint decoders outside of automatic | |
457 | * detection from being added to the region. | |
458 | */ | |
459 | #define CXL_REGION_F_AUTO 1 | |
460 | ||
779dd20c BW |
461 | /** |
462 | * struct cxl_region - CXL region | |
463 | * @dev: This region's device | |
464 | * @id: This region's id. Id is globally unique across all regions | |
465 | * @mode: Endpoint decoder allocation / access mode | |
466 | * @type: Endpoint decoder target type | |
f17b558d DW |
467 | * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown |
468 | * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge | |
d18bc74a | 469 | * @flags: Region state flags |
dd5ba0eb | 470 | * @params: active + config params for the region |
779dd20c BW |
471 | */ |
472 | struct cxl_region { | |
473 | struct device dev; | |
474 | int id; | |
475 | enum cxl_decoder_mode mode; | |
476 | enum cxl_decoder_type type; | |
f17b558d DW |
477 | struct cxl_nvdimm_bridge *cxl_nvb; |
478 | struct cxl_pmem_region *cxlr_pmem; | |
d18bc74a | 479 | unsigned long flags; |
dd5ba0eb | 480 | struct cxl_region_params params; |
779dd20c BW |
481 | }; |
482 | ||
8fdcb170 | 483 | struct cxl_nvdimm_bridge { |
2e52b625 | 484 | int id; |
8fdcb170 DW |
485 | struct device dev; |
486 | struct cxl_port *port; | |
487 | struct nvdimm_bus *nvdimm_bus; | |
488 | struct nvdimm_bus_descriptor nd_desc; | |
8fdcb170 DW |
489 | }; |
490 | ||
b5807c80 DJ |
491 | #define CXL_DEV_ID_LEN 19 |
492 | ||
21083f51 DW |
493 | struct cxl_nvdimm { |
494 | struct device dev; | |
495 | struct cxl_memdev *cxlmd; | |
b5807c80 | 496 | u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ |
04ad63f0 DW |
497 | }; |
498 | ||
499 | struct cxl_pmem_region_mapping { | |
500 | struct cxl_memdev *cxlmd; | |
501 | struct cxl_nvdimm *cxl_nvd; | |
502 | u64 start; | |
503 | u64 size; | |
504 | int position; | |
505 | }; | |
506 | ||
507 | struct cxl_pmem_region { | |
508 | struct device dev; | |
509 | struct cxl_region *cxlr; | |
510 | struct nd_region *nd_region; | |
04ad63f0 DW |
511 | struct range hpa_range; |
512 | int nr_mappings; | |
513 | struct cxl_pmem_region_mapping mapping[]; | |
21083f51 DW |
514 | }; |
515 | ||
4812be97 DW |
516 | /** |
517 | * struct cxl_port - logical collection of upstream port devices and | |
518 | * downstream port devices to construct a CXL memory | |
519 | * decode hierarchy. | |
520 | * @dev: this port's device | |
521 | * @uport: PCI or platform device implementing the upstream port capability | |
ee800010 | 522 | * @host_bridge: Shortcut to the platform attach point for this port |
4812be97 | 523 | * @id: id for port device-name |
7d4b5ca2 | 524 | * @dports: cxl_dport instances referenced by decoders |
2703c16c | 525 | * @endpoints: cxl_ep instances, endpoints that are a descendant of this port |
384e624b | 526 | * @regions: cxl_region_ref instances, regions mapped by this port |
1b58b4ca | 527 | * @parent_dport: dport that points to this port in the parent |
40ba17af | 528 | * @decoder_ida: allocator for decoder ids |
e4f6dfa9 | 529 | * @nr_dports: number of entries in @dports |
0c33b393 | 530 | * @hdm_end: track last allocated HDM decoder instance for allocation ordering |
176baefb | 531 | * @commit_end: cursor to track highest committed decoder for commit ordering |
4812be97 | 532 | * @component_reg_phys: component register capability base address (optional) |
2703c16c | 533 | * @dead: last ep has been removed, force port re-creation |
53fa1bff | 534 | * @depth: How deep this port is relative to the root. depth 0 is the root. |
c9700604 IW |
535 | * @cdat: Cached CDAT data |
536 | * @cdat_available: Should a CDAT attribute be available in sysfs | |
4812be97 DW |
537 | */ |
538 | struct cxl_port { | |
539 | struct device dev; | |
540 | struct device *uport; | |
ee800010 | 541 | struct device *host_bridge; |
4812be97 | 542 | int id; |
39178585 | 543 | struct xarray dports; |
256d0e9e | 544 | struct xarray endpoints; |
384e624b | 545 | struct xarray regions; |
1b58b4ca | 546 | struct cxl_dport *parent_dport; |
40ba17af | 547 | struct ida decoder_ida; |
e4f6dfa9 | 548 | int nr_dports; |
0c33b393 | 549 | int hdm_end; |
176baefb | 550 | int commit_end; |
4812be97 | 551 | resource_size_t component_reg_phys; |
2703c16c | 552 | bool dead; |
53fa1bff | 553 | unsigned int depth; |
c9700604 IW |
554 | struct cxl_cdat { |
555 | void *table; | |
556 | size_t length; | |
557 | } cdat; | |
558 | bool cdat_available; | |
4812be97 DW |
559 | }; |
560 | ||
39178585 DW |
561 | static inline struct cxl_dport * |
562 | cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) | |
563 | { | |
564 | return xa_load(&port->dports, (unsigned long)dport_dev); | |
565 | } | |
566 | ||
7d4b5ca2 DW |
567 | /** |
568 | * struct cxl_dport - CXL downstream port | |
569 | * @dport: PCI bridge or firmware device representing the downstream link | |
570 | * @port_id: unique hardware identifier for dport in decoder target list | |
571 | * @component_reg_phys: downstream port component registers | |
d5b1a271 RR |
572 | * @rcrb: base address for the Root Complex Register Block |
573 | * @rch: Indicate whether this dport was enumerated in RCH or VH mode | |
7d4b5ca2 | 574 | * @port: reference to cxl_port that contains this downstream port |
7d4b5ca2 DW |
575 | */ |
576 | struct cxl_dport { | |
577 | struct device *dport; | |
578 | int port_id; | |
579 | resource_size_t component_reg_phys; | |
d5b1a271 RR |
580 | resource_size_t rcrb; |
581 | bool rch; | |
7d4b5ca2 | 582 | struct cxl_port *port; |
7d4b5ca2 DW |
583 | }; |
584 | ||
2703c16c DW |
585 | /** |
586 | * struct cxl_ep - track an endpoint's interest in a port | |
587 | * @ep: device that hosts a generic CXL endpoint (expander or accelerator) | |
de516b40 | 588 | * @dport: which dport routes to this endpoint on @port |
7f8faf96 DW |
589 | * @next: cxl switch port across the link attached to @dport NULL if |
590 | * attached to an endpoint | |
2703c16c DW |
591 | */ |
592 | struct cxl_ep { | |
593 | struct device *ep; | |
de516b40 | 594 | struct cxl_dport *dport; |
7f8faf96 | 595 | struct cxl_port *next; |
2703c16c DW |
596 | }; |
597 | ||
384e624b DW |
598 | /** |
599 | * struct cxl_region_ref - track a region's interest in a port | |
600 | * @port: point in topology to install this reference | |
601 | * @decoder: decoder assigned for @region in @port | |
602 | * @region: region for this reference | |
603 | * @endpoints: cxl_ep references for region members beneath @port | |
27b3f8d1 | 604 | * @nr_targets_set: track how many targets have been programmed during setup |
384e624b DW |
605 | * @nr_eps: number of endpoints beneath @port |
606 | * @nr_targets: number of distinct targets needed to reach @nr_eps | |
607 | */ | |
608 | struct cxl_region_ref { | |
609 | struct cxl_port *port; | |
610 | struct cxl_decoder *decoder; | |
611 | struct cxl_region *region; | |
612 | struct xarray endpoints; | |
27b3f8d1 | 613 | int nr_targets_set; |
384e624b DW |
614 | int nr_eps; |
615 | int nr_targets; | |
616 | }; | |
617 | ||
d54c1bbe BW |
618 | /* |
619 | * The platform firmware device hosting the root is also the top of the | |
620 | * CXL port topology. All other CXL ports have another CXL port as their | |
621 | * parent and their ->uport / host device is out-of-line of the port | |
622 | * ancestry. | |
623 | */ | |
624 | static inline bool is_cxl_root(struct cxl_port *port) | |
625 | { | |
626 | return port->uport == port->dev.parent; | |
627 | } | |
628 | ||
3c5b9039 | 629 | bool is_cxl_port(struct device *dev); |
4812be97 | 630 | struct cxl_port *to_cxl_port(struct device *dev); |
98d2d3a2 | 631 | struct pci_bus; |
5ff7316f DW |
632 | int devm_cxl_register_pci_bus(struct device *host, struct device *uport, |
633 | struct pci_bus *bus); | |
634 | struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); | |
4812be97 DW |
635 | struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, |
636 | resource_size_t component_reg_phys, | |
1b58b4ca | 637 | struct cxl_dport *parent_dport); |
a46cfc0f | 638 | struct cxl_port *find_cxl_root(struct device *dev); |
2703c16c | 639 | int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); |
4029c32f DW |
640 | void cxl_bus_rescan(void); |
641 | void cxl_bus_drain(void); | |
1b58b4ca DW |
642 | struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, |
643 | struct cxl_dport **dport); | |
8dd2bc0f | 644 | bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); |
2703c16c | 645 | |
664bf115 | 646 | struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, |
98d2d3a2 DW |
647 | struct device *dport, int port_id, |
648 | resource_size_t component_reg_phys); | |
d5b1a271 RR |
649 | struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, |
650 | struct device *dport_dev, int port_id, | |
651 | resource_size_t component_reg_phys, | |
652 | resource_size_t rcrb); | |
2703c16c | 653 | |
40ba17af | 654 | struct cxl_decoder *to_cxl_decoder(struct device *dev); |
0f157c7f | 655 | struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); |
3d8f7cca | 656 | struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); |
3bf65915 | 657 | struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); |
8fdcb170 | 658 | bool is_root_decoder(struct device *dev); |
3d8f7cca | 659 | bool is_switch_decoder(struct device *dev); |
8ae3cebc | 660 | bool is_endpoint_decoder(struct device *dev); |
0f157c7f | 661 | struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, |
f9db85bf AS |
662 | unsigned int nr_targets, |
663 | cxl_calc_hb_fn calc_hb); | |
664 | struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); | |
e636479e DW |
665 | struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, |
666 | unsigned int nr_targets); | |
48667f67 | 667 | int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); |
3bf65915 | 668 | struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); |
d17d0540 | 669 | int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); |
48667f67 | 670 | int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); |
8dd2bc0f BW |
671 | int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); |
672 | ||
d17d0540 | 673 | struct cxl_hdm; |
664bf115 DW |
674 | struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port); |
675 | int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm); | |
676 | int devm_cxl_add_passthrough_decoder(struct cxl_port *port); | |
40ba17af | 677 | |
779dd20c BW |
678 | bool is_cxl_region(struct device *dev); |
679 | ||
b39cb105 | 680 | extern struct bus_type cxl_bus_type; |
6af7139c DW |
681 | |
682 | struct cxl_driver { | |
683 | const char *name; | |
684 | int (*probe)(struct device *dev); | |
685 | void (*remove)(struct device *dev); | |
686 | struct device_driver drv; | |
687 | int id; | |
688 | }; | |
689 | ||
690 | static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) | |
691 | { | |
692 | return container_of(drv, struct cxl_driver, drv); | |
693 | } | |
694 | ||
695 | int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, | |
696 | const char *modname); | |
697 | #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) | |
698 | void cxl_driver_unregister(struct cxl_driver *cxl_drv); | |
699 | ||
c57cae78 BW |
700 | #define module_cxl_driver(__cxl_driver) \ |
701 | module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) | |
702 | ||
21083f51 DW |
703 | #define CXL_DEVICE_NVDIMM_BRIDGE 1 |
704 | #define CXL_DEVICE_NVDIMM 2 | |
54cdbf84 BW |
705 | #define CXL_DEVICE_PORT 3 |
706 | #define CXL_DEVICE_ROOT 4 | |
8dd2bc0f | 707 | #define CXL_DEVICE_MEMORY_EXPANDER 5 |
8d48817d | 708 | #define CXL_DEVICE_REGION 6 |
04ad63f0 | 709 | #define CXL_DEVICE_PMEM_REGION 7 |
8fdcb170 | 710 | |
6af7139c DW |
711 | #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") |
712 | #define CXL_MODALIAS_FMT "cxl:t%d" | |
713 | ||
8fdcb170 DW |
714 | struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); |
715 | struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, | |
716 | struct cxl_port *port); | |
21083f51 DW |
717 | struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); |
718 | bool is_cxl_nvdimm(struct device *dev); | |
53989fad | 719 | bool is_cxl_nvdimm_bridge(struct device *dev); |
f17b558d | 720 | int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); |
04ad63f0 DW |
721 | struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct device *dev); |
722 | ||
723 | #ifdef CONFIG_CXL_REGION | |
724 | bool is_cxl_pmem_region(struct device *dev); | |
725 | struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); | |
a32320b7 DW |
726 | int cxl_add_to_region(struct cxl_port *root, |
727 | struct cxl_endpoint_decoder *cxled); | |
04ad63f0 DW |
728 | #else |
729 | static inline bool is_cxl_pmem_region(struct device *dev) | |
730 | { | |
731 | return false; | |
732 | } | |
733 | static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) | |
734 | { | |
735 | return NULL; | |
736 | } | |
a32320b7 DW |
737 | static inline int cxl_add_to_region(struct cxl_port *root, |
738 | struct cxl_endpoint_decoder *cxled) | |
739 | { | |
740 | return 0; | |
741 | } | |
04ad63f0 | 742 | #endif |
67dcdd4d DW |
743 | |
744 | /* | |
745 | * Unit test builds overrides this to __weak, find the 'strong' version | |
746 | * of these symbols in tools/testing/cxl/. | |
747 | */ | |
748 | #ifndef __mock | |
749 | #define __mock static | |
750 | #endif | |
3c5b9039 | 751 | |
8adaf747 | 752 | #endif /* __CXL_H__ */ |