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8adaf747 BW |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* Copyright(c) 2020 Intel Corporation. */ | |
3 | ||
4 | #ifndef __CXL_H__ | |
5 | #define __CXL_H__ | |
6 | ||
8fdcb170 | 7 | #include <linux/libnvdimm.h> |
8adaf747 BW |
8 | #include <linux/bitfield.h> |
9 | #include <linux/bitops.h> | |
80d10a6c | 10 | #include <linux/log2.h> |
8adaf747 BW |
11 | #include <linux/io.h> |
12 | ||
4812be97 DW |
13 | /** |
14 | * DOC: cxl objects | |
15 | * | |
16 | * The CXL core objects like ports, decoders, and regions are shared | |
17 | * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers | |
18 | * (port-driver, region-driver, nvdimm object-drivers... etc). | |
19 | */ | |
20 | ||
d17d0540 DW |
21 | /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ |
22 | #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K | |
23 | ||
08422378 BW |
24 | /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ |
25 | #define CXL_CM_OFFSET 0x1000 | |
26 | #define CXL_CM_CAP_HDR_OFFSET 0x0 | |
27 | #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) | |
28 | #define CM_CAP_HDR_CAP_ID 1 | |
29 | #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) | |
30 | #define CM_CAP_HDR_CAP_VERSION 1 | |
31 | #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) | |
32 | #define CM_CAP_HDR_CACHE_MEM_VERSION 1 | |
33 | #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) | |
34 | #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) | |
35 | ||
36 | #define CXL_CM_CAP_CAP_ID_HDM 0x5 | |
37 | #define CXL_CM_CAP_CAP_HDM_VERSION 1 | |
38 | ||
39 | /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ | |
40 | #define CXL_HDM_DECODER_CAP_OFFSET 0x0 | |
41 | #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) | |
42 | #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) | |
d17d0540 DW |
43 | #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) |
44 | #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) | |
45 | #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 | |
46 | #define CXL_HDM_DECODER_ENABLE BIT(1) | |
47 | #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) | |
48 | #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) | |
49 | #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) | |
50 | #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) | |
51 | #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) | |
52 | #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) | |
53 | #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) | |
54 | #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) | |
55 | #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) | |
56 | #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) | |
176baefb | 57 | #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) |
d17d0540 DW |
58 | #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12) |
59 | #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) | |
60 | #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) | |
9c57cde0 DW |
61 | #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) |
62 | #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) | |
08422378 | 63 | |
6423035f BW |
64 | static inline int cxl_hdm_decoder_count(u32 cap_hdr) |
65 | { | |
66 | int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); | |
67 | ||
68 | return val ? val * 2 : 1; | |
69 | } | |
70 | ||
419af595 DW |
71 | /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ |
72 | static inline int cxl_to_granularity(u16 ig, unsigned int *val) | |
73 | { | |
74 | if (ig > 6) | |
75 | return -EINVAL; | |
76 | *val = 256 << ig; | |
77 | return 0; | |
78 | } | |
79 | ||
80 | /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ | |
81 | static inline int cxl_to_ways(u8 eniw, unsigned int *val) | |
82 | { | |
83 | switch (eniw) { | |
84 | case 0 ... 4: | |
85 | *val = 1 << eniw; | |
86 | break; | |
87 | case 8 ... 10: | |
88 | *val = 3 << (eniw - 8); | |
89 | break; | |
90 | default: | |
91 | return -EINVAL; | |
92 | } | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
80d10a6c BW |
97 | static inline int granularity_to_cxl(int g, u16 *ig) |
98 | { | |
99 | if (g > SZ_16K || g < 256 || !is_power_of_2(g)) | |
100 | return -EINVAL; | |
101 | *ig = ilog2(g) - 8; | |
102 | return 0; | |
103 | } | |
104 | ||
c7e3548c | 105 | static inline int ways_to_cxl(unsigned int ways, u8 *iw) |
80d10a6c BW |
106 | { |
107 | if (ways > 16) | |
108 | return -EINVAL; | |
109 | if (is_power_of_2(ways)) { | |
110 | *iw = ilog2(ways); | |
111 | return 0; | |
112 | } | |
113 | if (ways % 3) | |
114 | return -EINVAL; | |
115 | ways /= 3; | |
116 | if (!is_power_of_2(ways)) | |
117 | return -EINVAL; | |
118 | *iw = ilog2(ways) + 8; | |
119 | return 0; | |
120 | } | |
121 | ||
8adaf747 BW |
122 | /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ |
123 | #define CXLDEV_CAP_ARRAY_OFFSET 0x0 | |
124 | #define CXLDEV_CAP_ARRAY_CAP_ID 0 | |
125 | #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) | |
126 | #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) | |
127 | /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ | |
128 | #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) | |
129 | /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ | |
130 | #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 | |
131 | #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 | |
132 | #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 | |
133 | #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 | |
134 | ||
135 | /* CXL 2.0 8.2.8.4 Mailbox Registers */ | |
136 | #define CXLDEV_MBOX_CAPS_OFFSET 0x00 | |
137 | #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) | |
138 | #define CXLDEV_MBOX_CTRL_OFFSET 0x04 | |
139 | #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) | |
140 | #define CXLDEV_MBOX_CMD_OFFSET 0x08 | |
141 | #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) | |
142 | #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) | |
143 | #define CXLDEV_MBOX_STATUS_OFFSET 0x10 | |
144 | #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) | |
145 | #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 | |
146 | #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 | |
147 | ||
8ac75dd6 | 148 | /* |
301e68dd KC |
149 | * Using struct_group() allows for per register-block-type helper routines, |
150 | * without requiring block-type agnostic code to include the prefix. | |
8ac75dd6 DW |
151 | */ |
152 | struct cxl_regs { | |
301e68dd KC |
153 | /* |
154 | * Common set of CXL Component register block base pointers | |
155 | * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure | |
156 | */ | |
157 | struct_group_tagged(cxl_component_regs, component, | |
158 | void __iomem *hdm_decoder; | |
159 | ); | |
160 | /* | |
161 | * Common set of CXL Device register block base pointers | |
162 | * @status: CXL 2.0 8.2.8.3 Device Status Registers | |
163 | * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers | |
164 | * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers | |
165 | */ | |
166 | struct_group_tagged(cxl_device_regs, device_regs, | |
167 | void __iomem *status, *mbox, *memdev; | |
168 | ); | |
8ac75dd6 DW |
169 | }; |
170 | ||
30af9729 IW |
171 | struct cxl_reg_map { |
172 | bool valid; | |
173 | unsigned long offset; | |
174 | unsigned long size; | |
175 | }; | |
176 | ||
08422378 BW |
177 | struct cxl_component_reg_map { |
178 | struct cxl_reg_map hdm_decoder; | |
179 | }; | |
180 | ||
30af9729 IW |
181 | struct cxl_device_reg_map { |
182 | struct cxl_reg_map status; | |
183 | struct cxl_reg_map mbox; | |
184 | struct cxl_reg_map memdev; | |
185 | }; | |
186 | ||
a261e9a1 DW |
187 | /** |
188 | * struct cxl_register_map - DVSEC harvested register block mapping parameters | |
189 | * @base: virtual base of the register-block-BAR + @block_offset | |
190 | * @block_offset: offset to start of register block in @barno | |
191 | * @reg_type: see enum cxl_regloc_type | |
192 | * @barno: PCI BAR number containing the register block | |
193 | * @component_map: cxl_reg_map for component registers | |
194 | * @device_map: cxl_reg_maps for device registers | |
195 | */ | |
30af9729 | 196 | struct cxl_register_map { |
a261e9a1 | 197 | void __iomem *base; |
30af9729 IW |
198 | u64 block_offset; |
199 | u8 reg_type; | |
200 | u8 barno; | |
201 | union { | |
08422378 | 202 | struct cxl_component_reg_map component_map; |
30af9729 IW |
203 | struct cxl_device_reg_map device_map; |
204 | }; | |
205 | }; | |
206 | ||
08422378 BW |
207 | void cxl_probe_component_regs(struct device *dev, void __iomem *base, |
208 | struct cxl_component_reg_map *map); | |
30af9729 IW |
209 | void cxl_probe_device_regs(struct device *dev, void __iomem *base, |
210 | struct cxl_device_reg_map *map); | |
08422378 BW |
211 | int cxl_map_component_regs(struct pci_dev *pdev, |
212 | struct cxl_component_regs *regs, | |
213 | struct cxl_register_map *map); | |
30af9729 IW |
214 | int cxl_map_device_regs(struct pci_dev *pdev, |
215 | struct cxl_device_regs *regs, | |
216 | struct cxl_register_map *map); | |
399d34eb | 217 | |
303ebc1b BW |
218 | enum cxl_regloc_type; |
219 | int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, | |
220 | struct cxl_register_map *map); | |
54cdbf84 BW |
221 | void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, |
222 | resource_size_t length); | |
303ebc1b | 223 | |
4812be97 | 224 | #define CXL_RESOURCE_NONE ((resource_size_t) -1) |
7d4b5ca2 | 225 | #define CXL_TARGET_STRLEN 20 |
4812be97 | 226 | |
40ba17af DW |
227 | /* |
228 | * cxl_decoder flags that define the type of memory / devices this | |
229 | * decoder supports as well as configuration lock status See "CXL 2.0 | |
230 | * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. | |
231 | */ | |
232 | #define CXL_DECODER_F_RAM BIT(0) | |
233 | #define CXL_DECODER_F_PMEM BIT(1) | |
234 | #define CXL_DECODER_F_TYPE2 BIT(2) | |
235 | #define CXL_DECODER_F_TYPE3 BIT(3) | |
236 | #define CXL_DECODER_F_LOCK BIT(4) | |
d17d0540 DW |
237 | #define CXL_DECODER_F_ENABLE BIT(5) |
238 | #define CXL_DECODER_F_MASK GENMASK(5, 0) | |
40ba17af DW |
239 | |
240 | enum cxl_decoder_type { | |
241 | CXL_DECODER_ACCELERATOR = 2, | |
242 | CXL_DECODER_EXPANDER = 3, | |
243 | }; | |
244 | ||
a5c25802 DW |
245 | /* |
246 | * Current specification goes up to 8, double that seems a reasonable | |
247 | * software max for the foreseeable future | |
248 | */ | |
249 | #define CXL_DECODER_MAX_INTERLEAVE 16 | |
250 | ||
e7748305 DW |
251 | #define CXL_DECODER_MIN_GRANULARITY 256 |
252 | ||
40ba17af | 253 | /** |
e636479e | 254 | * struct cxl_decoder - Common CXL HDM Decoder Attributes |
40ba17af DW |
255 | * @dev: this decoder's device |
256 | * @id: kernel device name id | |
e8b7ea58 | 257 | * @hpa_range: Host physical address range mapped by this decoder |
40ba17af DW |
258 | * @interleave_ways: number of cxl_dports in this decode |
259 | * @interleave_granularity: data stride per dport | |
260 | * @target_type: accelerator vs expander (type2 vs type3) selector | |
b9686e8c | 261 | * @region: currently assigned region for this decoder |
40ba17af | 262 | * @flags: memory type capabilities and locking |
176baefb DW |
263 | * @commit: device/decoder-type specific callback to commit settings to hw |
264 | * @reset: device/decoder-type specific callback to reset hw settings | |
265 | */ | |
40ba17af DW |
266 | struct cxl_decoder { |
267 | struct device dev; | |
268 | int id; | |
e50fe01e | 269 | struct range hpa_range; |
40ba17af DW |
270 | int interleave_ways; |
271 | int interleave_granularity; | |
272 | enum cxl_decoder_type target_type; | |
b9686e8c | 273 | struct cxl_region *region; |
40ba17af | 274 | unsigned long flags; |
176baefb DW |
275 | int (*commit)(struct cxl_decoder *cxld); |
276 | int (*reset)(struct cxl_decoder *cxld); | |
e636479e DW |
277 | }; |
278 | ||
b9686e8c DW |
279 | /* |
280 | * CXL_DECODER_DEAD prevents endpoints from being reattached to regions | |
281 | * while cxld_unregister() is running | |
282 | */ | |
2c866903 DW |
283 | enum cxl_decoder_mode { |
284 | CXL_DECODER_NONE, | |
285 | CXL_DECODER_RAM, | |
286 | CXL_DECODER_PMEM, | |
287 | CXL_DECODER_MIXED, | |
b9686e8c | 288 | CXL_DECODER_DEAD, |
2c866903 DW |
289 | }; |
290 | ||
3bf65915 DW |
291 | /** |
292 | * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder | |
293 | * @cxld: base cxl_decoder_object | |
294 | * @dpa_res: actively claimed DPA span of this decoder | |
295 | * @skip: offset into @dpa_res where @cxld.hpa_range maps | |
2c866903 | 296 | * @mode: which memory type / access-mode-partition this decoder targets |
b9686e8c | 297 | * @pos: interleave position in @cxld.region |
3bf65915 DW |
298 | */ |
299 | struct cxl_endpoint_decoder { | |
300 | struct cxl_decoder cxld; | |
301 | struct resource *dpa_res; | |
302 | resource_size_t skip; | |
2c866903 | 303 | enum cxl_decoder_mode mode; |
b9686e8c | 304 | int pos; |
3bf65915 DW |
305 | }; |
306 | ||
e636479e DW |
307 | /** |
308 | * struct cxl_switch_decoder - Switch specific CXL HDM Decoder | |
309 | * @cxld: base cxl_decoder object | |
310 | * @target_lock: coordinate coherent reads of the target list | |
311 | * @nr_targets: number of elements in @target | |
312 | * @target: active ordered target list in current decoder configuration | |
313 | * | |
314 | * The 'switch' decoder type represents the decoder instances of cxl_port's that | |
315 | * route from the root of a CXL memory decode topology to the endpoints. They | |
316 | * come in two flavors, root-level decoders, statically defined by platform | |
317 | * firmware, and mid-level decoders, where interleave-granularity, | |
318 | * interleave-width, and the target list are mutable. | |
319 | */ | |
320 | struct cxl_switch_decoder { | |
321 | struct cxl_decoder cxld; | |
86c8ea0f | 322 | seqlock_t target_lock; |
be185c29 | 323 | int nr_targets; |
40ba17af DW |
324 | struct cxl_dport *target[]; |
325 | }; | |
326 | ||
8fdcb170 | 327 | |
0f157c7f DW |
328 | /** |
329 | * struct cxl_root_decoder - Static platform CXL address decoder | |
330 | * @res: host / parent resource for region allocations | |
779dd20c | 331 | * @region_id: region id for next region provisioning event |
6aa41144 | 332 | * @calc_hb: which host bridge covers the n'th position by granularity |
0f157c7f DW |
333 | * @cxlsd: base cxl switch decoder |
334 | */ | |
335 | struct cxl_root_decoder { | |
336 | struct resource *res; | |
779dd20c | 337 | atomic_t region_id; |
6aa41144 | 338 | struct cxl_dport *(*calc_hb)(struct cxl_root_decoder *cxlrd, int pos); |
0f157c7f DW |
339 | struct cxl_switch_decoder cxlsd; |
340 | }; | |
341 | ||
dd5ba0eb BW |
342 | /* |
343 | * enum cxl_config_state - State machine for region configuration | |
344 | * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely | |
80d10a6c BW |
345 | * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more |
346 | * changes to interleave_ways or interleave_granularity | |
dd5ba0eb BW |
347 | * @CXL_CONFIG_ACTIVE: All targets have been added the region is now |
348 | * active | |
176baefb DW |
349 | * @CXL_CONFIG_RESET_PENDING: see commit_store() |
350 | * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware | |
dd5ba0eb BW |
351 | */ |
352 | enum cxl_config_state { | |
353 | CXL_CONFIG_IDLE, | |
80d10a6c | 354 | CXL_CONFIG_INTERLEAVE_ACTIVE, |
dd5ba0eb | 355 | CXL_CONFIG_ACTIVE, |
176baefb DW |
356 | CXL_CONFIG_RESET_PENDING, |
357 | CXL_CONFIG_COMMIT, | |
dd5ba0eb BW |
358 | }; |
359 | ||
360 | /** | |
361 | * struct cxl_region_params - region settings | |
362 | * @state: allow the driver to lockdown further parameter changes | |
363 | * @uuid: unique id for persistent regions | |
80d10a6c BW |
364 | * @interleave_ways: number of endpoints in the region |
365 | * @interleave_granularity: capacity each endpoint contributes to a stripe | |
23a22cd1 | 366 | * @res: allocated iomem capacity for this region |
038e6eb8 BS |
367 | * @targets: active ordered targets in current decoder configuration |
368 | * @nr_targets: number of targets | |
dd5ba0eb BW |
369 | * |
370 | * State transitions are protected by the cxl_region_rwsem | |
371 | */ | |
372 | struct cxl_region_params { | |
373 | enum cxl_config_state state; | |
374 | uuid_t uuid; | |
80d10a6c BW |
375 | int interleave_ways; |
376 | int interleave_granularity; | |
23a22cd1 | 377 | struct resource *res; |
b9686e8c DW |
378 | struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; |
379 | int nr_targets; | |
dd5ba0eb BW |
380 | }; |
381 | ||
779dd20c BW |
382 | /** |
383 | * struct cxl_region - CXL region | |
384 | * @dev: This region's device | |
385 | * @id: This region's id. Id is globally unique across all regions | |
386 | * @mode: Endpoint decoder allocation / access mode | |
387 | * @type: Endpoint decoder target type | |
dd5ba0eb | 388 | * @params: active + config params for the region |
779dd20c BW |
389 | */ |
390 | struct cxl_region { | |
391 | struct device dev; | |
392 | int id; | |
393 | enum cxl_decoder_mode mode; | |
394 | enum cxl_decoder_type type; | |
dd5ba0eb | 395 | struct cxl_region_params params; |
779dd20c BW |
396 | }; |
397 | ||
53989fad DW |
398 | /** |
399 | * enum cxl_nvdimm_brige_state - state machine for managing bus rescans | |
400 | * @CXL_NVB_NEW: Set at bridge create and after cxl_pmem_wq is destroyed | |
401 | * @CXL_NVB_DEAD: Set at brige unregistration to preclude async probing | |
402 | * @CXL_NVB_ONLINE: Target state after successful ->probe() | |
403 | * @CXL_NVB_OFFLINE: Target state after ->remove() or failed ->probe() | |
404 | */ | |
8fdcb170 DW |
405 | enum cxl_nvdimm_brige_state { |
406 | CXL_NVB_NEW, | |
407 | CXL_NVB_DEAD, | |
408 | CXL_NVB_ONLINE, | |
409 | CXL_NVB_OFFLINE, | |
410 | }; | |
411 | ||
412 | struct cxl_nvdimm_bridge { | |
2e52b625 | 413 | int id; |
8fdcb170 DW |
414 | struct device dev; |
415 | struct cxl_port *port; | |
416 | struct nvdimm_bus *nvdimm_bus; | |
417 | struct nvdimm_bus_descriptor nd_desc; | |
418 | struct work_struct state_work; | |
419 | enum cxl_nvdimm_brige_state state; | |
420 | }; | |
421 | ||
21083f51 DW |
422 | struct cxl_nvdimm { |
423 | struct device dev; | |
424 | struct cxl_memdev *cxlmd; | |
99183d26 | 425 | struct cxl_nvdimm_bridge *bridge; |
4d07ae22 | 426 | struct xarray pmem_regions; |
04ad63f0 DW |
427 | }; |
428 | ||
429 | struct cxl_pmem_region_mapping { | |
430 | struct cxl_memdev *cxlmd; | |
431 | struct cxl_nvdimm *cxl_nvd; | |
432 | u64 start; | |
433 | u64 size; | |
434 | int position; | |
435 | }; | |
436 | ||
437 | struct cxl_pmem_region { | |
438 | struct device dev; | |
439 | struct cxl_region *cxlr; | |
440 | struct nd_region *nd_region; | |
441 | struct cxl_nvdimm_bridge *bridge; | |
442 | struct range hpa_range; | |
443 | int nr_mappings; | |
444 | struct cxl_pmem_region_mapping mapping[]; | |
21083f51 DW |
445 | }; |
446 | ||
4812be97 DW |
447 | /** |
448 | * struct cxl_port - logical collection of upstream port devices and | |
449 | * downstream port devices to construct a CXL memory | |
450 | * decode hierarchy. | |
451 | * @dev: this port's device | |
452 | * @uport: PCI or platform device implementing the upstream port capability | |
ee800010 | 453 | * @host_bridge: Shortcut to the platform attach point for this port |
4812be97 | 454 | * @id: id for port device-name |
7d4b5ca2 | 455 | * @dports: cxl_dport instances referenced by decoders |
2703c16c | 456 | * @endpoints: cxl_ep instances, endpoints that are a descendant of this port |
384e624b | 457 | * @regions: cxl_region_ref instances, regions mapped by this port |
1b58b4ca | 458 | * @parent_dport: dport that points to this port in the parent |
40ba17af | 459 | * @decoder_ida: allocator for decoder ids |
e4f6dfa9 | 460 | * @nr_dports: number of entries in @dports |
0c33b393 | 461 | * @hdm_end: track last allocated HDM decoder instance for allocation ordering |
176baefb | 462 | * @commit_end: cursor to track highest committed decoder for commit ordering |
4812be97 | 463 | * @component_reg_phys: component register capability base address (optional) |
2703c16c | 464 | * @dead: last ep has been removed, force port re-creation |
53fa1bff | 465 | * @depth: How deep this port is relative to the root. depth 0 is the root. |
c9700604 IW |
466 | * @cdat: Cached CDAT data |
467 | * @cdat_available: Should a CDAT attribute be available in sysfs | |
4812be97 DW |
468 | */ |
469 | struct cxl_port { | |
470 | struct device dev; | |
471 | struct device *uport; | |
ee800010 | 472 | struct device *host_bridge; |
4812be97 | 473 | int id; |
39178585 | 474 | struct xarray dports; |
256d0e9e | 475 | struct xarray endpoints; |
384e624b | 476 | struct xarray regions; |
1b58b4ca | 477 | struct cxl_dport *parent_dport; |
40ba17af | 478 | struct ida decoder_ida; |
e4f6dfa9 | 479 | int nr_dports; |
0c33b393 | 480 | int hdm_end; |
176baefb | 481 | int commit_end; |
4812be97 | 482 | resource_size_t component_reg_phys; |
2703c16c | 483 | bool dead; |
53fa1bff | 484 | unsigned int depth; |
c9700604 IW |
485 | struct cxl_cdat { |
486 | void *table; | |
487 | size_t length; | |
488 | } cdat; | |
489 | bool cdat_available; | |
4812be97 DW |
490 | }; |
491 | ||
39178585 DW |
492 | static inline struct cxl_dport * |
493 | cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) | |
494 | { | |
495 | return xa_load(&port->dports, (unsigned long)dport_dev); | |
496 | } | |
497 | ||
7d4b5ca2 DW |
498 | /** |
499 | * struct cxl_dport - CXL downstream port | |
500 | * @dport: PCI bridge or firmware device representing the downstream link | |
501 | * @port_id: unique hardware identifier for dport in decoder target list | |
502 | * @component_reg_phys: downstream port component registers | |
503 | * @port: reference to cxl_port that contains this downstream port | |
7d4b5ca2 DW |
504 | */ |
505 | struct cxl_dport { | |
506 | struct device *dport; | |
507 | int port_id; | |
508 | resource_size_t component_reg_phys; | |
509 | struct cxl_port *port; | |
7d4b5ca2 DW |
510 | }; |
511 | ||
2703c16c DW |
512 | /** |
513 | * struct cxl_ep - track an endpoint's interest in a port | |
514 | * @ep: device that hosts a generic CXL endpoint (expander or accelerator) | |
de516b40 | 515 | * @dport: which dport routes to this endpoint on @port |
7f8faf96 DW |
516 | * @next: cxl switch port across the link attached to @dport NULL if |
517 | * attached to an endpoint | |
2703c16c DW |
518 | */ |
519 | struct cxl_ep { | |
520 | struct device *ep; | |
de516b40 | 521 | struct cxl_dport *dport; |
7f8faf96 | 522 | struct cxl_port *next; |
2703c16c DW |
523 | }; |
524 | ||
384e624b DW |
525 | /** |
526 | * struct cxl_region_ref - track a region's interest in a port | |
527 | * @port: point in topology to install this reference | |
528 | * @decoder: decoder assigned for @region in @port | |
529 | * @region: region for this reference | |
530 | * @endpoints: cxl_ep references for region members beneath @port | |
27b3f8d1 | 531 | * @nr_targets_set: track how many targets have been programmed during setup |
384e624b DW |
532 | * @nr_eps: number of endpoints beneath @port |
533 | * @nr_targets: number of distinct targets needed to reach @nr_eps | |
534 | */ | |
535 | struct cxl_region_ref { | |
536 | struct cxl_port *port; | |
537 | struct cxl_decoder *decoder; | |
538 | struct cxl_region *region; | |
539 | struct xarray endpoints; | |
27b3f8d1 | 540 | int nr_targets_set; |
384e624b DW |
541 | int nr_eps; |
542 | int nr_targets; | |
543 | }; | |
544 | ||
d54c1bbe BW |
545 | /* |
546 | * The platform firmware device hosting the root is also the top of the | |
547 | * CXL port topology. All other CXL ports have another CXL port as their | |
548 | * parent and their ->uport / host device is out-of-line of the port | |
549 | * ancestry. | |
550 | */ | |
551 | static inline bool is_cxl_root(struct cxl_port *port) | |
552 | { | |
553 | return port->uport == port->dev.parent; | |
554 | } | |
555 | ||
3c5b9039 | 556 | bool is_cxl_port(struct device *dev); |
4812be97 | 557 | struct cxl_port *to_cxl_port(struct device *dev); |
98d2d3a2 | 558 | struct pci_bus; |
5ff7316f DW |
559 | int devm_cxl_register_pci_bus(struct device *host, struct device *uport, |
560 | struct pci_bus *bus); | |
561 | struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); | |
4812be97 DW |
562 | struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, |
563 | resource_size_t component_reg_phys, | |
1b58b4ca | 564 | struct cxl_dport *parent_dport); |
7f8faf96 DW |
565 | int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd, |
566 | struct cxl_dport *parent_dport); | |
a46cfc0f | 567 | struct cxl_port *find_cxl_root(struct device *dev); |
2703c16c | 568 | int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); |
8dd2bc0f | 569 | int cxl_bus_rescan(void); |
1b58b4ca DW |
570 | struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, |
571 | struct cxl_dport **dport); | |
8dd2bc0f | 572 | bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); |
2703c16c | 573 | |
664bf115 | 574 | struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, |
98d2d3a2 DW |
575 | struct device *dport, int port_id, |
576 | resource_size_t component_reg_phys); | |
2703c16c | 577 | |
40ba17af | 578 | struct cxl_decoder *to_cxl_decoder(struct device *dev); |
0f157c7f | 579 | struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); |
3bf65915 | 580 | struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); |
8fdcb170 | 581 | bool is_root_decoder(struct device *dev); |
8ae3cebc | 582 | bool is_endpoint_decoder(struct device *dev); |
0f157c7f DW |
583 | struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, |
584 | unsigned int nr_targets); | |
e636479e DW |
585 | struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, |
586 | unsigned int nr_targets); | |
48667f67 | 587 | int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); |
3bf65915 | 588 | struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); |
d17d0540 | 589 | int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); |
48667f67 | 590 | int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); |
8dd2bc0f BW |
591 | int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); |
592 | ||
d17d0540 | 593 | struct cxl_hdm; |
664bf115 DW |
594 | struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port); |
595 | int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm); | |
596 | int devm_cxl_add_passthrough_decoder(struct cxl_port *port); | |
40ba17af | 597 | |
779dd20c BW |
598 | bool is_cxl_region(struct device *dev); |
599 | ||
b39cb105 | 600 | extern struct bus_type cxl_bus_type; |
6af7139c DW |
601 | |
602 | struct cxl_driver { | |
603 | const char *name; | |
604 | int (*probe)(struct device *dev); | |
605 | void (*remove)(struct device *dev); | |
606 | struct device_driver drv; | |
607 | int id; | |
608 | }; | |
609 | ||
610 | static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) | |
611 | { | |
612 | return container_of(drv, struct cxl_driver, drv); | |
613 | } | |
614 | ||
615 | int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, | |
616 | const char *modname); | |
617 | #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) | |
618 | void cxl_driver_unregister(struct cxl_driver *cxl_drv); | |
619 | ||
c57cae78 BW |
620 | #define module_cxl_driver(__cxl_driver) \ |
621 | module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) | |
622 | ||
21083f51 DW |
623 | #define CXL_DEVICE_NVDIMM_BRIDGE 1 |
624 | #define CXL_DEVICE_NVDIMM 2 | |
54cdbf84 BW |
625 | #define CXL_DEVICE_PORT 3 |
626 | #define CXL_DEVICE_ROOT 4 | |
8dd2bc0f | 627 | #define CXL_DEVICE_MEMORY_EXPANDER 5 |
8d48817d | 628 | #define CXL_DEVICE_REGION 6 |
04ad63f0 | 629 | #define CXL_DEVICE_PMEM_REGION 7 |
8fdcb170 | 630 | |
6af7139c DW |
631 | #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") |
632 | #define CXL_MODALIAS_FMT "cxl:t%d" | |
633 | ||
8fdcb170 DW |
634 | struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); |
635 | struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, | |
636 | struct cxl_port *port); | |
21083f51 DW |
637 | struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); |
638 | bool is_cxl_nvdimm(struct device *dev); | |
53989fad | 639 | bool is_cxl_nvdimm_bridge(struct device *dev); |
21083f51 | 640 | int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd); |
04ad63f0 DW |
641 | struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct device *dev); |
642 | ||
643 | #ifdef CONFIG_CXL_REGION | |
644 | bool is_cxl_pmem_region(struct device *dev); | |
645 | struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); | |
646 | #else | |
647 | static inline bool is_cxl_pmem_region(struct device *dev) | |
648 | { | |
649 | return false; | |
650 | } | |
651 | static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) | |
652 | { | |
653 | return NULL; | |
654 | } | |
655 | #endif | |
67dcdd4d DW |
656 | |
657 | /* | |
658 | * Unit test builds overrides this to __weak, find the 'strong' version | |
659 | * of these symbols in tools/testing/cxl/. | |
660 | */ | |
661 | #ifndef __mock | |
662 | #define __mock static | |
663 | #endif | |
3c5b9039 | 664 | |
8adaf747 | 665 | #endif /* __CXL_H__ */ |