projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 8adaf747 BW |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* Copyright(c) 2020 Intel Corporation. */ | |
| 3 | ||
| 4 | #ifndef __CXL_H__ | |
| 5 | #define __CXL_H__ | |
| 6 | ||
| 7 | #include <linux/bitfield.h> | |
| 8 | #include <linux/bitops.h> | |
| 9 | #include <linux/io.h> | |
| 10 | ||
| 11 | /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ | |
| 12 | #define CXLDEV_CAP_ARRAY_OFFSET 0x0 | |
| 13 | #define CXLDEV_CAP_ARRAY_CAP_ID 0 | |
| 14 | #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) | |
| 15 | #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) | |
| 16 | /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ | |
| 17 | #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) | |
| 18 | /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ | |
| 19 | #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 | |
| 20 | #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 | |
| 21 | #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 | |
| 22 | #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 | |
| 23 | ||
| 24 | /* CXL 2.0 8.2.8.4 Mailbox Registers */ | |
| 25 | #define CXLDEV_MBOX_CAPS_OFFSET 0x00 | |
| 26 | #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) | |
| 27 | #define CXLDEV_MBOX_CTRL_OFFSET 0x04 | |
| 28 | #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) | |
| 29 | #define CXLDEV_MBOX_CMD_OFFSET 0x08 | |
| 30 | #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) | |
| 31 | #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) | |
| 32 | #define CXLDEV_MBOX_STATUS_OFFSET 0x10 | |
| 33 | #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) | |
| 34 | #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 | |
| 35 | #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 | |
| 36 | ||
| b39cb105 | 37 | extern struct bus_type cxl_bus_type; |
| 8adaf747 | 38 | #endif /* __CXL_H__ */ |