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1 | # SPDX-License-Identifier: GPL-2.0-only |
2 | menuconfig CXL_BUS | |
3 | tristate "CXL (Compute Express Link) Devices Support" | |
4 | depends on PCI | |
5 | help | |
6 | CXL is a bus that is electrically compatible with PCI Express, but | |
7 | layers three protocols on that signalling (CXL.io, CXL.cache, and | |
8 | CXL.mem). The CXL.cache protocol allows devices to hold cachelines | |
9 | locally, the CXL.mem protocol allows devices to be fully coherent | |
10 | memory targets, the CXL.io protocol is equivalent to PCI Express. | |
11 | Say 'y' to enable support for the configuration and management of | |
12 | devices supporting these protocols. | |
13 | ||
14 | if CXL_BUS | |
15 | ||
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16 | config CXL_PCI |
17 | tristate "PCI manageability" | |
3feaa2d3 | 18 | default CXL_BUS |
4cdadfd5 | 19 | help |
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20 | The CXL specification defines a "CXL memory device" sub-class in the |
21 | PCI "memory controller" base class of devices. Device's identified by | |
22 | this class code provide support for volatile and / or persistent | |
23 | memory to be mapped into the system address map (Host-managed Device | |
24 | Memory (HDM)). | |
4cdadfd5 | 25 | |
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26 | Say 'y/m' to enable a driver that will attach to CXL memory expander |
27 | devices enumerated by the memory device class code for configuration | |
28 | and management primarily via the mailbox interface. See Chapter 2.3 | |
29 | Type 3 CXL Device in the CXL 2.0 specification for more details. | |
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30 | |
31 | If unsure say 'm'. | |
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32 | |
33 | config CXL_MEM_RAW_COMMANDS | |
34 | bool "RAW Command Interface for Memory Devices" | |
68cdd3d2 | 35 | depends on CXL_PCI |
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36 | help |
37 | Enable CXL RAW command interface. | |
38 | ||
39 | The CXL driver ioctl interface may assign a kernel ioctl command | |
40 | number for each specification defined opcode. At any given point in | |
41 | time the number of opcodes that the specification defines and a device | |
42 | may implement may exceed the kernel's set of associated ioctl function | |
43 | numbers. The mismatch is either by omission, specification is too new, | |
44 | or by design. When prototyping new hardware, or developing / debugging | |
45 | the driver it is useful to be able to submit any possible command to | |
46 | the hardware, even commands that may crash the kernel due to their | |
47 | potential impact to memory currently in use by the kernel. | |
48 | ||
49 | If developing CXL hardware or the driver say Y, otherwise say N. | |
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50 | |
51 | config CXL_ACPI | |
52 | tristate "CXL ACPI: Platform Support" | |
53 | depends on ACPI | |
3feaa2d3 | 54 | default CXL_BUS |
f4ce1f76 | 55 | select ACPI_TABLE_LIB |
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56 | help |
57 | Enable support for host managed device memory (HDM) resources | |
58 | published by a platform's ACPI CXL memory layout description. See | |
59 | Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 | |
60 | specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) | |
61 | (https://www.computeexpresslink.org/spec-landing). The CXL core | |
62 | consumes these resource to publish the root of a cxl_port decode | |
63 | hierarchy to map regions that represent System RAM, or Persistent | |
64 | Memory regions to be managed by LIBNVDIMM. | |
65 | ||
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66 | If unsure say 'm'. |
67 | ||
68 | config CXL_PMEM | |
69 | tristate "CXL PMEM: Persistent Memory Support" | |
70 | depends on LIBNVDIMM | |
71 | default CXL_BUS | |
72 | help | |
73 | In addition to typical memory resources a platform may also advertise | |
74 | support for persistent memory attached via CXL. This support is | |
75 | managed via a bridge driver from CXL to the LIBNVDIMM system | |
76 | subsystem. Say 'y/m' to enable support for enumerating and | |
77 | provisioning the persistent memory capacity of CXL memory expanders. | |
78 | ||
4812be97 | 79 | If unsure say 'm'. |
4cdadfd5 | 80 | endif |