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crypto: caam - fix hash context DMA unmap size
[linux-2.6-block.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
5228f0f7 4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
9c4a7965
KP		 5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
5af50730
RH		 35#include <linux/of_address.h>
36#include <linux/of_irq.h>
9c4a7965
KP		 37#include <linux/of_platform.h>
38#include <linux/dma-mapping.h>
39#include <linux/io.h>
40#include <linux/spinlock.h>
41#include <linux/rtnetlink.h>
5a0e3ad6 42#include <linux/slab.h>
9c4a7965
KP		 43
44#include <crypto/algapi.h>
45#include <crypto/aes.h>
3952f17e 46#include <crypto/des.h>
9c4a7965 47#include <crypto/sha.h>
497f2e6b 48#include <crypto/md5.h>
e98014ab 49#include <crypto/internal/aead.h>
9c4a7965 50#include <crypto/authenc.h>
4de9d0b5 51#include <crypto/skcipher.h>
acbf7c62
LN		 52#include <crypto/hash.h>
53#include <crypto/internal/hash.h>
4de9d0b5 54#include <crypto/scatterwalk.h>
9c4a7965
KP		 55
56#include "talitos.h"
57
922f9dc8 58static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
da9de146 59 unsigned int len, bool is_sec1)
81eb024c 60{
edc6bd69 61 ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
da9de146
LC		 62 if (is_sec1) {
63 ptr->len1 = cpu_to_be16(len);
64 } else {
65 ptr->len = cpu_to_be16(len);
922f9dc8 66 ptr->eptr = upper_32_bits(dma_addr);
da9de146 67 }
81eb024c
KP		 68}
69
340ff60a
HG		 70static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
71 struct talitos_ptr *src_ptr, bool is_sec1)
72{
73 dst_ptr->ptr = src_ptr->ptr;
922f9dc8 74 if (is_sec1) {
da9de146 75 dst_ptr->len1 = src_ptr->len1;
922f9dc8 76 } else {
da9de146
LC		 77 dst_ptr->len = src_ptr->len;
78 dst_ptr->eptr = src_ptr->eptr;
922f9dc8 79 }
538caf83
LC		 80}
81
922f9dc8
LC		 82static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
83 bool is_sec1)
538caf83 84{
922f9dc8
LC		 85 if (is_sec1)
86 return be16_to_cpu(ptr->len1);
87 else
88 return be16_to_cpu(ptr->len);
538caf83
LC		 89}
90
b096b544
LC		 91static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
92 bool is_sec1)
185eb79f 93{
922f9dc8 94 if (!is_sec1)
b096b544
LC		 95 ptr->j_extent = val;
96}
97
98static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
99{
100 if (!is_sec1)
101 ptr->j_extent |= val;
185eb79f
LC		 102}
103
9c4a7965
KP		 104/*
105 * map virtual single (contiguous) pointer to h/w descriptor pointer
106 */
6a4967c3
LC		 107static void __map_single_talitos_ptr(struct device *dev,
108 struct talitos_ptr *ptr,
109 unsigned int len, void *data,
110 enum dma_data_direction dir,
111 unsigned long attrs)
112{
113 dma_addr_t dma_addr = dma_map_single_attrs(dev, data, len, dir, attrs);
114 struct talitos_private *priv = dev_get_drvdata(dev);
115 bool is_sec1 = has_ftr_sec1(priv);
116
117 to_talitos_ptr(ptr, dma_addr, len, is_sec1);
118}
119
9c4a7965 120static void map_single_talitos_ptr(struct device *dev,
edc6bd69 121 struct talitos_ptr *ptr,
42e8b0d7 122 unsigned int len, void *data,
9c4a7965
KP		 123 enum dma_data_direction dir)
124{
6a4967c3
LC		 125 __map_single_talitos_ptr(dev, ptr, len, data, dir, 0);
126}
81eb024c 127
6a4967c3
LC		 128static void map_single_talitos_ptr_nosync(struct device *dev,
129 struct talitos_ptr *ptr,
130 unsigned int len, void *data,
131 enum dma_data_direction dir)
132{
133 __map_single_talitos_ptr(dev, ptr, len, data, dir,
134 DMA_ATTR_SKIP_CPU_SYNC);
9c4a7965
KP		 135}
136
137/*
138 * unmap bus single (contiguous) h/w descriptor pointer
139 */
140static void unmap_single_talitos_ptr(struct device *dev,
edc6bd69 141 struct talitos_ptr *ptr,
9c4a7965
KP		 142 enum dma_data_direction dir)
143{
922f9dc8
LC		 144 struct talitos_private *priv = dev_get_drvdata(dev);
145 bool is_sec1 = has_ftr_sec1(priv);
146
edc6bd69 147 dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
922f9dc8 148 from_talitos_ptr_len(ptr, is_sec1), dir);
9c4a7965
KP		 149}
150
151static int reset_channel(struct device *dev, int ch)
152{
153 struct talitos_private *priv = dev_get_drvdata(dev);
154 unsigned int timeout = TALITOS_TIMEOUT;
dd3c0987 155 bool is_sec1 = has_ftr_sec1(priv);
9c4a7965 156
dd3c0987
LC		 157 if (is_sec1) {
158 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
159 TALITOS1_CCCR_LO_RESET);
9c4a7965 160
dd3c0987
LC		 161 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
162 TALITOS1_CCCR_LO_RESET) && --timeout)
163 cpu_relax();
164 } else {
165 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
166 TALITOS2_CCCR_RESET);
167
168 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
169 TALITOS2_CCCR_RESET) && --timeout)
170 cpu_relax();
171 }
9c4a7965
KP		 172
173 if (timeout == 0) {
174 dev_err(dev, "failed to reset channel %d\n", ch);
175 return -EIO;
176 }
177
81eb024c 178 /* set 36-bit addressing, done writeback enable and done IRQ enable */
ad42d5fc 179 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
81eb024c 180 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
37b5e889
LC		 181 /* enable chaining descriptors */
182 if (is_sec1)
183 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
184 TALITOS_CCCR_LO_NE);
9c4a7965 185
fe5720e2
KP		 186 /* and ICCR writeback, if available */
187 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
ad42d5fc 188 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
fe5720e2
KP		 189 TALITOS_CCCR_LO_IWSE);
190
9c4a7965
KP		 191 return 0;
192}
193
194static int reset_device(struct device *dev)
195{
196 struct talitos_private *priv = dev_get_drvdata(dev);
197 unsigned int timeout = TALITOS_TIMEOUT;
dd3c0987
LC		 198 bool is_sec1 = has_ftr_sec1(priv);
199 u32 mcr = is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
9c4a7965 200
c3e337f8 201 setbits32(priv->reg + TALITOS_MCR, mcr);
9c4a7965 202
dd3c0987 203 while ((in_be32(priv->reg + TALITOS_MCR) & mcr)
9c4a7965
KP		 204 && --timeout)
205 cpu_relax();
206
2cdba3cf 207 if (priv->irq[1]) {
c3e337f8
KP		 208 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
209 setbits32(priv->reg + TALITOS_MCR, mcr);
210 }
211
9c4a7965
KP		 212 if (timeout == 0) {
213 dev_err(dev, "failed to reset device\n");
214 return -EIO;
215 }
216
217 return 0;
218}
219
220/*
221 * Reset and initialize the device
222 */
223static int init_device(struct device *dev)
224{
225 struct talitos_private *priv = dev_get_drvdata(dev);
226 int ch, err;
dd3c0987 227 bool is_sec1 = has_ftr_sec1(priv);
9c4a7965
KP		 228
229 /*
230 * Master reset
231 * errata documentation: warning: certain SEC interrupts
232 * are not fully cleared by writing the MCR:SWR bit,
233 * set bit twice to completely reset
234 */
235 err = reset_device(dev);
236 if (err)
237 return err;
238
239 err = reset_device(dev);
240 if (err)
241 return err;
242
243 /* reset channels */
244 for (ch = 0; ch < priv->num_channels; ch++) {
245 err = reset_channel(dev, ch);
246 if (err)
247 return err;
248 }
249
250 /* enable channel done and error interrupts */
dd3c0987
LC		 251 if (is_sec1) {
252 clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
253 clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
254 /* disable parity error check in DEU (erroneous? test vect.) */
255 setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
256 } else {
257 setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT);
258 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
259 }
9c4a7965 260
fe5720e2
KP		 261 /* disable integrity check error interrupts (use writeback instead) */
262 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
5fa7fa14 263 setbits32(priv->reg_mdeu + TALITOS_EUICR_LO,
fe5720e2
KP		 264 TALITOS_MDEUICR_LO_ICE);
265
9c4a7965
KP		 266 return 0;
267}
268
269/**
270 * talitos_submit - submits a descriptor to the device for processing
271 * @dev: the SEC device to be used
5228f0f7 272 * @ch: the SEC device channel to be used
9c4a7965
KP		 273 * @desc: the descriptor to be processed by the device
274 * @callback: whom to call when processing is complete
275 * @context: a handle for use by caller (optional)
276 *
277 * desc must contain valid dma-mapped (bus physical) address pointers.
278 * callback must check err and feedback in descriptor header
279 * for device processing status.
280 */
865d5061
HG		 281int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
282 void (*callback)(struct device *dev,
283 struct talitos_desc *desc,
284 void *context, int error),
285 void *context)
9c4a7965
KP		 286{
287 struct talitos_private *priv = dev_get_drvdata(dev);
288 struct talitos_request *request;
5228f0f7 289 unsigned long flags;
9c4a7965 290 int head;
7d607c6a 291 bool is_sec1 = has_ftr_sec1(priv);
9c4a7965 292
4b992628 293 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 294
4b992628 295 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 296 /* h/w fifo is full */
4b992628 297 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 298 return -EAGAIN;
299 }
300
4b992628
KP		 301 head = priv->chan[ch].head;
302 request = &priv->chan[ch].fifo[head];
ec6644d6 303
9c4a7965 304 /* map descriptor and save caller data */
7d607c6a
LC		 305 if (is_sec1) {
306 desc->hdr1 = desc->hdr;
7d607c6a
LC		 307 request->dma_desc = dma_map_single(dev, &desc->hdr1,
308 TALITOS_DESC_SIZE,
309 DMA_BIDIRECTIONAL);
310 } else {
311 request->dma_desc = dma_map_single(dev, desc,
312 TALITOS_DESC_SIZE,
313 DMA_BIDIRECTIONAL);
314 }
9c4a7965
KP		 315 request->callback = callback;
316 request->context = context;
317
318 /* increment fifo head */
4b992628 319 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 320
321 smp_wmb();
322 request->desc = desc;
323
324 /* GO! */
325 wmb();
ad42d5fc
KP		 326 out_be32(priv->chan[ch].reg + TALITOS_FF,
327 upper_32_bits(request->dma_desc));
328 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
a752447a 329 lower_32_bits(request->dma_desc));
9c4a7965 330
4b992628 331 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 332
333 return -EINPROGRESS;
334}
865d5061 335EXPORT_SYMBOL(talitos_submit);
9c4a7965
KP		 336
337/*
338 * process what was done, notify callback of error if not
339 */
340static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
341{
342 struct talitos_private *priv = dev_get_drvdata(dev);
343 struct talitos_request *request, saved_req;
344 unsigned long flags;
345 int tail, status;
7d607c6a 346 bool is_sec1 = has_ftr_sec1(priv);
9c4a7965 347
4b992628 348 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 349
4b992628
KP		 350 tail = priv->chan[ch].tail;
351 while (priv->chan[ch].fifo[tail].desc) {
7d607c6a
LC		 352 __be32 hdr;
353
4b992628 354 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 355
356 /* descriptors with their done bits set don't get the error */
357 rmb();
37b5e889
LC		 358 if (!is_sec1)
359 hdr = request->desc->hdr;
360 else if (request->desc->next_desc)
361 hdr = (request->desc + 1)->hdr1;
362 else
363 hdr = request->desc->hdr1;
7d607c6a
LC		 364
365 if ((hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 366 status = 0;
ca38a814 367 else
9c4a7965
KP		 368 if (!error)
369 break;
370 else
371 status = error;
372
373 dma_unmap_single(dev, request->dma_desc,
7d607c6a 374 TALITOS_DESC_SIZE,
e938e465 375 DMA_BIDIRECTIONAL);
9c4a7965
KP		 376
377 /* copy entries so we can call callback outside lock */
378 saved_req.desc = request->desc;
379 saved_req.callback = request->callback;
380 saved_req.context = request->context;
381
382 /* release request entry in fifo */
383 smp_wmb();
384 request->desc = NULL;
385
386 /* increment fifo tail */
4b992628 387 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 388
4b992628 389 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 390
4b992628 391 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 392
9c4a7965
KP		 393 saved_req.callback(dev, saved_req.desc, saved_req.context,
394 status);
395 /* channel may resume processing in single desc error case */
396 if (error && !reset_ch && status == error)
397 return;
4b992628
KP		 398 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
399 tail = priv->chan[ch].tail;
9c4a7965
KP		 400 }
401
4b992628 402 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 403}
404
405/*
406 * process completed requests for channels that have done status
407 */
dd3c0987
LC		 408#define DEF_TALITOS1_DONE(name, ch_done_mask) \
409static void talitos1_done_##name(unsigned long data) \
410{ \
411 struct device *dev = (struct device *)data; \
412 struct talitos_private *priv = dev_get_drvdata(dev); \
413 unsigned long flags; \
414 \
415 if (ch_done_mask & 0x10000000) \
416 flush_channel(dev, 0, 0, 0); \
dd3c0987
LC		 417 if (ch_done_mask & 0x40000000) \
418 flush_channel(dev, 1, 0, 0); \
419 if (ch_done_mask & 0x00010000) \
420 flush_channel(dev, 2, 0, 0); \
421 if (ch_done_mask & 0x00040000) \
422 flush_channel(dev, 3, 0, 0); \
423 \
dd3c0987
LC		 424 /* At this point, all completed channels have been processed */ \
425 /* Unmask done interrupts for channels completed later on. */ \
426 spin_lock_irqsave(&priv->reg_lock, flags); \
427 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
428 clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT); \
429 spin_unlock_irqrestore(&priv->reg_lock, flags); \
430}
431
432DEF_TALITOS1_DONE(4ch, TALITOS1_ISR_4CHDONE)
9c02e285 433DEF_TALITOS1_DONE(ch0, TALITOS1_ISR_CH_0_DONE)
dd3c0987
LC		 434
435#define DEF_TALITOS2_DONE(name, ch_done_mask) \
436static void talitos2_done_##name(unsigned long data) \
c3e337f8
KP		 437{ \
438 struct device *dev = (struct device *)data; \
439 struct talitos_private *priv = dev_get_drvdata(dev); \
511d63cb 440 unsigned long flags; \
c3e337f8
KP		 441 \
442 if (ch_done_mask & 1) \
443 flush_channel(dev, 0, 0, 0); \
c3e337f8
KP		 444 if (ch_done_mask & (1 << 2)) \
445 flush_channel(dev, 1, 0, 0); \
446 if (ch_done_mask & (1 << 4)) \
447 flush_channel(dev, 2, 0, 0); \
448 if (ch_done_mask & (1 << 6)) \
449 flush_channel(dev, 3, 0, 0); \
450 \
c3e337f8
KP		 451 /* At this point, all completed channels have been processed */ \
452 /* Unmask done interrupts for channels completed later on. */ \
511d63cb 453 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8 454 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
dd3c0987 455 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); \
511d63cb 456 spin_unlock_irqrestore(&priv->reg_lock, flags); \
9c4a7965 457}
dd3c0987
LC		 458
459DEF_TALITOS2_DONE(4ch, TALITOS2_ISR_4CHDONE)
9c02e285 460DEF_TALITOS2_DONE(ch0, TALITOS2_ISR_CH_0_DONE)
dd3c0987
LC		 461DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
462DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
9c4a7965
KP		 463
464/*
465 * locate current (offending) descriptor
466 */
3e721aeb 467static u32 current_desc_hdr(struct device *dev, int ch)
9c4a7965
KP		 468{
469 struct talitos_private *priv = dev_get_drvdata(dev);
b62ffd8c 470 int tail, iter;
9c4a7965
KP		 471 dma_addr_t cur_desc;
472
b62ffd8c
HG		 473 cur_desc = ((u64)in_be32(priv->chan[ch].reg + TALITOS_CDPR)) << 32;
474 cur_desc |= in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
9c4a7965 475
b62ffd8c
HG		 476 if (!cur_desc) {
477 dev_err(dev, "CDPR is NULL, giving up search for offending descriptor\n");
478 return 0;
479 }
480
481 tail = priv->chan[ch].tail;
482
483 iter = tail;
37b5e889
LC		 484 while (priv->chan[ch].fifo[iter].dma_desc != cur_desc &&
485 priv->chan[ch].fifo[iter].desc->next_desc != cur_desc) {
b62ffd8c
HG		 486 iter = (iter + 1) & (priv->fifo_len - 1);
487 if (iter == tail) {
9c4a7965 488 dev_err(dev, "couldn't locate current descriptor\n");
3e721aeb 489 return 0;
9c4a7965
KP		 490 }
491 }
492
37b5e889
LC		 493 if (priv->chan[ch].fifo[iter].desc->next_desc == cur_desc)
494 return (priv->chan[ch].fifo[iter].desc + 1)->hdr;
495
b62ffd8c 496 return priv->chan[ch].fifo[iter].desc->hdr;
9c4a7965
KP		 497}
498
499/*
500 * user diagnostics; report root cause of error based on execution unit status
501 */
3e721aeb 502static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
9c4a7965
KP		 503{
504 struct talitos_private *priv = dev_get_drvdata(dev);
505 int i;
506
3e721aeb 507 if (!desc_hdr)
ad42d5fc 508 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
3e721aeb
KP		 509
510 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
9c4a7965
KP		 511 case DESC_HDR_SEL0_AFEU:
512 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
5fa7fa14
LC		 513 in_be32(priv->reg_afeu + TALITOS_EUISR),
514 in_be32(priv->reg_afeu + TALITOS_EUISR_LO));
9c4a7965
KP		 515 break;
516 case DESC_HDR_SEL0_DEU:
517 dev_err(dev, "DEUISR 0x%08x_%08x\n",
5fa7fa14
LC		 518 in_be32(priv->reg_deu + TALITOS_EUISR),
519 in_be32(priv->reg_deu + TALITOS_EUISR_LO));
9c4a7965
KP		 520 break;
521 case DESC_HDR_SEL0_MDEUA:
522 case DESC_HDR_SEL0_MDEUB:
523 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
5fa7fa14
LC		 524 in_be32(priv->reg_mdeu + TALITOS_EUISR),
525 in_be32(priv->reg_mdeu + TALITOS_EUISR_LO));
9c4a7965
KP		 526 break;
527 case DESC_HDR_SEL0_RNG:
528 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
5fa7fa14
LC		 529 in_be32(priv->reg_rngu + TALITOS_ISR),
530 in_be32(priv->reg_rngu + TALITOS_ISR_LO));
9c4a7965
KP		 531 break;
532 case DESC_HDR_SEL0_PKEU:
533 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
5fa7fa14
LC		 534 in_be32(priv->reg_pkeu + TALITOS_EUISR),
535 in_be32(priv->reg_pkeu + TALITOS_EUISR_LO));
9c4a7965
KP		 536 break;
537 case DESC_HDR_SEL0_AESU:
538 dev_err(dev, "AESUISR 0x%08x_%08x\n",
5fa7fa14
LC		 539 in_be32(priv->reg_aesu + TALITOS_EUISR),
540 in_be32(priv->reg_aesu + TALITOS_EUISR_LO));
9c4a7965
KP		 541 break;
542 case DESC_HDR_SEL0_CRCU:
543 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
5fa7fa14
LC		 544 in_be32(priv->reg_crcu + TALITOS_EUISR),
545 in_be32(priv->reg_crcu + TALITOS_EUISR_LO));
9c4a7965
KP		 546 break;
547 case DESC_HDR_SEL0_KEU:
548 dev_err(dev, "KEUISR 0x%08x_%08x\n",
5fa7fa14
LC		 549 in_be32(priv->reg_pkeu + TALITOS_EUISR),
550 in_be32(priv->reg_pkeu + TALITOS_EUISR_LO));
9c4a7965
KP		 551 break;
552 }
553
3e721aeb 554 switch (desc_hdr & DESC_HDR_SEL1_MASK) {
9c4a7965
KP		 555 case DESC_HDR_SEL1_MDEUA:
556 case DESC_HDR_SEL1_MDEUB:
557 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
5fa7fa14
LC		 558 in_be32(priv->reg_mdeu + TALITOS_EUISR),
559 in_be32(priv->reg_mdeu + TALITOS_EUISR_LO));
9c4a7965
KP		 560 break;
561 case DESC_HDR_SEL1_CRCU:
562 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
5fa7fa14
LC		 563 in_be32(priv->reg_crcu + TALITOS_EUISR),
564 in_be32(priv->reg_crcu + TALITOS_EUISR_LO));
9c4a7965
KP		 565 break;
566 }
567
568 for (i = 0; i < 8; i++)
569 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
ad42d5fc
KP		 570 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
571 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
9c4a7965
KP		 572}
573
574/*
575 * recover from error interrupts
576 */
5e718a09 577static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
9c4a7965 578{
9c4a7965
KP		 579 struct talitos_private *priv = dev_get_drvdata(dev);
580 unsigned int timeout = TALITOS_TIMEOUT;
dd3c0987 581 int ch, error, reset_dev = 0;
42e8b0d7 582 u32 v_lo;
dd3c0987
LC		 583 bool is_sec1 = has_ftr_sec1(priv);
584 int reset_ch = is_sec1 ? 1 : 0; /* only SEC2 supports continuation */
9c4a7965
KP		 585
586 for (ch = 0; ch < priv->num_channels; ch++) {
587 /* skip channels without errors */
dd3c0987
LC		 588 if (is_sec1) {
589 /* bits 29, 31, 17, 19 */
590 if (!(isr & (1 << (29 + (ch & 1) * 2 - (ch & 2) * 6))))
591 continue;
592 } else {
593 if (!(isr & (1 << (ch * 2 + 1))))
594 continue;
595 }
9c4a7965
KP		 596
597 error = -EINVAL;
598
ad42d5fc 599 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
9c4a7965
KP		 600
601 if (v_lo & TALITOS_CCPSR_LO_DOF) {
602 dev_err(dev, "double fetch fifo overflow error\n");
603 error = -EAGAIN;
604 reset_ch = 1;
605 }
606 if (v_lo & TALITOS_CCPSR_LO_SOF) {
607 /* h/w dropped descriptor */
608 dev_err(dev, "single fetch fifo overflow error\n");
609 error = -EAGAIN;
610 }
611 if (v_lo & TALITOS_CCPSR_LO_MDTE)
612 dev_err(dev, "master data transfer error\n");
613 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
4d9b3a5b 614 dev_err(dev, is_sec1 ? "pointer not complete error\n"
dd3c0987 615 : "s/g data length zero error\n");
9c4a7965 616 if (v_lo & TALITOS_CCPSR_LO_FPZ)
dd3c0987
LC		 617 dev_err(dev, is_sec1 ? "parity error\n"
618 : "fetch pointer zero error\n");
9c4a7965
KP		 619 if (v_lo & TALITOS_CCPSR_LO_IDH)
620 dev_err(dev, "illegal descriptor header error\n");
621 if (v_lo & TALITOS_CCPSR_LO_IEU)
dd3c0987
LC		 622 dev_err(dev, is_sec1 ? "static assignment error\n"
623 : "invalid exec unit error\n");
9c4a7965 624 if (v_lo & TALITOS_CCPSR_LO_EU)
3e721aeb 625 report_eu_error(dev, ch, current_desc_hdr(dev, ch));
dd3c0987
LC		 626 if (!is_sec1) {
627 if (v_lo & TALITOS_CCPSR_LO_GB)
628 dev_err(dev, "gather boundary error\n");
629 if (v_lo & TALITOS_CCPSR_LO_GRL)
630 dev_err(dev, "gather return/length error\n");
631 if (v_lo & TALITOS_CCPSR_LO_SB)
632 dev_err(dev, "scatter boundary error\n");
633 if (v_lo & TALITOS_CCPSR_LO_SRL)
634 dev_err(dev, "scatter return/length error\n");
635 }
9c4a7965
KP		 636
637 flush_channel(dev, ch, error, reset_ch);
638
639 if (reset_ch) {
640 reset_channel(dev, ch);
641 } else {
ad42d5fc 642 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
dd3c0987 643 TALITOS2_CCCR_CONT);
ad42d5fc
KP		 644 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
645 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
dd3c0987 646 TALITOS2_CCCR_CONT) && --timeout)
9c4a7965
KP		 647 cpu_relax();
648 if (timeout == 0) {
649 dev_err(dev, "failed to restart channel %d\n",
650 ch);
651 reset_dev = 1;
652 }
653 }
654 }
dd3c0987
LC		 655 if (reset_dev || (is_sec1 && isr & ~TALITOS1_ISR_4CHERR) ||
656 (!is_sec1 && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) {
657 if (is_sec1 && (isr_lo & TALITOS1_ISR_TEA_ERR))
658 dev_err(dev, "TEA error: ISR 0x%08x_%08x\n",
659 isr, isr_lo);
660 else
661 dev_err(dev, "done overflow, internal time out, or "
662 "rngu error: ISR 0x%08x_%08x\n", isr, isr_lo);
9c4a7965
KP		 663
664 /* purge request queues */
665 for (ch = 0; ch < priv->num_channels; ch++)
666 flush_channel(dev, ch, -EIO, 1);
667
668 /* reset and reinitialize the device */
669 init_device(dev);
670 }
671}
672
dd3c0987
LC		 673#define DEF_TALITOS1_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
674static irqreturn_t talitos1_interrupt_##name(int irq, void *data) \
675{ \
676 struct device *dev = data; \
677 struct talitos_private *priv = dev_get_drvdata(dev); \
678 u32 isr, isr_lo; \
679 unsigned long flags; \
680 \
681 spin_lock_irqsave(&priv->reg_lock, flags); \
682 isr = in_be32(priv->reg + TALITOS_ISR); \
683 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
684 /* Acknowledge interrupt */ \
685 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
686 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
687 \
688 if (unlikely(isr & ch_err_mask || isr_lo & TALITOS1_IMR_LO_INIT)) { \
689 spin_unlock_irqrestore(&priv->reg_lock, flags); \
690 talitos_error(dev, isr & ch_err_mask, isr_lo); \
691 } \
692 else { \
693 if (likely(isr & ch_done_mask)) { \
694 /* mask further done interrupts. */ \
695 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
696 /* done_task will unmask done interrupts at exit */ \
697 tasklet_schedule(&priv->done_task[tlet]); \
698 } \
699 spin_unlock_irqrestore(&priv->reg_lock, flags); \
700 } \
701 \
702 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
703 IRQ_NONE; \
704}
705
706DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)
707
708#define DEF_TALITOS2_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
709static irqreturn_t talitos2_interrupt_##name(int irq, void *data) \
c3e337f8
KP		 710{ \
711 struct device *dev = data; \
712 struct talitos_private *priv = dev_get_drvdata(dev); \
713 u32 isr, isr_lo; \
511d63cb 714 unsigned long flags; \
c3e337f8 715 \
511d63cb 716 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 717 isr = in_be32(priv->reg + TALITOS_ISR); \
718 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
719 /* Acknowledge interrupt */ \
720 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
721 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
722 \
511d63cb
HG		 723 if (unlikely(isr & ch_err_mask || isr_lo)) { \
724 spin_unlock_irqrestore(&priv->reg_lock, flags); \
725 talitos_error(dev, isr & ch_err_mask, isr_lo); \
726 } \
727 else { \
c3e337f8
KP		 728 if (likely(isr & ch_done_mask)) { \
729 /* mask further done interrupts. */ \
730 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
731 /* done_task will unmask done interrupts at exit */ \
732 tasklet_schedule(&priv->done_task[tlet]); \
733 } \
511d63cb
HG		 734 spin_unlock_irqrestore(&priv->reg_lock, flags); \
735 } \
c3e337f8
KP		 736 \
737 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
738 IRQ_NONE; \
9c4a7965 739}
dd3c0987
LC		 740
741DEF_TALITOS2_INTERRUPT(4ch, TALITOS2_ISR_4CHDONE, TALITOS2_ISR_4CHERR, 0)
742DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
743 0)
744DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
745 1)
9c4a7965
KP		 746
747/*
748 * hwrng
749 */
750static int talitos_rng_data_present(struct hwrng *rng, int wait)
751{
752 struct device *dev = (struct device *)rng->priv;
753 struct talitos_private *priv = dev_get_drvdata(dev);
754 u32 ofl;
755 int i;
756
757 for (i = 0; i < 20; i++) {
5fa7fa14 758 ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
9c4a7965
KP		 759 TALITOS_RNGUSR_LO_OFL;
760 if (ofl || !wait)
761 break;
762 udelay(10);
763 }
764
765 return !!ofl;
766}
767
768static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
769{
770 struct device *dev = (struct device *)rng->priv;
771 struct talitos_private *priv = dev_get_drvdata(dev);
772
773 /* rng fifo requires 64-bit accesses */
5fa7fa14
LC		 774 *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
775 *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
9c4a7965
KP		 776
777 return sizeof(u32);
778}
779
780static int talitos_rng_init(struct hwrng *rng)
781{
782 struct device *dev = (struct device *)rng->priv;
783 struct talitos_private *priv = dev_get_drvdata(dev);
784 unsigned int timeout = TALITOS_TIMEOUT;
785
5fa7fa14
LC		 786 setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
787 while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
788 & TALITOS_RNGUSR_LO_RD)
9c4a7965
KP		 789 && --timeout)
790 cpu_relax();
791 if (timeout == 0) {
792 dev_err(dev, "failed to reset rng hw\n");
793 return -ENODEV;
794 }
795
796 /* start generating */
5fa7fa14 797 setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
9c4a7965
KP		 798
799 return 0;
800}
801
802static int talitos_register_rng(struct device *dev)
803{
804 struct talitos_private *priv = dev_get_drvdata(dev);
35a3bb3d 805 int err;
9c4a7965
KP		 806
807 priv->rng.name = dev_driver_string(dev),
808 priv->rng.init = talitos_rng_init,
809 priv->rng.data_present = talitos_rng_data_present,
810 priv->rng.data_read = talitos_rng_data_read,
811 priv->rng.priv = (unsigned long)dev;
812
35a3bb3d
AS		 813 err = hwrng_register(&priv->rng);
814 if (!err)
815 priv->rng_registered = true;
816
817 return err;
9c4a7965
KP		 818}
819
820static void talitos_unregister_rng(struct device *dev)
821{
822 struct talitos_private *priv = dev_get_drvdata(dev);
823
35a3bb3d
AS		 824 if (!priv->rng_registered)
825 return;
826
9c4a7965 827 hwrng_unregister(&priv->rng);
35a3bb3d 828 priv->rng_registered = false;
9c4a7965
KP		 829}
830
831/*
832 * crypto alg
833 */
834#define TALITOS_CRA_PRIORITY 3000
7405c8d7
LC		 835/*
836 * Defines a priority for doing AEAD with descriptors type
837 * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
838 */
839#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
03d2c511 840#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
3952f17e 841#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 842
9c4a7965
KP		 843struct talitos_ctx {
844 struct device *dev;
5228f0f7 845 int ch;
9c4a7965
KP		 846 __be32 desc_hdr_template;
847 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 848 u8 iv[TALITOS_MAX_IV_LENGTH];
2e13ce08 849 dma_addr_t dma_key;
9c4a7965
KP		 850 unsigned int keylen;
851 unsigned int enckeylen;
852 unsigned int authkeylen;
9c4a7965
KP		 853};
854
497f2e6b
LN		 855#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
856#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
857
858struct talitos_ahash_req_ctx {
60f208d7 859 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
497f2e6b 860 unsigned int hw_context_size;
3c0dd190
LC		 861 u8 buf[2][HASH_MAX_BLOCK_SIZE];
862 int buf_idx;
60f208d7 863 unsigned int swinit;
497f2e6b
LN		 864 unsigned int first;
865 unsigned int last;
866 unsigned int to_hash_later;
42e8b0d7 867 unsigned int nbuf;
497f2e6b
LN		 868 struct scatterlist bufsl[2];
869 struct scatterlist *psrc;
870};
871
3639ca84
HG		 872struct talitos_export_state {
873 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
874 u8 buf[HASH_MAX_BLOCK_SIZE];
875 unsigned int swinit;
876 unsigned int first;
877 unsigned int last;
878 unsigned int to_hash_later;
879 unsigned int nbuf;
880};
881
56af8cd4
LN		 882static int aead_setkey(struct crypto_aead *authenc,
883 const u8 *key, unsigned int keylen)
9c4a7965
KP		 884{
885 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
2e13ce08 886 struct device *dev = ctx->dev;
c306a98d 887 struct crypto_authenc_keys keys;
9c4a7965 888
c306a98d 889 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
9c4a7965
KP		 890 goto badkey;
891
c306a98d 892 if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
9c4a7965
KP		 893 goto badkey;
894
2e13ce08
LC		 895 if (ctx->keylen)
896 dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
897
c306a98d
MK		 898 memcpy(ctx->key, keys.authkey, keys.authkeylen);
899 memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
9c4a7965 900
c306a98d
MK		 901 ctx->keylen = keys.authkeylen + keys.enckeylen;
902 ctx->enckeylen = keys.enckeylen;
903 ctx->authkeylen = keys.authkeylen;
2e13ce08
LC		 904 ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
905 DMA_TO_DEVICE);
9c4a7965 906
8f0691fc 907 memzero_explicit(&keys, sizeof(keys));
9c4a7965
KP		 908 return 0;
909
910badkey:
911 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
8f0691fc 912 memzero_explicit(&keys, sizeof(keys));
9c4a7965
KP		 913 return -EINVAL;
914}
915
916/*
56af8cd4 917 * talitos_edesc - s/w-extended descriptor
9c4a7965
KP		 918 * @src_nents: number of segments in input scatterlist
919 * @dst_nents: number of segments in output scatterlist
aeb4c132 920 * @icv_ool: whether ICV is out-of-line
79fd31d3 921 * @iv_dma: dma address of iv for checking continuity and link table
9c4a7965 922 * @dma_len: length of dma mapped link_tbl space
6f65f6ac 923 * @dma_link_tbl: bus physical address of link_tbl/buf
9c4a7965 924 * @desc: h/w descriptor
6f65f6ac
LC		 925 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
926 * @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
9c4a7965
KP		 927 *
928 * if decrypting (with authcheck), or either one of src_nents or dst_nents
929 * is greater than 1, an integrity check value is concatenated to the end
930 * of link_tbl data
931 */
56af8cd4 932struct talitos_edesc {
9c4a7965
KP		 933 int src_nents;
934 int dst_nents;
aeb4c132 935 bool icv_ool;
79fd31d3 936 dma_addr_t iv_dma;
9c4a7965
KP		 937 int dma_len;
938 dma_addr_t dma_link_tbl;
939 struct talitos_desc desc;
6f65f6ac
LC		 940 union {
941 struct talitos_ptr link_tbl[0];
942 u8 buf[0];
943 };
9c4a7965
KP		 944};
945
4de9d0b5
LN		 946static void talitos_sg_unmap(struct device *dev,
947 struct talitos_edesc *edesc,
948 struct scatterlist *src,
6a1e8d14
LC		 949 struct scatterlist *dst,
950 unsigned int len, unsigned int offset)
4de9d0b5 951{
6a1e8d14
LC		 952 struct talitos_private *priv = dev_get_drvdata(dev);
953 bool is_sec1 = has_ftr_sec1(priv);
4de9d0b5
LN		 954 unsigned int src_nents = edesc->src_nents ? : 1;
955 unsigned int dst_nents = edesc->dst_nents ? : 1;
956
6a1e8d14
LC		 957 if (is_sec1 && dst && dst_nents > 1) {
958 dma_sync_single_for_device(dev, edesc->dma_link_tbl + offset,
959 len, DMA_FROM_DEVICE);
960 sg_pcopy_from_buffer(dst, dst_nents, edesc->buf + offset, len,
961 offset);
962 }
4de9d0b5 963 if (src != dst) {
6a1e8d14
LC		 964 if (src_nents == 1 || !is_sec1)
965 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
4de9d0b5 966
6a1e8d14 967 if (dst && (dst_nents == 1 || !is_sec1))
b8a011d4 968 dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
6a1e8d14 969 } else if (src_nents == 1 || !is_sec1) {
b8a011d4 970 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
246a87cd
LC		 971 }
972}
973
9c4a7965 974static void ipsec_esp_unmap(struct device *dev,
56af8cd4 975 struct talitos_edesc *edesc,
9c4a7965
KP		 976 struct aead_request *areq)
977{
549bd8bc
LC		 978 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
979 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
980 unsigned int ivsize = crypto_aead_ivsize(aead);
9a655608
LC		 981 bool is_ipsec_esp = edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP;
982 struct talitos_ptr *civ_ptr = &edesc->desc.ptr[is_ipsec_esp ? 2 : 3];
549bd8bc 983
9a655608 984 if (is_ipsec_esp)
549bd8bc
LC		 985 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6],
986 DMA_FROM_DEVICE);
9a655608 987 unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE);
9c4a7965 988
6a1e8d14
LC		 989 talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen,
990 areq->assoclen);
9c4a7965
KP		 991
992 if (edesc->dma_len)
993 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
994 DMA_BIDIRECTIONAL);
549bd8bc 995
9a655608 996 if (!is_ipsec_esp) {
549bd8bc
LC		 997 unsigned int dst_nents = edesc->dst_nents ? : 1;
998
999 sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize,
1000 areq->assoclen + areq->cryptlen - ivsize);
1001 }
9c4a7965
KP		 1002}
1003
1004/*
1005 * ipsec_esp descriptor callbacks
1006 */
1007static void ipsec_esp_encrypt_done(struct device *dev,
1008 struct talitos_desc *desc, void *context,
1009 int err)
1010{
549bd8bc
LC		 1011 struct talitos_private *priv = dev_get_drvdata(dev);
1012 bool is_sec1 = has_ftr_sec1(priv);
9c4a7965 1013 struct aead_request *areq = context;
9c4a7965 1014 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
aeb4c132 1015 unsigned int authsize = crypto_aead_authsize(authenc);
2e13ce08 1016 unsigned int ivsize = crypto_aead_ivsize(authenc);
19bbbc63 1017 struct talitos_edesc *edesc;
9c4a7965
KP		 1018 struct scatterlist *sg;
1019 void *icvdata;
1020
19bbbc63
KP		 1021 edesc = container_of(desc, struct talitos_edesc, desc);
1022
9c4a7965
KP		 1023 ipsec_esp_unmap(dev, edesc, areq);
1024
1025 /* copy the generated ICV to dst */
aeb4c132 1026 if (edesc->icv_ool) {
549bd8bc
LC		 1027 if (is_sec1)
1028 icvdata = edesc->buf + areq->assoclen + areq->cryptlen;
1029 else
1030 icvdata = &edesc->link_tbl[edesc->src_nents +
1031 edesc->dst_nents + 2];
9c4a7965 1032 sg = sg_last(areq->dst, edesc->dst_nents);
aeb4c132
HX		 1033 memcpy((char *)sg_virt(sg) + sg->length - authsize,
1034 icvdata, authsize);
9c4a7965
KP		 1035 }
1036
2e13ce08
LC		 1037 dma_unmap_single(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
1038
9c4a7965
KP		 1039 kfree(edesc);
1040
1041 aead_request_complete(areq, err);
1042}
1043
fe5720e2 1044static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 1045 struct talitos_desc *desc,
1046 void *context, int err)
9c4a7965
KP		 1047{
1048 struct aead_request *req = context;
9c4a7965 1049 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
aeb4c132 1050 unsigned int authsize = crypto_aead_authsize(authenc);
19bbbc63 1051 struct talitos_edesc *edesc;
9c4a7965 1052 struct scatterlist *sg;
aeb4c132 1053 char *oicv, *icv;
549bd8bc
LC		 1054 struct talitos_private *priv = dev_get_drvdata(dev);
1055 bool is_sec1 = has_ftr_sec1(priv);
9c4a7965 1056
19bbbc63
KP		 1057 edesc = container_of(desc, struct talitos_edesc, desc);
1058
9c4a7965
KP		 1059 ipsec_esp_unmap(dev, edesc, req);
1060
1061 if (!err) {
1062 /* auth check */
9c4a7965 1063 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
aeb4c132
HX		 1064 icv = (char *)sg_virt(sg) + sg->length - authsize;
1065
1066 if (edesc->dma_len) {
549bd8bc
LC		 1067 if (is_sec1)
1068 oicv = (char *)&edesc->dma_link_tbl +
1069 req->assoclen + req->cryptlen;
1070 else
1071 oicv = (char *)
1072 &edesc->link_tbl[edesc->src_nents +
aeb4c132
HX		 1073 edesc->dst_nents + 2];
1074 if (edesc->icv_ool)
1075 icv = oicv + authsize;
1076 } else
1077 oicv = (char *)&edesc->link_tbl[0];
1078
79960943 1079 err = crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0;
9c4a7965
KP		 1080 }
1081
1082 kfree(edesc);
1083
1084 aead_request_complete(req, err);
1085}
1086
fe5720e2 1087static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 1088 struct talitos_desc *desc,
1089 void *context, int err)
fe5720e2
KP		 1090{
1091 struct aead_request *req = context;
19bbbc63
KP		 1092 struct talitos_edesc *edesc;
1093
1094 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 1095
1096 ipsec_esp_unmap(dev, edesc, req);
1097
1098 /* check ICV auth status */
e938e465
KP		 1099 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
1100 DESC_HDR_LO_ICCR1_PASS))
1101 err = -EBADMSG;
fe5720e2
KP		 1102
1103 kfree(edesc);
1104
1105 aead_request_complete(req, err);
1106}
1107
9c4a7965
KP		 1108/*
1109 * convert scatterlist to SEC h/w link table format
1110 * stop at cryptlen bytes
1111 */
aeb4c132
HX		 1112static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
1113 unsigned int offset, int cryptlen,
1114 struct talitos_ptr *link_tbl_ptr)
9c4a7965 1115{
70bcaca7 1116 int n_sg = sg_count;
aeb4c132 1117 int count = 0;
70bcaca7 1118
aeb4c132
HX		 1119 while (cryptlen && sg && n_sg--) {
1120 unsigned int len = sg_dma_len(sg);
9c4a7965 1121
aeb4c132
HX		 1122 if (offset >= len) {
1123 offset -= len;
1124 goto next;
1125 }
1126
1127 len -= offset;
1128
1129 if (len > cryptlen)
1130 len = cryptlen;
1131
1132 to_talitos_ptr(link_tbl_ptr + count,
da9de146 1133 sg_dma_address(sg) + offset, len, 0);
b096b544 1134 to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0);
aeb4c132
HX		 1135 count++;
1136 cryptlen -= len;
1137 offset = 0;
1138
1139next:
1140 sg = sg_next(sg);
70bcaca7 1141 }
9c4a7965
KP		 1142
1143 /* tag end of link table */
aeb4c132 1144 if (count > 0)
b096b544
LC		 1145 to_talitos_ptr_ext_set(link_tbl_ptr + count - 1,
1146 DESC_PTR_LNKTBL_RETURN, 0);
70bcaca7 1147
aeb4c132
HX		 1148 return count;
1149}
1150
2b122730
LC		 1151static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
1152 unsigned int len, struct talitos_edesc *edesc,
1153 struct talitos_ptr *ptr, int sg_count,
1154 unsigned int offset, int tbl_off, int elen)
246a87cd 1155{
246a87cd
LC		 1156 struct talitos_private *priv = dev_get_drvdata(dev);
1157 bool is_sec1 = has_ftr_sec1(priv);
1158
87a81dce
LC		 1159 if (!src) {
1160 to_talitos_ptr(ptr, 0, 0, is_sec1);
1161 return 1;
1162 }
2b122730 1163 to_talitos_ptr_ext_set(ptr, elen, is_sec1);
6a1e8d14 1164 if (sg_count == 1) {
da9de146 1165 to_talitos_ptr(ptr, sg_dma_address(src) + offset, len, is_sec1);
6a1e8d14 1166 return sg_count;
246a87cd 1167 }
246a87cd 1168 if (is_sec1) {
da9de146 1169 to_talitos_ptr(ptr, edesc->dma_link_tbl + offset, len, is_sec1);
6a1e8d14 1170 return sg_count;
246a87cd 1171 }
2b122730 1172 sg_count = sg_to_link_tbl_offset(src, sg_count, offset, len + elen,
6a1e8d14
LC		 1173 &edesc->link_tbl[tbl_off]);
1174 if (sg_count == 1) {
1175 /* Only one segment now, so no link tbl needed*/
1176 copy_talitos_ptr(ptr, &edesc->link_tbl[tbl_off], is_sec1);
1177 return sg_count;
1178 }
1179 to_talitos_ptr(ptr, edesc->dma_link_tbl +
da9de146 1180 tbl_off * sizeof(struct talitos_ptr), len, is_sec1);
6a1e8d14
LC		 1181 to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP, is_sec1);
1182
1183 return sg_count;
246a87cd
LC		 1184}
1185
2b122730
LC		 1186static int talitos_sg_map(struct device *dev, struct scatterlist *src,
1187 unsigned int len, struct talitos_edesc *edesc,
1188 struct talitos_ptr *ptr, int sg_count,
1189 unsigned int offset, int tbl_off)
1190{
1191 return talitos_sg_map_ext(dev, src, len, edesc, ptr, sg_count, offset,
1192 tbl_off, 0);
1193}
1194
9c4a7965
KP		 1195/*
1196 * fill in and submit ipsec_esp descriptor
1197 */
56af8cd4 1198static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
aeb4c132
HX		 1199 void (*callback)(struct device *dev,
1200 struct talitos_desc *desc,
1201 void *context, int error))
9c4a7965
KP		 1202{
1203 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
aeb4c132 1204 unsigned int authsize = crypto_aead_authsize(aead);
9c4a7965
KP		 1205 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
1206 struct device *dev = ctx->dev;
1207 struct talitos_desc *desc = &edesc->desc;
1208 unsigned int cryptlen = areq->cryptlen;
e41256f1 1209 unsigned int ivsize = crypto_aead_ivsize(aead);
aeb4c132 1210 int tbl_off = 0;
fa86a267 1211 int sg_count, ret;
2b122730 1212 int elen = 0;
549bd8bc
LC		 1213 bool sync_needed = false;
1214 struct talitos_private *priv = dev_get_drvdata(dev);
1215 bool is_sec1 = has_ftr_sec1(priv);
9a655608
LC		 1216 bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
1217 struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
1218 struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
9c4a7965
KP		 1219
1220 /* hmac key */
2e13ce08 1221 to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1);
79fd31d3 1222
549bd8bc
LC		 1223 sg_count = edesc->src_nents ?: 1;
1224 if (is_sec1 && sg_count > 1)
1225 sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
1226 areq->assoclen + cryptlen);
1227 else
1228 sg_count = dma_map_sg(dev, areq->src, sg_count,
1229 (areq->src == areq->dst) ?
1230 DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
79fd31d3 1231
549bd8bc
LC		 1232 /* hmac data */
1233 ret = talitos_sg_map(dev, areq->src, areq->assoclen, edesc,
1234 &desc->ptr[1], sg_count, 0, tbl_off);
340ff60a 1235
549bd8bc 1236 if (ret > 1) {
340ff60a 1237 tbl_off += ret;
549bd8bc 1238 sync_needed = true;
79fd31d3
HG		 1239 }
1240
9c4a7965 1241 /* cipher iv */
9a655608 1242 to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1);
9c4a7965
KP		 1243
1244 /* cipher key */
2e13ce08
LC		 1245 to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
1246 ctx->enckeylen, is_sec1);
9c4a7965
KP		 1247
1248 /*
1249 * cipher in
1250 * map and adjust cipher len to aead request cryptlen.
1251 * extent is bytes of HMAC postpended to ciphertext,
1252 * typically 12 for ipsec
1253 */
2b122730
LC		 1254 if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
1255 elen = authsize;
9c4a7965 1256
2b122730
LC		 1257 ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
1258 sg_count, areq->assoclen, tbl_off, elen);
549bd8bc 1259
ec8c7d14
LC		 1260 if (ret > 1) {
1261 tbl_off += ret;
549bd8bc
LC		 1262 sync_needed = true;
1263 }
9c4a7965 1264
549bd8bc
LC		 1265 /* cipher out */
1266 if (areq->src != areq->dst) {
1267 sg_count = edesc->dst_nents ? : 1;
1268 if (!is_sec1 || sg_count == 1)
1269 dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
1270 }
9c4a7965 1271
e04a61be
LC		 1272 ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[5],
1273 sg_count, areq->assoclen, tbl_off);
aeb4c132 1274
9a655608 1275 if (is_ipsec_esp)
549bd8bc 1276 to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1);
aeb4c132 1277
e04a61be
LC		 1278 /* ICV data */
1279 if (ret > 1) {
1280 tbl_off += ret;
aeb4c132 1281 edesc->icv_ool = true;
549bd8bc
LC		 1282 sync_needed = true;
1283
9a655608 1284 if (is_ipsec_esp) {
549bd8bc
LC		 1285 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1286 int offset = (edesc->src_nents + edesc->dst_nents + 2) *
1287 sizeof(struct talitos_ptr) + authsize;
1288
1289 /* Add an entry to the link table for ICV data */
e04a61be 1290 to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1);
549bd8bc
LC		 1291 to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RETURN,
1292 is_sec1);
549bd8bc
LC		 1293
1294 /* icv data follows link tables */
1295 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl + offset,
da9de146 1296 authsize, is_sec1);
e04a61be
LC		 1297 } else {
1298 dma_addr_t addr = edesc->dma_link_tbl;
1299
1300 if (is_sec1)
1301 addr += areq->assoclen + cryptlen;
1302 else
1303 addr += sizeof(struct talitos_ptr) * tbl_off;
1304
da9de146 1305 to_talitos_ptr(&desc->ptr[6], addr, authsize, is_sec1);
e04a61be 1306 }
9a655608 1307 } else if (!is_ipsec_esp) {
e04a61be
LC		 1308 ret = talitos_sg_map(dev, areq->dst, authsize, edesc,
1309 &desc->ptr[6], sg_count, areq->assoclen +
1310 cryptlen,
1311 tbl_off);
1312 if (ret > 1) {
1313 tbl_off += ret;
1314 edesc->icv_ool = true;
1315 sync_needed = true;
1316 } else {
1317 edesc->icv_ool = false;
549bd8bc 1318 }
340ff60a 1319 } else {
549bd8bc
LC		 1320 edesc->icv_ool = false;
1321 }
1322
9c4a7965 1323 /* iv out */
9a655608 1324 if (is_ipsec_esp)
549bd8bc
LC		 1325 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
1326 DMA_FROM_DEVICE);
1327
1328 if (sync_needed)
1329 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1330 edesc->dma_len,
1331 DMA_BIDIRECTIONAL);
9c4a7965 1332
5228f0f7 1333 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
fa86a267
KP		 1334 if (ret != -EINPROGRESS) {
1335 ipsec_esp_unmap(dev, edesc, areq);
1336 kfree(edesc);
1337 }
1338 return ret;
9c4a7965
KP		 1339}
1340
9c4a7965 1341/*
56af8cd4 1342 * allocate and map the extended descriptor
9c4a7965 1343 */
4de9d0b5
LN		 1344static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1345 struct scatterlist *src,
1346 struct scatterlist *dst,
79fd31d3
HG		 1347 u8 *iv,
1348 unsigned int assoclen,
4de9d0b5
LN		 1349 unsigned int cryptlen,
1350 unsigned int authsize,
79fd31d3 1351 unsigned int ivsize,
4de9d0b5 1352 int icv_stashing,
62293a37
HG		 1353 u32 cryptoflags,
1354 bool encrypt)
9c4a7965 1355{
56af8cd4 1356 struct talitos_edesc *edesc;
6a1e8d14 1357 int src_nents, dst_nents, alloc_len, dma_len, src_len, dst_len;
79fd31d3 1358 dma_addr_t iv_dma = 0;
4de9d0b5 1359 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1360 GFP_ATOMIC;
6f65f6ac
LC		 1361 struct talitos_private *priv = dev_get_drvdata(dev);
1362 bool is_sec1 = has_ftr_sec1(priv);
1363 int max_len = is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
9c4a7965 1364
6f65f6ac 1365 if (cryptlen + authsize > max_len) {
4de9d0b5 1366 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1367 return ERR_PTR(-EINVAL);
1368 }
1369
62293a37 1370 if (!dst || dst == src) {
6a1e8d14
LC		 1371 src_len = assoclen + cryptlen + authsize;
1372 src_nents = sg_nents_for_len(src, src_len);
8e409fe1
LC		 1373 if (src_nents < 0) {
1374 dev_err(dev, "Invalid number of src SG.\n");
c56c2e17 1375 return ERR_PTR(-EINVAL);
8e409fe1 1376 }
62293a37
HG		 1377 src_nents = (src_nents == 1) ? 0 : src_nents;
1378 dst_nents = dst ? src_nents : 0;
6a1e8d14 1379 dst_len = 0;
62293a37 1380 } else { /* dst && dst != src*/
6a1e8d14
LC		 1381 src_len = assoclen + cryptlen + (encrypt ? 0 : authsize);
1382 src_nents = sg_nents_for_len(src, src_len);
8e409fe1
LC		 1383 if (src_nents < 0) {
1384 dev_err(dev, "Invalid number of src SG.\n");
c56c2e17 1385 return ERR_PTR(-EINVAL);
8e409fe1 1386 }
62293a37 1387 src_nents = (src_nents == 1) ? 0 : src_nents;
6a1e8d14
LC		 1388 dst_len = assoclen + cryptlen + (encrypt ? authsize : 0);
1389 dst_nents = sg_nents_for_len(dst, dst_len);
8e409fe1
LC		 1390 if (dst_nents < 0) {
1391 dev_err(dev, "Invalid number of dst SG.\n");
c56c2e17 1392 return ERR_PTR(-EINVAL);
8e409fe1 1393 }
62293a37 1394 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
9c4a7965
KP		 1395 }
1396
1397 /*
1398 * allocate space for base edesc plus the link tables,
aeb4c132
HX		 1399 * allowing for two separate entries for AD and generated ICV (+ 2),
1400 * and space for two sets of ICVs (stashed and generated)
9c4a7965 1401 */
56af8cd4 1402 alloc_len = sizeof(struct talitos_edesc);
aeb4c132 1403 if (src_nents || dst_nents) {
6f65f6ac 1404 if (is_sec1)
6a1e8d14
LC		 1405 dma_len = (src_nents ? src_len : 0) +
1406 (dst_nents ? dst_len : 0);
6f65f6ac 1407 else
aeb4c132
HX		 1408 dma_len = (src_nents + dst_nents + 2) *
1409 sizeof(struct talitos_ptr) + authsize * 2;
9c4a7965
KP		 1410 alloc_len += dma_len;
1411 } else {
1412 dma_len = 0;
4de9d0b5 1413 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1414 }
1415
37b5e889
LC		 1416 /* if its a ahash, add space for a second desc next to the first one */
1417 if (is_sec1 && !dst)
1418 alloc_len += sizeof(struct talitos_desc);
1bea445b 1419 alloc_len += ivsize;
37b5e889 1420
586725f8 1421 edesc = kmalloc(alloc_len, GFP_DMA | flags);
c56c2e17
CL		 1422 if (!edesc)
1423 return ERR_PTR(-ENOMEM);
1bea445b
CL		 1424 if (ivsize) {
1425 iv = memcpy(((u8 *)edesc) + alloc_len - ivsize, iv, ivsize);
c56c2e17 1426 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1bea445b 1427 }
e4a647c4 1428 memset(&edesc->desc, 0, sizeof(edesc->desc));
9c4a7965
KP		 1429
1430 edesc->src_nents = src_nents;
1431 edesc->dst_nents = dst_nents;
79fd31d3 1432 edesc->iv_dma = iv_dma;
9c4a7965 1433 edesc->dma_len = dma_len;
37b5e889
LC		 1434 if (dma_len) {
1435 void *addr = &edesc->link_tbl[0];
1436
1437 if (is_sec1 && !dst)
1438 addr += sizeof(struct talitos_desc);
1439 edesc->dma_link_tbl = dma_map_single(dev, addr,
497f2e6b
LN		 1440 edesc->dma_len,
1441 DMA_BIDIRECTIONAL);
37b5e889 1442 }
9c4a7965
KP		 1443 return edesc;
1444}
1445
79fd31d3 1446static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
62293a37 1447 int icv_stashing, bool encrypt)
4de9d0b5
LN		 1448{
1449 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
aeb4c132 1450 unsigned int authsize = crypto_aead_authsize(authenc);
4de9d0b5 1451 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
79fd31d3 1452 unsigned int ivsize = crypto_aead_ivsize(authenc);
4de9d0b5 1453
aeb4c132 1454 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
79fd31d3 1455 iv, areq->assoclen, areq->cryptlen,
aeb4c132 1456 authsize, ivsize, icv_stashing,
62293a37 1457 areq->base.flags, encrypt);
4de9d0b5
LN		 1458}
1459
56af8cd4 1460static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1461{
1462 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1463 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1464 struct talitos_edesc *edesc;
9c4a7965
KP		 1465
1466 /* allocate extended descriptor */
62293a37 1467 edesc = aead_edesc_alloc(req, req->iv, 0, true);
9c4a7965
KP		 1468 if (IS_ERR(edesc))
1469 return PTR_ERR(edesc);
1470
1471 /* set encrypt */
70bcaca7 1472 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965 1473
aeb4c132 1474 return ipsec_esp(edesc, req, ipsec_esp_encrypt_done);
9c4a7965
KP		 1475}
1476
56af8cd4 1477static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1478{
1479 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
aeb4c132 1480 unsigned int authsize = crypto_aead_authsize(authenc);
9c4a7965 1481 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
fe5720e2 1482 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1483 struct talitos_edesc *edesc;
9c4a7965
KP		 1484 struct scatterlist *sg;
1485 void *icvdata;
1486
1487 req->cryptlen -= authsize;
1488
1489 /* allocate extended descriptor */
62293a37 1490 edesc = aead_edesc_alloc(req, req->iv, 1, false);
9c4a7965
KP		 1491 if (IS_ERR(edesc))
1492 return PTR_ERR(edesc);
1493
fe5720e2 1494 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1495 ((!edesc->src_nents && !edesc->dst_nents) ||
1496 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1497
fe5720e2 1498 /* decrypt and check the ICV */
e938e465
KP		 1499 edesc->desc.hdr = ctx->desc_hdr_template |
1500 DESC_HDR_DIR_INBOUND |
fe5720e2 1501 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1502
fe5720e2 1503 /* reset integrity check result bits */
9c4a7965 1504
aeb4c132 1505 return ipsec_esp(edesc, req, ipsec_esp_decrypt_hwauth_done);
e938e465 1506 }
fe5720e2 1507
e938e465
KP		 1508 /* Have to check the ICV with software */
1509 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1510
e938e465
KP		 1511 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1512 if (edesc->dma_len)
aeb4c132
HX		 1513 icvdata = (char *)&edesc->link_tbl[edesc->src_nents +
1514 edesc->dst_nents + 2];
e938e465
KP		 1515 else
1516 icvdata = &edesc->link_tbl[0];
fe5720e2 1517
e938e465 1518 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1519
aeb4c132 1520 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - authsize, authsize);
9c4a7965 1521
aeb4c132 1522 return ipsec_esp(edesc, req, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1523}
1524
4de9d0b5
LN		 1525static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1526 const u8 *key, unsigned int keylen)
1527{
1528 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
2e13ce08 1529 struct device *dev = ctx->dev;
f384cdc4 1530 u32 tmp[DES_EXPKEY_WORDS];
4de9d0b5 1531
03d2c511
MH		 1532 if (keylen > TALITOS_MAX_KEY_SIZE) {
1533 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1534 return -EINVAL;
1535 }
1536
f384cdc4 1537 if (unlikely(crypto_ablkcipher_get_flags(cipher) &
231baecd 1538 CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) &&
f384cdc4
LC		 1539 !des_ekey(tmp, key)) {
1540 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_WEAK_KEY);
1541 return -EINVAL;
1542 }
1543
2e13ce08
LC		 1544 if (ctx->keylen)
1545 dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
1546
4de9d0b5
LN		 1547 memcpy(&ctx->key, key, keylen);
1548 ctx->keylen = keylen;
1549
2e13ce08
LC		 1550 ctx->dma_key = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE);
1551
4de9d0b5 1552 return 0;
4de9d0b5
LN		 1553}
1554
1555static void common_nonsnoop_unmap(struct device *dev,
1556 struct talitos_edesc *edesc,
1557 struct ablkcipher_request *areq)
1558{
1559 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
032d197e 1560
6a1e8d14 1561 talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->nbytes, 0);
4de9d0b5
LN		 1562 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1563
4de9d0b5
LN		 1564 if (edesc->dma_len)
1565 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1566 DMA_BIDIRECTIONAL);
1567}
1568
1569static void ablkcipher_done(struct device *dev,
1570 struct talitos_desc *desc, void *context,
1571 int err)
1572{
1573 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1574 struct talitos_edesc *edesc;
1575
1576 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1577
1578 common_nonsnoop_unmap(dev, edesc, areq);
1579
1580 kfree(edesc);
1581
1582 areq->base.complete(&areq->base, err);
1583}
1584
1585static int common_nonsnoop(struct talitos_edesc *edesc,
1586 struct ablkcipher_request *areq,
4de9d0b5
LN		 1587 void (*callback) (struct device *dev,
1588 struct talitos_desc *desc,
1589 void *context, int error))
1590{
1591 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1592 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1593 struct device *dev = ctx->dev;
1594 struct talitos_desc *desc = &edesc->desc;
1595 unsigned int cryptlen = areq->nbytes;
79fd31d3 1596 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
4de9d0b5 1597 int sg_count, ret;
6a1e8d14 1598 bool sync_needed = false;
922f9dc8
LC		 1599 struct talitos_private *priv = dev_get_drvdata(dev);
1600 bool is_sec1 = has_ftr_sec1(priv);
4de9d0b5
LN		 1601
1602 /* first DWORD empty */
4de9d0b5
LN		 1603
1604 /* cipher iv */
da9de146 1605 to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1);
4de9d0b5
LN		 1606
1607 /* cipher key */
2e13ce08 1608 to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1);
4de9d0b5 1609
6a1e8d14
LC		 1610 sg_count = edesc->src_nents ?: 1;
1611 if (is_sec1 && sg_count > 1)
1612 sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
1613 cryptlen);
1614 else
1615 sg_count = dma_map_sg(dev, areq->src, sg_count,
1616 (areq->src == areq->dst) ?
1617 DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
4de9d0b5
LN		 1618 /*
1619 * cipher in
1620 */
6a1e8d14
LC		 1621 sg_count = talitos_sg_map(dev, areq->src, cryptlen, edesc,
1622 &desc->ptr[3], sg_count, 0, 0);
1623 if (sg_count > 1)
1624 sync_needed = true;
4de9d0b5
LN		 1625
1626 /* cipher out */
6a1e8d14
LC		 1627 if (areq->src != areq->dst) {
1628 sg_count = edesc->dst_nents ? : 1;
1629 if (!is_sec1 || sg_count == 1)
1630 dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
1631 }
1632
1633 ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4],
1634 sg_count, 0, (edesc->src_nents + 1));
1635 if (ret > 1)
1636 sync_needed = true;
4de9d0b5
LN		 1637
1638 /* iv out */
a2b35aa8 1639 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
4de9d0b5
LN		 1640 DMA_FROM_DEVICE);
1641
1642 /* last DWORD empty */
4de9d0b5 1643
6a1e8d14
LC		 1644 if (sync_needed)
1645 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1646 edesc->dma_len, DMA_BIDIRECTIONAL);
1647
5228f0f7 1648 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
4de9d0b5
LN		 1649 if (ret != -EINPROGRESS) {
1650 common_nonsnoop_unmap(dev, edesc, areq);
1651 kfree(edesc);
1652 }
1653 return ret;
1654}
1655
e938e465 1656static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
62293a37 1657 areq, bool encrypt)
4de9d0b5
LN		 1658{
1659 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1660 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
79fd31d3 1661 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
4de9d0b5 1662
aeb4c132 1663 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
79fd31d3 1664 areq->info, 0, areq->nbytes, 0, ivsize, 0,
62293a37 1665 areq->base.flags, encrypt);
4de9d0b5
LN		 1666}
1667
1668static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1669{
1670 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1671 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1672 struct talitos_edesc *edesc;
1673
1674 /* allocate extended descriptor */
62293a37 1675 edesc = ablkcipher_edesc_alloc(areq, true);
4de9d0b5
LN		 1676 if (IS_ERR(edesc))
1677 return PTR_ERR(edesc);
1678
1679 /* set encrypt */
1680 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1681
febec542 1682 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1683}
1684
1685static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1686{
1687 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1688 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1689 struct talitos_edesc *edesc;
1690
1691 /* allocate extended descriptor */
62293a37 1692 edesc = ablkcipher_edesc_alloc(areq, false);
4de9d0b5
LN		 1693 if (IS_ERR(edesc))
1694 return PTR_ERR(edesc);
1695
1696 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1697
febec542 1698 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1699}
1700
497f2e6b
LN		 1701static void common_nonsnoop_hash_unmap(struct device *dev,
1702 struct talitos_edesc *edesc,
1703 struct ahash_request *areq)
1704{
1705 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
ad4cd51f
LC		 1706 struct talitos_private *priv = dev_get_drvdata(dev);
1707 bool is_sec1 = has_ftr_sec1(priv);
1708 struct talitos_desc *desc = &edesc->desc;
1709 struct talitos_desc *desc2 = desc + 1;
1710
1711 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1712 if (desc->next_desc &&
1713 desc->ptr[5].ptr != desc2->ptr[5].ptr)
1714 unmap_single_talitos_ptr(dev, &desc2->ptr[5], DMA_FROM_DEVICE);
497f2e6b 1715
6a1e8d14 1716 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL, 0, 0);
032d197e 1717
ad4cd51f
LC		 1718 /* When using hashctx-in, must unmap it. */
1719 if (from_talitos_ptr_len(&edesc->desc.ptr[1], is_sec1))
1720 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1721 DMA_TO_DEVICE);
1722 else if (desc->next_desc)
1723 unmap_single_talitos_ptr(dev, &desc2->ptr[1],
1724 DMA_TO_DEVICE);
1725
1726 if (is_sec1 && req_ctx->nbuf)
1727 unmap_single_talitos_ptr(dev, &desc->ptr[3],
1728 DMA_TO_DEVICE);
1729
497f2e6b
LN		 1730 if (edesc->dma_len)
1731 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1732 DMA_BIDIRECTIONAL);
1733
37b5e889
LC		 1734 if (edesc->desc.next_desc)
1735 dma_unmap_single(dev, be32_to_cpu(edesc->desc.next_desc),
1736 TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
497f2e6b
LN		 1737}
1738
1739static void ahash_done(struct device *dev,
1740 struct talitos_desc *desc, void *context,
1741 int err)
1742{
1743 struct ahash_request *areq = context;
1744 struct talitos_edesc *edesc =
1745 container_of(desc, struct talitos_edesc, desc);
1746 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1747
1748 if (!req_ctx->last && req_ctx->to_hash_later) {
1749 /* Position any partial block for next update/final/finup */
3c0dd190 1750 req_ctx->buf_idx = (req_ctx->buf_idx + 1) & 1;
5e833bc4 1751 req_ctx->nbuf = req_ctx->to_hash_later;
497f2e6b
LN		 1752 }
1753 common_nonsnoop_hash_unmap(dev, edesc, areq);
1754
1755 kfree(edesc);
1756
1757 areq->base.complete(&areq->base, err);
1758}
1759
2d02905e
LC		 1760/*
1761 * SEC1 doesn't like hashing of 0 sized message, so we do the padding
1762 * ourself and submit a padded block
1763 */
5b2cf268 1764static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
2d02905e
LC		 1765 struct talitos_edesc *edesc,
1766 struct talitos_ptr *ptr)
1767{
1768 static u8 padded_hash[64] = {
1769 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1770 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1771 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1772 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1773 };
1774
1775 pr_err_once("Bug in SEC1, padding ourself\n");
1776 edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
1777 map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
1778 (char *)padded_hash, DMA_TO_DEVICE);
1779}
1780
497f2e6b
LN		 1781static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1782 struct ahash_request *areq, unsigned int length,
37b5e889 1783 unsigned int offset,
497f2e6b
LN		 1784 void (*callback) (struct device *dev,
1785 struct talitos_desc *desc,
1786 void *context, int error))
1787{
1788 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1789 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1790 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1791 struct device *dev = ctx->dev;
1792 struct talitos_desc *desc = &edesc->desc;
032d197e 1793 int ret;
6a1e8d14 1794 bool sync_needed = false;
922f9dc8
LC		 1795 struct talitos_private *priv = dev_get_drvdata(dev);
1796 bool is_sec1 = has_ftr_sec1(priv);
6a1e8d14 1797 int sg_count;
497f2e6b
LN		 1798
1799 /* first DWORD empty */
497f2e6b 1800
60f208d7
KP		 1801 /* hash context in */
1802 if (!req_ctx->first || req_ctx->swinit) {
6a4967c3
LC		 1803 map_single_talitos_ptr_nosync(dev, &desc->ptr[1],
1804 req_ctx->hw_context_size,
1805 req_ctx->hw_context,
1806 DMA_TO_DEVICE);
60f208d7 1807 req_ctx->swinit = 0;
497f2e6b 1808 }
afd62fa2
LC		 1809 /* Indicate next op is not the first. */
1810 req_ctx->first = 0;
497f2e6b
LN		 1811
1812 /* HMAC key */
1813 if (ctx->keylen)
2e13ce08
LC		 1814 to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
1815 is_sec1);
497f2e6b 1816
37b5e889
LC		 1817 if (is_sec1 && req_ctx->nbuf)
1818 length -= req_ctx->nbuf;
1819
6a1e8d14
LC		 1820 sg_count = edesc->src_nents ?: 1;
1821 if (is_sec1 && sg_count > 1)
37b5e889
LC		 1822 sg_pcopy_to_buffer(req_ctx->psrc, sg_count,
1823 edesc->buf + sizeof(struct talitos_desc),
1824 length, req_ctx->nbuf);
1825 else if (length)
6a1e8d14
LC		 1826 sg_count = dma_map_sg(dev, req_ctx->psrc, sg_count,
1827 DMA_TO_DEVICE);
497f2e6b
LN		 1828 /*
1829 * data in
1830 */
37b5e889 1831 if (is_sec1 && req_ctx->nbuf) {
ad4cd51f
LC		 1832 map_single_talitos_ptr(dev, &desc->ptr[3], req_ctx->nbuf,
1833 req_ctx->buf[req_ctx->buf_idx],
1834 DMA_TO_DEVICE);
37b5e889
LC		 1835 } else {
1836 sg_count = talitos_sg_map(dev, req_ctx->psrc, length, edesc,
1837 &desc->ptr[3], sg_count, offset, 0);
1838 if (sg_count > 1)
1839 sync_needed = true;
1840 }
497f2e6b
LN		 1841
1842 /* fifth DWORD empty */
497f2e6b
LN		 1843
1844 /* hash/HMAC out -or- hash context out */
1845 if (req_ctx->last)
1846 map_single_talitos_ptr(dev, &desc->ptr[5],
1847 crypto_ahash_digestsize(tfm),
a2b35aa8 1848 areq->result, DMA_FROM_DEVICE);
497f2e6b 1849 else
6a4967c3
LC		 1850 map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
1851 req_ctx->hw_context_size,
1852 req_ctx->hw_context,
1853 DMA_FROM_DEVICE);
497f2e6b
LN		 1854
1855 /* last DWORD empty */
497f2e6b 1856
2d02905e
LC		 1857 if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
1858 talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
1859
37b5e889
LC		 1860 if (is_sec1 && req_ctx->nbuf && length) {
1861 struct talitos_desc *desc2 = desc + 1;
1862 dma_addr_t next_desc;
1863
1864 memset(desc2, 0, sizeof(*desc2));
1865 desc2->hdr = desc->hdr;
1866 desc2->hdr &= ~DESC_HDR_MODE0_MDEU_INIT;
1867 desc2->hdr1 = desc2->hdr;
1868 desc->hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
1869 desc->hdr |= DESC_HDR_MODE0_MDEU_CONT;
1870 desc->hdr &= ~DESC_HDR_DONE_NOTIFY;
1871
ad4cd51f
LC		 1872 if (desc->ptr[1].ptr)
1873 copy_talitos_ptr(&desc2->ptr[1], &desc->ptr[1],
1874 is_sec1);
1875 else
6a4967c3
LC		 1876 map_single_talitos_ptr_nosync(dev, &desc2->ptr[1],
1877 req_ctx->hw_context_size,
1878 req_ctx->hw_context,
1879 DMA_TO_DEVICE);
37b5e889
LC		 1880 copy_talitos_ptr(&desc2->ptr[2], &desc->ptr[2], is_sec1);
1881 sg_count = talitos_sg_map(dev, req_ctx->psrc, length, edesc,
1882 &desc2->ptr[3], sg_count, offset, 0);
1883 if (sg_count > 1)
1884 sync_needed = true;
1885 copy_talitos_ptr(&desc2->ptr[5], &desc->ptr[5], is_sec1);
1886 if (req_ctx->last)
6a4967c3
LC		 1887 map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
1888 req_ctx->hw_context_size,
1889 req_ctx->hw_context,
1890 DMA_FROM_DEVICE);
37b5e889
LC		 1891
1892 next_desc = dma_map_single(dev, &desc2->hdr1, TALITOS_DESC_SIZE,
1893 DMA_BIDIRECTIONAL);
1894 desc->next_desc = cpu_to_be32(next_desc);
1895 }
1896
6a1e8d14
LC		 1897 if (sync_needed)
1898 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1899 edesc->dma_len, DMA_BIDIRECTIONAL);
1900
5228f0f7 1901 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
497f2e6b
LN		 1902 if (ret != -EINPROGRESS) {
1903 common_nonsnoop_hash_unmap(dev, edesc, areq);
1904 kfree(edesc);
1905 }
1906 return ret;
1907}
1908
1909static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1910 unsigned int nbytes)
1911{
1912 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1913 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1914 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
37b5e889
LC		 1915 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1916 bool is_sec1 = has_ftr_sec1(priv);
1917
1918 if (is_sec1)
1919 nbytes -= req_ctx->nbuf;
497f2e6b 1920
aeb4c132 1921 return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, NULL, 0,
62293a37 1922 nbytes, 0, 0, 0, areq->base.flags, false);
497f2e6b
LN		 1923}
1924
1925static int ahash_init(struct ahash_request *areq)
1926{
1927 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
6a4967c3
LC		 1928 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1929 struct device *dev = ctx->dev;
497f2e6b 1930 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
49f9783b 1931 unsigned int size;
6a4967c3 1932 dma_addr_t dma;
497f2e6b
LN		 1933
1934 /* Initialize the context */
3c0dd190 1935 req_ctx->buf_idx = 0;
5e833bc4 1936 req_ctx->nbuf = 0;
60f208d7
KP		 1937 req_ctx->first = 1; /* first indicates h/w must init its context */
1938 req_ctx->swinit = 0; /* assume h/w init of context */
49f9783b 1939 size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
497f2e6b
LN		 1940 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1941 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
49f9783b 1942 req_ctx->hw_context_size = size;
497f2e6b 1943
6a4967c3
LC		 1944 dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
1945 DMA_TO_DEVICE);
1946 dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
1947
497f2e6b
LN		 1948 return 0;
1949}
1950
60f208d7
KP		 1951/*
1952 * on h/w without explicit sha224 support, we initialize h/w context
1953 * manually with sha224 constants, and tell it to run sha256.
1954 */
1955static int ahash_init_sha224_swinit(struct ahash_request *areq)
1956{
1957 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1958
a752447a
KP		 1959 req_ctx->hw_context[0] = SHA224_H0;
1960 req_ctx->hw_context[1] = SHA224_H1;
1961 req_ctx->hw_context[2] = SHA224_H2;
1962 req_ctx->hw_context[3] = SHA224_H3;
1963 req_ctx->hw_context[4] = SHA224_H4;
1964 req_ctx->hw_context[5] = SHA224_H5;
1965 req_ctx->hw_context[6] = SHA224_H6;
1966 req_ctx->hw_context[7] = SHA224_H7;
60f208d7
KP		 1967
1968 /* init 64-bit count */
1969 req_ctx->hw_context[8] = 0;
1970 req_ctx->hw_context[9] = 0;
1971
6a4967c3
LC		 1972 ahash_init(areq);
1973 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1974
60f208d7
KP		 1975 return 0;
1976}
1977
497f2e6b
LN		 1978static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1979{
1980 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1981 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1982 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1983 struct talitos_edesc *edesc;
1984 unsigned int blocksize =
1985 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1986 unsigned int nbytes_to_hash;
1987 unsigned int to_hash_later;
5e833bc4 1988 unsigned int nsg;
8e409fe1 1989 int nents;
37b5e889
LC		 1990 struct device *dev = ctx->dev;
1991 struct talitos_private *priv = dev_get_drvdata(dev);
1992 bool is_sec1 = has_ftr_sec1(priv);
1993 int offset = 0;
3c0dd190 1994 u8 *ctx_buf = req_ctx->buf[req_ctx->buf_idx];
497f2e6b 1995
5e833bc4
LN		 1996 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1997 /* Buffer up to one whole block */
8e409fe1
LC		 1998 nents = sg_nents_for_len(areq->src, nbytes);
1999 if (nents < 0) {
2000 dev_err(ctx->dev, "Invalid number of src SG.\n");
2001 return nents;
2002 }
2003 sg_copy_to_buffer(areq->src, nents,
3c0dd190 2004 ctx_buf + req_ctx->nbuf, nbytes);
5e833bc4 2005 req_ctx->nbuf += nbytes;
497f2e6b
LN		 2006 return 0;
2007 }
2008
5e833bc4
LN		 2009 /* At least (blocksize + 1) bytes are available to hash */
2010 nbytes_to_hash = nbytes + req_ctx->nbuf;
2011 to_hash_later = nbytes_to_hash & (blocksize - 1);
2012
2013 if (req_ctx->last)
2014 to_hash_later = 0;
2015 else if (to_hash_later)
2016 /* There is a partial block. Hash the full block(s) now */
2017 nbytes_to_hash -= to_hash_later;
2018 else {
2019 /* Keep one block buffered */
2020 nbytes_to_hash -= blocksize;
2021 to_hash_later = blocksize;
2022 }
2023
2024 /* Chain in any previously buffered data */
37b5e889 2025 if (!is_sec1 && req_ctx->nbuf) {
5e833bc4
LN		 2026 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
2027 sg_init_table(req_ctx->bufsl, nsg);
3c0dd190 2028 sg_set_buf(req_ctx->bufsl, ctx_buf, req_ctx->nbuf);
5e833bc4 2029 if (nsg > 1)
c56f6d12 2030 sg_chain(req_ctx->bufsl, 2, areq->src);
497f2e6b 2031 req_ctx->psrc = req_ctx->bufsl;
37b5e889
LC		 2032 } else if (is_sec1 && req_ctx->nbuf && req_ctx->nbuf < blocksize) {
2033 if (nbytes_to_hash > blocksize)
2034 offset = blocksize - req_ctx->nbuf;
2035 else
2036 offset = nbytes_to_hash - req_ctx->nbuf;
2037 nents = sg_nents_for_len(areq->src, offset);
2038 if (nents < 0) {
2039 dev_err(ctx->dev, "Invalid number of src SG.\n");
2040 return nents;
2041 }
2042 sg_copy_to_buffer(areq->src, nents,
3c0dd190 2043 ctx_buf + req_ctx->nbuf, offset);
37b5e889
LC		 2044 req_ctx->nbuf += offset;
2045 req_ctx->psrc = areq->src;
5e833bc4 2046 } else
497f2e6b 2047 req_ctx->psrc = areq->src;
5e833bc4
LN		 2048
2049 if (to_hash_later) {
8e409fe1
LC		 2050 nents = sg_nents_for_len(areq->src, nbytes);
2051 if (nents < 0) {
2052 dev_err(ctx->dev, "Invalid number of src SG.\n");
2053 return nents;
2054 }
d0525723 2055 sg_pcopy_to_buffer(areq->src, nents,
3c0dd190 2056 req_ctx->buf[(req_ctx->buf_idx + 1) & 1],
5e833bc4
LN		 2057 to_hash_later,
2058 nbytes - to_hash_later);
497f2e6b 2059 }
5e833bc4 2060 req_ctx->to_hash_later = to_hash_later;
497f2e6b 2061
5e833bc4 2062 /* Allocate extended descriptor */
497f2e6b
LN		 2063 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
2064 if (IS_ERR(edesc))
2065 return PTR_ERR(edesc);
2066
2067 edesc->desc.hdr = ctx->desc_hdr_template;
2068
2069 /* On last one, request SEC to pad; otherwise continue */
2070 if (req_ctx->last)
2071 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
2072 else
2073 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
2074
60f208d7
KP		 2075 /* request SEC to INIT hash. */
2076 if (req_ctx->first && !req_ctx->swinit)
497f2e6b
LN		 2077 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
2078
2079 /* When the tfm context has a keylen, it's an HMAC.
2080 * A first or last (ie. not middle) descriptor must request HMAC.
2081 */
2082 if (ctx->keylen && (req_ctx->first || req_ctx->last))
2083 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
2084
37b5e889 2085 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash, offset,
497f2e6b
LN		 2086 ahash_done);
2087}
2088
2089static int ahash_update(struct ahash_request *areq)
2090{
2091 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
2092
2093 req_ctx->last = 0;
2094
2095 return ahash_process_req(areq, areq->nbytes);
2096}
2097
2098static int ahash_final(struct ahash_request *areq)
2099{
2100 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
2101
2102 req_ctx->last = 1;
2103
2104 return ahash_process_req(areq, 0);
2105}
2106
2107static int ahash_finup(struct ahash_request *areq)
2108{
2109 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
2110
2111 req_ctx->last = 1;
2112
2113 return ahash_process_req(areq, areq->nbytes);
2114}
2115
2116static int ahash_digest(struct ahash_request *areq)
2117{
2118 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
60f208d7 2119 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
497f2e6b 2120
60f208d7 2121 ahash->init(areq);
497f2e6b
LN		 2122 req_ctx->last = 1;
2123
2124 return ahash_process_req(areq, areq->nbytes);
2125}
2126
3639ca84
HG		 2127static int ahash_export(struct ahash_request *areq, void *out)
2128{
2129 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
2130 struct talitos_export_state *export = out;
6a4967c3
LC		 2131 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
2132 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
2133 struct device *dev = ctx->dev;
2134 dma_addr_t dma;
2135
2136 dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
2137 DMA_FROM_DEVICE);
2138 dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_FROM_DEVICE);
3639ca84
HG		 2139
2140 memcpy(export->hw_context, req_ctx->hw_context,
2141 req_ctx->hw_context_size);
3c0dd190 2142 memcpy(export->buf, req_ctx->buf[req_ctx->buf_idx], req_ctx->nbuf);
3639ca84
HG		 2143 export->swinit = req_ctx->swinit;
2144 export->first = req_ctx->first;
2145 export->last = req_ctx->last;
2146 export->to_hash_later = req_ctx->to_hash_later;
2147 export->nbuf = req_ctx->nbuf;
2148
2149 return 0;
2150}
2151
2152static int ahash_import(struct ahash_request *areq, const void *in)
2153{
2154 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
2155 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
6a4967c3
LC		 2156 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
2157 struct device *dev = ctx->dev;
3639ca84 2158 const struct talitos_export_state *export = in;
49f9783b 2159 unsigned int size;
6a4967c3 2160 dma_addr_t dma;
3639ca84
HG		 2161
2162 memset(req_ctx, 0, sizeof(*req_ctx));
49f9783b 2163 size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
3639ca84
HG		 2164 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
2165 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
49f9783b 2166 req_ctx->hw_context_size = size;
49f9783b 2167 memcpy(req_ctx->hw_context, export->hw_context, size);
3c0dd190 2168 memcpy(req_ctx->buf[0], export->buf, export->nbuf);
3639ca84
HG		 2169 req_ctx->swinit = export->swinit;
2170 req_ctx->first = export->first;
2171 req_ctx->last = export->last;
2172 req_ctx->to_hash_later = export->to_hash_later;
2173 req_ctx->nbuf = export->nbuf;
2174
6a4967c3
LC		 2175 dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
2176 DMA_TO_DEVICE);
2177 dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
2178
3639ca84
HG		 2179 return 0;
2180}
2181
79b3a418
LN		 2182static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
2183 u8 *hash)
2184{
2185 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
2186
2187 struct scatterlist sg[1];
2188 struct ahash_request *req;
f1c90ac3 2189 struct crypto_wait wait;
79b3a418
LN		 2190 int ret;
2191
f1c90ac3 2192 crypto_init_wait(&wait);
79b3a418
LN		 2193
2194 req = ahash_request_alloc(tfm, GFP_KERNEL);
2195 if (!req)
2196 return -ENOMEM;
2197
2198 /* Keep tfm keylen == 0 during hash of the long key */
2199 ctx->keylen = 0;
2200 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
f1c90ac3 2201 crypto_req_done, &wait);
79b3a418
LN		 2202
2203 sg_init_one(&sg[0], key, keylen);
2204
2205 ahash_request_set_crypt(req, sg, hash, keylen);
f1c90ac3
GBY		 2206 ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
2207
79b3a418
LN		 2208 ahash_request_free(req);
2209
2210 return ret;
2211}
2212
2213static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
2214 unsigned int keylen)
2215{
2216 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
2e13ce08 2217 struct device *dev = ctx->dev;
79b3a418
LN		 2218 unsigned int blocksize =
2219 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
2220 unsigned int digestsize = crypto_ahash_digestsize(tfm);
2221 unsigned int keysize = keylen;
2222 u8 hash[SHA512_DIGEST_SIZE];
2223 int ret;
2224
2225 if (keylen <= blocksize)
2226 memcpy(ctx->key, key, keysize);
2227 else {
2228 /* Must get the hash of the long key */
2229 ret = keyhash(tfm, key, keylen, hash);
2230
2231 if (ret) {
2232 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
2233 return -EINVAL;
2234 }
2235
2236 keysize = digestsize;
2237 memcpy(ctx->key, hash, digestsize);
2238 }
2239
2e13ce08
LC		 2240 if (ctx->keylen)
2241 dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
2242
79b3a418 2243 ctx->keylen = keysize;
2e13ce08 2244 ctx->dma_key = dma_map_single(dev, ctx->key, keysize, DMA_TO_DEVICE);
79b3a418
LN		 2245
2246 return 0;
2247}
2248
2249
9c4a7965 2250struct talitos_alg_template {
d5e4aaef 2251 u32 type;
b0057763 2252 u32 priority;
d5e4aaef
LN		 2253 union {
2254 struct crypto_alg crypto;
acbf7c62 2255 struct ahash_alg hash;
aeb4c132 2256 struct aead_alg aead;
d5e4aaef 2257 } alg;
9c4a7965
KP		 2258 __be32 desc_hdr_template;
2259};
2260
2261static struct talitos_alg_template driver_algs[] = {
991155ba 2262 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef 2263 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2264 .alg.aead = {
2265 .base = {
2266 .cra_name = "authenc(hmac(sha1),cbc(aes))",
2267 .cra_driver_name = "authenc-hmac-sha1-"
2268 "cbc-aes-talitos",
2269 .cra_blocksize = AES_BLOCK_SIZE,
2270 .cra_flags = CRYPTO_ALG_ASYNC,
2271 },
2272 .ivsize = AES_BLOCK_SIZE,
2273 .maxauthsize = SHA1_DIGEST_SIZE,
56af8cd4 2274 },
9c4a7965
KP		 2275 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2276 DESC_HDR_SEL0_AESU |
2277 DESC_HDR_MODE0_AESU_CBC |
2278 DESC_HDR_SEL1_MDEUA |
2279 DESC_HDR_MODE1_MDEU_INIT |
2280 DESC_HDR_MODE1_MDEU_PAD |
2281 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 2282 },
7405c8d7
LC		 2283 { .type = CRYPTO_ALG_TYPE_AEAD,
2284 .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
2285 .alg.aead = {
2286 .base = {
2287 .cra_name = "authenc(hmac(sha1),cbc(aes))",
2288 .cra_driver_name = "authenc-hmac-sha1-"
2289 "cbc-aes-talitos",
2290 .cra_blocksize = AES_BLOCK_SIZE,
2291 .cra_flags = CRYPTO_ALG_ASYNC,
2292 },
2293 .ivsize = AES_BLOCK_SIZE,
2294 .maxauthsize = SHA1_DIGEST_SIZE,
2295 },
2296 .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
2297 DESC_HDR_SEL0_AESU |
2298 DESC_HDR_MODE0_AESU_CBC |
2299 DESC_HDR_SEL1_MDEUA |
2300 DESC_HDR_MODE1_MDEU_INIT |
2301 DESC_HDR_MODE1_MDEU_PAD |
2302 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
2303 },
d5e4aaef 2304 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2305 .alg.aead = {
2306 .base = {
2307 .cra_name = "authenc(hmac(sha1),"
2308 "cbc(des3_ede))",
2309 .cra_driver_name = "authenc-hmac-sha1-"
2310 "cbc-3des-talitos",
2311 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2312 .cra_flags = CRYPTO_ALG_ASYNC,
2313 },
2314 .ivsize = DES3_EDE_BLOCK_SIZE,
2315 .maxauthsize = SHA1_DIGEST_SIZE,
56af8cd4 2316 },
70bcaca7
LN		 2317 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2318 DESC_HDR_SEL0_DEU |
2319 DESC_HDR_MODE0_DEU_CBC |
2320 DESC_HDR_MODE0_DEU_3DES |
2321 DESC_HDR_SEL1_MDEUA |
2322 DESC_HDR_MODE1_MDEU_INIT |
2323 DESC_HDR_MODE1_MDEU_PAD |
2324 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 2325 },
7405c8d7
LC		 2326 { .type = CRYPTO_ALG_TYPE_AEAD,
2327 .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
2328 .alg.aead = {
2329 .base = {
2330 .cra_name = "authenc(hmac(sha1),"
2331 "cbc(des3_ede))",
2332 .cra_driver_name = "authenc-hmac-sha1-"
2333 "cbc-3des-talitos",
2334 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2335 .cra_flags = CRYPTO_ALG_ASYNC,
2336 },
2337 .ivsize = DES3_EDE_BLOCK_SIZE,
2338 .maxauthsize = SHA1_DIGEST_SIZE,
2339 },
2340 .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
2341 DESC_HDR_SEL0_DEU |
2342 DESC_HDR_MODE0_DEU_CBC |
2343 DESC_HDR_MODE0_DEU_3DES |
2344 DESC_HDR_SEL1_MDEUA |
2345 DESC_HDR_MODE1_MDEU_INIT |
2346 DESC_HDR_MODE1_MDEU_PAD |
2347 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
2348 },
357fb605 2349 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2350 .alg.aead = {
2351 .base = {
2352 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2353 .cra_driver_name = "authenc-hmac-sha224-"
2354 "cbc-aes-talitos",
2355 .cra_blocksize = AES_BLOCK_SIZE,
2356 .cra_flags = CRYPTO_ALG_ASYNC,
2357 },
2358 .ivsize = AES_BLOCK_SIZE,
2359 .maxauthsize = SHA224_DIGEST_SIZE,
357fb605
HG		 2360 },
2361 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2362 DESC_HDR_SEL0_AESU |
2363 DESC_HDR_MODE0_AESU_CBC |
2364 DESC_HDR_SEL1_MDEUA |
2365 DESC_HDR_MODE1_MDEU_INIT |
2366 DESC_HDR_MODE1_MDEU_PAD |
2367 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2368 },
7405c8d7
LC		 2369 { .type = CRYPTO_ALG_TYPE_AEAD,
2370 .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
2371 .alg.aead = {
2372 .base = {
2373 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2374 .cra_driver_name = "authenc-hmac-sha224-"
2375 "cbc-aes-talitos",
2376 .cra_blocksize = AES_BLOCK_SIZE,
2377 .cra_flags = CRYPTO_ALG_ASYNC,
2378 },
2379 .ivsize = AES_BLOCK_SIZE,
2380 .maxauthsize = SHA224_DIGEST_SIZE,
2381 },
2382 .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
2383 DESC_HDR_SEL0_AESU |
2384 DESC_HDR_MODE0_AESU_CBC |
2385 DESC_HDR_SEL1_MDEUA |
2386 DESC_HDR_MODE1_MDEU_INIT |
2387 DESC_HDR_MODE1_MDEU_PAD |
2388 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2389 },
357fb605 2390 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2391 .alg.aead = {
2392 .base = {
2393 .cra_name = "authenc(hmac(sha224),"
2394 "cbc(des3_ede))",
2395 .cra_driver_name = "authenc-hmac-sha224-"
2396 "cbc-3des-talitos",
2397 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2398 .cra_flags = CRYPTO_ALG_ASYNC,
2399 },
2400 .ivsize = DES3_EDE_BLOCK_SIZE,
2401 .maxauthsize = SHA224_DIGEST_SIZE,
357fb605
HG		 2402 },
2403 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2404 DESC_HDR_SEL0_DEU |
2405 DESC_HDR_MODE0_DEU_CBC |
2406 DESC_HDR_MODE0_DEU_3DES |
2407 DESC_HDR_SEL1_MDEUA |
2408 DESC_HDR_MODE1_MDEU_INIT |
2409 DESC_HDR_MODE1_MDEU_PAD |
2410 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2411 },
7405c8d7
LC		 2412 { .type = CRYPTO_ALG_TYPE_AEAD,
2413 .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
2414 .alg.aead = {
2415 .base = {
2416 .cra_name = "authenc(hmac(sha224),"
2417 "cbc(des3_ede))",
2418 .cra_driver_name = "authenc-hmac-sha224-"
2419 "cbc-3des-talitos",
2420 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2421 .cra_flags = CRYPTO_ALG_ASYNC,
2422 },
2423 .ivsize = DES3_EDE_BLOCK_SIZE,
2424 .maxauthsize = SHA224_DIGEST_SIZE,
2425 },
2426 .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
2427 DESC_HDR_SEL0_DEU |
2428 DESC_HDR_MODE0_DEU_CBC |
2429 DESC_HDR_MODE0_DEU_3DES |
2430 DESC_HDR_SEL1_MDEUA |
2431 DESC_HDR_MODE1_MDEU_INIT |
2432 DESC_HDR_MODE1_MDEU_PAD |
2433 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2434 },
d5e4aaef 2435 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2436 .alg.aead = {
2437 .base = {
2438 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2439 .cra_driver_name = "authenc-hmac-sha256-"
2440 "cbc-aes-talitos",
2441 .cra_blocksize = AES_BLOCK_SIZE,
2442 .cra_flags = CRYPTO_ALG_ASYNC,
2443 },
2444 .ivsize = AES_BLOCK_SIZE,
2445 .maxauthsize = SHA256_DIGEST_SIZE,
56af8cd4 2446 },
3952f17e
LN		 2447 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2448 DESC_HDR_SEL0_AESU |
2449 DESC_HDR_MODE0_AESU_CBC |
2450 DESC_HDR_SEL1_MDEUA |
2451 DESC_HDR_MODE1_MDEU_INIT |
2452 DESC_HDR_MODE1_MDEU_PAD |
2453 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2454 },
7405c8d7
LC		 2455 { .type = CRYPTO_ALG_TYPE_AEAD,
2456 .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
2457 .alg.aead = {
2458 .base = {
2459 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2460 .cra_driver_name = "authenc-hmac-sha256-"
2461 "cbc-aes-talitos",
2462 .cra_blocksize = AES_BLOCK_SIZE,
2463 .cra_flags = CRYPTO_ALG_ASYNC,
2464 },
2465 .ivsize = AES_BLOCK_SIZE,
2466 .maxauthsize = SHA256_DIGEST_SIZE,
2467 },
2468 .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
2469 DESC_HDR_SEL0_AESU |
2470 DESC_HDR_MODE0_AESU_CBC |
2471 DESC_HDR_SEL1_MDEUA |
2472 DESC_HDR_MODE1_MDEU_INIT |
2473 DESC_HDR_MODE1_MDEU_PAD |
2474 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2475 },
d5e4aaef 2476 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2477 .alg.aead = {
2478 .base = {
2479 .cra_name = "authenc(hmac(sha256),"
2480 "cbc(des3_ede))",
2481 .cra_driver_name = "authenc-hmac-sha256-"
2482 "cbc-3des-talitos",
2483 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2484 .cra_flags = CRYPTO_ALG_ASYNC,
2485 },
2486 .ivsize = DES3_EDE_BLOCK_SIZE,
2487 .maxauthsize = SHA256_DIGEST_SIZE,
56af8cd4 2488 },
3952f17e
LN		 2489 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2490 DESC_HDR_SEL0_DEU |
2491 DESC_HDR_MODE0_DEU_CBC |
2492 DESC_HDR_MODE0_DEU_3DES |
2493 DESC_HDR_SEL1_MDEUA |
2494 DESC_HDR_MODE1_MDEU_INIT |
2495 DESC_HDR_MODE1_MDEU_PAD |
2496 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2497 },
7405c8d7
LC		 2498 { .type = CRYPTO_ALG_TYPE_AEAD,
2499 .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
2500 .alg.aead = {
2501 .base = {
2502 .cra_name = "authenc(hmac(sha256),"
2503 "cbc(des3_ede))",
2504 .cra_driver_name = "authenc-hmac-sha256-"
2505 "cbc-3des-talitos",
2506 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2507 .cra_flags = CRYPTO_ALG_ASYNC,
2508 },
2509 .ivsize = DES3_EDE_BLOCK_SIZE,
2510 .maxauthsize = SHA256_DIGEST_SIZE,
2511 },
2512 .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
2513 DESC_HDR_SEL0_DEU |
2514 DESC_HDR_MODE0_DEU_CBC |
2515 DESC_HDR_MODE0_DEU_3DES |
2516 DESC_HDR_SEL1_MDEUA |
2517 DESC_HDR_MODE1_MDEU_INIT |
2518 DESC_HDR_MODE1_MDEU_PAD |
2519 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2520 },
d5e4aaef 2521 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2522 .alg.aead = {
2523 .base = {
2524 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2525 .cra_driver_name = "authenc-hmac-sha384-"
2526 "cbc-aes-talitos",
2527 .cra_blocksize = AES_BLOCK_SIZE,
2528 .cra_flags = CRYPTO_ALG_ASYNC,
2529 },
2530 .ivsize = AES_BLOCK_SIZE,
2531 .maxauthsize = SHA384_DIGEST_SIZE,
357fb605
HG		 2532 },
2533 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2534 DESC_HDR_SEL0_AESU |
2535 DESC_HDR_MODE0_AESU_CBC |
2536 DESC_HDR_SEL1_MDEUB |
2537 DESC_HDR_MODE1_MDEU_INIT |
2538 DESC_HDR_MODE1_MDEU_PAD |
2539 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2540 },
2541 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2542 .alg.aead = {
2543 .base = {
2544 .cra_name = "authenc(hmac(sha384),"
2545 "cbc(des3_ede))",
2546 .cra_driver_name = "authenc-hmac-sha384-"
2547 "cbc-3des-talitos",
2548 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2549 .cra_flags = CRYPTO_ALG_ASYNC,
2550 },
2551 .ivsize = DES3_EDE_BLOCK_SIZE,
2552 .maxauthsize = SHA384_DIGEST_SIZE,
357fb605
HG		 2553 },
2554 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2555 DESC_HDR_SEL0_DEU |
2556 DESC_HDR_MODE0_DEU_CBC |
2557 DESC_HDR_MODE0_DEU_3DES |
2558 DESC_HDR_SEL1_MDEUB |
2559 DESC_HDR_MODE1_MDEU_INIT |
2560 DESC_HDR_MODE1_MDEU_PAD |
2561 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2562 },
2563 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2564 .alg.aead = {
2565 .base = {
2566 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2567 .cra_driver_name = "authenc-hmac-sha512-"
2568 "cbc-aes-talitos",
2569 .cra_blocksize = AES_BLOCK_SIZE,
2570 .cra_flags = CRYPTO_ALG_ASYNC,
2571 },
2572 .ivsize = AES_BLOCK_SIZE,
2573 .maxauthsize = SHA512_DIGEST_SIZE,
357fb605
HG		 2574 },
2575 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2576 DESC_HDR_SEL0_AESU |
2577 DESC_HDR_MODE0_AESU_CBC |
2578 DESC_HDR_SEL1_MDEUB |
2579 DESC_HDR_MODE1_MDEU_INIT |
2580 DESC_HDR_MODE1_MDEU_PAD |
2581 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2582 },
2583 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2584 .alg.aead = {
2585 .base = {
2586 .cra_name = "authenc(hmac(sha512),"
2587 "cbc(des3_ede))",
2588 .cra_driver_name = "authenc-hmac-sha512-"
2589 "cbc-3des-talitos",
2590 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2591 .cra_flags = CRYPTO_ALG_ASYNC,
2592 },
2593 .ivsize = DES3_EDE_BLOCK_SIZE,
2594 .maxauthsize = SHA512_DIGEST_SIZE,
357fb605
HG		 2595 },
2596 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2597 DESC_HDR_SEL0_DEU |
2598 DESC_HDR_MODE0_DEU_CBC |
2599 DESC_HDR_MODE0_DEU_3DES |
2600 DESC_HDR_SEL1_MDEUB |
2601 DESC_HDR_MODE1_MDEU_INIT |
2602 DESC_HDR_MODE1_MDEU_PAD |
2603 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2604 },
2605 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2606 .alg.aead = {
2607 .base = {
2608 .cra_name = "authenc(hmac(md5),cbc(aes))",
2609 .cra_driver_name = "authenc-hmac-md5-"
2610 "cbc-aes-talitos",
2611 .cra_blocksize = AES_BLOCK_SIZE,
2612 .cra_flags = CRYPTO_ALG_ASYNC,
2613 },
2614 .ivsize = AES_BLOCK_SIZE,
2615 .maxauthsize = MD5_DIGEST_SIZE,
56af8cd4 2616 },
3952f17e
LN		 2617 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2618 DESC_HDR_SEL0_AESU |
2619 DESC_HDR_MODE0_AESU_CBC |
2620 DESC_HDR_SEL1_MDEUA |
2621 DESC_HDR_MODE1_MDEU_INIT |
2622 DESC_HDR_MODE1_MDEU_PAD |
2623 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2624 },
7405c8d7
LC		 2625 { .type = CRYPTO_ALG_TYPE_AEAD,
2626 .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
2627 .alg.aead = {
2628 .base = {
2629 .cra_name = "authenc(hmac(md5),cbc(aes))",
2630 .cra_driver_name = "authenc-hmac-md5-"
2631 "cbc-aes-talitos",
2632 .cra_blocksize = AES_BLOCK_SIZE,
2633 .cra_flags = CRYPTO_ALG_ASYNC,
2634 },
2635 .ivsize = AES_BLOCK_SIZE,
2636 .maxauthsize = MD5_DIGEST_SIZE,
2637 },
2638 .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
2639 DESC_HDR_SEL0_AESU |
2640 DESC_HDR_MODE0_AESU_CBC |
2641 DESC_HDR_SEL1_MDEUA |
2642 DESC_HDR_MODE1_MDEU_INIT |
2643 DESC_HDR_MODE1_MDEU_PAD |
2644 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2645 },
d5e4aaef 2646 { .type = CRYPTO_ALG_TYPE_AEAD,
aeb4c132
HX		 2647 .alg.aead = {
2648 .base = {
2649 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2650 .cra_driver_name = "authenc-hmac-md5-"
2651 "cbc-3des-talitos",
2652 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2653 .cra_flags = CRYPTO_ALG_ASYNC,
2654 },
2655 .ivsize = DES3_EDE_BLOCK_SIZE,
2656 .maxauthsize = MD5_DIGEST_SIZE,
56af8cd4 2657 },
3952f17e
LN		 2658 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2659 DESC_HDR_SEL0_DEU |
2660 DESC_HDR_MODE0_DEU_CBC |
2661 DESC_HDR_MODE0_DEU_3DES |
2662 DESC_HDR_SEL1_MDEUA |
2663 DESC_HDR_MODE1_MDEU_INIT |
2664 DESC_HDR_MODE1_MDEU_PAD |
2665 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5 2666 },
7405c8d7
LC		 2667 { .type = CRYPTO_ALG_TYPE_AEAD,
2668 .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
2669 .alg.aead = {
2670 .base = {
2671 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2672 .cra_driver_name = "authenc-hmac-md5-"
2673 "cbc-3des-talitos",
2674 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2675 .cra_flags = CRYPTO_ALG_ASYNC,
2676 },
2677 .ivsize = DES3_EDE_BLOCK_SIZE,
2678 .maxauthsize = MD5_DIGEST_SIZE,
2679 },
2680 .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
2681 DESC_HDR_SEL0_DEU |
2682 DESC_HDR_MODE0_DEU_CBC |
2683 DESC_HDR_MODE0_DEU_3DES |
2684 DESC_HDR_SEL1_MDEUA |
2685 DESC_HDR_MODE1_MDEU_INIT |
2686 DESC_HDR_MODE1_MDEU_PAD |
2687 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2688 },
4de9d0b5 2689 /* ABLKCIPHER algorithms. */
5e75ae1b
LC		 2690 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2691 .alg.crypto = {
2692 .cra_name = "ecb(aes)",
2693 .cra_driver_name = "ecb-aes-talitos",
2694 .cra_blocksize = AES_BLOCK_SIZE,
2695 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2696 CRYPTO_ALG_ASYNC,
2697 .cra_ablkcipher = {
2698 .min_keysize = AES_MIN_KEY_SIZE,
2699 .max_keysize = AES_MAX_KEY_SIZE,
2700 .ivsize = AES_BLOCK_SIZE,
2701 }
2702 },
2703 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2704 DESC_HDR_SEL0_AESU,
2705 },
d5e4aaef
LN		 2706 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2707 .alg.crypto = {
4de9d0b5
LN		 2708 .cra_name = "cbc(aes)",
2709 .cra_driver_name = "cbc-aes-talitos",
2710 .cra_blocksize = AES_BLOCK_SIZE,
2711 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2712 CRYPTO_ALG_ASYNC,
4de9d0b5 2713 .cra_ablkcipher = {
4de9d0b5
LN		 2714 .min_keysize = AES_MIN_KEY_SIZE,
2715 .max_keysize = AES_MAX_KEY_SIZE,
2716 .ivsize = AES_BLOCK_SIZE,
2717 }
2718 },
2719 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2720 DESC_HDR_SEL0_AESU |
2721 DESC_HDR_MODE0_AESU_CBC,
2722 },
5e75ae1b
LC		 2723 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2724 .alg.crypto = {
2725 .cra_name = "ctr(aes)",
2726 .cra_driver_name = "ctr-aes-talitos",
2727 .cra_blocksize = AES_BLOCK_SIZE,
2728 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2729 CRYPTO_ALG_ASYNC,
2730 .cra_ablkcipher = {
2731 .min_keysize = AES_MIN_KEY_SIZE,
2732 .max_keysize = AES_MAX_KEY_SIZE,
2733 .ivsize = AES_BLOCK_SIZE,
2734 }
2735 },
70d355cc 2736 .desc_hdr_template = DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
5e75ae1b
LC		 2737 DESC_HDR_SEL0_AESU |
2738 DESC_HDR_MODE0_AESU_CTR,
2739 },
2740 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2741 .alg.crypto = {
2742 .cra_name = "ecb(des)",
2743 .cra_driver_name = "ecb-des-talitos",
2744 .cra_blocksize = DES_BLOCK_SIZE,
2745 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2746 CRYPTO_ALG_ASYNC,
2747 .cra_ablkcipher = {
2748 .min_keysize = DES_KEY_SIZE,
2749 .max_keysize = DES_KEY_SIZE,
2750 .ivsize = DES_BLOCK_SIZE,
2751 }
2752 },
2753 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2754 DESC_HDR_SEL0_DEU,
2755 },
2756 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2757 .alg.crypto = {
2758 .cra_name = "cbc(des)",
2759 .cra_driver_name = "cbc-des-talitos",
2760 .cra_blocksize = DES_BLOCK_SIZE,
2761 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2762 CRYPTO_ALG_ASYNC,
2763 .cra_ablkcipher = {
2764 .min_keysize = DES_KEY_SIZE,
2765 .max_keysize = DES_KEY_SIZE,
2766 .ivsize = DES_BLOCK_SIZE,
2767 }
2768 },
2769 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2770 DESC_HDR_SEL0_DEU |
2771 DESC_HDR_MODE0_DEU_CBC,
2772 },
2773 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2774 .alg.crypto = {
2775 .cra_name = "ecb(des3_ede)",
2776 .cra_driver_name = "ecb-3des-talitos",
2777 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2778 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2779 CRYPTO_ALG_ASYNC,
2780 .cra_ablkcipher = {
2781 .min_keysize = DES3_EDE_KEY_SIZE,
2782 .max_keysize = DES3_EDE_KEY_SIZE,
2783 .ivsize = DES3_EDE_BLOCK_SIZE,
2784 }
2785 },
2786 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2787 DESC_HDR_SEL0_DEU |
2788 DESC_HDR_MODE0_DEU_3DES,
2789 },
d5e4aaef
LN		 2790 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2791 .alg.crypto = {
4de9d0b5
LN		 2792 .cra_name = "cbc(des3_ede)",
2793 .cra_driver_name = "cbc-3des-talitos",
2794 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2795 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2796 CRYPTO_ALG_ASYNC,
4de9d0b5 2797 .cra_ablkcipher = {
4de9d0b5
LN		 2798 .min_keysize = DES3_EDE_KEY_SIZE,
2799 .max_keysize = DES3_EDE_KEY_SIZE,
2800 .ivsize = DES3_EDE_BLOCK_SIZE,
2801 }
2802 },
2803 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2804 DESC_HDR_SEL0_DEU |
2805 DESC_HDR_MODE0_DEU_CBC |
2806 DESC_HDR_MODE0_DEU_3DES,
497f2e6b
LN		 2807 },
2808 /* AHASH algorithms. */
2809 { .type = CRYPTO_ALG_TYPE_AHASH,
2810 .alg.hash = {
497f2e6b 2811 .halg.digestsize = MD5_DIGEST_SIZE,
3639ca84 2812 .halg.statesize = sizeof(struct talitos_export_state),
497f2e6b
LN		 2813 .halg.base = {
2814 .cra_name = "md5",
2815 .cra_driver_name = "md5-talitos",
b3988618 2816 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
6a38f622 2817 .cra_flags = CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2818 }
2819 },
2820 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2821 DESC_HDR_SEL0_MDEUA |
2822 DESC_HDR_MODE0_MDEU_MD5,
2823 },
2824 { .type = CRYPTO_ALG_TYPE_AHASH,
2825 .alg.hash = {
497f2e6b 2826 .halg.digestsize = SHA1_DIGEST_SIZE,
3639ca84 2827 .halg.statesize = sizeof(struct talitos_export_state),
497f2e6b
LN		 2828 .halg.base = {
2829 .cra_name = "sha1",
2830 .cra_driver_name = "sha1-talitos",
2831 .cra_blocksize = SHA1_BLOCK_SIZE,
6a38f622 2832 .cra_flags = CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2833 }
2834 },
2835 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2836 DESC_HDR_SEL0_MDEUA |
2837 DESC_HDR_MODE0_MDEU_SHA1,
2838 },
60f208d7
KP		 2839 { .type = CRYPTO_ALG_TYPE_AHASH,
2840 .alg.hash = {
60f208d7 2841 .halg.digestsize = SHA224_DIGEST_SIZE,
3639ca84 2842 .halg.statesize = sizeof(struct talitos_export_state),
60f208d7
KP		 2843 .halg.base = {
2844 .cra_name = "sha224",
2845 .cra_driver_name = "sha224-talitos",
2846 .cra_blocksize = SHA224_BLOCK_SIZE,
6a38f622 2847 .cra_flags = CRYPTO_ALG_ASYNC,
60f208d7
KP		 2848 }
2849 },
2850 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2851 DESC_HDR_SEL0_MDEUA |
2852 DESC_HDR_MODE0_MDEU_SHA224,
2853 },
497f2e6b
LN		 2854 { .type = CRYPTO_ALG_TYPE_AHASH,
2855 .alg.hash = {
497f2e6b 2856 .halg.digestsize = SHA256_DIGEST_SIZE,
3639ca84 2857 .halg.statesize = sizeof(struct talitos_export_state),
497f2e6b
LN		 2858 .halg.base = {
2859 .cra_name = "sha256",
2860 .cra_driver_name = "sha256-talitos",
2861 .cra_blocksize = SHA256_BLOCK_SIZE,
6a38f622 2862 .cra_flags = CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2863 }
2864 },
2865 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2866 DESC_HDR_SEL0_MDEUA |
2867 DESC_HDR_MODE0_MDEU_SHA256,
2868 },
2869 { .type = CRYPTO_ALG_TYPE_AHASH,
2870 .alg.hash = {
497f2e6b 2871 .halg.digestsize = SHA384_DIGEST_SIZE,
3639ca84 2872 .halg.statesize = sizeof(struct talitos_export_state),
497f2e6b
LN		 2873 .halg.base = {
2874 .cra_name = "sha384",
2875 .cra_driver_name = "sha384-talitos",
2876 .cra_blocksize = SHA384_BLOCK_SIZE,
6a38f622 2877 .cra_flags = CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2878 }
2879 },
2880 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2881 DESC_HDR_SEL0_MDEUB |
2882 DESC_HDR_MODE0_MDEUB_SHA384,
2883 },
2884 { .type = CRYPTO_ALG_TYPE_AHASH,
2885 .alg.hash = {
497f2e6b 2886 .halg.digestsize = SHA512_DIGEST_SIZE,
3639ca84 2887 .halg.statesize = sizeof(struct talitos_export_state),
497f2e6b
LN		 2888 .halg.base = {
2889 .cra_name = "sha512",
2890 .cra_driver_name = "sha512-talitos",
2891 .cra_blocksize = SHA512_BLOCK_SIZE,
6a38f622 2892 .cra_flags = CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2893 }
2894 },
2895 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2896 DESC_HDR_SEL0_MDEUB |
2897 DESC_HDR_MODE0_MDEUB_SHA512,
2898 },
79b3a418
LN		 2899 { .type = CRYPTO_ALG_TYPE_AHASH,
2900 .alg.hash = {
79b3a418 2901 .halg.digestsize = MD5_DIGEST_SIZE,
3639ca84 2902 .halg.statesize = sizeof(struct talitos_export_state),
79b3a418
LN		 2903 .halg.base = {
2904 .cra_name = "hmac(md5)",
2905 .cra_driver_name = "hmac-md5-talitos",
b3988618 2906 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
6a38f622 2907 .cra_flags = CRYPTO_ALG_ASYNC,
79b3a418
LN		 2908 }
2909 },
2910 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2911 DESC_HDR_SEL0_MDEUA |
2912 DESC_HDR_MODE0_MDEU_MD5,
2913 },
2914 { .type = CRYPTO_ALG_TYPE_AHASH,
2915 .alg.hash = {
79b3a418 2916 .halg.digestsize = SHA1_DIGEST_SIZE,
3639ca84 2917 .halg.statesize = sizeof(struct talitos_export_state),
79b3a418
LN		 2918 .halg.base = {
2919 .cra_name = "hmac(sha1)",
2920 .cra_driver_name = "hmac-sha1-talitos",
2921 .cra_blocksize = SHA1_BLOCK_SIZE,
6a38f622 2922 .cra_flags = CRYPTO_ALG_ASYNC,
79b3a418
LN		 2923 }
2924 },
2925 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2926 DESC_HDR_SEL0_MDEUA |
2927 DESC_HDR_MODE0_MDEU_SHA1,
2928 },
2929 { .type = CRYPTO_ALG_TYPE_AHASH,
2930 .alg.hash = {
79b3a418 2931 .halg.digestsize = SHA224_DIGEST_SIZE,
3639ca84 2932 .halg.statesize = sizeof(struct talitos_export_state),
79b3a418
LN		 2933 .halg.base = {
2934 .cra_name = "hmac(sha224)",
2935 .cra_driver_name = "hmac-sha224-talitos",
2936 .cra_blocksize = SHA224_BLOCK_SIZE,
6a38f622 2937 .cra_flags = CRYPTO_ALG_ASYNC,
79b3a418
LN		 2938 }
2939 },
2940 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2941 DESC_HDR_SEL0_MDEUA |
2942 DESC_HDR_MODE0_MDEU_SHA224,
2943 },
2944 { .type = CRYPTO_ALG_TYPE_AHASH,
2945 .alg.hash = {
79b3a418 2946 .halg.digestsize = SHA256_DIGEST_SIZE,
3639ca84 2947 .halg.statesize = sizeof(struct talitos_export_state),
79b3a418
LN		 2948 .halg.base = {
2949 .cra_name = "hmac(sha256)",
2950 .cra_driver_name = "hmac-sha256-talitos",
2951 .cra_blocksize = SHA256_BLOCK_SIZE,
6a38f622 2952 .cra_flags = CRYPTO_ALG_ASYNC,
79b3a418
LN		 2953 }
2954 },
2955 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2956 DESC_HDR_SEL0_MDEUA |
2957 DESC_HDR_MODE0_MDEU_SHA256,
2958 },
2959 { .type = CRYPTO_ALG_TYPE_AHASH,
2960 .alg.hash = {
79b3a418 2961 .halg.digestsize = SHA384_DIGEST_SIZE,
3639ca84 2962 .halg.statesize = sizeof(struct talitos_export_state),
79b3a418
LN		 2963 .halg.base = {
2964 .cra_name = "hmac(sha384)",
2965 .cra_driver_name = "hmac-sha384-talitos",
2966 .cra_blocksize = SHA384_BLOCK_SIZE,
6a38f622 2967 .cra_flags = CRYPTO_ALG_ASYNC,
79b3a418
LN		 2968 }
2969 },
2970 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2971 DESC_HDR_SEL0_MDEUB |
2972 DESC_HDR_MODE0_MDEUB_SHA384,
2973 },
2974 { .type = CRYPTO_ALG_TYPE_AHASH,
2975 .alg.hash = {
79b3a418 2976 .halg.digestsize = SHA512_DIGEST_SIZE,
3639ca84 2977 .halg.statesize = sizeof(struct talitos_export_state),
79b3a418
LN		 2978 .halg.base = {
2979 .cra_name = "hmac(sha512)",
2980 .cra_driver_name = "hmac-sha512-talitos",
2981 .cra_blocksize = SHA512_BLOCK_SIZE,
6a38f622 2982 .cra_flags = CRYPTO_ALG_ASYNC,
79b3a418
LN		 2983 }
2984 },
2985 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2986 DESC_HDR_SEL0_MDEUB |
2987 DESC_HDR_MODE0_MDEUB_SHA512,
2988 }
9c4a7965
KP		 2989};
2990
2991struct talitos_crypto_alg {
2992 struct list_head entry;
2993 struct device *dev;
acbf7c62 2994 struct talitos_alg_template algt;
9c4a7965
KP		 2995};
2996
89d124cb
JE		 2997static int talitos_init_common(struct talitos_ctx *ctx,
2998 struct talitos_crypto_alg *talitos_alg)
9c4a7965 2999{
5228f0f7 3000 struct talitos_private *priv;
9c4a7965
KP		 3001
3002 /* update context with ptr to dev */
3003 ctx->dev = talitos_alg->dev;
19bbbc63 3004
5228f0f7
KP		 3005 /* assign SEC channel to tfm in round-robin fashion */
3006 priv = dev_get_drvdata(ctx->dev);
3007 ctx->ch = atomic_inc_return(&priv->last_chan) &
3008 (priv->num_channels - 1);
3009
9c4a7965 3010 /* copy descriptor header template value */
acbf7c62 3011 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965 3012
602dba5a
KP		 3013 /* select done notification */
3014 ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
3015
497f2e6b
LN		 3016 return 0;
3017}
3018
89d124cb
JE		 3019static int talitos_cra_init(struct crypto_tfm *tfm)
3020{
3021 struct crypto_alg *alg = tfm->__crt_alg;
3022 struct talitos_crypto_alg *talitos_alg;
3023 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
3024
3025 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
3026 talitos_alg = container_of(__crypto_ahash_alg(alg),
3027 struct talitos_crypto_alg,
3028 algt.alg.hash);
3029 else
3030 talitos_alg = container_of(alg, struct talitos_crypto_alg,
3031 algt.alg.crypto);
3032
3033 return talitos_init_common(ctx, talitos_alg);
3034}
3035
aeb4c132 3036static int talitos_cra_init_aead(struct crypto_aead *tfm)
497f2e6b 3037{
89d124cb
JE		 3038 struct aead_alg *alg = crypto_aead_alg(tfm);
3039 struct talitos_crypto_alg *talitos_alg;
3040 struct talitos_ctx *ctx = crypto_aead_ctx(tfm);
3041
3042 talitos_alg = container_of(alg, struct talitos_crypto_alg,
3043 algt.alg.aead);
3044
3045 return talitos_init_common(ctx, talitos_alg);
9c4a7965
KP		 3046}
3047
497f2e6b
LN		 3048static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
3049{
3050 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
3051
3052 talitos_cra_init(tfm);
3053
3054 ctx->keylen = 0;
3055 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
3056 sizeof(struct talitos_ahash_req_ctx));
3057
3058 return 0;
3059}
3060
2e13ce08
LC		 3061static void talitos_cra_exit(struct crypto_tfm *tfm)
3062{
3063 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
3064 struct device *dev = ctx->dev;
3065
3066 if (ctx->keylen)
3067 dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
3068}
3069
9c4a7965
KP		 3070/*
3071 * given the alg's descriptor header template, determine whether descriptor
3072 * type and primary/secondary execution units required match the hw
3073 * capabilities description provided in the device tree node.
3074 */
3075static int hw_supports(struct device *dev, __be32 desc_hdr_template)
3076{
3077 struct talitos_private *priv = dev_get_drvdata(dev);
3078 int ret;
3079
3080 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
3081 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
3082
3083 if (SECONDARY_EU(desc_hdr_template))
3084 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
3085 & priv->exec_units);
3086
3087 return ret;
3088}
3089
2dc11581 3090static int talitos_remove(struct platform_device *ofdev)
9c4a7965
KP		 3091{
3092 struct device *dev = &ofdev->dev;
3093 struct talitos_private *priv = dev_get_drvdata(dev);
3094 struct talitos_crypto_alg *t_alg, *n;
3095 int i;
3096
3097 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 3098 switch (t_alg->algt.type) {
3099 case CRYPTO_ALG_TYPE_ABLKCIPHER:
acbf7c62 3100 break;
aeb4c132
HX		 3101 case CRYPTO_ALG_TYPE_AEAD:
3102 crypto_unregister_aead(&t_alg->algt.alg.aead);
acbf7c62
LN		 3103 case CRYPTO_ALG_TYPE_AHASH:
3104 crypto_unregister_ahash(&t_alg->algt.alg.hash);
3105 break;
3106 }
9c4a7965 3107 list_del(&t_alg->entry);
9c4a7965
KP		 3108 }
3109
3110 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
3111 talitos_unregister_rng(dev);
3112
c3e337f8 3113 for (i = 0; i < 2; i++)
2cdba3cf 3114 if (priv->irq[i]) {
c3e337f8
KP		 3115 free_irq(priv->irq[i], dev);
3116 irq_dispose_mapping(priv->irq[i]);
3117 }
9c4a7965 3118
c3e337f8 3119 tasklet_kill(&priv->done_task[0]);
2cdba3cf 3120 if (priv->irq[1])
c3e337f8 3121 tasklet_kill(&priv->done_task[1]);
9c4a7965 3122
9c4a7965
KP		 3123 return 0;
3124}
3125
3126static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
3127 struct talitos_alg_template
3128 *template)
3129{
60f208d7 3130 struct talitos_private *priv = dev_get_drvdata(dev);
9c4a7965
KP		 3131 struct talitos_crypto_alg *t_alg;
3132 struct crypto_alg *alg;
3133
24b92ff2
LC		 3134 t_alg = devm_kzalloc(dev, sizeof(struct talitos_crypto_alg),
3135 GFP_KERNEL);
9c4a7965
KP		 3136 if (!t_alg)
3137 return ERR_PTR(-ENOMEM);
3138
acbf7c62
LN		 3139 t_alg->algt = *template;
3140
3141 switch (t_alg->algt.type) {
3142 case CRYPTO_ALG_TYPE_ABLKCIPHER:
497f2e6b
LN		 3143 alg = &t_alg->algt.alg.crypto;
3144 alg->cra_init = talitos_cra_init;
2e13ce08 3145 alg->cra_exit = talitos_cra_exit;
d4cd3283 3146 alg->cra_type = &crypto_ablkcipher_type;
b286e003
KP		 3147 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
3148 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
3149 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
497f2e6b 3150 break;
acbf7c62 3151 case CRYPTO_ALG_TYPE_AEAD:
aeb4c132 3152 alg = &t_alg->algt.alg.aead.base;
2e13ce08 3153 alg->cra_exit = talitos_cra_exit;
aeb4c132
HX		 3154 t_alg->algt.alg.aead.init = talitos_cra_init_aead;
3155 t_alg->algt.alg.aead.setkey = aead_setkey;
3156 t_alg->algt.alg.aead.encrypt = aead_encrypt;
3157 t_alg->algt.alg.aead.decrypt = aead_decrypt;
6cda075a
LC		 3158 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
3159 !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) {
24b92ff2 3160 devm_kfree(dev, t_alg);
6cda075a
LC		 3161 return ERR_PTR(-ENOTSUPP);
3162 }
acbf7c62
LN		 3163 break;
3164 case CRYPTO_ALG_TYPE_AHASH:
3165 alg = &t_alg->algt.alg.hash.halg.base;
497f2e6b 3166 alg->cra_init = talitos_cra_init_ahash;
ad4cd51f 3167 alg->cra_exit = talitos_cra_exit;
b286e003
KP		 3168 t_alg->algt.alg.hash.init = ahash_init;
3169 t_alg->algt.alg.hash.update = ahash_update;
3170 t_alg->algt.alg.hash.final = ahash_final;
3171 t_alg->algt.alg.hash.finup = ahash_finup;
3172 t_alg->algt.alg.hash.digest = ahash_digest;
56136631
LC		 3173 if (!strncmp(alg->cra_name, "hmac", 4))
3174 t_alg->algt.alg.hash.setkey = ahash_setkey;
3639ca84
HG		 3175 t_alg->algt.alg.hash.import = ahash_import;
3176 t_alg->algt.alg.hash.export = ahash_export;
b286e003 3177
79b3a418 3178 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
0b2730d8 3179 !strncmp(alg->cra_name, "hmac", 4)) {
24b92ff2 3180 devm_kfree(dev, t_alg);
79b3a418 3181 return ERR_PTR(-ENOTSUPP);
0b2730d8 3182 }
60f208d7 3183 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
79b3a418
LN		 3184 (!strcmp(alg->cra_name, "sha224") ||
3185 !strcmp(alg->cra_name, "hmac(sha224)"))) {
60f208d7
KP		 3186 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
3187 t_alg->algt.desc_hdr_template =
3188 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
3189 DESC_HDR_SEL0_MDEUA |
3190 DESC_HDR_MODE0_MDEU_SHA256;
3191 }
497f2e6b 3192 break;
1d11911a
KP		 3193 default:
3194 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
24b92ff2 3195 devm_kfree(dev, t_alg);
1d11911a 3196 return ERR_PTR(-EINVAL);
acbf7c62 3197 }
9c4a7965 3198
9c4a7965 3199 alg->cra_module = THIS_MODULE;
b0057763
LC		 3200 if (t_alg->algt.priority)
3201 alg->cra_priority = t_alg->algt.priority;
3202 else
3203 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 3204 alg->cra_alignmask = 0;
9c4a7965 3205 alg->cra_ctxsize = sizeof(struct talitos_ctx);
d912bb76 3206 alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
9c4a7965 3207
9c4a7965
KP		 3208 t_alg->dev = dev;
3209
3210 return t_alg;
3211}
3212
c3e337f8
KP		 3213static int talitos_probe_irq(struct platform_device *ofdev)
3214{
3215 struct device *dev = &ofdev->dev;
3216 struct device_node *np = ofdev->dev.of_node;
3217 struct talitos_private *priv = dev_get_drvdata(dev);
3218 int err;
dd3c0987 3219 bool is_sec1 = has_ftr_sec1(priv);
c3e337f8
KP		 3220
3221 priv->irq[0] = irq_of_parse_and_map(np, 0);
2cdba3cf 3222 if (!priv->irq[0]) {
c3e337f8
KP		 3223 dev_err(dev, "failed to map irq\n");
3224 return -EINVAL;
3225 }
dd3c0987
LC		 3226 if (is_sec1) {
3227 err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
3228 dev_driver_string(dev), dev);
3229 goto primary_out;
3230 }
c3e337f8
KP		 3231
3232 priv->irq[1] = irq_of_parse_and_map(np, 1);
3233
3234 /* get the primary irq line */
2cdba3cf 3235 if (!priv->irq[1]) {
dd3c0987 3236 err = request_irq(priv->irq[0], talitos2_interrupt_4ch, 0,
c3e337f8
KP		 3237 dev_driver_string(dev), dev);
3238 goto primary_out;
3239 }
3240
dd3c0987 3241 err = request_irq(priv->irq[0], talitos2_interrupt_ch0_2, 0,
c3e337f8
KP		 3242 dev_driver_string(dev), dev);
3243 if (err)
3244 goto primary_out;
3245
3246 /* get the secondary irq line */
dd3c0987 3247 err = request_irq(priv->irq[1], talitos2_interrupt_ch1_3, 0,
c3e337f8
KP		 3248 dev_driver_string(dev), dev);
3249 if (err) {
3250 dev_err(dev, "failed to request secondary irq\n");
3251 irq_dispose_mapping(priv->irq[1]);
2cdba3cf 3252 priv->irq[1] = 0;
c3e337f8
KP		 3253 }
3254
3255 return err;
3256
3257primary_out:
3258 if (err) {
3259 dev_err(dev, "failed to request primary irq\n");
3260 irq_dispose_mapping(priv->irq[0]);
2cdba3cf 3261 priv->irq[0] = 0;
c3e337f8
KP		 3262 }
3263
3264 return err;
3265}
3266
1c48a5c9 3267static int talitos_probe(struct platform_device *ofdev)
9c4a7965
KP		 3268{
3269 struct device *dev = &ofdev->dev;
61c7a080 3270 struct device_node *np = ofdev->dev.of_node;
9c4a7965 3271 struct talitos_private *priv;
9c4a7965 3272 int i, err;
5fa7fa14 3273 int stride;
fd5ea7f0 3274 struct resource *res;
9c4a7965 3275
24b92ff2 3276 priv = devm_kzalloc(dev, sizeof(struct talitos_private), GFP_KERNEL);
9c4a7965
KP		 3277 if (!priv)
3278 return -ENOMEM;
3279
f3de9cb1
KH		 3280 INIT_LIST_HEAD(&priv->alg_list);
3281
9c4a7965
KP		 3282 dev_set_drvdata(dev, priv);
3283
3284 priv->ofdev = ofdev;
3285
511d63cb
HG		 3286 spin_lock_init(&priv->reg_lock);
3287
fd5ea7f0
LC		 3288 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
3289 if (!res)
3290 return -ENXIO;
3291 priv->reg = devm_ioremap(dev, res->start, resource_size(res));
9c4a7965
KP		 3292 if (!priv->reg) {
3293 dev_err(dev, "failed to of_iomap\n");
3294 err = -ENOMEM;
3295 goto err_out;
3296 }
3297
3298 /* get SEC version capabilities from device tree */
fa14c6cf
LC		 3299 of_property_read_u32(np, "fsl,num-channels", &priv->num_channels);
3300 of_property_read_u32(np, "fsl,channel-fifo-len", &priv->chfifo_len);
3301 of_property_read_u32(np, "fsl,exec-units-mask", &priv->exec_units);
3302 of_property_read_u32(np, "fsl,descriptor-types-mask",
3303 &priv->desc_types);
9c4a7965
KP		 3304
3305 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
3306 !priv->exec_units || !priv->desc_types) {
3307 dev_err(dev, "invalid property data in device tree node\n");
3308 err = -EINVAL;
3309 goto err_out;
3310 }
3311
f3c85bc1
LN		 3312 if (of_device_is_compatible(np, "fsl,sec3.0"))
3313 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
3314
fe5720e2 3315 if (of_device_is_compatible(np, "fsl,sec2.1"))
60f208d7 3316 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
79b3a418
LN		 3317 TALITOS_FTR_SHA224_HWINIT |
3318 TALITOS_FTR_HMAC_OK;
fe5720e2 3319
21590888
LC		 3320 if (of_device_is_compatible(np, "fsl,sec1.0"))
3321 priv->features |= TALITOS_FTR_SEC1;
3322
5fa7fa14
LC		 3323 if (of_device_is_compatible(np, "fsl,sec1.2")) {
3324 priv->reg_deu = priv->reg + TALITOS12_DEU;
3325 priv->reg_aesu = priv->reg + TALITOS12_AESU;
3326 priv->reg_mdeu = priv->reg + TALITOS12_MDEU;
3327 stride = TALITOS1_CH_STRIDE;
3328 } else if (of_device_is_compatible(np, "fsl,sec1.0")) {
3329 priv->reg_deu = priv->reg + TALITOS10_DEU;
3330 priv->reg_aesu = priv->reg + TALITOS10_AESU;
3331 priv->reg_mdeu = priv->reg + TALITOS10_MDEU;
3332 priv->reg_afeu = priv->reg + TALITOS10_AFEU;
3333 priv->reg_rngu = priv->reg + TALITOS10_RNGU;
3334 priv->reg_pkeu = priv->reg + TALITOS10_PKEU;
3335 stride = TALITOS1_CH_STRIDE;
3336 } else {
3337 priv->reg_deu = priv->reg + TALITOS2_DEU;
3338 priv->reg_aesu = priv->reg + TALITOS2_AESU;
3339 priv->reg_mdeu = priv->reg + TALITOS2_MDEU;
3340 priv->reg_afeu = priv->reg + TALITOS2_AFEU;
3341 priv->reg_rngu = priv->reg + TALITOS2_RNGU;
3342 priv->reg_pkeu = priv->reg + TALITOS2_PKEU;
3343 priv->reg_keu = priv->reg + TALITOS2_KEU;
3344 priv->reg_crcu = priv->reg + TALITOS2_CRCU;
3345 stride = TALITOS2_CH_STRIDE;
3346 }
3347
dd3c0987
LC		 3348 err = talitos_probe_irq(ofdev);
3349 if (err)
3350 goto err_out;
3351
3352 if (of_device_is_compatible(np, "fsl,sec1.0")) {
9c02e285
LC		 3353 if (priv->num_channels == 1)
3354 tasklet_init(&priv->done_task[0], talitos1_done_ch0,
dd3c0987 3355 (unsigned long)dev);
9c02e285
LC		 3356 else
3357 tasklet_init(&priv->done_task[0], talitos1_done_4ch,
3358 (unsigned long)dev);
3359 } else {
3360 if (priv->irq[1]) {
dd3c0987
LC		 3361 tasklet_init(&priv->done_task[0], talitos2_done_ch0_2,
3362 (unsigned long)dev);
3363 tasklet_init(&priv->done_task[1], talitos2_done_ch1_3,
3364 (unsigned long)dev);
9c02e285
LC		 3365 } else if (priv->num_channels == 1) {
3366 tasklet_init(&priv->done_task[0], talitos2_done_ch0,
3367 (unsigned long)dev);
3368 } else {
3369 tasklet_init(&priv->done_task[0], talitos2_done_4ch,
3370 (unsigned long)dev);
dd3c0987
LC		 3371 }
3372 }
3373
a86854d0
KC		 3374 priv->chan = devm_kcalloc(dev,
3375 priv->num_channels,
3376 sizeof(struct talitos_channel),
3377 GFP_KERNEL);
4b992628
KP		 3378 if (!priv->chan) {
3379 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 3380 err = -ENOMEM;
3381 goto err_out;
3382 }
3383
f641dddd
MH		 3384 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
3385
c3e337f8 3386 for (i = 0; i < priv->num_channels; i++) {
5fa7fa14 3387 priv->chan[i].reg = priv->reg + stride * (i + 1);
2cdba3cf 3388 if (!priv->irq[1] || !(i & 1))
c3e337f8 3389 priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
ad42d5fc 3390
4b992628
KP		 3391 spin_lock_init(&priv->chan[i].head_lock);
3392 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965 3393
a86854d0
KC		 3394 priv->chan[i].fifo = devm_kcalloc(dev,
3395 priv->fifo_len,
3396 sizeof(struct talitos_request),
3397 GFP_KERNEL);
4b992628 3398 if (!priv->chan[i].fifo) {
9c4a7965
KP		 3399 dev_err(dev, "failed to allocate request fifo %d\n", i);
3400 err = -ENOMEM;
3401 goto err_out;
3402 }
9c4a7965 3403
4b992628
KP		 3404 atomic_set(&priv->chan[i].submit_count,
3405 -(priv->chfifo_len - 1));
f641dddd 3406 }
9c4a7965 3407
81eb024c
KP		 3408 dma_set_mask(dev, DMA_BIT_MASK(36));
3409
9c4a7965
KP		 3410 /* reset and initialize the h/w */
3411 err = init_device(dev);
3412 if (err) {
3413 dev_err(dev, "failed to initialize device\n");
3414 goto err_out;
3415 }
3416
3417 /* register the RNG, if available */
3418 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
3419 err = talitos_register_rng(dev);
3420 if (err) {
3421 dev_err(dev, "failed to register hwrng: %d\n", err);
3422 goto err_out;
3423 } else
3424 dev_info(dev, "hwrng\n");
3425 }
3426
3427 /* register crypto algorithms the device supports */
9c4a7965
KP		 3428 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
3429 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
3430 struct talitos_crypto_alg *t_alg;
aeb4c132 3431 struct crypto_alg *alg = NULL;
9c4a7965
KP		 3432
3433 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
3434 if (IS_ERR(t_alg)) {
3435 err = PTR_ERR(t_alg);
0b2730d8 3436 if (err == -ENOTSUPP)
79b3a418 3437 continue;
9c4a7965
KP		 3438 goto err_out;
3439 }
3440
acbf7c62
LN		 3441 switch (t_alg->algt.type) {
3442 case CRYPTO_ALG_TYPE_ABLKCIPHER:
acbf7c62
LN		 3443 err = crypto_register_alg(
3444 &t_alg->algt.alg.crypto);
aeb4c132 3445 alg = &t_alg->algt.alg.crypto;
acbf7c62 3446 break;
aeb4c132
HX		 3447
3448 case CRYPTO_ALG_TYPE_AEAD:
3449 err = crypto_register_aead(
3450 &t_alg->algt.alg.aead);
3451 alg = &t_alg->algt.alg.aead.base;
3452 break;
3453
acbf7c62
LN		 3454 case CRYPTO_ALG_TYPE_AHASH:
3455 err = crypto_register_ahash(
3456 &t_alg->algt.alg.hash);
aeb4c132 3457 alg = &t_alg->algt.alg.hash.halg.base;
acbf7c62
LN		 3458 break;
3459 }
9c4a7965
KP		 3460 if (err) {
3461 dev_err(dev, "%s alg registration failed\n",
aeb4c132 3462 alg->cra_driver_name);
24b92ff2 3463 devm_kfree(dev, t_alg);
991155ba 3464 } else
9c4a7965 3465 list_add_tail(&t_alg->entry, &priv->alg_list);
9c4a7965
KP		 3466 }
3467 }
5b859b6e
KP		 3468 if (!list_empty(&priv->alg_list))
3469 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
3470 (char *)of_get_property(np, "compatible", NULL));
9c4a7965
KP		 3471
3472 return 0;
3473
3474err_out:
3475 talitos_remove(ofdev);
9c4a7965
KP		 3476
3477 return err;
3478}
3479
6c3f975a 3480static const struct of_device_id talitos_match[] = {
0635b7db
LC		 3481#ifdef CONFIG_CRYPTO_DEV_TALITOS1
3482 {
3483 .compatible = "fsl,sec1.0",
3484 },
3485#endif
3486#ifdef CONFIG_CRYPTO_DEV_TALITOS2
9c4a7965
KP		 3487 {
3488 .compatible = "fsl,sec2.0",
3489 },
0635b7db 3490#endif
9c4a7965
KP		 3491 {},
3492};
3493MODULE_DEVICE_TABLE(of, talitos_match);
3494
1c48a5c9 3495static struct platform_driver talitos_driver = {
4018294b
GL		 3496 .driver = {
3497 .name = "talitos",
4018294b
GL		 3498 .of_match_table = talitos_match,
3499 },
9c4a7965 3500 .probe = talitos_probe,
596f1034 3501 .remove = talitos_remove,
9c4a7965
KP		 3502};
3503
741e8c2d 3504module_platform_driver(talitos_driver);
9c4a7965
KP		 3505
3506MODULE_LICENSE("GPL");
3507MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
3508MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Linux 6.x block layer and io_uring tree(s)