[linux-block.git] / drivers / crypto / stm32 / stm32-crc32.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) STMicroelectronics SA 2017
 * Author: Fabien Dessenne <fabien.dessenne@st.com>
 */

#include <linux/bitrev.h>
#include <linux/clk.h>
#include <linux/crc32poly.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

#include <crypto/internal/hash.h>

#include <asm/unaligned.h>

#define DRIVER_NAME             "stm32-crc32"
#define CHKSUM_DIGEST_SIZE      4
#define CHKSUM_BLOCK_SIZE       1

/* Registers */
#define CRC_DR                  0x00000000
#define CRC_CR                  0x00000008
#define CRC_INIT                0x00000010
#define CRC_POL                 0x00000014

/* Registers values */
#define CRC_CR_RESET            BIT(0)
#define CRC_CR_REVERSE          (BIT(7) | BIT(6) | BIT(5))
#define CRC_INIT_DEFAULT        0xFFFFFFFF

#define CRC_AUTOSUSPEND_DELAY	50

struct stm32_crc {
	struct list_head list;
	struct device    *dev;
	void __iomem     *regs;
	struct clk       *clk;
	u8               pending_data[sizeof(u32)];
	size_t           nb_pending_bytes;
};

struct stm32_crc_list {
	struct list_head dev_list;
	spinlock_t       lock; /* protect dev_list */
};

static struct stm32_crc_list crc_list = {
	.dev_list = LIST_HEAD_INIT(crc_list.dev_list),
	.lock     = __SPIN_LOCK_UNLOCKED(crc_list.lock),
};

struct stm32_crc_ctx {
	u32 key;
	u32 poly;
};

struct stm32_crc_desc_ctx {
	u32    partial; /* crc32c: partial in first 4 bytes of that struct */
	struct stm32_crc *crc;
};

static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
{
	struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);

	mctx->key = CRC_INIT_DEFAULT;
	mctx->poly = CRC32_POLY_LE;
	return 0;
}

static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
{
	struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);

	mctx->key = CRC_INIT_DEFAULT;
	mctx->poly = CRC32C_POLY_LE;
	return 0;
}

static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
			    unsigned int keylen)
{
	struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);

	if (keylen != sizeof(u32))
		return -EINVAL;

	mctx->key = get_unaligned_le32(key);
	return 0;
}

static int stm32_crc_init(struct shash_desc *desc)
{
	struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
	struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
	struct stm32_crc *crc;

	spin_lock_bh(&crc_list.lock);
	list_for_each_entry(crc, &crc_list.dev_list, list) {
		ctx->crc = crc;
		break;
	}
	spin_unlock_bh(&crc_list.lock);

	pm_runtime_get_sync(ctx->crc->dev);

	/* Reset, set key, poly and configure in bit reverse mode */
	writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
	writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
	writel_relaxed(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);

	/* Store partial result */
	ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR);
	ctx->crc->nb_pending_bytes = 0;

	pm_runtime_mark_last_busy(ctx->crc->dev);
	pm_runtime_put_autosuspend(ctx->crc->dev);

	return 0;
}

static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
			    unsigned int length)
{
	struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
	struct stm32_crc *crc = ctx->crc;
	u32 *d32;
	unsigned int i;

	pm_runtime_get_sync(crc->dev);

	if (unlikely(crc->nb_pending_bytes)) {
		while (crc->nb_pending_bytes != sizeof(u32) && length) {
			/* Fill in pending data */
			crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
			length--;
		}

		if (crc->nb_pending_bytes == sizeof(u32)) {
			/* Process completed pending data */
			writel_relaxed(*(u32 *)crc->pending_data,
				       crc->regs + CRC_DR);
			crc->nb_pending_bytes = 0;
		}
	}

	d32 = (u32 *)d8;
	for (i = 0; i < length >> 2; i++)
		/* Process 32 bits data */
		writel_relaxed(*(d32++), crc->regs + CRC_DR);

	/* Store partial result */
	ctx->partial = readl_relaxed(crc->regs + CRC_DR);

	pm_runtime_mark_last_busy(crc->dev);
	pm_runtime_put_autosuspend(crc->dev);

	/* Check for pending data (non 32 bits) */
	length &= 3;
	if (likely(!length))
		return 0;

	if ((crc->nb_pending_bytes + length) >= sizeof(u32)) {
		/* Shall not happen */
		dev_err(crc->dev, "Pending data overflow\n");
		return -EINVAL;
	}

	d8 = (const u8 *)d32;
	for (i = 0; i < length; i++)
		/* Store pending data */
		crc->pending_data[crc->nb_pending_bytes++] = *(d8++);

	return 0;
}

static int stm32_crc_final(struct shash_desc *desc, u8 *out)
{
	struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
	struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);

	/* Send computed CRC */
	put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
			   ~ctx->partial : ctx->partial, out);

	return 0;
}

static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
			   unsigned int length, u8 *out)
{
	return stm32_crc_update(desc, data, length) ?:
	       stm32_crc_final(desc, out);
}

static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
			    unsigned int length, u8 *out)
{
	return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
}

static struct shash_alg algs[] = {
	/* CRC-32 */
	{
		.setkey         = stm32_crc_setkey,
		.init           = stm32_crc_init,
		.update         = stm32_crc_update,
		.final          = stm32_crc_final,
		.finup          = stm32_crc_finup,
		.digest         = stm32_crc_digest,
		.descsize       = sizeof(struct stm32_crc_desc_ctx),
		.digestsize     = CHKSUM_DIGEST_SIZE,
		.base           = {
			.cra_name               = "crc32",
			.cra_driver_name        = DRIVER_NAME,
			.cra_priority           = 200,
			.cra_flags		= CRYPTO_ALG_OPTIONAL_KEY,
			.cra_blocksize          = CHKSUM_BLOCK_SIZE,
			.cra_alignmask          = 3,
			.cra_ctxsize            = sizeof(struct stm32_crc_ctx),
			.cra_module             = THIS_MODULE,
			.cra_init               = stm32_crc32_cra_init,
		}
	},
	/* CRC-32Castagnoli */
	{
		.setkey         = stm32_crc_setkey,
		.init           = stm32_crc_init,
		.update         = stm32_crc_update,
		.final          = stm32_crc_final,
		.finup          = stm32_crc_finup,
		.digest         = stm32_crc_digest,
		.descsize       = sizeof(struct stm32_crc_desc_ctx),
		.digestsize     = CHKSUM_DIGEST_SIZE,
		.base           = {
			.cra_name               = "crc32c",
			.cra_driver_name        = DRIVER_NAME,
			.cra_priority           = 200,
			.cra_flags		= CRYPTO_ALG_OPTIONAL_KEY,
			.cra_blocksize          = CHKSUM_BLOCK_SIZE,
			.cra_alignmask          = 3,
			.cra_ctxsize            = sizeof(struct stm32_crc_ctx),
			.cra_module             = THIS_MODULE,
			.cra_init               = stm32_crc32c_cra_init,
		}
	}
};

static int stm32_crc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct stm32_crc *crc;
	int ret;

	crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
	if (!crc)
		return -ENOMEM;

	crc->dev = dev;

	crc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(crc->regs)) {
		dev_err(dev, "Cannot map CRC IO\n");
		return PTR_ERR(crc->regs);
	}

	crc->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(crc->clk)) {
		dev_err(dev, "Could not get clock\n");
		return PTR_ERR(crc->clk);
	}

	ret = clk_prepare_enable(crc->clk);
	if (ret) {
		dev_err(crc->dev, "Failed to enable clock\n");
		return ret;
	}

	pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
	pm_runtime_use_autosuspend(dev);

	pm_runtime_get_noresume(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	platform_set_drvdata(pdev, crc);

	spin_lock(&crc_list.lock);
	list_add(&crc->list, &crc_list.dev_list);
	spin_unlock(&crc_list.lock);

	ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
	if (ret) {
		dev_err(dev, "Failed to register\n");
		clk_disable_unprepare(crc->clk);
		return ret;
	}

	dev_info(dev, "Initialized\n");

	pm_runtime_put_sync(dev);

	return 0;
}

static int stm32_crc_remove(struct platform_device *pdev)
{
	struct stm32_crc *crc = platform_get_drvdata(pdev);
	int ret = pm_runtime_get_sync(crc->dev);

	if (ret < 0)
		return ret;

	spin_lock(&crc_list.lock);
	list_del(&crc->list);
	spin_unlock(&crc_list.lock);

	crypto_unregister_shashes(algs, ARRAY_SIZE(algs));

	pm_runtime_disable(crc->dev);
	pm_runtime_put_noidle(crc->dev);

	clk_disable_unprepare(crc->clk);

	return 0;
}

#ifdef CONFIG_PM
static int stm32_crc_runtime_suspend(struct device *dev)
{
	struct stm32_crc *crc = dev_get_drvdata(dev);

	clk_disable_unprepare(crc->clk);

	return 0;
}

static int stm32_crc_runtime_resume(struct device *dev)
{
	struct stm32_crc *crc = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(crc->clk);
	if (ret) {
		dev_err(crc->dev, "Failed to prepare_enable clock\n");
		return ret;
	}

	return 0;
}
#endif

static const struct dev_pm_ops stm32_crc_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				pm_runtime_force_resume)
	SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
			   stm32_crc_runtime_resume, NULL)
};

static const struct of_device_id stm32_dt_ids[] = {
	{ .compatible = "st,stm32f7-crc", },
	{},
};
MODULE_DEVICE_TABLE(of, stm32_dt_ids);

static struct platform_driver stm32_crc_driver = {
	.probe  = stm32_crc_probe,
	.remove = stm32_crc_remove,
	.driver = {
		.name           = DRIVER_NAME,
		.pm		= &stm32_crc_pm_ops,
		.of_match_table = stm32_dt_ids,
	},
};

module_platform_driver(stm32_crc_driver);

MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
af873fce	1	// SPDX-License-Identifier: GPL-2.0-only
b51dbe90 FD	2	/*
	3	* Copyright (C) STMicroelectronics SA 2017
	4	* Author: Fabien Dessenne <fabien.dessenne@st.com>
b51dbe90 FD	5	*/
	6
	7	#include <linux/bitrev.h>
	8	#include <linux/clk.h>
f7aee878	9	#include <linux/crc32poly.h>
b51dbe90	10	#include <linux/module.h>
ac316725	11	#include <linux/mod_devicetable.h>
b51dbe90	12	#include <linux/platform_device.h>
73463ade	13	#include <linux/pm_runtime.h>
b51dbe90 FD	14
	15	#include <crypto/internal/hash.h>
	16
	17	#include <asm/unaligned.h>
	18
	19	#define DRIVER_NAME "stm32-crc32"
	20	#define CHKSUM_DIGEST_SIZE 4
	21	#define CHKSUM_BLOCK_SIZE 1
	22
	23	/* Registers */
	24	#define CRC_DR 0x00000000
	25	#define CRC_CR 0x00000008
	26	#define CRC_INIT 0x00000010
	27	#define CRC_POL 0x00000014
	28
	29	/* Registers values */
	30	#define CRC_CR_RESET BIT(0)
	31	#define CRC_CR_REVERSE (BIT(7) \| BIT(6) \| BIT(5))
	32	#define CRC_INIT_DEFAULT 0xFFFFFFFF
	33
73463ade	34	#define CRC_AUTOSUSPEND_DELAY 50
73463ade	35
b51dbe90 FD	36	struct stm32_crc {
	37	struct list_head list;
	38	struct device *dev;
	39	void __iomem *regs;
	40	struct clk *clk;
	41	u8 pending_data[sizeof(u32)];
	42	size_t nb_pending_bytes;
	43	};
	44
	45	struct stm32_crc_list {
	46	struct list_head dev_list;
	47	spinlock_t lock; /* protect dev_list */
	48	};
	49
	50	static struct stm32_crc_list crc_list = {
	51	.dev_list = LIST_HEAD_INIT(crc_list.dev_list),
	52	.lock = __SPIN_LOCK_UNLOCKED(crc_list.lock),
	53	};
	54
	55	struct stm32_crc_ctx {
	56	u32 key;
	57	u32 poly;
	58	};
	59
	60	struct stm32_crc_desc_ctx {
	61	u32 partial; /* crc32c: partial in first 4 bytes of that struct */
	62	struct stm32_crc *crc;
	63	};
	64
	65	static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
	66	{
	67	struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
	68
	69	mctx->key = CRC_INIT_DEFAULT;
f7aee878	70	mctx->poly = CRC32_POLY_LE;
b51dbe90 FD	71	return 0;
	72	}
	73
	74	static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
	75	{
	76	struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
	77
	78	mctx->key = CRC_INIT_DEFAULT;
f7aee878	79	mctx->poly = CRC32C_POLY_LE;
b51dbe90 FD	80	return 0;
	81	}
	82
	83	static int stm32_crc_setkey(struct crypto_shash tfm, const u8 key,
	84	unsigned int keylen)
	85	{
	86	struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
	87
674f368a	88	if (keylen != sizeof(u32))
b51dbe90	89	return -EINVAL;
b51dbe90 FD	90
	91	mctx->key = get_unaligned_le32(key);
	92	return 0;
	93	}
	94
	95	static int stm32_crc_init(struct shash_desc *desc)
	96	{
	97	struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
	98	struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
	99	struct stm32_crc *crc;
	100
	101	spin_lock_bh(&crc_list.lock);
	102	list_for_each_entry(crc, &crc_list.dev_list, list) {
	103	ctx->crc = crc;
	104	break;
	105	}
	106	spin_unlock_bh(&crc_list.lock);
	107
73463ade	108	pm_runtime_get_sync(ctx->crc->dev);
73463ade	109
b51dbe90	110	/* Reset, set key, poly and configure in bit reverse mode */
39177519	111	writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
	112	writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
	113	writel_relaxed(CRC_CR_RESET \| CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
b51dbe90 FD	114
b51dbe90 FD	115	/* Store partial result */
39177519	116	ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR);
b51dbe90 FD	117	ctx->crc->nb_pending_bytes = 0;
b51dbe90 FD	118
73463ade	119	pm_runtime_mark_last_busy(ctx->crc->dev);
	120	pm_runtime_put_autosuspend(ctx->crc->dev);
	121
b51dbe90 FD	122	return 0;
	123	}
	124
	125	static int stm32_crc_update(struct shash_desc desc, const u8 d8,
	126	unsigned int length)
	127	{
	128	struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
	129	struct stm32_crc *crc = ctx->crc;
	130	u32 *d32;
	131	unsigned int i;
	132
73463ade	133	pm_runtime_get_sync(crc->dev);
73463ade	134
b51dbe90 FD	135	if (unlikely(crc->nb_pending_bytes)) {
	136	while (crc->nb_pending_bytes != sizeof(u32) && length) {
	137	/* Fill in pending data */
	138	crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
	139	length--;
	140	}
	141
	142	if (crc->nb_pending_bytes == sizeof(u32)) {
	143	/* Process completed pending data */
39177519	144	writel_relaxed((u32 )crc->pending_data,
39177519	145	crc->regs + CRC_DR);
b51dbe90 FD	146	crc->nb_pending_bytes = 0;
	147	}
	148	}
	149
	150	d32 = (u32 *)d8;
	151	for (i = 0; i < length >> 2; i++)
	152	/* Process 32 bits data */
39177519	153	writel_relaxed(*(d32++), crc->regs + CRC_DR);
b51dbe90 FD	154
b51dbe90 FD	155	/* Store partial result */
39177519	156	ctx->partial = readl_relaxed(crc->regs + CRC_DR);
b51dbe90	157
73463ade	158	pm_runtime_mark_last_busy(crc->dev);
	159	pm_runtime_put_autosuspend(crc->dev);
	160
b51dbe90 FD	161	/* Check for pending data (non 32 bits) */
	162	length &= 3;
	163	if (likely(!length))
	164	return 0;
	165
	166	if ((crc->nb_pending_bytes + length) >= sizeof(u32)) {
	167	/* Shall not happen */
	168	dev_err(crc->dev, "Pending data overflow\n");
	169	return -EINVAL;
	170	}
	171
	172	d8 = (const u8 *)d32;
	173	for (i = 0; i < length; i++)
	174	/* Store pending data */
	175	crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
	176
	177	return 0;
	178	}
	179
	180	static int stm32_crc_final(struct shash_desc desc, u8 out)
	181	{
	182	struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
	183	struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
	184
	185	/* Send computed CRC */
f7aee878	186	put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
b51dbe90 FD	187	~ctx->partial : ctx->partial, out);
	188
	189	return 0;
	190	}
	191
	192	static int stm32_crc_finup(struct shash_desc desc, const u8 data,
	193	unsigned int length, u8 *out)
	194	{
	195	return stm32_crc_update(desc, data, length) ?:
	196	stm32_crc_final(desc, out);
	197	}
	198
	199	static int stm32_crc_digest(struct shash_desc desc, const u8 data,
	200	unsigned int length, u8 *out)
	201	{
	202	return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
	203	}
	204
	205	static struct shash_alg algs[] = {
	206	/* CRC-32 */
	207	{
	208	.setkey = stm32_crc_setkey,
	209	.init = stm32_crc_init,
	210	.update = stm32_crc_update,
	211	.final = stm32_crc_final,
	212	.finup = stm32_crc_finup,
	213	.digest = stm32_crc_digest,
	214	.descsize = sizeof(struct stm32_crc_desc_ctx),
	215	.digestsize = CHKSUM_DIGEST_SIZE,
	216	.base = {
	217	.cra_name = "crc32",
	218	.cra_driver_name = DRIVER_NAME,
	219	.cra_priority = 200,
a208fa8f	220	.cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
b51dbe90 FD	221	.cra_blocksize = CHKSUM_BLOCK_SIZE,
	222	.cra_alignmask = 3,
	223	.cra_ctxsize = sizeof(struct stm32_crc_ctx),
	224	.cra_module = THIS_MODULE,
	225	.cra_init = stm32_crc32_cra_init,
	226	}
	227	},
	228	/* CRC-32Castagnoli */
	229	{
	230	.setkey = stm32_crc_setkey,
	231	.init = stm32_crc_init,
	232	.update = stm32_crc_update,
	233	.final = stm32_crc_final,
	234	.finup = stm32_crc_finup,
	235	.digest = stm32_crc_digest,
	236	.descsize = sizeof(struct stm32_crc_desc_ctx),
	237	.digestsize = CHKSUM_DIGEST_SIZE,
	238	.base = {
	239	.cra_name = "crc32c",
	240	.cra_driver_name = DRIVER_NAME,
	241	.cra_priority = 200,
a208fa8f	242	.cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
b51dbe90 FD	243	.cra_blocksize = CHKSUM_BLOCK_SIZE,
	244	.cra_alignmask = 3,
	245	.cra_ctxsize = sizeof(struct stm32_crc_ctx),
	246	.cra_module = THIS_MODULE,
	247	.cra_init = stm32_crc32c_cra_init,
	248	}
	249	}
	250	};
	251
	252	static int stm32_crc_probe(struct platform_device *pdev)
	253	{
	254	struct device *dev = &pdev->dev;
	255	struct stm32_crc *crc;
b51dbe90 FD	256	int ret;
	257
	258	crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
	259	if (!crc)
	260	return -ENOMEM;
	261
	262	crc->dev = dev;
	263
473b4d99	264	crc->regs = devm_platform_ioremap_resource(pdev, 0);
b51dbe90 FD	265	if (IS_ERR(crc->regs)) {
	266	dev_err(dev, "Cannot map CRC IO\n");
	267	return PTR_ERR(crc->regs);
	268	}
	269
	270	crc->clk = devm_clk_get(dev, NULL);
	271	if (IS_ERR(crc->clk)) {
	272	dev_err(dev, "Could not get clock\n");
	273	return PTR_ERR(crc->clk);
	274	}
	275
	276	ret = clk_prepare_enable(crc->clk);
	277	if (ret) {
	278	dev_err(crc->dev, "Failed to enable clock\n");
	279	return ret;
	280	}
	281
73463ade	282	pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
	283	pm_runtime_use_autosuspend(dev);
	284
	285	pm_runtime_get_noresume(dev);
	286	pm_runtime_set_active(dev);
	287	pm_runtime_enable(dev);
	288
b51dbe90 FD	289	platform_set_drvdata(pdev, crc);
	290
	291	spin_lock(&crc_list.lock);
	292	list_add(&crc->list, &crc_list.dev_list);
	293	spin_unlock(&crc_list.lock);
	294
	295	ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
	296	if (ret) {
	297	dev_err(dev, "Failed to register\n");
	298	clk_disable_unprepare(crc->clk);
	299	return ret;
	300	}
	301
	302	dev_info(dev, "Initialized\n");
	303
73463ade	304	pm_runtime_put_sync(dev);
73463ade	305
b51dbe90 FD	306	return 0;
	307	}
	308
	309	static int stm32_crc_remove(struct platform_device *pdev)
	310	{
	311	struct stm32_crc *crc = platform_get_drvdata(pdev);
73463ade	312	int ret = pm_runtime_get_sync(crc->dev);
	313
	314	if (ret < 0)
	315	return ret;
b51dbe90 FD	316
	317	spin_lock(&crc_list.lock);
	318	list_del(&crc->list);
	319	spin_unlock(&crc_list.lock);
	320
0373d085	321	crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
b51dbe90	322
73463ade	323	pm_runtime_disable(crc->dev);
	324	pm_runtime_put_noidle(crc->dev);
	325
b51dbe90 FD	326	clk_disable_unprepare(crc->clk);
	327
	328	return 0;
	329	}
	330
73463ade	331	#ifdef CONFIG_PM
	332	static int stm32_crc_runtime_suspend(struct device *dev)
	333	{
	334	struct stm32_crc *crc = dev_get_drvdata(dev);
	335
	336	clk_disable_unprepare(crc->clk);
	337
	338	return 0;
	339	}
	340
	341	static int stm32_crc_runtime_resume(struct device *dev)
	342	{
	343	struct stm32_crc *crc = dev_get_drvdata(dev);
	344	int ret;
	345
	346	ret = clk_prepare_enable(crc->clk);
	347	if (ret) {
	348	dev_err(crc->dev, "Failed to prepare_enable clock\n");
	349	return ret;
	350	}
	351
	352	return 0;
	353	}
	354	#endif
	355
	356	static const struct dev_pm_ops stm32_crc_pm_ops = {
	357	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	358	pm_runtime_force_resume)
	359	SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
	360	stm32_crc_runtime_resume, NULL)
	361	};
	362
b51dbe90 FD	363	static const struct of_device_id stm32_dt_ids[] = {
	364	{ .compatible = "st,stm32f7-crc", },
	365	{},
	366	};
929562b1	367	MODULE_DEVICE_TABLE(of, stm32_dt_ids);
b51dbe90 FD	368
	369	static struct platform_driver stm32_crc_driver = {
	370	.probe = stm32_crc_probe,
	371	.remove = stm32_crc_remove,
	372	.driver = {
	373	.name = DRIVER_NAME,
73463ade	374	.pm = &stm32_crc_pm_ops,
b51dbe90 FD	375	.of_match_table = stm32_dt_ids,
	376	},
	377	};
	378
	379	module_platform_driver(stm32_crc_driver);
	380
	381	MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
	382	MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
	383	MODULE_LICENSE("GPL");