[linux-2.6-block.git] / drivers / crypto / rockchip / rk3288_crypto.c

/*
 * Crypto acceleration support for Rockchip RK3288
 *
 * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
 *
 * Author: Zain Wang <zain.wang@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * Some ideas are from marvell-cesa.c and s5p-sss.c driver.
 */

#include "rk3288_crypto.h"
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/crypto.h>
#include <linux/reset.h>

static int rk_crypto_enable_clk(struct rk_crypto_info *dev)
{
	int err;

	err = clk_prepare_enable(dev->sclk);
	if (err) {
		dev_err(dev->dev, "[%s:%d], Couldn't enable clock sclk\n",
			__func__, __LINE__);
		goto err_return;
	}
	err = clk_prepare_enable(dev->aclk);
	if (err) {
		dev_err(dev->dev, "[%s:%d], Couldn't enable clock aclk\n",
			__func__, __LINE__);
		goto err_aclk;
	}
	err = clk_prepare_enable(dev->hclk);
	if (err) {
		dev_err(dev->dev, "[%s:%d], Couldn't enable clock hclk\n",
			__func__, __LINE__);
		goto err_hclk;
	}
	err = clk_prepare_enable(dev->dmaclk);
	if (err) {
		dev_err(dev->dev, "[%s:%d], Couldn't enable clock dmaclk\n",
			__func__, __LINE__);
		goto err_dmaclk;
	}
	return err;
err_dmaclk:
	clk_disable_unprepare(dev->hclk);
err_hclk:
	clk_disable_unprepare(dev->aclk);
err_aclk:
	clk_disable_unprepare(dev->sclk);
err_return:
	return err;
}

static void rk_crypto_disable_clk(struct rk_crypto_info *dev)
{
	clk_disable_unprepare(dev->dmaclk);
	clk_disable_unprepare(dev->hclk);
	clk_disable_unprepare(dev->aclk);
	clk_disable_unprepare(dev->sclk);
}

static int check_alignment(struct scatterlist *sg_src,
			   struct scatterlist *sg_dst,
			   int align_mask)
{
	int in, out, align;

	in = IS_ALIGNED((uint32_t)sg_src->offset, 4) &&
	     IS_ALIGNED((uint32_t)sg_src->length, align_mask);
	if (!sg_dst)
		return in;
	out = IS_ALIGNED((uint32_t)sg_dst->offset, 4) &&
	      IS_ALIGNED((uint32_t)sg_dst->length, align_mask);
	align = in && out;

	return (align && (sg_src->length == sg_dst->length));
}

static int rk_load_data(struct rk_crypto_info *dev,
			struct scatterlist *sg_src,
			struct scatterlist *sg_dst)
{
	unsigned int count;

	dev->aligned = dev->aligned ?
		check_alignment(sg_src, sg_dst, dev->align_size) :
		dev->aligned;
	if (dev->aligned) {
		count = min(dev->left_bytes, sg_src->length);
		dev->left_bytes -= count;

		if (!dma_map_sg(dev->dev, sg_src, 1, DMA_TO_DEVICE)) {
			dev_err(dev->dev, "[%s:%d] dma_map_sg(src)  error\n",
				__func__, __LINE__);
			return -EINVAL;
		}
		dev->addr_in = sg_dma_address(sg_src);

		if (sg_dst) {
			if (!dma_map_sg(dev->dev, sg_dst, 1, DMA_FROM_DEVICE)) {
				dev_err(dev->dev,
					"[%s:%d] dma_map_sg(dst)  error\n",
					__func__, __LINE__);
				dma_unmap_sg(dev->dev, sg_src, 1,
					     DMA_TO_DEVICE);
				return -EINVAL;
			}
			dev->addr_out = sg_dma_address(sg_dst);
		}
	} else {
		count = (dev->left_bytes > PAGE_SIZE) ?
			PAGE_SIZE : dev->left_bytes;

		if (!sg_pcopy_to_buffer(dev->first, dev->src_nents,
					dev->addr_vir, count,
					dev->total - dev->left_bytes)) {
			dev_err(dev->dev, "[%s:%d] pcopy err\n",
				__func__, __LINE__);
			return -EINVAL;
		}
		dev->left_bytes -= count;
		sg_init_one(&dev->sg_tmp, dev->addr_vir, count);
		if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1, DMA_TO_DEVICE)) {
			dev_err(dev->dev, "[%s:%d] dma_map_sg(sg_tmp)  error\n",
				__func__, __LINE__);
			return -ENOMEM;
		}
		dev->addr_in = sg_dma_address(&dev->sg_tmp);

		if (sg_dst) {
			if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1,
					DMA_FROM_DEVICE)) {
				dev_err(dev->dev,
					"[%s:%d] dma_map_sg(sg_tmp)  error\n",
					__func__, __LINE__);
				dma_unmap_sg(dev->dev, &dev->sg_tmp, 1,
					     DMA_TO_DEVICE);
				return -ENOMEM;
			}
			dev->addr_out = sg_dma_address(&dev->sg_tmp);
		}
	}
	dev->count = count;
	return 0;
}

static void rk_unload_data(struct rk_crypto_info *dev)
{
	struct scatterlist *sg_in, *sg_out;

	sg_in = dev->aligned ? dev->sg_src : &dev->sg_tmp;
	dma_unmap_sg(dev->dev, sg_in, 1, DMA_TO_DEVICE);

	if (dev->sg_dst) {
		sg_out = dev->aligned ? dev->sg_dst : &dev->sg_tmp;
		dma_unmap_sg(dev->dev, sg_out, 1, DMA_FROM_DEVICE);
	}
}

static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id)
{
	struct rk_crypto_info *dev  = platform_get_drvdata(dev_id);
	u32 interrupt_status;

	spin_lock(&dev->lock);
	interrupt_status = CRYPTO_READ(dev, RK_CRYPTO_INTSTS);
	CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, interrupt_status);

	if (interrupt_status & 0x0a) {
		dev_warn(dev->dev, "DMA Error\n");
		dev->err = -EFAULT;
	}
	tasklet_schedule(&dev->done_task);

	spin_unlock(&dev->lock);
	return IRQ_HANDLED;
}

static int rk_crypto_enqueue(struct rk_crypto_info *dev,
			      struct crypto_async_request *async_req)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&dev->lock, flags);
	ret = crypto_enqueue_request(&dev->queue, async_req);
	if (dev->busy) {
		spin_unlock_irqrestore(&dev->lock, flags);
		return ret;
	}
	dev->busy = true;
	spin_unlock_irqrestore(&dev->lock, flags);
	tasklet_schedule(&dev->queue_task);

	return ret;
}

static void rk_crypto_queue_task_cb(unsigned long data)
{
	struct rk_crypto_info *dev = (struct rk_crypto_info *)data;
	struct crypto_async_request *async_req, *backlog;
	unsigned long flags;
	int err = 0;

	dev->err = 0;
	spin_lock_irqsave(&dev->lock, flags);
	backlog   = crypto_get_backlog(&dev->queue);
	async_req = crypto_dequeue_request(&dev->queue);

	if (!async_req) {
		dev->busy = false;
		spin_unlock_irqrestore(&dev->lock, flags);
		return;
	}
	spin_unlock_irqrestore(&dev->lock, flags);

	if (backlog) {
		backlog->complete(backlog, -EINPROGRESS);
		backlog = NULL;
	}

	dev->async_req = async_req;
	err = dev->start(dev);
	if (err)
		dev->complete(dev->async_req, err);
}

static void rk_crypto_done_task_cb(unsigned long data)
{
	struct rk_crypto_info *dev = (struct rk_crypto_info *)data;

	if (dev->err) {
		dev->complete(dev->async_req, dev->err);
		return;
	}

	dev->err = dev->update(dev);
	if (dev->err)
		dev->complete(dev->async_req, dev->err);
}

static struct rk_crypto_tmp *rk_cipher_algs[] = {
	&rk_ecb_aes_alg,
	&rk_cbc_aes_alg,
	&rk_ecb_des_alg,
	&rk_cbc_des_alg,
	&rk_ecb_des3_ede_alg,
	&rk_cbc_des3_ede_alg,
	&rk_ahash_sha1,
	&rk_ahash_sha256,
	&rk_ahash_md5,
};

static int rk_crypto_register(struct rk_crypto_info *crypto_info)
{
	unsigned int i, k;
	int err = 0;

	for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
		rk_cipher_algs[i]->dev = crypto_info;
		if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
			err = crypto_register_alg(
					&rk_cipher_algs[i]->alg.crypto);
		else
			err = crypto_register_ahash(
					&rk_cipher_algs[i]->alg.hash);
		if (err)
			goto err_cipher_algs;
	}
	return 0;

err_cipher_algs:
	for (k = 0; k < i; k++) {
		if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
			crypto_unregister_alg(&rk_cipher_algs[k]->alg.crypto);
		else
			crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash);
	}
	return err;
}

static void rk_crypto_unregister(void)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
		if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
			crypto_unregister_alg(&rk_cipher_algs[i]->alg.crypto);
		else
			crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash);
	}
}

static void rk_crypto_action(void *data)
{
	struct rk_crypto_info *crypto_info = data;

	reset_control_assert(crypto_info->rst);
}

static const struct of_device_id crypto_of_id_table[] = {
	{ .compatible = "rockchip,rk3288-crypto" },
	{}
};
MODULE_DEVICE_TABLE(of, crypto_of_id_table);

static int rk_crypto_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct device *dev = &pdev->dev;
	struct rk_crypto_info *crypto_info;
	int err = 0;

	crypto_info = devm_kzalloc(&pdev->dev,
				   sizeof(*crypto_info), GFP_KERNEL);
	if (!crypto_info) {
		err = -ENOMEM;
		goto err_crypto;
	}

	crypto_info->rst = devm_reset_control_get(dev, "crypto-rst");
	if (IS_ERR(crypto_info->rst)) {
		err = PTR_ERR(crypto_info->rst);
		goto err_crypto;
	}

	reset_control_assert(crypto_info->rst);
	usleep_range(10, 20);
	reset_control_deassert(crypto_info->rst);

	err = devm_add_action_or_reset(dev, rk_crypto_action, crypto_info);
	if (err)
		goto err_crypto;

	spin_lock_init(&crypto_info->lock);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	crypto_info->reg = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(crypto_info->reg)) {
		err = PTR_ERR(crypto_info->reg);
		goto err_crypto;
	}

	crypto_info->aclk = devm_clk_get(&pdev->dev, "aclk");
	if (IS_ERR(crypto_info->aclk)) {
		err = PTR_ERR(crypto_info->aclk);
		goto err_crypto;
	}

	crypto_info->hclk = devm_clk_get(&pdev->dev, "hclk");
	if (IS_ERR(crypto_info->hclk)) {
		err = PTR_ERR(crypto_info->hclk);
		goto err_crypto;
	}

	crypto_info->sclk = devm_clk_get(&pdev->dev, "sclk");
	if (IS_ERR(crypto_info->sclk)) {
		err = PTR_ERR(crypto_info->sclk);
		goto err_crypto;
	}

	crypto_info->dmaclk = devm_clk_get(&pdev->dev, "apb_pclk");
	if (IS_ERR(crypto_info->dmaclk)) {
		err = PTR_ERR(crypto_info->dmaclk);
		goto err_crypto;
	}

	crypto_info->irq = platform_get_irq(pdev, 0);
	if (crypto_info->irq < 0) {
		dev_warn(crypto_info->dev,
			 "control Interrupt is not available.\n");
		err = crypto_info->irq;
		goto err_crypto;
	}

	err = devm_request_irq(&pdev->dev, crypto_info->irq,
			       rk_crypto_irq_handle, IRQF_SHARED,
			       "rk-crypto", pdev);

	if (err) {
		dev_err(crypto_info->dev, "irq request failed.\n");
		goto err_crypto;
	}

	crypto_info->dev = &pdev->dev;
	platform_set_drvdata(pdev, crypto_info);

	tasklet_init(&crypto_info->queue_task,
		     rk_crypto_queue_task_cb, (unsigned long)crypto_info);
	tasklet_init(&crypto_info->done_task,
		     rk_crypto_done_task_cb, (unsigned long)crypto_info);
	crypto_init_queue(&crypto_info->queue, 50);

	crypto_info->enable_clk = rk_crypto_enable_clk;
	crypto_info->disable_clk = rk_crypto_disable_clk;
	crypto_info->load_data = rk_load_data;
	crypto_info->unload_data = rk_unload_data;
	crypto_info->enqueue = rk_crypto_enqueue;
	crypto_info->busy = false;

	err = rk_crypto_register(crypto_info);
	if (err) {
		dev_err(dev, "err in register alg");
		goto err_register_alg;
	}

	dev_info(dev, "Crypto Accelerator successfully registered\n");
	return 0;

err_register_alg:
	tasklet_kill(&crypto_info->queue_task);
	tasklet_kill(&crypto_info->done_task);
err_crypto:
	return err;
}

static int rk_crypto_remove(struct platform_device *pdev)
{
	struct rk_crypto_info *crypto_tmp = platform_get_drvdata(pdev);

	rk_crypto_unregister();
	tasklet_kill(&crypto_tmp->done_task);
	tasklet_kill(&crypto_tmp->queue_task);
	return 0;
}

static struct platform_driver crypto_driver = {
	.probe		= rk_crypto_probe,
	.remove		= rk_crypto_remove,
	.driver		= {
		.name	= "rk3288-crypto",
		.of_match_table	= crypto_of_id_table,
	},
};

module_platform_driver(crypto_driver);

MODULE_AUTHOR("Zain Wang <zain.wang@rock-chips.com>");
MODULE_DESCRIPTION("Support for Rockchip's cryptographic engine");
MODULE_LICENSE("GPL");
Commit	Line	Data
433cd2c6 ZW	1	/*
	2	* Crypto acceleration support for Rockchip RK3288
	3	*
	4	* Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
	5	*
	6	* Author: Zain Wang <zain.wang@rock-chips.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* Some ideas are from marvell-cesa.c and s5p-sss.c driver.
	13	*/
	14
	15	#include "rk3288_crypto.h"
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/of.h>
	19	#include <linux/clk.h>
	20	#include <linux/crypto.h>
	21	#include <linux/reset.h>
	22
	23	static int rk_crypto_enable_clk(struct rk_crypto_info *dev)
	24	{
	25	int err;
	26
	27	err = clk_prepare_enable(dev->sclk);
	28	if (err) {
	29	dev_err(dev->dev, "[%s:%d], Couldn't enable clock sclk\n",
	30	__func__, __LINE__);
	31	goto err_return;
	32	}
	33	err = clk_prepare_enable(dev->aclk);
	34	if (err) {
	35	dev_err(dev->dev, "[%s:%d], Couldn't enable clock aclk\n",
	36	__func__, __LINE__);
	37	goto err_aclk;
	38	}
	39	err = clk_prepare_enable(dev->hclk);
	40	if (err) {
	41	dev_err(dev->dev, "[%s:%d], Couldn't enable clock hclk\n",
	42	__func__, __LINE__);
	43	goto err_hclk;
	44	}
	45	err = clk_prepare_enable(dev->dmaclk);
	46	if (err) {
	47	dev_err(dev->dev, "[%s:%d], Couldn't enable clock dmaclk\n",
	48	__func__, __LINE__);
	49	goto err_dmaclk;
	50	}
	51	return err;
	52	err_dmaclk:
	53	clk_disable_unprepare(dev->hclk);
	54	err_hclk:
	55	clk_disable_unprepare(dev->aclk);
	56	err_aclk:
	57	clk_disable_unprepare(dev->sclk);
	58	err_return:
	59	return err;
	60	}
	61
	62	static void rk_crypto_disable_clk(struct rk_crypto_info *dev)
	63	{
	64	clk_disable_unprepare(dev->dmaclk);
65	clk_disable_unprepare(dev->hclk);
66	clk_disable_unprepare(dev->aclk);
67	clk_disable_unprepare(dev->sclk);
68	}
69
70	static int check_alignment(struct scatterlist *sg_src,
71	struct scatterlist *sg_dst,
72	int align_mask)
73	{
74	int in, out, align;
75
76	in = IS_ALIGNED((uint32_t)sg_src->offset, 4) &&
77	IS_ALIGNED((uint32_t)sg_src->length, align_mask);
78	if (!sg_dst)
79	return in;
80	out = IS_ALIGNED((uint32_t)sg_dst->offset, 4) &&
81	IS_ALIGNED((uint32_t)sg_dst->length, align_mask);
82	align = in && out;
83
84	return (align && (sg_src->length == sg_dst->length));
85	}
86
87	static int rk_load_data(struct rk_crypto_info *dev,
88	struct scatterlist *sg_src,
89	struct scatterlist *sg_dst)
90	{
91	unsigned int count;
92
93	dev->aligned = dev->aligned ?
94	check_alignment(sg_src, sg_dst, dev->align_size) :
95	dev->aligned;
96	if (dev->aligned) {
97	count = min(dev->left_bytes, sg_src->length);
98	dev->left_bytes -= count;
99
100	if (!dma_map_sg(dev->dev, sg_src, 1, DMA_TO_DEVICE)) {
101	dev_err(dev->dev, "[%s:%d] dma_map_sg(src) error\n",
102	__func__, __LINE__);
103	return -EINVAL;
104	}
105	dev->addr_in = sg_dma_address(sg_src);
106
107	if (sg_dst) {
108	if (!dma_map_sg(dev->dev, sg_dst, 1, DMA_FROM_DEVICE)) {
109	dev_err(dev->dev,
110	"[%s:%d] dma_map_sg(dst) error\n",
111	__func__, __LINE__);
112	dma_unmap_sg(dev->dev, sg_src, 1,
113	DMA_TO_DEVICE);
114	return -EINVAL;
115	}
116	dev->addr_out = sg_dma_address(sg_dst);
117	}
118	} else {
119	count = (dev->left_bytes > PAGE_SIZE) ?
120	PAGE_SIZE : dev->left_bytes;
121
4359669a	122	if (!sg_pcopy_to_buffer(dev->first, dev->src_nents,
433cd2c6 ZW	123	dev->addr_vir, count,
	124	dev->total - dev->left_bytes)) {
	125	dev_err(dev->dev, "[%s:%d] pcopy err\n",
	126	__func__, __LINE__);
	127	return -EINVAL;
	128	}
	129	dev->left_bytes -= count;
	130	sg_init_one(&dev->sg_tmp, dev->addr_vir, count);
	131	if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1, DMA_TO_DEVICE)) {
	132	dev_err(dev->dev, "[%s:%d] dma_map_sg(sg_tmp) error\n",
	133	__func__, __LINE__);
	134	return -ENOMEM;
	135	}
	136	dev->addr_in = sg_dma_address(&dev->sg_tmp);
	137
	138	if (sg_dst) {
	139	if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1,
	140	DMA_FROM_DEVICE)) {
	141	dev_err(dev->dev,
	142	"[%s:%d] dma_map_sg(sg_tmp) error\n",
	143	__func__, __LINE__);
	144	dma_unmap_sg(dev->dev, &dev->sg_tmp, 1,
	145	DMA_TO_DEVICE);
	146	return -ENOMEM;
	147	}
	148	dev->addr_out = sg_dma_address(&dev->sg_tmp);
	149	}
	150	}
	151	dev->count = count;
	152	return 0;
	153	}
	154
	155	static void rk_unload_data(struct rk_crypto_info *dev)
	156	{
	157	struct scatterlist sg_in, sg_out;
	158
	159	sg_in = dev->aligned ? dev->sg_src : &dev->sg_tmp;
	160	dma_unmap_sg(dev->dev, sg_in, 1, DMA_TO_DEVICE);
	161
	162	if (dev->sg_dst) {
	163	sg_out = dev->aligned ? dev->sg_dst : &dev->sg_tmp;
	164	dma_unmap_sg(dev->dev, sg_out, 1, DMA_FROM_DEVICE);
	165	}
	166	}
	167
	168	static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id)
	169	{
	170	struct rk_crypto_info *dev = platform_get_drvdata(dev_id);
	171	u32 interrupt_status;
433cd2c6 ZW	172
	173	spin_lock(&dev->lock);
	174	interrupt_status = CRYPTO_READ(dev, RK_CRYPTO_INTSTS);
	175	CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, interrupt_status);
641eacd1	176
433cd2c6 ZW	177	if (interrupt_status & 0x0a) {
433cd2c6 ZW	178	dev_warn(dev->dev, "DMA Error\n");
641eacd1	179	dev->err = -EFAULT;
433cd2c6	180	}
641eacd1 ZW	181	tasklet_schedule(&dev->done_task);
641eacd1 ZW	182
433cd2c6 ZW	183	spin_unlock(&dev->lock);
	184	return IRQ_HANDLED;
	185	}
	186
5a7801f6 ZW	187	static int rk_crypto_enqueue(struct rk_crypto_info *dev,
	188	struct crypto_async_request *async_req)
	189	{
	190	unsigned long flags;
	191	int ret;
	192
	193	spin_lock_irqsave(&dev->lock, flags);
	194	ret = crypto_enqueue_request(&dev->queue, async_req);
	195	if (dev->busy) {
	196	spin_unlock_irqrestore(&dev->lock, flags);
	197	return ret;
	198	}
	199	dev->busy = true;
	200	spin_unlock_irqrestore(&dev->lock, flags);
	201	tasklet_schedule(&dev->queue_task);
	202
	203	return ret;
	204	}
	205
641eacd1	206	static void rk_crypto_queue_task_cb(unsigned long data)
433cd2c6 ZW	207	{
433cd2c6 ZW	208	struct rk_crypto_info dev = (struct rk_crypto_info )data;
5a7801f6 ZW	209	struct crypto_async_request async_req, backlog;
5a7801f6 ZW	210	unsigned long flags;
433cd2c6 ZW	211	int err = 0;
433cd2c6 ZW	212
641eacd1	213	dev->err = 0;
5a7801f6 ZW	214	spin_lock_irqsave(&dev->lock, flags);
	215	backlog = crypto_get_backlog(&dev->queue);
	216	async_req = crypto_dequeue_request(&dev->queue);
	217
	218	if (!async_req) {
	219	dev->busy = false;
	220	spin_unlock_irqrestore(&dev->lock, flags);
	221	return;
	222	}
	223	spin_unlock_irqrestore(&dev->lock, flags);
	224
	225	if (backlog) {
	226	backlog->complete(backlog, -EINPROGRESS);
	227	backlog = NULL;
	228	}
	229
	230	dev->async_req = async_req;
433cd2c6 ZW	231	err = dev->start(dev);
433cd2c6 ZW	232	if (err)
5a7801f6	233	dev->complete(dev->async_req, err);
433cd2c6 ZW	234	}
433cd2c6 ZW	235
641eacd1 ZW	236	static void rk_crypto_done_task_cb(unsigned long data)
	237	{
	238	struct rk_crypto_info dev = (struct rk_crypto_info )data;
	239
	240	if (dev->err) {
5a7801f6	241	dev->complete(dev->async_req, dev->err);
641eacd1 ZW	242	return;
	243	}
	244
	245	dev->err = dev->update(dev);
	246	if (dev->err)
5a7801f6	247	dev->complete(dev->async_req, dev->err);
641eacd1 ZW	248	}
641eacd1 ZW	249
433cd2c6 ZW	250	static struct rk_crypto_tmp *rk_cipher_algs[] = {
	251	&rk_ecb_aes_alg,
	252	&rk_cbc_aes_alg,
	253	&rk_ecb_des_alg,
	254	&rk_cbc_des_alg,
	255	&rk_ecb_des3_ede_alg,
	256	&rk_cbc_des3_ede_alg,
bfd927ff ZW	257	&rk_ahash_sha1,
	258	&rk_ahash_sha256,
	259	&rk_ahash_md5,
433cd2c6 ZW	260	};
	261
	262	static int rk_crypto_register(struct rk_crypto_info *crypto_info)
	263	{
	264	unsigned int i, k;
	265	int err = 0;
	266
	267	for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
	268	rk_cipher_algs[i]->dev = crypto_info;
bfd927ff ZW	269	if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
	270	err = crypto_register_alg(
	271	&rk_cipher_algs[i]->alg.crypto);
	272	else
	273	err = crypto_register_ahash(
	274	&rk_cipher_algs[i]->alg.hash);
433cd2c6 ZW	275	if (err)
	276	goto err_cipher_algs;
	277	}
	278	return 0;
	279
	280	err_cipher_algs:
bfd927ff ZW	281	for (k = 0; k < i; k++) {
	282	if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
	283	crypto_unregister_alg(&rk_cipher_algs[k]->alg.crypto);
	284	else
	285	crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash);
	286	}
433cd2c6 ZW	287	return err;
	288	}
	289
	290	static void rk_crypto_unregister(void)
	291	{
	292	unsigned int i;
	293
bfd927ff ZW	294	for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
	295	if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
	296	crypto_unregister_alg(&rk_cipher_algs[i]->alg.crypto);
	297	else
	298	crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash);
	299	}
433cd2c6 ZW	300	}
	301
	302	static void rk_crypto_action(void *data)
	303	{
	304	struct rk_crypto_info *crypto_info = data;
	305
	306	reset_control_assert(crypto_info->rst);
	307	}
	308
	309	static const struct of_device_id crypto_of_id_table[] = {
	310	{ .compatible = "rockchip,rk3288-crypto" },
	311	{}
	312	};
	313	MODULE_DEVICE_TABLE(of, crypto_of_id_table);
	314
	315	static int rk_crypto_probe(struct platform_device *pdev)
	316	{
	317	struct resource *res;
	318	struct device *dev = &pdev->dev;
	319	struct rk_crypto_info *crypto_info;
	320	int err = 0;
	321
	322	crypto_info = devm_kzalloc(&pdev->dev,
	323	sizeof(*crypto_info), GFP_KERNEL);
	324	if (!crypto_info) {
	325	err = -ENOMEM;
	326	goto err_crypto;
	327	}
	328
	329	crypto_info->rst = devm_reset_control_get(dev, "crypto-rst");
	330	if (IS_ERR(crypto_info->rst)) {
	331	err = PTR_ERR(crypto_info->rst);
	332	goto err_crypto;
	333	}
	334
	335	reset_control_assert(crypto_info->rst);
	336	usleep_range(10, 20);
	337	reset_control_deassert(crypto_info->rst);
	338
16d56963 SM	339	err = devm_add_action_or_reset(dev, rk_crypto_action, crypto_info);
16d56963 SM	340	if (err)
433cd2c6	341	goto err_crypto;
433cd2c6 ZW	342
	343	spin_lock_init(&crypto_info->lock);
	344
	345	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	346	crypto_info->reg = devm_ioremap_resource(&pdev->dev, res);
	347	if (IS_ERR(crypto_info->reg)) {
	348	err = PTR_ERR(crypto_info->reg);
	349	goto err_crypto;
	350	}
	351
	352	crypto_info->aclk = devm_clk_get(&pdev->dev, "aclk");
	353	if (IS_ERR(crypto_info->aclk)) {
	354	err = PTR_ERR(crypto_info->aclk);
	355	goto err_crypto;
	356	}
	357
	358	crypto_info->hclk = devm_clk_get(&pdev->dev, "hclk");
	359	if (IS_ERR(crypto_info->hclk)) {
	360	err = PTR_ERR(crypto_info->hclk);
	361	goto err_crypto;
	362	}
	363
	364	crypto_info->sclk = devm_clk_get(&pdev->dev, "sclk");
	365	if (IS_ERR(crypto_info->sclk)) {
	366	err = PTR_ERR(crypto_info->sclk);
	367	goto err_crypto;
	368	}
	369
	370	crypto_info->dmaclk = devm_clk_get(&pdev->dev, "apb_pclk");
	371	if (IS_ERR(crypto_info->dmaclk)) {
	372	err = PTR_ERR(crypto_info->dmaclk);
	373	goto err_crypto;
	374	}
	375
	376	crypto_info->irq = platform_get_irq(pdev, 0);
	377	if (crypto_info->irq < 0) {
	378	dev_warn(crypto_info->dev,
	379	"control Interrupt is not available.\n");
	380	err = crypto_info->irq;
	381	goto err_crypto;
	382	}
	383
	384	err = devm_request_irq(&pdev->dev, crypto_info->irq,
	385	rk_crypto_irq_handle, IRQF_SHARED,
	386	"rk-crypto", pdev);
	387
	388	if (err) {
	389	dev_err(crypto_info->dev, "irq request failed.\n");
	390	goto err_crypto;
	391	}
	392
	393	crypto_info->dev = &pdev->dev;
	394	platform_set_drvdata(pdev, crypto_info);
	395
641eacd1 ZW	396	tasklet_init(&crypto_info->queue_task,
	397	rk_crypto_queue_task_cb, (unsigned long)crypto_info);
	398	tasklet_init(&crypto_info->done_task,
	399	rk_crypto_done_task_cb, (unsigned long)crypto_info);
433cd2c6 ZW	400	crypto_init_queue(&crypto_info->queue, 50);
	401
	402	crypto_info->enable_clk = rk_crypto_enable_clk;
	403	crypto_info->disable_clk = rk_crypto_disable_clk;
	404	crypto_info->load_data = rk_load_data;
	405	crypto_info->unload_data = rk_unload_data;
5a7801f6 ZW	406	crypto_info->enqueue = rk_crypto_enqueue;
5a7801f6 ZW	407	crypto_info->busy = false;
433cd2c6 ZW	408
	409	err = rk_crypto_register(crypto_info);
	410	if (err) {
	411	dev_err(dev, "err in register alg");
	412	goto err_register_alg;
	413	}
	414
	415	dev_info(dev, "Crypto Accelerator successfully registered\n");
	416	return 0;
	417
	418	err_register_alg:
641eacd1 ZW	419	tasklet_kill(&crypto_info->queue_task);
641eacd1 ZW	420	tasklet_kill(&crypto_info->done_task);
433cd2c6 ZW	421	err_crypto:
	422	return err;
	423	}
	424
	425	static int rk_crypto_remove(struct platform_device *pdev)
	426	{
	427	struct rk_crypto_info *crypto_tmp = platform_get_drvdata(pdev);
	428
	429	rk_crypto_unregister();
641eacd1 ZW	430	tasklet_kill(&crypto_tmp->done_task);
641eacd1 ZW	431	tasklet_kill(&crypto_tmp->queue_task);
433cd2c6 ZW	432	return 0;
	433	}
	434
	435	static struct platform_driver crypto_driver = {
	436	.probe = rk_crypto_probe,
	437	.remove = rk_crypto_remove,
	438	.driver = {
	439	.name = "rk3288-crypto",
	440	.of_match_table = crypto_of_id_table,
	441	},
	442	};
	443
	444	module_platform_driver(crypto_driver);
	445
	446	MODULE_AUTHOR("Zain Wang <zain.wang@rock-chips.com>");
	447	MODULE_DESCRIPTION("Support for Rockchip's cryptographic engine");
	448	MODULE_LICENSE("GPL");