[linux-block.git] / drivers / crypto / qcom-rng.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017-18 Linaro Limited
//
// Based on msm-rng.c and downstream driver

#include <crypto/internal/rng.h>
#include <linux/clk.h>
#include <linux/crypto.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

/* Device specific register offsets */
#define PRNG_DATA_OUT		0x0000
#define PRNG_STATUS		0x0004
#define PRNG_LFSR_CFG		0x0100
#define PRNG_CONFIG		0x0104

/* Device specific register masks and config values */
#define PRNG_LFSR_CFG_MASK	0x0000ffff
#define PRNG_LFSR_CFG_CLOCKS	0x0000dddd
#define PRNG_CONFIG_HW_ENABLE	BIT(1)
#define PRNG_STATUS_DATA_AVAIL	BIT(0)

#define WORD_SZ			4

struct qcom_rng {
	struct mutex lock;
	void __iomem *base;
	struct clk *clk;
};

struct qcom_rng_ctx {
	struct qcom_rng *rng;
};

static struct qcom_rng *qcom_rng_dev;

static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
{
	unsigned int currsize = 0;
	u32 val;

	/* read random data from hardware */
	do {
		val = readl_relaxed(rng->base + PRNG_STATUS);
		if (!(val & PRNG_STATUS_DATA_AVAIL))
			break;

		val = readl_relaxed(rng->base + PRNG_DATA_OUT);
		if (!val)
			break;

		if ((max - currsize) >= WORD_SZ) {
			memcpy(data, &val, WORD_SZ);
			data += WORD_SZ;
			currsize += WORD_SZ;
		} else {
			/* copy only remaining bytes */
			memcpy(data, &val, max - currsize);
			break;
		}
	} while (currsize < max);

	return currsize;
}

static int qcom_rng_generate(struct crypto_rng *tfm,
			     const u8 *src, unsigned int slen,
			     u8 *dstn, unsigned int dlen)
{
	struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
	struct qcom_rng *rng = ctx->rng;
	int ret;

	ret = clk_prepare_enable(rng->clk);
	if (ret)
		return ret;

	mutex_lock(&rng->lock);

	ret = qcom_rng_read(rng, dstn, dlen);

	mutex_unlock(&rng->lock);
	clk_disable_unprepare(rng->clk);

	return 0;
}

static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
			 unsigned int slen)
{
	return 0;
}

static int qcom_rng_enable(struct qcom_rng *rng)
{
	u32 val;
	int ret;

	ret = clk_prepare_enable(rng->clk);
	if (ret)
		return ret;

	/* Enable PRNG only if it is not already enabled */
	val = readl_relaxed(rng->base + PRNG_CONFIG);
	if (val & PRNG_CONFIG_HW_ENABLE)
		goto already_enabled;

	val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
	val &= ~PRNG_LFSR_CFG_MASK;
	val |= PRNG_LFSR_CFG_CLOCKS;
	writel(val, rng->base + PRNG_LFSR_CFG);

	val = readl_relaxed(rng->base + PRNG_CONFIG);
	val |= PRNG_CONFIG_HW_ENABLE;
	writel(val, rng->base + PRNG_CONFIG);

already_enabled:
	clk_disable_unprepare(rng->clk);

	return 0;
}

static int qcom_rng_init(struct crypto_tfm *tfm)
{
	struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);

	ctx->rng = qcom_rng_dev;

	return qcom_rng_enable(ctx->rng);
}

static struct rng_alg qcom_rng_alg = {
	.generate	= qcom_rng_generate,
	.seed		= qcom_rng_seed,
	.seedsize	= 0,
	.base		= {
		.cra_name		= "stdrng",
		.cra_driver_name	= "qcom-rng",
		.cra_flags		= CRYPTO_ALG_TYPE_RNG,
		.cra_priority		= 300,
		.cra_ctxsize		= sizeof(struct qcom_rng_ctx),
		.cra_module		= THIS_MODULE,
		.cra_init		= qcom_rng_init,
	}
};

static int qcom_rng_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct qcom_rng *rng;
	int ret;

	rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
	if (!rng)
		return -ENOMEM;

	platform_set_drvdata(pdev, rng);
	mutex_init(&rng->lock);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	rng->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(rng->base))
		return PTR_ERR(rng->base);

	rng->clk = devm_clk_get(&pdev->dev, "core");
	if (IS_ERR(rng->clk))
		return PTR_ERR(rng->clk);

	qcom_rng_dev = rng;
	ret = crypto_register_rng(&qcom_rng_alg);
	if (ret) {
		dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
		qcom_rng_dev = NULL;
	}

	return ret;
}

static int qcom_rng_remove(struct platform_device *pdev)
{
	crypto_unregister_rng(&qcom_rng_alg);

	qcom_rng_dev = NULL;

	return 0;
}

static const struct of_device_id qcom_rng_of_match[] = {
	{ .compatible = "qcom,prng" },
	{}
};
MODULE_DEVICE_TABLE(of, qcom_rng_of_match);

static struct platform_driver qcom_rng_driver = {
	.probe = qcom_rng_probe,
	.remove =  qcom_rng_remove,
	.driver = {
		.name = KBUILD_MODNAME,
		.of_match_table = of_match_ptr(qcom_rng_of_match),
	}
};
module_platform_driver(qcom_rng_driver);

MODULE_ALIAS("platform:" KBUILD_MODNAME);
MODULE_DESCRIPTION("Qualcomm random number generator driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ceec5f5b VK	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (c) 2017-18 Linaro Limited
	3	//
	4	// Based on msm-rng.c and downstream driver
	5
	6	#include <crypto/internal/rng.h>
	7	#include <linux/clk.h>
	8	#include <linux/crypto.h>
	9	#include <linux/module.h>
	10	#include <linux/of.h>
	11	#include <linux/platform_device.h>
	12
	13	/* Device specific register offsets */
	14	#define PRNG_DATA_OUT 0x0000
	15	#define PRNG_STATUS 0x0004
	16	#define PRNG_LFSR_CFG 0x0100
	17	#define PRNG_CONFIG 0x0104
	18
	19	/* Device specific register masks and config values */
	20	#define PRNG_LFSR_CFG_MASK 0x0000ffff
	21	#define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
	22	#define PRNG_CONFIG_HW_ENABLE BIT(1)
	23	#define PRNG_STATUS_DATA_AVAIL BIT(0)
	24
	25	#define WORD_SZ 4
	26
	27	struct qcom_rng {
	28	struct mutex lock;
	29	void __iomem *base;
	30	struct clk *clk;
	31	};
	32
	33	struct qcom_rng_ctx {
	34	struct qcom_rng *rng;
	35	};
	36
	37	static struct qcom_rng *qcom_rng_dev;
	38
	39	static int qcom_rng_read(struct qcom_rng rng, u8 data, unsigned int max)
	40	{
	41	unsigned int currsize = 0;
	42	u32 val;
	43
	44	/* read random data from hardware */
	45	do {
	46	val = readl_relaxed(rng->base + PRNG_STATUS);
	47	if (!(val & PRNG_STATUS_DATA_AVAIL))
	48	break;
	49
	50	val = readl_relaxed(rng->base + PRNG_DATA_OUT);
	51	if (!val)
	52	break;
	53
	54	if ((max - currsize) >= WORD_SZ) {
	55	memcpy(data, &val, WORD_SZ);
	56	data += WORD_SZ;
	57	currsize += WORD_SZ;
	58	} else {
	59	/* copy only remaining bytes */
	60	memcpy(data, &val, max - currsize);
	61	break;
	62	}
	63	} while (currsize < max);
	64
65	return currsize;
66	}
67
68	static int qcom_rng_generate(struct crypto_rng *tfm,
69	const u8 *src, unsigned int slen,
70	u8 *dstn, unsigned int dlen)
71	{
72	struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
73	struct qcom_rng *rng = ctx->rng;
74	int ret;
75
76	ret = clk_prepare_enable(rng->clk);
77	if (ret)
78	return ret;
79
80	mutex_lock(&rng->lock);
81
82	ret = qcom_rng_read(rng, dstn, dlen);
83
84	mutex_unlock(&rng->lock);
85	clk_disable_unprepare(rng->clk);
86
87	return 0;
88	}
89
90	static int qcom_rng_seed(struct crypto_rng tfm, const u8 seed,
91	unsigned int slen)
92	{
93	return 0;
94	}
95
96	static int qcom_rng_enable(struct qcom_rng *rng)
97	{
98	u32 val;
99	int ret;
100
101	ret = clk_prepare_enable(rng->clk);
102	if (ret)
103	return ret;
104
105	/* Enable PRNG only if it is not already enabled */
106	val = readl_relaxed(rng->base + PRNG_CONFIG);
107	if (val & PRNG_CONFIG_HW_ENABLE)
108	goto already_enabled;
109
110	val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
111	val &= ~PRNG_LFSR_CFG_MASK;
112	val \|= PRNG_LFSR_CFG_CLOCKS;
113	writel(val, rng->base + PRNG_LFSR_CFG);
114
115	val = readl_relaxed(rng->base + PRNG_CONFIG);
116	val \|= PRNG_CONFIG_HW_ENABLE;
117	writel(val, rng->base + PRNG_CONFIG);
118
119	already_enabled:
120	clk_disable_unprepare(rng->clk);
121
122	return 0;
123	}
124
125	static int qcom_rng_init(struct crypto_tfm *tfm)
126	{
127	struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);
128
129	ctx->rng = qcom_rng_dev;
130
131	return qcom_rng_enable(ctx->rng);
132	}
133
134	static struct rng_alg qcom_rng_alg = {
135	.generate = qcom_rng_generate,
136	.seed = qcom_rng_seed,
137	.seedsize = 0,
138	.base = {
139	.cra_name = "stdrng",
140	.cra_driver_name = "qcom-rng",
141	.cra_flags = CRYPTO_ALG_TYPE_RNG,
142	.cra_priority = 300,
143	.cra_ctxsize = sizeof(struct qcom_rng_ctx),
144	.cra_module = THIS_MODULE,
145	.cra_init = qcom_rng_init,
146	}
147	};
148
149	static int qcom_rng_probe(struct platform_device *pdev)
150	{
151	struct resource *res;
152	struct qcom_rng *rng;
153	int ret;
154
155	rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
156	if (!rng)
157	return -ENOMEM;
158
159	platform_set_drvdata(pdev, rng);
160	mutex_init(&rng->lock);
161
162	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
163	rng->base = devm_ioremap_resource(&pdev->dev, res);
164	if (IS_ERR(rng->base))
165	return PTR_ERR(rng->base);
166
167	rng->clk = devm_clk_get(&pdev->dev, "core");
168	if (IS_ERR(rng->clk))
169	return PTR_ERR(rng->clk);
170
171	qcom_rng_dev = rng;
172	ret = crypto_register_rng(&qcom_rng_alg);
173	if (ret) {
174	dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
175	qcom_rng_dev = NULL;
176	}
177
178	return ret;
179	}
180
181	static int qcom_rng_remove(struct platform_device *pdev)
182	{
183	crypto_unregister_rng(&qcom_rng_alg);
184
185	qcom_rng_dev = NULL;
186
187	return 0;
188	}
189
190	static const struct of_device_id qcom_rng_of_match[] = {
191	{ .compatible = "qcom,prng" },
192	{}
193	};
194	MODULE_DEVICE_TABLE(of, qcom_rng_of_match);
195
196	static struct platform_driver qcom_rng_driver = {
197	.probe = qcom_rng_probe,
198	.remove = qcom_rng_remove,
199	.driver = {
200	.name = KBUILD_MODNAME,
201	.of_match_table = of_match_ptr(qcom_rng_of_match),
202	}
203	};
204	module_platform_driver(qcom_rng_driver);
205
206	MODULE_ALIAS("platform:" KBUILD_MODNAME);
207	MODULE_DESCRIPTION("Qualcomm random number generator driver");
208	MODULE_LICENSE("GPL v2");