[linux-2.6-block.git] / drivers / crypto / qcom-rng.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017-18 Linaro Limited
//
// Based on msm-rng.c and downstream driver

#include <crypto/internal/rng.h>
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/crypto.h>
#include <linux/hw_random.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

/* Device specific register offsets */
#define PRNG_DATA_OUT		0x0000
#define PRNG_STATUS		0x0004
#define PRNG_LFSR_CFG		0x0100
#define PRNG_CONFIG		0x0104

/* Device specific register masks and config values */
#define PRNG_LFSR_CFG_MASK	0x0000ffff
#define PRNG_LFSR_CFG_CLOCKS	0x0000dddd
#define PRNG_CONFIG_HW_ENABLE	BIT(1)
#define PRNG_STATUS_DATA_AVAIL	BIT(0)

#define WORD_SZ			4

#define QCOM_TRNG_QUALITY	1024

struct qcom_rng {
	struct mutex lock;
	void __iomem *base;
	struct clk *clk;
	struct hwrng hwrng;
	struct qcom_rng_of_data *of_data;
};

struct qcom_rng_ctx {
	struct qcom_rng *rng;
};

struct qcom_rng_of_data {
	bool skip_init;
	bool hwrng_support;
};

static struct qcom_rng *qcom_rng_dev;

static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
{
	unsigned int currsize = 0;
	u32 val;
	int ret;

	/* read random data from hardware */
	do {
		ret = readl_poll_timeout(rng->base + PRNG_STATUS, val,
					 val & PRNG_STATUS_DATA_AVAIL,
					 200, 10000);
		if (ret)
			return ret;

		val = readl_relaxed(rng->base + PRNG_DATA_OUT);
		if (!val)
			return -EINVAL;

		if ((max - currsize) >= WORD_SZ) {
			memcpy(data, &val, WORD_SZ);
			data += WORD_SZ;
			currsize += WORD_SZ;
		} else {
			/* copy only remaining bytes */
			memcpy(data, &val, max - currsize);
			currsize = max;
		}
	} while (currsize < max);

	return currsize;
}

static int qcom_rng_generate(struct crypto_rng *tfm,
			     const u8 *src, unsigned int slen,
			     u8 *dstn, unsigned int dlen)
{
	struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
	struct qcom_rng *rng = ctx->rng;
	int ret;

	ret = clk_prepare_enable(rng->clk);
	if (ret)
		return ret;

	mutex_lock(&rng->lock);

	ret = qcom_rng_read(rng, dstn, dlen);

	mutex_unlock(&rng->lock);
	clk_disable_unprepare(rng->clk);

	if (ret >= 0)
		ret = 0;

	return ret;
}

static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
			 unsigned int slen)
{
	return 0;
}

static int qcom_hwrng_read(struct hwrng *hwrng, void *data, size_t max, bool wait)
{
	struct qcom_rng *qrng = container_of(hwrng, struct qcom_rng, hwrng);

	return qcom_rng_read(qrng, data, max);
}

static int qcom_rng_enable(struct qcom_rng *rng)
{
	u32 val;
	int ret;

	ret = clk_prepare_enable(rng->clk);
	if (ret)
		return ret;

	/* Enable PRNG only if it is not already enabled */
	val = readl_relaxed(rng->base + PRNG_CONFIG);
	if (val & PRNG_CONFIG_HW_ENABLE)
		goto already_enabled;

	val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
	val &= ~PRNG_LFSR_CFG_MASK;
	val |= PRNG_LFSR_CFG_CLOCKS;
	writel(val, rng->base + PRNG_LFSR_CFG);

	val = readl_relaxed(rng->base + PRNG_CONFIG);
	val |= PRNG_CONFIG_HW_ENABLE;
	writel(val, rng->base + PRNG_CONFIG);

already_enabled:
	clk_disable_unprepare(rng->clk);

	return 0;
}

static int qcom_rng_init(struct crypto_tfm *tfm)
{
	struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);

	ctx->rng = qcom_rng_dev;

	if (!ctx->rng->of_data->skip_init)
		return qcom_rng_enable(ctx->rng);

	return 0;
}

static struct rng_alg qcom_rng_alg = {
	.generate	= qcom_rng_generate,
	.seed		= qcom_rng_seed,
	.seedsize	= 0,
	.base		= {
		.cra_name		= "stdrng",
		.cra_driver_name	= "qcom-rng",
		.cra_flags		= CRYPTO_ALG_TYPE_RNG,
		.cra_priority		= 300,
		.cra_ctxsize		= sizeof(struct qcom_rng_ctx),
		.cra_module		= THIS_MODULE,
		.cra_init		= qcom_rng_init,
	}
};

static int qcom_rng_probe(struct platform_device *pdev)
{
	struct qcom_rng *rng;
	int ret;

	rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
	if (!rng)
		return -ENOMEM;

	platform_set_drvdata(pdev, rng);
	mutex_init(&rng->lock);

	rng->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(rng->base))
		return PTR_ERR(rng->base);

	rng->clk = devm_clk_get_optional(&pdev->dev, "core");
	if (IS_ERR(rng->clk))
		return PTR_ERR(rng->clk);

	rng->of_data = (struct qcom_rng_of_data *)of_device_get_match_data(&pdev->dev);

	qcom_rng_dev = rng;
	ret = crypto_register_rng(&qcom_rng_alg);
	if (ret) {
		dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
		qcom_rng_dev = NULL;
		return ret;
	}

	if (rng->of_data->hwrng_support) {
		rng->hwrng.name = "qcom_hwrng";
		rng->hwrng.read = qcom_hwrng_read;
		rng->hwrng.quality = QCOM_TRNG_QUALITY;
		ret = devm_hwrng_register(&pdev->dev, &rng->hwrng);
		if (ret) {
			dev_err(&pdev->dev, "Register hwrng failed: %d\n", ret);
			qcom_rng_dev = NULL;
			goto fail;
		}
	}

	return ret;
fail:
	crypto_unregister_rng(&qcom_rng_alg);
	return ret;
}

static void qcom_rng_remove(struct platform_device *pdev)
{
	crypto_unregister_rng(&qcom_rng_alg);

	qcom_rng_dev = NULL;
}

static struct qcom_rng_of_data qcom_prng_of_data = {
	.skip_init = false,
	.hwrng_support = false,
};

static struct qcom_rng_of_data qcom_prng_ee_of_data = {
	.skip_init = true,
	.hwrng_support = false,
};

static struct qcom_rng_of_data qcom_trng_of_data = {
	.skip_init = true,
	.hwrng_support = true,
};

static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = {
	{ .id = "QCOM8160", .driver_data = 1 },
	{}
};
MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);

static const struct of_device_id __maybe_unused qcom_rng_of_match[] = {
	{ .compatible = "qcom,prng", .data = &qcom_prng_of_data },
	{ .compatible = "qcom,prng-ee", .data = &qcom_prng_ee_of_data },
	{ .compatible = "qcom,trng", .data = &qcom_trng_of_data },
	{}
};
MODULE_DEVICE_TABLE(of, qcom_rng_of_match);

static struct platform_driver qcom_rng_driver = {
	.probe = qcom_rng_probe,
	.remove_new =  qcom_rng_remove,
	.driver = {
		.name = KBUILD_MODNAME,
		.of_match_table = of_match_ptr(qcom_rng_of_match),
		.acpi_match_table = ACPI_PTR(qcom_rng_acpi_match),
	}
};
module_platform_driver(qcom_rng_driver);

MODULE_ALIAS("platform:" KBUILD_MODNAME);
MODULE_DESCRIPTION("Qualcomm random number generator driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ceec5f5b VK	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (c) 2017-18 Linaro Limited
	3	//
	4	// Based on msm-rng.c and downstream driver
	5
	6	#include <crypto/internal/rng.h>
d96542ac	7	#include <linux/acpi.h>
ceec5f5b VK	8	#include <linux/clk.h>
ceec5f5b VK	9	#include <linux/crypto.h>
f29cd5bb	10	#include <linux/hw_random.h>
0c3dc787	11	#include <linux/io.h>
a680b183	12	#include <linux/iopoll.h>
882aa652	13	#include <linux/kernel.h>
ceec5f5b VK	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/platform_device.h>
	17
	18	/* Device specific register offsets */
	19	#define PRNG_DATA_OUT 0x0000
	20	#define PRNG_STATUS 0x0004
	21	#define PRNG_LFSR_CFG 0x0100
	22	#define PRNG_CONFIG 0x0104
	23
	24	/* Device specific register masks and config values */
	25	#define PRNG_LFSR_CFG_MASK 0x0000ffff
	26	#define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
	27	#define PRNG_CONFIG_HW_ENABLE BIT(1)
	28	#define PRNG_STATUS_DATA_AVAIL BIT(0)
	29
	30	#define WORD_SZ 4
	31
f29cd5bb OPS	32	#define QCOM_TRNG_QUALITY 1024
f29cd5bb OPS	33
ceec5f5b VK	34	struct qcom_rng {
	35	struct mutex lock;
	36	void __iomem *base;
	37	struct clk *clk;
f29cd5bb OPS	38	struct hwrng hwrng;
f29cd5bb OPS	39	struct qcom_rng_of_data *of_data;
ceec5f5b VK	40	};
	41
	42	struct qcom_rng_ctx {
	43	struct qcom_rng *rng;
	44	};
	45
f29cd5bb OPS	46	struct qcom_rng_of_data {
	47	bool skip_init;
	48	bool hwrng_support;
	49	};
	50
ceec5f5b VK	51	static struct qcom_rng *qcom_rng_dev;
	52
	53	static int qcom_rng_read(struct qcom_rng rng, u8 data, unsigned int max)
	54	{
	55	unsigned int currsize = 0;
	56	u32 val;
a680b183	57	int ret;
ceec5f5b VK	58
	59	/* read random data from hardware */
	60	do {
a680b183 BM	61	ret = readl_poll_timeout(rng->base + PRNG_STATUS, val,
	62	val & PRNG_STATUS_DATA_AVAIL,
	63	200, 10000);
	64	if (ret)
	65	return ret;
ceec5f5b VK	66
	67	val = readl_relaxed(rng->base + PRNG_DATA_OUT);
	68	if (!val)
a680b183	69	return -EINVAL;
ceec5f5b VK	70
	71	if ((max - currsize) >= WORD_SZ) {
	72	memcpy(data, &val, WORD_SZ);
	73	data += WORD_SZ;
	74	currsize += WORD_SZ;
	75	} else {
	76	/* copy only remaining bytes */
	77	memcpy(data, &val, max - currsize);
f29cd5bb	78	currsize = max;
ceec5f5b VK	79	}
	80	} while (currsize < max);
	81
f29cd5bb	82	return currsize;
ceec5f5b VK	83	}
	84
	85	static int qcom_rng_generate(struct crypto_rng *tfm,
	86	const u8 *src, unsigned int slen,
	87	u8 *dstn, unsigned int dlen)
	88	{
	89	struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
	90	struct qcom_rng *rng = ctx->rng;
	91	int ret;
	92
	93	ret = clk_prepare_enable(rng->clk);
	94	if (ret)
	95	return ret;
	96
	97	mutex_lock(&rng->lock);
	98
	99	ret = qcom_rng_read(rng, dstn, dlen);
	100
	101	mutex_unlock(&rng->lock);
	102	clk_disable_unprepare(rng->clk);
	103
f29cd5bb OPS	104	if (ret >= 0)
	105	ret = 0;
	106
a680b183	107	return ret;
ceec5f5b VK	108	}
	109
	110	static int qcom_rng_seed(struct crypto_rng tfm, const u8 seed,
	111	unsigned int slen)
	112	{
	113	return 0;
	114	}
	115
f29cd5bb OPS	116	static int qcom_hwrng_read(struct hwrng hwrng, void data, size_t max, bool wait)
	117	{
	118	struct qcom_rng *qrng = container_of(hwrng, struct qcom_rng, hwrng);
	119
	120	return qcom_rng_read(qrng, data, max);
	121	}
	122
ceec5f5b VK	123	static int qcom_rng_enable(struct qcom_rng *rng)
	124	{
	125	u32 val;
	126	int ret;
	127
	128	ret = clk_prepare_enable(rng->clk);
	129	if (ret)
	130	return ret;
	131
	132	/* Enable PRNG only if it is not already enabled */
	133	val = readl_relaxed(rng->base + PRNG_CONFIG);
	134	if (val & PRNG_CONFIG_HW_ENABLE)
	135	goto already_enabled;
	136
	137	val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
	138	val &= ~PRNG_LFSR_CFG_MASK;
	139	val \|= PRNG_LFSR_CFG_CLOCKS;
	140	writel(val, rng->base + PRNG_LFSR_CFG);
	141
	142	val = readl_relaxed(rng->base + PRNG_CONFIG);
	143	val \|= PRNG_CONFIG_HW_ENABLE;
	144	writel(val, rng->base + PRNG_CONFIG);
	145
	146	already_enabled:
	147	clk_disable_unprepare(rng->clk);
	148
	149	return 0;
	150	}
	151
	152	static int qcom_rng_init(struct crypto_tfm *tfm)
	153	{
	154	struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);
	155
	156	ctx->rng = qcom_rng_dev;
	157
f29cd5bb	158	if (!ctx->rng->of_data->skip_init)
ba3ab637 VK	159	return qcom_rng_enable(ctx->rng);
	160
	161	return 0;
ceec5f5b VK	162	}
	163
	164	static struct rng_alg qcom_rng_alg = {
	165	.generate = qcom_rng_generate,
	166	.seed = qcom_rng_seed,
	167	.seedsize = 0,
	168	.base = {
	169	.cra_name = "stdrng",
	170	.cra_driver_name = "qcom-rng",
	171	.cra_flags = CRYPTO_ALG_TYPE_RNG,
	172	.cra_priority = 300,
	173	.cra_ctxsize = sizeof(struct qcom_rng_ctx),
	174	.cra_module = THIS_MODULE,
	175	.cra_init = qcom_rng_init,
	176	}
	177	};
	178
	179	static int qcom_rng_probe(struct platform_device *pdev)
	180	{
ceec5f5b VK	181	struct qcom_rng *rng;
	182	int ret;
	183
	184	rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
	185	if (!rng)
	186	return -ENOMEM;
	187
	188	platform_set_drvdata(pdev, rng);
	189	mutex_init(&rng->lock);
	190
2229c740	191	rng->base = devm_platform_ioremap_resource(pdev, 0);
ceec5f5b VK	192	if (IS_ERR(rng->base))
	193	return PTR_ERR(rng->base);
	194
cdb8b7e1 KD	195	rng->clk = devm_clk_get_optional(&pdev->dev, "core");
	196	if (IS_ERR(rng->clk))
	197	return PTR_ERR(rng->clk);
ceec5f5b	198
f29cd5bb	199	rng->of_data = (struct qcom_rng_of_data *)of_device_get_match_data(&pdev->dev);
ba3ab637	200
ceec5f5b VK	201	qcom_rng_dev = rng;
	202	ret = crypto_register_rng(&qcom_rng_alg);
	203	if (ret) {
	204	dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
	205	qcom_rng_dev = NULL;
f29cd5bb OPS	206	return ret;
	207	}
	208
	209	if (rng->of_data->hwrng_support) {
	210	rng->hwrng.name = "qcom_hwrng";
	211	rng->hwrng.read = qcom_hwrng_read;
	212	rng->hwrng.quality = QCOM_TRNG_QUALITY;
	213	ret = devm_hwrng_register(&pdev->dev, &rng->hwrng);
	214	if (ret) {
	215	dev_err(&pdev->dev, "Register hwrng failed: %d\n", ret);
	216	qcom_rng_dev = NULL;
	217	goto fail;
	218	}
ceec5f5b VK	219	}
ceec5f5b VK	220
f29cd5bb OPS	221	return ret;
	222	fail:
	223	crypto_unregister_rng(&qcom_rng_alg);
ceec5f5b VK	224	return ret;
	225	}
	226
37548f1d	227	static void qcom_rng_remove(struct platform_device *pdev)
ceec5f5b VK	228	{
	229	crypto_unregister_rng(&qcom_rng_alg);
	230
	231	qcom_rng_dev = NULL;
ceec5f5b VK	232	}
ceec5f5b VK	233
f29cd5bb OPS	234	static struct qcom_rng_of_data qcom_prng_of_data = {
	235	.skip_init = false,
	236	.hwrng_support = false,
	237	};
	238
	239	static struct qcom_rng_of_data qcom_prng_ee_of_data = {
	240	.skip_init = true,
	241	.hwrng_support = false,
	242	};
	243
	244	static struct qcom_rng_of_data qcom_trng_of_data = {
	245	.skip_init = true,
	246	.hwrng_support = true,
	247	};
	248
882aa652	249	static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = {
d96542ac TT	250	{ .id = "QCOM8160", .driver_data = 1 },
	251	{}
	252	};
	253	MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
d96542ac	254
882aa652	255	static const struct of_device_id __maybe_unused qcom_rng_of_match[] = {
f29cd5bb OPS	256	{ .compatible = "qcom,prng", .data = &qcom_prng_of_data },
	257	{ .compatible = "qcom,prng-ee", .data = &qcom_prng_ee_of_data },
	258	{ .compatible = "qcom,trng", .data = &qcom_trng_of_data },
ceec5f5b VK	259	{}
	260	};
	261	MODULE_DEVICE_TABLE(of, qcom_rng_of_match);
	262
	263	static struct platform_driver qcom_rng_driver = {
	264	.probe = qcom_rng_probe,
37548f1d	265	.remove_new = qcom_rng_remove,
ceec5f5b VK	266	.driver = {
	267	.name = KBUILD_MODNAME,
	268	.of_match_table = of_match_ptr(qcom_rng_of_match),
d96542ac	269	.acpi_match_table = ACPI_PTR(qcom_rng_acpi_match),
ceec5f5b VK	270	}
	271	};
	272	module_platform_driver(qcom_rng_driver);
	273
	274	MODULE_ALIAS("platform:" KBUILD_MODNAME);
	275	MODULE_DESCRIPTION("Qualcomm random number generator driver");
	276	MODULE_LICENSE("GPL v2");