[linux-2.6-block.git] / drivers / crypto / padlock-sha.c

/*
 * Cryptographic API.
 *
 * Support for VIA PadLock hardware crypto engine.
 *
 * Copyright (c) 2006  Michal Ludvig <michal@logix.cz>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <crypto/internal/hash.h>
#include <crypto/padlock.h>
#include <crypto/sha.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/scatterlist.h>
#include <asm/cpu_device_id.h>
#include <asm/fpu/api.h>

struct padlock_sha_desc {
	struct shash_desc fallback;
};

struct padlock_sha_ctx {
	struct crypto_shash *fallback;
};

static int padlock_sha_init(struct shash_desc *desc)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);

	dctx->fallback.tfm = ctx->fallback;
	return crypto_shash_init(&dctx->fallback);
}

static int padlock_sha_update(struct shash_desc *desc,
			      const u8 *data, unsigned int length)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);

	return crypto_shash_update(&dctx->fallback, data, length);
}

static int padlock_sha_export(struct shash_desc *desc, void *out)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);

	return crypto_shash_export(&dctx->fallback, out);
}

static int padlock_sha_import(struct shash_desc *desc, const void *in)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);

	dctx->fallback.tfm = ctx->fallback;
	return crypto_shash_import(&dctx->fallback, in);
}

static inline void padlock_output_block(uint32_t *src,
		 	uint32_t *dst, size_t count)
{
	while (count--)
		*dst++ = swab32(*src++);
}

static int padlock_sha1_finup(struct shash_desc *desc, const u8 *in,
			      unsigned int count, u8 *out)
{
	/* We can't store directly to *out as it may be unaligned. */
	/* BTW Don't reduce the buffer size below 128 Bytes!
	 *     PadLock microcode needs it that big. */
	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct sha1_state state;
	unsigned int space;
	unsigned int leftover;
	int err;

	err = crypto_shash_export(&dctx->fallback, &state);
	if (err)
		goto out;

	if (state.count + count > ULONG_MAX)
		return crypto_shash_finup(&dctx->fallback, in, count, out);

	leftover = ((state.count - 1) & (SHA1_BLOCK_SIZE - 1)) + 1;
	space =  SHA1_BLOCK_SIZE - leftover;
	if (space) {
		if (count > space) {
			err = crypto_shash_update(&dctx->fallback, in, space) ?:
			      crypto_shash_export(&dctx->fallback, &state);
			if (err)
				goto out;
			count -= space;
			in += space;
		} else {
			memcpy(state.buffer + leftover, in, count);
			in = state.buffer;
			count += leftover;
			state.count &= ~(SHA1_BLOCK_SIZE - 1);
		}
	}

	memcpy(result, &state.state, SHA1_DIGEST_SIZE);

	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8" /* rep xsha1 */
		      : \
		      : "c"((unsigned long)state.count + count), \
			"a"((unsigned long)state.count), \
			"S"(in), "D"(result));

	padlock_output_block((uint32_t *)result, (uint32_t *)out, 5);

out:
	return err;
}

static int padlock_sha1_final(struct shash_desc *desc, u8 *out)
{
	u8 buf[4];

	return padlock_sha1_finup(desc, buf, 0, out);
}

static int padlock_sha256_finup(struct shash_desc *desc, const u8 *in,
				unsigned int count, u8 *out)
{
	/* We can't store directly to *out as it may be unaligned. */
	/* BTW Don't reduce the buffer size below 128 Bytes!
	 *     PadLock microcode needs it that big. */
	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct sha256_state state;
	unsigned int space;
	unsigned int leftover;
	int err;

	err = crypto_shash_export(&dctx->fallback, &state);
	if (err)
		goto out;

	if (state.count + count > ULONG_MAX)
		return crypto_shash_finup(&dctx->fallback, in, count, out);

	leftover = ((state.count - 1) & (SHA256_BLOCK_SIZE - 1)) + 1;
	space =  SHA256_BLOCK_SIZE - leftover;
	if (space) {
		if (count > space) {
			err = crypto_shash_update(&dctx->fallback, in, space) ?:
			      crypto_shash_export(&dctx->fallback, &state);
			if (err)
				goto out;
			count -= space;
			in += space;
		} else {
			memcpy(state.buf + leftover, in, count);
			in = state.buf;
			count += leftover;
			state.count &= ~(SHA1_BLOCK_SIZE - 1);
		}
	}

	memcpy(result, &state.state, SHA256_DIGEST_SIZE);

	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0" /* rep xsha256 */
		      : \
		      : "c"((unsigned long)state.count + count), \
			"a"((unsigned long)state.count), \
			"S"(in), "D"(result));

	padlock_output_block((uint32_t *)result, (uint32_t *)out, 8);

out:
	return err;
}

static int padlock_sha256_final(struct shash_desc *desc, u8 *out)
{
	u8 buf[4];

	return padlock_sha256_finup(desc, buf, 0, out);
}

static int padlock_cra_init(struct crypto_tfm *tfm)
{
	struct crypto_shash *hash = __crypto_shash_cast(tfm);
	const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
	struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);
	struct crypto_shash *fallback_tfm;
	int err = -ENOMEM;

	/* Allocate a fallback and abort if it failed. */
	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
					  CRYPTO_ALG_NEED_FALLBACK);
	if (IS_ERR(fallback_tfm)) {
		printk(KERN_WARNING PFX "Fallback driver '%s' could not be loaded!\n",
		       fallback_driver_name);
		err = PTR_ERR(fallback_tfm);
		goto out;
	}

	ctx->fallback = fallback_tfm;
	hash->descsize += crypto_shash_descsize(fallback_tfm);
	return 0;

out:
	return err;
}

static void padlock_cra_exit(struct crypto_tfm *tfm)
{
	struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);

	crypto_free_shash(ctx->fallback);
}

static struct shash_alg sha1_alg = {
	.digestsize	=	SHA1_DIGEST_SIZE,
	.init   	= 	padlock_sha_init,
	.update 	=	padlock_sha_update,
	.finup  	=	padlock_sha1_finup,
	.final  	=	padlock_sha1_final,
	.export		=	padlock_sha_export,
	.import		=	padlock_sha_import,
	.descsize	=	sizeof(struct padlock_sha_desc),
	.statesize	=	sizeof(struct sha1_state),
	.base		=	{
		.cra_name		=	"sha1",
		.cra_driver_name	=	"sha1-padlock",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_flags		=	CRYPTO_ALG_NEED_FALLBACK,
		.cra_blocksize		=	SHA1_BLOCK_SIZE,
		.cra_ctxsize		=	sizeof(struct padlock_sha_ctx),
		.cra_module		=	THIS_MODULE,
		.cra_init		=	padlock_cra_init,
		.cra_exit		=	padlock_cra_exit,
	}
};

static struct shash_alg sha256_alg = {
	.digestsize	=	SHA256_DIGEST_SIZE,
	.init   	= 	padlock_sha_init,
	.update 	=	padlock_sha_update,
	.finup  	=	padlock_sha256_finup,
	.final  	=	padlock_sha256_final,
	.export		=	padlock_sha_export,
	.import		=	padlock_sha_import,
	.descsize	=	sizeof(struct padlock_sha_desc),
	.statesize	=	sizeof(struct sha256_state),
	.base		=	{
		.cra_name		=	"sha256",
		.cra_driver_name	=	"sha256-padlock",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_flags		=	CRYPTO_ALG_NEED_FALLBACK,
		.cra_blocksize		=	SHA256_BLOCK_SIZE,
		.cra_ctxsize		=	sizeof(struct padlock_sha_ctx),
		.cra_module		=	THIS_MODULE,
		.cra_init		=	padlock_cra_init,
		.cra_exit		=	padlock_cra_exit,
	}
};

/* Add two shash_alg instance for hardware-implemented *
* multiple-parts hash supported by VIA Nano Processor.*/
static int padlock_sha1_init_nano(struct shash_desc *desc)
{
	struct sha1_state *sctx = shash_desc_ctx(desc);

	*sctx = (struct sha1_state){
		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
	};

	return 0;
}

static int padlock_sha1_update_nano(struct shash_desc *desc,
			const u8 *data,	unsigned int len)
{
	struct sha1_state *sctx = shash_desc_ctx(desc);
	unsigned int partial, done;
	const u8 *src;
	/*The PHE require the out buffer must 128 bytes and 16-bytes aligned*/
	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	partial = sctx->count & 0x3f;
	sctx->count += len;
	done = 0;
	src = data;
	memcpy(dst, (u8 *)(sctx->state), SHA1_DIGEST_SIZE);

	if ((partial + len) >= SHA1_BLOCK_SIZE) {

		/* Append the bytes in state's buffer to a block to handle */
		if (partial) {
			done = -partial;
			memcpy(sctx->buffer + partial, data,
				done + SHA1_BLOCK_SIZE);
			src = sctx->buffer;
			asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
			: "+S"(src), "+D"(dst) \
			: "a"((long)-1), "c"((unsigned long)1));
			done += SHA1_BLOCK_SIZE;
			src = data + done;
		}

		/* Process the left bytes from the input data */
		if (len - done >= SHA1_BLOCK_SIZE) {
			asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1),
			"c"((unsigned long)((len - done) / SHA1_BLOCK_SIZE)));
			done += ((len - done) - (len - done) % SHA1_BLOCK_SIZE);
			src = data + done;
		}
		partial = 0;
	}
	memcpy((u8 *)(sctx->state), dst, SHA1_DIGEST_SIZE);
	memcpy(sctx->buffer + partial, src, len - done);

	return 0;
}

static int padlock_sha1_final_nano(struct shash_desc *desc, u8 *out)
{
	struct sha1_state *state = (struct sha1_state *)shash_desc_ctx(desc);
	unsigned int partial, padlen;
	__be64 bits;
	static const u8 padding[64] = { 0x80, };

	bits = cpu_to_be64(state->count << 3);

	/* Pad out to 56 mod 64 */
	partial = state->count & 0x3f;
	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	padlock_sha1_update_nano(desc, padding, padlen);

	/* Append length field bytes */
	padlock_sha1_update_nano(desc, (const u8 *)&bits, sizeof(bits));

	/* Swap to output */
	padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 5);

	return 0;
}

static int padlock_sha256_init_nano(struct shash_desc *desc)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);

	*sctx = (struct sha256_state){
		.state = { SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, \
				SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7},
	};

	return 0;
}

static int padlock_sha256_update_nano(struct shash_desc *desc, const u8 *data,
			  unsigned int len)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);
	unsigned int partial, done;
	const u8 *src;
	/*The PHE require the out buffer must 128 bytes and 16-bytes aligned*/
	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	partial = sctx->count & 0x3f;
	sctx->count += len;
	done = 0;
	src = data;
	memcpy(dst, (u8 *)(sctx->state), SHA256_DIGEST_SIZE);

	if ((partial + len) >= SHA256_BLOCK_SIZE) {

		/* Append the bytes in state's buffer to a block to handle */
		if (partial) {
			done = -partial;
			memcpy(sctx->buf + partial, data,
				done + SHA256_BLOCK_SIZE);
			src = sctx->buf;
			asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1), "c"((unsigned long)1));
			done += SHA256_BLOCK_SIZE;
			src = data + done;
		}

		/* Process the left bytes from input data*/
		if (len - done >= SHA256_BLOCK_SIZE) {
			asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1),
			"c"((unsigned long)((len - done) / 64)));
			done += ((len - done) - (len - done) % 64);
			src = data + done;
		}
		partial = 0;
	}
	memcpy((u8 *)(sctx->state), dst, SHA256_DIGEST_SIZE);
	memcpy(sctx->buf + partial, src, len - done);

	return 0;
}

static int padlock_sha256_final_nano(struct shash_desc *desc, u8 *out)
{
	struct sha256_state *state =
		(struct sha256_state *)shash_desc_ctx(desc);
	unsigned int partial, padlen;
	__be64 bits;
	static const u8 padding[64] = { 0x80, };

	bits = cpu_to_be64(state->count << 3);

	/* Pad out to 56 mod 64 */
	partial = state->count & 0x3f;
	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	padlock_sha256_update_nano(desc, padding, padlen);

	/* Append length field bytes */
	padlock_sha256_update_nano(desc, (const u8 *)&bits, sizeof(bits));

	/* Swap to output */
	padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 8);

	return 0;
}

static int padlock_sha_export_nano(struct shash_desc *desc,
				void *out)
{
	int statesize = crypto_shash_statesize(desc->tfm);
	void *sctx = shash_desc_ctx(desc);

	memcpy(out, sctx, statesize);
	return 0;
}

static int padlock_sha_import_nano(struct shash_desc *desc,
				const void *in)
{
	int statesize = crypto_shash_statesize(desc->tfm);
	void *sctx = shash_desc_ctx(desc);

	memcpy(sctx, in, statesize);
	return 0;
}

static struct shash_alg sha1_alg_nano = {
	.digestsize	=	SHA1_DIGEST_SIZE,
	.init		=	padlock_sha1_init_nano,
	.update		=	padlock_sha1_update_nano,
	.final		=	padlock_sha1_final_nano,
	.export		=	padlock_sha_export_nano,
	.import		=	padlock_sha_import_nano,
	.descsize	=	sizeof(struct sha1_state),
	.statesize	=	sizeof(struct sha1_state),
	.base		=	{
		.cra_name		=	"sha1",
		.cra_driver_name	=	"sha1-padlock-nano",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_blocksize		=	SHA1_BLOCK_SIZE,
		.cra_module		=	THIS_MODULE,
	}
};

static struct shash_alg sha256_alg_nano = {
	.digestsize	=	SHA256_DIGEST_SIZE,
	.init		=	padlock_sha256_init_nano,
	.update		=	padlock_sha256_update_nano,
	.final		=	padlock_sha256_final_nano,
	.export		=	padlock_sha_export_nano,
	.import		=	padlock_sha_import_nano,
	.descsize	=	sizeof(struct sha256_state),
	.statesize	=	sizeof(struct sha256_state),
	.base		=	{
		.cra_name		=	"sha256",
		.cra_driver_name	=	"sha256-padlock-nano",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_blocksize		=	SHA256_BLOCK_SIZE,
		.cra_module		=	THIS_MODULE,
	}
};

static const struct x86_cpu_id padlock_sha_ids[] = {
	X86_FEATURE_MATCH(X86_FEATURE_PHE),
	{}
};
MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);

static int __init padlock_init(void)
{
	int rc = -ENODEV;
	struct cpuinfo_x86 *c = &cpu_data(0);
	struct shash_alg *sha1;
	struct shash_alg *sha256;

	if (!x86_match_cpu(padlock_sha_ids) || !boot_cpu_has(X86_FEATURE_PHE_EN))
		return -ENODEV;

	/* Register the newly added algorithm module if on *
	* VIA Nano processor, or else just do as before */
	if (c->x86_model < 0x0f) {
		sha1 = &sha1_alg;
		sha256 = &sha256_alg;
	} else {
		sha1 = &sha1_alg_nano;
		sha256 = &sha256_alg_nano;
	}

	rc = crypto_register_shash(sha1);
	if (rc)
		goto out;

	rc = crypto_register_shash(sha256);
	if (rc)
		goto out_unreg1;

	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for SHA1/SHA256 algorithms.\n");

	return 0;

out_unreg1:
	crypto_unregister_shash(sha1);

out:
	printk(KERN_ERR PFX "VIA PadLock SHA1/SHA256 initialization failed.\n");
	return rc;
}

static void __exit padlock_fini(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (c->x86_model >= 0x0f) {
		crypto_unregister_shash(&sha1_alg_nano);
		crypto_unregister_shash(&sha256_alg_nano);
	} else {
		crypto_unregister_shash(&sha1_alg);
		crypto_unregister_shash(&sha256_alg);
	}
}

module_init(padlock_init);
module_exit(padlock_fini);

MODULE_DESCRIPTION("VIA PadLock SHA1/SHA256 algorithms support.");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Michal Ludvig");

MODULE_ALIAS_CRYPTO("sha1-all");
MODULE_ALIAS_CRYPTO("sha256-all");
MODULE_ALIAS_CRYPTO("sha1-padlock");
MODULE_ALIAS_CRYPTO("sha256-padlock");
Commit	Line	Data
6c833275 ML	1	/*
	2	* Cryptographic API.
	3	*
	4	* Support for VIA PadLock hardware crypto engine.
	5	*
	6	* Copyright (c) 2006 Michal Ludvig <michal@logix.cz>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*/
	14
7d024608	15	#include <crypto/internal/hash.h>
21493088	16	#include <crypto/padlock.h>
5265eeb2	17	#include <crypto/sha.h>
6010439f	18	#include <linux/err.h>
6c833275 ML	19	#include <linux/module.h>
	20	#include <linux/init.h>
	21	#include <linux/errno.h>
6c833275 ML	22	#include <linux/interrupt.h>
	23	#include <linux/kernel.h>
	24	#include <linux/scatterlist.h>
3bd391f0	25	#include <asm/cpu_device_id.h>
df6b35f4	26	#include <asm/fpu/api.h>
4c6ab3ee	27
bbbee467 HX	28	struct padlock_sha_desc {
bbbee467 HX	29	struct shash_desc fallback;
6c833275 ML	30	};
6c833275 ML	31
bbbee467 HX	32	struct padlock_sha_ctx {
	33	struct crypto_shash *fallback;
	34	};
6c833275	35
bbbee467	36	static int padlock_sha_init(struct shash_desc *desc)
6c833275	37	{
bbbee467 HX	38	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
bbbee467 HX	39	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);
6c833275	40
bbbee467	41	dctx->fallback.tfm = ctx->fallback;
bbbee467	42	return crypto_shash_init(&dctx->fallback);
6c833275 ML	43	}
6c833275 ML	44
bbbee467 HX	45	static int padlock_sha_update(struct shash_desc *desc,
bbbee467 HX	46	const u8 *data, unsigned int length)
6c833275	47	{
bbbee467	48	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
6c833275	49
bbbee467	50	return crypto_shash_update(&dctx->fallback, data, length);
6c833275 ML	51	}
6c833275 ML	52
a8d7ac27 HX	53	static int padlock_sha_export(struct shash_desc desc, void out)
	54	{
	55	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	56
	57	return crypto_shash_export(&dctx->fallback, out);
	58	}
	59
	60	static int padlock_sha_import(struct shash_desc desc, const void in)
	61	{
	62	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	63	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);
	64
	65	dctx->fallback.tfm = ctx->fallback;
a8d7ac27 HX	66	return crypto_shash_import(&dctx->fallback, in);
	67	}
	68
6c833275 ML	69	static inline void padlock_output_block(uint32_t *src,
	70	uint32_t *dst, size_t count)
	71	{
	72	while (count--)
	73	dst++ = swab32(src++);
	74	}
	75
bbbee467 HX	76	static int padlock_sha1_finup(struct shash_desc desc, const u8 in,
bbbee467 HX	77	unsigned int count, u8 *out)
6c833275 ML	78	{
	79	/* We can't store directly to out as it may be unaligned. /
	80	/* BTW Don't reduce the buffer size below 128 Bytes!
	81	* PadLock microcode needs it that big. */
4c6ab3ee HX	82	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	83	((aligned(STACK_ALIGN)));
	84	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
bbbee467 HX	85	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	86	struct sha1_state state;
	87	unsigned int space;
	88	unsigned int leftover;
bbbee467 HX	89	int err;
bbbee467 HX	90
bbbee467 HX	91	err = crypto_shash_export(&dctx->fallback, &state);
	92	if (err)
	93	goto out;
	94
	95	if (state.count + count > ULONG_MAX)
	96	return crypto_shash_finup(&dctx->fallback, in, count, out);
	97
	98	leftover = ((state.count - 1) & (SHA1_BLOCK_SIZE - 1)) + 1;
	99	space = SHA1_BLOCK_SIZE - leftover;
	100	if (space) {
	101	if (count > space) {
	102	err = crypto_shash_update(&dctx->fallback, in, space) ?:
	103	crypto_shash_export(&dctx->fallback, &state);
	104	if (err)
	105	goto out;
	106	count -= space;
	107	in += space;
	108	} else {
	109	memcpy(state.buffer + leftover, in, count);
	110	in = state.buffer;
	111	count += leftover;
e9b25f16	112	state.count &= ~(SHA1_BLOCK_SIZE - 1);
bbbee467 HX	113	}
	114	}
	115
	116	memcpy(result, &state.state, SHA1_DIGEST_SIZE);
6c833275	117
6c833275	118	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8" /* rep xsha1 */
bbbee467	119	: \
faae8908 HX	120	: "c"((unsigned long)state.count + count), \
faae8908 HX	121	"a"((unsigned long)state.count), \
bbbee467	122	"S"(in), "D"(result));
6c833275 ML	123
6c833275 ML	124	padlock_output_block((uint32_t )result, (uint32_t )out, 5);
bbbee467 HX	125
	126	out:
	127	return err;
6c833275 ML	128	}
6c833275 ML	129
bbbee467 HX	130	static int padlock_sha1_final(struct shash_desc desc, u8 out)
	131	{
	132	u8 buf[4];
	133
	134	return padlock_sha1_finup(desc, buf, 0, out);
	135	}
	136
	137	static int padlock_sha256_finup(struct shash_desc desc, const u8 in,
	138	unsigned int count, u8 *out)
6c833275 ML	139	{
	140	/* We can't store directly to out as it may be unaligned. /
	141	/* BTW Don't reduce the buffer size below 128 Bytes!
	142	* PadLock microcode needs it that big. */
4c6ab3ee HX	143	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	144	((aligned(STACK_ALIGN)));
	145	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
bbbee467 HX	146	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	147	struct sha256_state state;
	148	unsigned int space;
	149	unsigned int leftover;
bbbee467	150	int err;
6c833275	151
bbbee467 HX	152	err = crypto_shash_export(&dctx->fallback, &state);
	153	if (err)
	154	goto out;
	155
	156	if (state.count + count > ULONG_MAX)
	157	return crypto_shash_finup(&dctx->fallback, in, count, out);
	158
	159	leftover = ((state.count - 1) & (SHA256_BLOCK_SIZE - 1)) + 1;
	160	space = SHA256_BLOCK_SIZE - leftover;
	161	if (space) {
	162	if (count > space) {
	163	err = crypto_shash_update(&dctx->fallback, in, space) ?:
	164	crypto_shash_export(&dctx->fallback, &state);
	165	if (err)
	166	goto out;
	167	count -= space;
	168	in += space;
	169	} else {
	170	memcpy(state.buf + leftover, in, count);
	171	in = state.buf;
	172	count += leftover;
e9b25f16	173	state.count &= ~(SHA1_BLOCK_SIZE - 1);
bbbee467 HX	174	}
	175	}
	176
	177	memcpy(result, &state.state, SHA256_DIGEST_SIZE);
6c833275 ML	178
6c833275 ML	179	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0" /* rep xsha256 */
bbbee467	180	: \
faae8908 HX	181	: "c"((unsigned long)state.count + count), \
faae8908 HX	182	"a"((unsigned long)state.count), \
bbbee467	183	"S"(in), "D"(result));
6c833275 ML	184
6c833275 ML	185	padlock_output_block((uint32_t )result, (uint32_t )out, 8);
bbbee467 HX	186
	187	out:
	188	return err;
6c833275 ML	189	}
6c833275 ML	190
bbbee467	191	static int padlock_sha256_final(struct shash_desc desc, u8 out)
6c833275	192	{
bbbee467	193	u8 buf[4];
6c833275	194
bbbee467	195	return padlock_sha256_finup(desc, buf, 0, out);
6c833275 ML	196	}
6c833275 ML	197
6010439f	198	static int padlock_cra_init(struct crypto_tfm *tfm)
6c833275	199	{
bbbee467	200	struct crypto_shash *hash = __crypto_shash_cast(tfm);
1f4fe5a3	201	const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
bbbee467	202	struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);
7d024608 HX	203	struct crypto_shash *fallback_tfm;
7d024608 HX	204	int err = -ENOMEM;
6010439f	205
6c833275	206	/* Allocate a fallback and abort if it failed. */
7d024608 HX	207	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
7d024608 HX	208	CRYPTO_ALG_NEED_FALLBACK);
6010439f	209	if (IS_ERR(fallback_tfm)) {
6c833275 ML	210	printk(KERN_WARNING PFX "Fallback driver '%s' could not be loaded!\n",
6c833275 ML	211	fallback_driver_name);
7d024608	212	err = PTR_ERR(fallback_tfm);
bbbee467	213	goto out;
6c833275 ML	214	}
6c833275 ML	215
bbbee467 HX	216	ctx->fallback = fallback_tfm;
bbbee467 HX	217	hash->descsize += crypto_shash_descsize(fallback_tfm);
6c833275	218	return 0;
7d024608	219
7d024608 HX	220	out:
7d024608 HX	221	return err;
6c833275 ML	222	}
6c833275 ML	223
6c833275 ML	224	static void padlock_cra_exit(struct crypto_tfm *tfm)
6c833275 ML	225	{
bbbee467	226	struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);
7d024608	227
bbbee467	228	crypto_free_shash(ctx->fallback);
6c833275 ML	229	}
6c833275 ML	230
bbbee467 HX	231	static struct shash_alg sha1_alg = {
	232	.digestsize = SHA1_DIGEST_SIZE,
	233	.init = padlock_sha_init,
	234	.update = padlock_sha_update,
	235	.finup = padlock_sha1_finup,
	236	.final = padlock_sha1_final,
a8d7ac27 HX	237	.export = padlock_sha_export,
a8d7ac27 HX	238	.import = padlock_sha_import,
bbbee467	239	.descsize = sizeof(struct padlock_sha_desc),
a8d7ac27	240	.statesize = sizeof(struct sha1_state),
bbbee467 HX	241	.base = {
	242	.cra_name = "sha1",
	243	.cra_driver_name = "sha1-padlock",
	244	.cra_priority = PADLOCK_CRA_PRIORITY,
e50944e2	245	.cra_flags = CRYPTO_ALG_NEED_FALLBACK,
bbbee467 HX	246	.cra_blocksize = SHA1_BLOCK_SIZE,
	247	.cra_ctxsize = sizeof(struct padlock_sha_ctx),
	248	.cra_module = THIS_MODULE,
	249	.cra_init = padlock_cra_init,
	250	.cra_exit = padlock_cra_exit,
6c833275 ML	251	}
	252	};
	253
bbbee467 HX	254	static struct shash_alg sha256_alg = {
	255	.digestsize = SHA256_DIGEST_SIZE,
	256	.init = padlock_sha_init,
	257	.update = padlock_sha_update,
	258	.finup = padlock_sha256_finup,
	259	.final = padlock_sha256_final,
a8d7ac27 HX	260	.export = padlock_sha_export,
a8d7ac27 HX	261	.import = padlock_sha_import,
bbbee467	262	.descsize = sizeof(struct padlock_sha_desc),
a8d7ac27	263	.statesize = sizeof(struct sha256_state),
bbbee467 HX	264	.base = {
	265	.cra_name = "sha256",
	266	.cra_driver_name = "sha256-padlock",
	267	.cra_priority = PADLOCK_CRA_PRIORITY,
e50944e2	268	.cra_flags = CRYPTO_ALG_NEED_FALLBACK,
bbbee467 HX	269	.cra_blocksize = SHA256_BLOCK_SIZE,
	270	.cra_ctxsize = sizeof(struct padlock_sha_ctx),
	271	.cra_module = THIS_MODULE,
	272	.cra_init = padlock_cra_init,
	273	.cra_exit = padlock_cra_exit,
6c833275 ML	274	}
	275	};
	276
0475add3 BW	277	/* Add two shash_alg instance for hardware-implemented *
	278	* multiple-parts hash supported by VIA Nano Processor.*/
	279	static int padlock_sha1_init_nano(struct shash_desc *desc)
	280	{
	281	struct sha1_state *sctx = shash_desc_ctx(desc);
	282
	283	*sctx = (struct sha1_state){
	284	.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
	285	};
	286
	287	return 0;
	288	}
	289
	290	static int padlock_sha1_update_nano(struct shash_desc *desc,
	291	const u8 *data, unsigned int len)
	292	{
	293	struct sha1_state *sctx = shash_desc_ctx(desc);
	294	unsigned int partial, done;
	295	const u8 *src;
	296	/The PHE require the out buffer must 128 bytes and 16-bytes aligned/
	297	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	298	((aligned(STACK_ALIGN)));
	299	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0475add3 BW	300
	301	partial = sctx->count & 0x3f;
	302	sctx->count += len;
	303	done = 0;
	304	src = data;
	305	memcpy(dst, (u8 *)(sctx->state), SHA1_DIGEST_SIZE);
	306
	307	if ((partial + len) >= SHA1_BLOCK_SIZE) {
	308
	309	/* Append the bytes in state's buffer to a block to handle */
	310	if (partial) {
	311	done = -partial;
	312	memcpy(sctx->buffer + partial, data,
	313	done + SHA1_BLOCK_SIZE);
	314	src = sctx->buffer;
0475add3 BW	315	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
	316	: "+S"(src), "+D"(dst) \
	317	: "a"((long)-1), "c"((unsigned long)1));
0475add3 BW	318	done += SHA1_BLOCK_SIZE;
	319	src = data + done;
	320	}
	321
	322	/* Process the left bytes from the input data */
	323	if (len - done >= SHA1_BLOCK_SIZE) {
0475add3 BW	324	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
	325	: "+S"(src), "+D"(dst)
	326	: "a"((long)-1),
	327	"c"((unsigned long)((len - done) / SHA1_BLOCK_SIZE)));
0475add3 BW	328	done += ((len - done) - (len - done) % SHA1_BLOCK_SIZE);
	329	src = data + done;
	330	}
	331	partial = 0;
	332	}
	333	memcpy((u8 *)(sctx->state), dst, SHA1_DIGEST_SIZE);
	334	memcpy(sctx->buffer + partial, src, len - done);
	335
	336	return 0;
	337	}
	338
	339	static int padlock_sha1_final_nano(struct shash_desc desc, u8 out)
	340	{
	341	struct sha1_state state = (struct sha1_state )shash_desc_ctx(desc);
	342	unsigned int partial, padlen;
	343	__be64 bits;
	344	static const u8 padding[64] = { 0x80, };
	345
	346	bits = cpu_to_be64(state->count << 3);
	347
	348	/* Pad out to 56 mod 64 */
	349	partial = state->count & 0x3f;
	350	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	351	padlock_sha1_update_nano(desc, padding, padlen);
	352
	353	/* Append length field bytes */
	354	padlock_sha1_update_nano(desc, (const u8 *)&bits, sizeof(bits));
	355
	356	/* Swap to output */
	357	padlock_output_block((uint32_t )(state->state), (uint32_t )out, 5);
	358
	359	return 0;
	360	}
	361
	362	static int padlock_sha256_init_nano(struct shash_desc *desc)
	363	{
	364	struct sha256_state *sctx = shash_desc_ctx(desc);
	365
	366	*sctx = (struct sha256_state){
	367	.state = { SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, \
	368	SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7},
	369	};
	370
	371	return 0;
	372	}
	373
	374	static int padlock_sha256_update_nano(struct shash_desc desc, const u8 data,
	375	unsigned int len)
	376	{
	377	struct sha256_state *sctx = shash_desc_ctx(desc);
	378	unsigned int partial, done;
	379	const u8 *src;
	380	/The PHE require the out buffer must 128 bytes and 16-bytes aligned/
	381	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	382	((aligned(STACK_ALIGN)));
	383	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0475add3 BW	384
	385	partial = sctx->count & 0x3f;
	386	sctx->count += len;
	387	done = 0;
	388	src = data;
	389	memcpy(dst, (u8 *)(sctx->state), SHA256_DIGEST_SIZE);
	390
	391	if ((partial + len) >= SHA256_BLOCK_SIZE) {
	392
	393	/* Append the bytes in state's buffer to a block to handle */
	394	if (partial) {
	395	done = -partial;
	396	memcpy(sctx->buf + partial, data,
	397	done + SHA256_BLOCK_SIZE);
	398	src = sctx->buf;
0475add3 BW	399	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
	400	: "+S"(src), "+D"(dst)
	401	: "a"((long)-1), "c"((unsigned long)1));
0475add3 BW	402	done += SHA256_BLOCK_SIZE;
	403	src = data + done;
	404	}
	405
	406	/* Process the left bytes from input data*/
	407	if (len - done >= SHA256_BLOCK_SIZE) {
0475add3 BW	408	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
	409	: "+S"(src), "+D"(dst)
	410	: "a"((long)-1),
	411	"c"((unsigned long)((len - done) / 64)));
0475add3 BW	412	done += ((len - done) - (len - done) % 64);
	413	src = data + done;
	414	}
	415	partial = 0;
	416	}
	417	memcpy((u8 *)(sctx->state), dst, SHA256_DIGEST_SIZE);
	418	memcpy(sctx->buf + partial, src, len - done);
	419
	420	return 0;
	421	}
	422
	423	static int padlock_sha256_final_nano(struct shash_desc desc, u8 out)
	424	{
	425	struct sha256_state *state =
	426	(struct sha256_state *)shash_desc_ctx(desc);
	427	unsigned int partial, padlen;
	428	__be64 bits;
	429	static const u8 padding[64] = { 0x80, };
	430
	431	bits = cpu_to_be64(state->count << 3);
	432
	433	/* Pad out to 56 mod 64 */
	434	partial = state->count & 0x3f;
	435	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	436	padlock_sha256_update_nano(desc, padding, padlen);
	437
	438	/* Append length field bytes */
	439	padlock_sha256_update_nano(desc, (const u8 *)&bits, sizeof(bits));
	440
	441	/* Swap to output */
	442	padlock_output_block((uint32_t )(state->state), (uint32_t )out, 8);
	443
	444	return 0;
	445	}
	446
	447	static int padlock_sha_export_nano(struct shash_desc *desc,
	448	void *out)
	449	{
	450	int statesize = crypto_shash_statesize(desc->tfm);
	451	void *sctx = shash_desc_ctx(desc);
	452
	453	memcpy(out, sctx, statesize);
	454	return 0;
	455	}
	456
	457	static int padlock_sha_import_nano(struct shash_desc *desc,
	458	const void *in)
	459	{
	460	int statesize = crypto_shash_statesize(desc->tfm);
	461	void *sctx = shash_desc_ctx(desc);
	462
	463	memcpy(sctx, in, statesize);
	464	return 0;
	465	}
	466
	467	static struct shash_alg sha1_alg_nano = {
	468	.digestsize = SHA1_DIGEST_SIZE,
	469	.init = padlock_sha1_init_nano,
	470	.update = padlock_sha1_update_nano,
	471	.final = padlock_sha1_final_nano,
	472	.export = padlock_sha_export_nano,
	473	.import = padlock_sha_import_nano,
	474	.descsize = sizeof(struct sha1_state),
	475	.statesize = sizeof(struct sha1_state),
476	.base = {
477	.cra_name = "sha1",
478	.cra_driver_name = "sha1-padlock-nano",
479	.cra_priority = PADLOCK_CRA_PRIORITY,
0475add3 BW	480	.cra_blocksize = SHA1_BLOCK_SIZE,
	481	.cra_module = THIS_MODULE,
	482	}
	483	};
	484
	485	static struct shash_alg sha256_alg_nano = {
	486	.digestsize = SHA256_DIGEST_SIZE,
	487	.init = padlock_sha256_init_nano,
	488	.update = padlock_sha256_update_nano,
	489	.final = padlock_sha256_final_nano,
	490	.export = padlock_sha_export_nano,
	491	.import = padlock_sha_import_nano,
	492	.descsize = sizeof(struct sha256_state),
	493	.statesize = sizeof(struct sha256_state),
	494	.base = {
	495	.cra_name = "sha256",
	496	.cra_driver_name = "sha256-padlock-nano",
	497	.cra_priority = PADLOCK_CRA_PRIORITY,
0475add3 BW	498	.cra_blocksize = SHA256_BLOCK_SIZE,
	499	.cra_module = THIS_MODULE,
	500	}
	501	};
	502
16d5cee5	503	static const struct x86_cpu_id padlock_sha_ids[] = {
3bd391f0 AK	504	X86_FEATURE_MATCH(X86_FEATURE_PHE),
	505	{}
	506	};
	507	MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);
	508
6c833275 ML	509	static int __init padlock_init(void)
	510	{
	511	int rc = -ENODEV;
0475add3 BW	512	struct cpuinfo_x86 *c = &cpu_data(0);
	513	struct shash_alg *sha1;
	514	struct shash_alg *sha256;
6c833275	515
362f924b	516	if (!x86_match_cpu(padlock_sha_ids) \|\| !boot_cpu_has(X86_FEATURE_PHE_EN))
6c833275	517	return -ENODEV;
6c833275	518
0475add3 BW	519	/* Register the newly added algorithm module if on *
	520	* VIA Nano processor, or else just do as before */
	521	if (c->x86_model < 0x0f) {
	522	sha1 = &sha1_alg;
	523	sha256 = &sha256_alg;
	524	} else {
	525	sha1 = &sha1_alg_nano;
	526	sha256 = &sha256_alg_nano;
	527	}
	528
	529	rc = crypto_register_shash(sha1);
6c833275 ML	530	if (rc)
	531	goto out;
	532
0475add3	533	rc = crypto_register_shash(sha256);
6c833275 ML	534	if (rc)
	535	goto out_unreg1;
	536
	537	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for SHA1/SHA256 algorithms.\n");
	538
	539	return 0;
	540
	541	out_unreg1:
0475add3 BW	542	crypto_unregister_shash(sha1);
0475add3 BW	543
6c833275 ML	544	out:
	545	printk(KERN_ERR PFX "VIA PadLock SHA1/SHA256 initialization failed.\n");
	546	return rc;
	547	}
	548
	549	static void __exit padlock_fini(void)
	550	{
0475add3 BW	551	struct cpuinfo_x86 *c = &cpu_data(0);
	552
	553	if (c->x86_model >= 0x0f) {
	554	crypto_unregister_shash(&sha1_alg_nano);
	555	crypto_unregister_shash(&sha256_alg_nano);
	556	} else {
	557	crypto_unregister_shash(&sha1_alg);
	558	crypto_unregister_shash(&sha256_alg);
	559	}
6c833275 ML	560	}
	561
	562	module_init(padlock_init);
	563	module_exit(padlock_fini);
	564
	565	MODULE_DESCRIPTION("VIA PadLock SHA1/SHA256 algorithms support.");
	566	MODULE_LICENSE("GPL");
	567	MODULE_AUTHOR("Michal Ludvig");
	568
5d26a105 KC	569	MODULE_ALIAS_CRYPTO("sha1-all");
	570	MODULE_ALIAS_CRYPTO("sha256-all");
	571	MODULE_ALIAS_CRYPTO("sha1-padlock");
	572	MODULE_ALIAS_CRYPTO("sha256-padlock");