[linux-block.git] / drivers / crypto / padlock-sha.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Cryptographic API.
 *
 * Support for VIA PadLock hardware crypto engine.
 *
 * Copyright (c) 2006  Michal Ludvig <michal@logix.cz>
 */

#include <crypto/internal/hash.h>
#include <crypto/padlock.h>
#include <crypto/sha.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/scatterlist.h>
#include <asm/cpu_device_id.h>
#include <asm/fpu/api.h>

struct padlock_sha_desc {
	struct shash_desc fallback;
};

struct padlock_sha_ctx {
	struct crypto_shash *fallback;
};

static int padlock_sha_init(struct shash_desc *desc)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);

	dctx->fallback.tfm = ctx->fallback;
	return crypto_shash_init(&dctx->fallback);
}

static int padlock_sha_update(struct shash_desc *desc,
			      const u8 *data, unsigned int length)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);

	return crypto_shash_update(&dctx->fallback, data, length);
}

static int padlock_sha_export(struct shash_desc *desc, void *out)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);

	return crypto_shash_export(&dctx->fallback, out);
}

static int padlock_sha_import(struct shash_desc *desc, const void *in)
{
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);

	dctx->fallback.tfm = ctx->fallback;
	return crypto_shash_import(&dctx->fallback, in);
}

static inline void padlock_output_block(uint32_t *src,
		 	uint32_t *dst, size_t count)
{
	while (count--)
		*dst++ = swab32(*src++);
}

static int padlock_sha1_finup(struct shash_desc *desc, const u8 *in,
			      unsigned int count, u8 *out)
{
	/* We can't store directly to *out as it may be unaligned. */
	/* BTW Don't reduce the buffer size below 128 Bytes!
	 *     PadLock microcode needs it that big. */
	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct sha1_state state;
	unsigned int space;
	unsigned int leftover;
	int err;

	err = crypto_shash_export(&dctx->fallback, &state);
	if (err)
		goto out;

	if (state.count + count > ULONG_MAX)
		return crypto_shash_finup(&dctx->fallback, in, count, out);

	leftover = ((state.count - 1) & (SHA1_BLOCK_SIZE - 1)) + 1;
	space =  SHA1_BLOCK_SIZE - leftover;
	if (space) {
		if (count > space) {
			err = crypto_shash_update(&dctx->fallback, in, space) ?:
			      crypto_shash_export(&dctx->fallback, &state);
			if (err)
				goto out;
			count -= space;
			in += space;
		} else {
			memcpy(state.buffer + leftover, in, count);
			in = state.buffer;
			count += leftover;
			state.count &= ~(SHA1_BLOCK_SIZE - 1);
		}
	}

	memcpy(result, &state.state, SHA1_DIGEST_SIZE);

	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8" /* rep xsha1 */
		      : \
		      : "c"((unsigned long)state.count + count), \
			"a"((unsigned long)state.count), \
			"S"(in), "D"(result));

	padlock_output_block((uint32_t *)result, (uint32_t *)out, 5);

out:
	return err;
}

static int padlock_sha1_final(struct shash_desc *desc, u8 *out)
{
	u8 buf[4];

	return padlock_sha1_finup(desc, buf, 0, out);
}

static int padlock_sha256_finup(struct shash_desc *desc, const u8 *in,
				unsigned int count, u8 *out)
{
	/* We can't store directly to *out as it may be unaligned. */
	/* BTW Don't reduce the buffer size below 128 Bytes!
	 *     PadLock microcode needs it that big. */
	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	struct sha256_state state;
	unsigned int space;
	unsigned int leftover;
	int err;

	err = crypto_shash_export(&dctx->fallback, &state);
	if (err)
		goto out;

	if (state.count + count > ULONG_MAX)
		return crypto_shash_finup(&dctx->fallback, in, count, out);

	leftover = ((state.count - 1) & (SHA256_BLOCK_SIZE - 1)) + 1;
	space =  SHA256_BLOCK_SIZE - leftover;
	if (space) {
		if (count > space) {
			err = crypto_shash_update(&dctx->fallback, in, space) ?:
			      crypto_shash_export(&dctx->fallback, &state);
			if (err)
				goto out;
			count -= space;
			in += space;
		} else {
			memcpy(state.buf + leftover, in, count);
			in = state.buf;
			count += leftover;
			state.count &= ~(SHA1_BLOCK_SIZE - 1);
		}
	}

	memcpy(result, &state.state, SHA256_DIGEST_SIZE);

	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0" /* rep xsha256 */
		      : \
		      : "c"((unsigned long)state.count + count), \
			"a"((unsigned long)state.count), \
			"S"(in), "D"(result));

	padlock_output_block((uint32_t *)result, (uint32_t *)out, 8);

out:
	return err;
}

static int padlock_sha256_final(struct shash_desc *desc, u8 *out)
{
	u8 buf[4];

	return padlock_sha256_finup(desc, buf, 0, out);
}

static int padlock_init_tfm(struct crypto_shash *hash)
{
	const char *fallback_driver_name = crypto_shash_alg_name(hash);
	struct padlock_sha_ctx *ctx = crypto_shash_ctx(hash);
	struct crypto_shash *fallback_tfm;

	/* Allocate a fallback and abort if it failed. */
	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
					  CRYPTO_ALG_NEED_FALLBACK);
	if (IS_ERR(fallback_tfm)) {
		printk(KERN_WARNING PFX "Fallback driver '%s' could not be loaded!\n",
		       fallback_driver_name);
		return PTR_ERR(fallback_tfm);
	}

	ctx->fallback = fallback_tfm;
	hash->descsize += crypto_shash_descsize(fallback_tfm);
	return 0;
}

static void padlock_exit_tfm(struct crypto_shash *hash)
{
	struct padlock_sha_ctx *ctx = crypto_shash_ctx(hash);

	crypto_free_shash(ctx->fallback);
}

static struct shash_alg sha1_alg = {
	.digestsize	=	SHA1_DIGEST_SIZE,
	.init   	= 	padlock_sha_init,
	.update 	=	padlock_sha_update,
	.finup  	=	padlock_sha1_finup,
	.final  	=	padlock_sha1_final,
	.export		=	padlock_sha_export,
	.import		=	padlock_sha_import,
	.init_tfm	=	padlock_init_tfm,
	.exit_tfm	=	padlock_exit_tfm,
	.descsize	=	sizeof(struct padlock_sha_desc),
	.statesize	=	sizeof(struct sha1_state),
	.base		=	{
		.cra_name		=	"sha1",
		.cra_driver_name	=	"sha1-padlock",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_flags		=	CRYPTO_ALG_NEED_FALLBACK,
		.cra_blocksize		=	SHA1_BLOCK_SIZE,
		.cra_ctxsize		=	sizeof(struct padlock_sha_ctx),
		.cra_module		=	THIS_MODULE,
	}
};

static struct shash_alg sha256_alg = {
	.digestsize	=	SHA256_DIGEST_SIZE,
	.init   	= 	padlock_sha_init,
	.update 	=	padlock_sha_update,
	.finup  	=	padlock_sha256_finup,
	.final  	=	padlock_sha256_final,
	.export		=	padlock_sha_export,
	.import		=	padlock_sha_import,
	.init_tfm	=	padlock_init_tfm,
	.exit_tfm	=	padlock_exit_tfm,
	.descsize	=	sizeof(struct padlock_sha_desc),
	.statesize	=	sizeof(struct sha256_state),
	.base		=	{
		.cra_name		=	"sha256",
		.cra_driver_name	=	"sha256-padlock",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_flags		=	CRYPTO_ALG_NEED_FALLBACK,
		.cra_blocksize		=	SHA256_BLOCK_SIZE,
		.cra_ctxsize		=	sizeof(struct padlock_sha_ctx),
		.cra_module		=	THIS_MODULE,
	}
};

/* Add two shash_alg instance for hardware-implemented *
* multiple-parts hash supported by VIA Nano Processor.*/
static int padlock_sha1_init_nano(struct shash_desc *desc)
{
	struct sha1_state *sctx = shash_desc_ctx(desc);

	*sctx = (struct sha1_state){
		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
	};

	return 0;
}

static int padlock_sha1_update_nano(struct shash_desc *desc,
			const u8 *data,	unsigned int len)
{
	struct sha1_state *sctx = shash_desc_ctx(desc);
	unsigned int partial, done;
	const u8 *src;
	/*The PHE require the out buffer must 128 bytes and 16-bytes aligned*/
	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	partial = sctx->count & 0x3f;
	sctx->count += len;
	done = 0;
	src = data;
	memcpy(dst, (u8 *)(sctx->state), SHA1_DIGEST_SIZE);

	if ((partial + len) >= SHA1_BLOCK_SIZE) {

		/* Append the bytes in state's buffer to a block to handle */
		if (partial) {
			done = -partial;
			memcpy(sctx->buffer + partial, data,
				done + SHA1_BLOCK_SIZE);
			src = sctx->buffer;
			asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
			: "+S"(src), "+D"(dst) \
			: "a"((long)-1), "c"((unsigned long)1));
			done += SHA1_BLOCK_SIZE;
			src = data + done;
		}

		/* Process the left bytes from the input data */
		if (len - done >= SHA1_BLOCK_SIZE) {
			asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1),
			"c"((unsigned long)((len - done) / SHA1_BLOCK_SIZE)));
			done += ((len - done) - (len - done) % SHA1_BLOCK_SIZE);
			src = data + done;
		}
		partial = 0;
	}
	memcpy((u8 *)(sctx->state), dst, SHA1_DIGEST_SIZE);
	memcpy(sctx->buffer + partial, src, len - done);

	return 0;
}

static int padlock_sha1_final_nano(struct shash_desc *desc, u8 *out)
{
	struct sha1_state *state = (struct sha1_state *)shash_desc_ctx(desc);
	unsigned int partial, padlen;
	__be64 bits;
	static const u8 padding[64] = { 0x80, };

	bits = cpu_to_be64(state->count << 3);

	/* Pad out to 56 mod 64 */
	partial = state->count & 0x3f;
	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	padlock_sha1_update_nano(desc, padding, padlen);

	/* Append length field bytes */
	padlock_sha1_update_nano(desc, (const u8 *)&bits, sizeof(bits));

	/* Swap to output */
	padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 5);

	return 0;
}

static int padlock_sha256_init_nano(struct shash_desc *desc)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);

	*sctx = (struct sha256_state){
		.state = { SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, \
				SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7},
	};

	return 0;
}

static int padlock_sha256_update_nano(struct shash_desc *desc, const u8 *data,
			  unsigned int len)
{
	struct sha256_state *sctx = shash_desc_ctx(desc);
	unsigned int partial, done;
	const u8 *src;
	/*The PHE require the out buffer must 128 bytes and 16-bytes aligned*/
	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
		((aligned(STACK_ALIGN)));
	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	partial = sctx->count & 0x3f;
	sctx->count += len;
	done = 0;
	src = data;
	memcpy(dst, (u8 *)(sctx->state), SHA256_DIGEST_SIZE);

	if ((partial + len) >= SHA256_BLOCK_SIZE) {

		/* Append the bytes in state's buffer to a block to handle */
		if (partial) {
			done = -partial;
			memcpy(sctx->buf + partial, data,
				done + SHA256_BLOCK_SIZE);
			src = sctx->buf;
			asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1), "c"((unsigned long)1));
			done += SHA256_BLOCK_SIZE;
			src = data + done;
		}

		/* Process the left bytes from input data*/
		if (len - done >= SHA256_BLOCK_SIZE) {
			asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
			: "+S"(src), "+D"(dst)
			: "a"((long)-1),
			"c"((unsigned long)((len - done) / 64)));
			done += ((len - done) - (len - done) % 64);
			src = data + done;
		}
		partial = 0;
	}
	memcpy((u8 *)(sctx->state), dst, SHA256_DIGEST_SIZE);
	memcpy(sctx->buf + partial, src, len - done);

	return 0;
}

static int padlock_sha256_final_nano(struct shash_desc *desc, u8 *out)
{
	struct sha256_state *state =
		(struct sha256_state *)shash_desc_ctx(desc);
	unsigned int partial, padlen;
	__be64 bits;
	static const u8 padding[64] = { 0x80, };

	bits = cpu_to_be64(state->count << 3);

	/* Pad out to 56 mod 64 */
	partial = state->count & 0x3f;
	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	padlock_sha256_update_nano(desc, padding, padlen);

	/* Append length field bytes */
	padlock_sha256_update_nano(desc, (const u8 *)&bits, sizeof(bits));

	/* Swap to output */
	padlock_output_block((uint32_t *)(state->state), (uint32_t *)out, 8);

	return 0;
}

static int padlock_sha_export_nano(struct shash_desc *desc,
				void *out)
{
	int statesize = crypto_shash_statesize(desc->tfm);
	void *sctx = shash_desc_ctx(desc);

	memcpy(out, sctx, statesize);
	return 0;
}

static int padlock_sha_import_nano(struct shash_desc *desc,
				const void *in)
{
	int statesize = crypto_shash_statesize(desc->tfm);
	void *sctx = shash_desc_ctx(desc);

	memcpy(sctx, in, statesize);
	return 0;
}

static struct shash_alg sha1_alg_nano = {
	.digestsize	=	SHA1_DIGEST_SIZE,
	.init		=	padlock_sha1_init_nano,
	.update		=	padlock_sha1_update_nano,
	.final		=	padlock_sha1_final_nano,
	.export		=	padlock_sha_export_nano,
	.import		=	padlock_sha_import_nano,
	.descsize	=	sizeof(struct sha1_state),
	.statesize	=	sizeof(struct sha1_state),
	.base		=	{
		.cra_name		=	"sha1",
		.cra_driver_name	=	"sha1-padlock-nano",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_blocksize		=	SHA1_BLOCK_SIZE,
		.cra_module		=	THIS_MODULE,
	}
};

static struct shash_alg sha256_alg_nano = {
	.digestsize	=	SHA256_DIGEST_SIZE,
	.init		=	padlock_sha256_init_nano,
	.update		=	padlock_sha256_update_nano,
	.final		=	padlock_sha256_final_nano,
	.export		=	padlock_sha_export_nano,
	.import		=	padlock_sha_import_nano,
	.descsize	=	sizeof(struct sha256_state),
	.statesize	=	sizeof(struct sha256_state),
	.base		=	{
		.cra_name		=	"sha256",
		.cra_driver_name	=	"sha256-padlock-nano",
		.cra_priority		=	PADLOCK_CRA_PRIORITY,
		.cra_blocksize		=	SHA256_BLOCK_SIZE,
		.cra_module		=	THIS_MODULE,
	}
};

static const struct x86_cpu_id padlock_sha_ids[] = {
	X86_MATCH_FEATURE(X86_FEATURE_PHE, NULL),
	{}
};
MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);

static int __init padlock_init(void)
{
	int rc = -ENODEV;
	struct cpuinfo_x86 *c = &cpu_data(0);
	struct shash_alg *sha1;
	struct shash_alg *sha256;

	if (!x86_match_cpu(padlock_sha_ids) || !boot_cpu_has(X86_FEATURE_PHE_EN))
		return -ENODEV;

	/* Register the newly added algorithm module if on *
	* VIA Nano processor, or else just do as before */
	if (c->x86_model < 0x0f) {
		sha1 = &sha1_alg;
		sha256 = &sha256_alg;
	} else {
		sha1 = &sha1_alg_nano;
		sha256 = &sha256_alg_nano;
	}

	rc = crypto_register_shash(sha1);
	if (rc)
		goto out;

	rc = crypto_register_shash(sha256);
	if (rc)
		goto out_unreg1;

	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for SHA1/SHA256 algorithms.\n");

	return 0;

out_unreg1:
	crypto_unregister_shash(sha1);

out:
	printk(KERN_ERR PFX "VIA PadLock SHA1/SHA256 initialization failed.\n");
	return rc;
}

static void __exit padlock_fini(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (c->x86_model >= 0x0f) {
		crypto_unregister_shash(&sha1_alg_nano);
		crypto_unregister_shash(&sha256_alg_nano);
	} else {
		crypto_unregister_shash(&sha1_alg);
		crypto_unregister_shash(&sha256_alg);
	}
}

module_init(padlock_init);
module_exit(padlock_fini);

MODULE_DESCRIPTION("VIA PadLock SHA1/SHA256 algorithms support.");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Michal Ludvig");

MODULE_ALIAS_CRYPTO("sha1-all");
MODULE_ALIAS_CRYPTO("sha256-all");
MODULE_ALIAS_CRYPTO("sha1-padlock");
MODULE_ALIAS_CRYPTO("sha256-padlock");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
6c833275 ML	2	/*
	3	* Cryptographic API.
	4	*
	5	* Support for VIA PadLock hardware crypto engine.
	6	*
	7	* Copyright (c) 2006 Michal Ludvig <michal@logix.cz>
6c833275 ML	8	*/
6c833275 ML	9
7d024608	10	#include <crypto/internal/hash.h>
21493088	11	#include <crypto/padlock.h>
5265eeb2	12	#include <crypto/sha.h>
6010439f	13	#include <linux/err.h>
6c833275 ML	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/errno.h>
6c833275 ML	17	#include <linux/interrupt.h>
	18	#include <linux/kernel.h>
	19	#include <linux/scatterlist.h>
3bd391f0	20	#include <asm/cpu_device_id.h>
df6b35f4	21	#include <asm/fpu/api.h>
4c6ab3ee	22
bbbee467 HX	23	struct padlock_sha_desc {
bbbee467 HX	24	struct shash_desc fallback;
6c833275 ML	25	};
6c833275 ML	26
bbbee467 HX	27	struct padlock_sha_ctx {
	28	struct crypto_shash *fallback;
	29	};
6c833275	30
bbbee467	31	static int padlock_sha_init(struct shash_desc *desc)
6c833275	32	{
bbbee467 HX	33	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
bbbee467 HX	34	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);
6c833275	35
bbbee467	36	dctx->fallback.tfm = ctx->fallback;
bbbee467	37	return crypto_shash_init(&dctx->fallback);
6c833275 ML	38	}
6c833275 ML	39
bbbee467 HX	40	static int padlock_sha_update(struct shash_desc *desc,
bbbee467 HX	41	const u8 *data, unsigned int length)
6c833275	42	{
bbbee467	43	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
6c833275	44
bbbee467	45	return crypto_shash_update(&dctx->fallback, data, length);
6c833275 ML	46	}
6c833275 ML	47
a8d7ac27 HX	48	static int padlock_sha_export(struct shash_desc desc, void out)
	49	{
	50	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	51
	52	return crypto_shash_export(&dctx->fallback, out);
	53	}
	54
	55	static int padlock_sha_import(struct shash_desc desc, const void in)
	56	{
	57	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	58	struct padlock_sha_ctx *ctx = crypto_shash_ctx(desc->tfm);
	59
	60	dctx->fallback.tfm = ctx->fallback;
a8d7ac27 HX	61	return crypto_shash_import(&dctx->fallback, in);
	62	}
	63
6c833275 ML	64	static inline void padlock_output_block(uint32_t *src,
	65	uint32_t *dst, size_t count)
	66	{
	67	while (count--)
	68	dst++ = swab32(src++);
	69	}
	70
bbbee467 HX	71	static int padlock_sha1_finup(struct shash_desc desc, const u8 in,
bbbee467 HX	72	unsigned int count, u8 *out)
6c833275 ML	73	{
	74	/* We can't store directly to out as it may be unaligned. /
	75	/* BTW Don't reduce the buffer size below 128 Bytes!
	76	* PadLock microcode needs it that big. */
4c6ab3ee HX	77	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	78	((aligned(STACK_ALIGN)));
	79	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
bbbee467 HX	80	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	81	struct sha1_state state;
	82	unsigned int space;
	83	unsigned int leftover;
bbbee467 HX	84	int err;
bbbee467 HX	85
bbbee467 HX	86	err = crypto_shash_export(&dctx->fallback, &state);
	87	if (err)
	88	goto out;
	89
	90	if (state.count + count > ULONG_MAX)
	91	return crypto_shash_finup(&dctx->fallback, in, count, out);
	92
	93	leftover = ((state.count - 1) & (SHA1_BLOCK_SIZE - 1)) + 1;
	94	space = SHA1_BLOCK_SIZE - leftover;
	95	if (space) {
	96	if (count > space) {
	97	err = crypto_shash_update(&dctx->fallback, in, space) ?:
	98	crypto_shash_export(&dctx->fallback, &state);
	99	if (err)
	100	goto out;
	101	count -= space;
	102	in += space;
	103	} else {
	104	memcpy(state.buffer + leftover, in, count);
	105	in = state.buffer;
	106	count += leftover;
e9b25f16	107	state.count &= ~(SHA1_BLOCK_SIZE - 1);
bbbee467 HX	108	}
	109	}
	110
	111	memcpy(result, &state.state, SHA1_DIGEST_SIZE);
6c833275	112
6c833275	113	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8" /* rep xsha1 */
bbbee467	114	: \
faae8908 HX	115	: "c"((unsigned long)state.count + count), \
faae8908 HX	116	"a"((unsigned long)state.count), \
bbbee467	117	"S"(in), "D"(result));
6c833275 ML	118
6c833275 ML	119	padlock_output_block((uint32_t )result, (uint32_t )out, 5);
bbbee467 HX	120
	121	out:
	122	return err;
6c833275 ML	123	}
6c833275 ML	124
bbbee467 HX	125	static int padlock_sha1_final(struct shash_desc desc, u8 out)
	126	{
	127	u8 buf[4];
	128
	129	return padlock_sha1_finup(desc, buf, 0, out);
	130	}
	131
	132	static int padlock_sha256_finup(struct shash_desc desc, const u8 in,
	133	unsigned int count, u8 *out)
6c833275 ML	134	{
	135	/* We can't store directly to out as it may be unaligned. /
	136	/* BTW Don't reduce the buffer size below 128 Bytes!
	137	* PadLock microcode needs it that big. */
4c6ab3ee HX	138	char buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	139	((aligned(STACK_ALIGN)));
	140	char *result = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
bbbee467 HX	141	struct padlock_sha_desc *dctx = shash_desc_ctx(desc);
	142	struct sha256_state state;
	143	unsigned int space;
	144	unsigned int leftover;
bbbee467	145	int err;
6c833275	146
bbbee467 HX	147	err = crypto_shash_export(&dctx->fallback, &state);
	148	if (err)
	149	goto out;
	150
	151	if (state.count + count > ULONG_MAX)
	152	return crypto_shash_finup(&dctx->fallback, in, count, out);
	153
	154	leftover = ((state.count - 1) & (SHA256_BLOCK_SIZE - 1)) + 1;
	155	space = SHA256_BLOCK_SIZE - leftover;
	156	if (space) {
	157	if (count > space) {
	158	err = crypto_shash_update(&dctx->fallback, in, space) ?:
	159	crypto_shash_export(&dctx->fallback, &state);
	160	if (err)
	161	goto out;
	162	count -= space;
	163	in += space;
	164	} else {
	165	memcpy(state.buf + leftover, in, count);
	166	in = state.buf;
	167	count += leftover;
e9b25f16	168	state.count &= ~(SHA1_BLOCK_SIZE - 1);
bbbee467 HX	169	}
	170	}
	171
	172	memcpy(result, &state.state, SHA256_DIGEST_SIZE);
6c833275 ML	173
6c833275 ML	174	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0" /* rep xsha256 */
bbbee467	175	: \
faae8908 HX	176	: "c"((unsigned long)state.count + count), \
faae8908 HX	177	"a"((unsigned long)state.count), \
bbbee467	178	"S"(in), "D"(result));
6c833275 ML	179
6c833275 ML	180	padlock_output_block((uint32_t )result, (uint32_t )out, 8);
bbbee467 HX	181
	182	out:
	183	return err;
6c833275 ML	184	}
6c833275 ML	185
bbbee467	186	static int padlock_sha256_final(struct shash_desc desc, u8 out)
6c833275	187	{
bbbee467	188	u8 buf[4];
6c833275	189
bbbee467	190	return padlock_sha256_finup(desc, buf, 0, out);
6c833275 ML	191	}
6c833275 ML	192
96895693	193	static int padlock_init_tfm(struct crypto_shash *hash)
6c833275	194	{
96895693 HX	195	const char *fallback_driver_name = crypto_shash_alg_name(hash);
96895693 HX	196	struct padlock_sha_ctx *ctx = crypto_shash_ctx(hash);
7d024608	197	struct crypto_shash *fallback_tfm;
6010439f	198
6c833275	199	/* Allocate a fallback and abort if it failed. */
7d024608 HX	200	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
7d024608 HX	201	CRYPTO_ALG_NEED_FALLBACK);
6010439f	202	if (IS_ERR(fallback_tfm)) {
6c833275 ML	203	printk(KERN_WARNING PFX "Fallback driver '%s' could not be loaded!\n",
6c833275 ML	204	fallback_driver_name);
96895693	205	return PTR_ERR(fallback_tfm);
6c833275 ML	206	}
6c833275 ML	207
bbbee467 HX	208	ctx->fallback = fallback_tfm;
bbbee467 HX	209	hash->descsize += crypto_shash_descsize(fallback_tfm);
6c833275 ML	210	return 0;
	211	}
	212
96895693	213	static void padlock_exit_tfm(struct crypto_shash *hash)
6c833275	214	{
96895693	215	struct padlock_sha_ctx *ctx = crypto_shash_ctx(hash);
7d024608	216
bbbee467	217	crypto_free_shash(ctx->fallback);
6c833275 ML	218	}
6c833275 ML	219
bbbee467 HX	220	static struct shash_alg sha1_alg = {
	221	.digestsize = SHA1_DIGEST_SIZE,
	222	.init = padlock_sha_init,
	223	.update = padlock_sha_update,
	224	.finup = padlock_sha1_finup,
	225	.final = padlock_sha1_final,
a8d7ac27 HX	226	.export = padlock_sha_export,
a8d7ac27 HX	227	.import = padlock_sha_import,
96895693 HX	228	.init_tfm = padlock_init_tfm,
96895693 HX	229	.exit_tfm = padlock_exit_tfm,
bbbee467	230	.descsize = sizeof(struct padlock_sha_desc),
a8d7ac27	231	.statesize = sizeof(struct sha1_state),
bbbee467 HX	232	.base = {
	233	.cra_name = "sha1",
	234	.cra_driver_name = "sha1-padlock",
	235	.cra_priority = PADLOCK_CRA_PRIORITY,
e50944e2	236	.cra_flags = CRYPTO_ALG_NEED_FALLBACK,
bbbee467 HX	237	.cra_blocksize = SHA1_BLOCK_SIZE,
	238	.cra_ctxsize = sizeof(struct padlock_sha_ctx),
	239	.cra_module = THIS_MODULE,
6c833275 ML	240	}
	241	};
	242
bbbee467 HX	243	static struct shash_alg sha256_alg = {
	244	.digestsize = SHA256_DIGEST_SIZE,
	245	.init = padlock_sha_init,
	246	.update = padlock_sha_update,
	247	.finup = padlock_sha256_finup,
	248	.final = padlock_sha256_final,
a8d7ac27 HX	249	.export = padlock_sha_export,
a8d7ac27 HX	250	.import = padlock_sha_import,
96895693 HX	251	.init_tfm = padlock_init_tfm,
96895693 HX	252	.exit_tfm = padlock_exit_tfm,
bbbee467	253	.descsize = sizeof(struct padlock_sha_desc),
a8d7ac27	254	.statesize = sizeof(struct sha256_state),
bbbee467 HX	255	.base = {
	256	.cra_name = "sha256",
	257	.cra_driver_name = "sha256-padlock",
	258	.cra_priority = PADLOCK_CRA_PRIORITY,
e50944e2	259	.cra_flags = CRYPTO_ALG_NEED_FALLBACK,
bbbee467 HX	260	.cra_blocksize = SHA256_BLOCK_SIZE,
	261	.cra_ctxsize = sizeof(struct padlock_sha_ctx),
	262	.cra_module = THIS_MODULE,
6c833275 ML	263	}
	264	};
	265
0475add3 BW	266	/* Add two shash_alg instance for hardware-implemented *
	267	* multiple-parts hash supported by VIA Nano Processor.*/
	268	static int padlock_sha1_init_nano(struct shash_desc *desc)
	269	{
	270	struct sha1_state *sctx = shash_desc_ctx(desc);
	271
	272	*sctx = (struct sha1_state){
	273	.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
	274	};
	275
	276	return 0;
	277	}
	278
	279	static int padlock_sha1_update_nano(struct shash_desc *desc,
	280	const u8 *data, unsigned int len)
	281	{
	282	struct sha1_state *sctx = shash_desc_ctx(desc);
	283	unsigned int partial, done;
	284	const u8 *src;
	285	/The PHE require the out buffer must 128 bytes and 16-bytes aligned/
	286	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	287	((aligned(STACK_ALIGN)));
	288	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0475add3 BW	289
	290	partial = sctx->count & 0x3f;
	291	sctx->count += len;
	292	done = 0;
	293	src = data;
	294	memcpy(dst, (u8 *)(sctx->state), SHA1_DIGEST_SIZE);
	295
	296	if ((partial + len) >= SHA1_BLOCK_SIZE) {
	297
	298	/* Append the bytes in state's buffer to a block to handle */
	299	if (partial) {
	300	done = -partial;
	301	memcpy(sctx->buffer + partial, data,
	302	done + SHA1_BLOCK_SIZE);
	303	src = sctx->buffer;
0475add3 BW	304	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
	305	: "+S"(src), "+D"(dst) \
	306	: "a"((long)-1), "c"((unsigned long)1));
0475add3 BW	307	done += SHA1_BLOCK_SIZE;
	308	src = data + done;
	309	}
	310
	311	/* Process the left bytes from the input data */
	312	if (len - done >= SHA1_BLOCK_SIZE) {
0475add3 BW	313	asm volatile (".byte 0xf3,0x0f,0xa6,0xc8"
	314	: "+S"(src), "+D"(dst)
	315	: "a"((long)-1),
	316	"c"((unsigned long)((len - done) / SHA1_BLOCK_SIZE)));
0475add3 BW	317	done += ((len - done) - (len - done) % SHA1_BLOCK_SIZE);
	318	src = data + done;
	319	}
	320	partial = 0;
	321	}
	322	memcpy((u8 *)(sctx->state), dst, SHA1_DIGEST_SIZE);
	323	memcpy(sctx->buffer + partial, src, len - done);
	324
	325	return 0;
	326	}
	327
	328	static int padlock_sha1_final_nano(struct shash_desc desc, u8 out)
	329	{
	330	struct sha1_state state = (struct sha1_state )shash_desc_ctx(desc);
	331	unsigned int partial, padlen;
	332	__be64 bits;
	333	static const u8 padding[64] = { 0x80, };
	334
	335	bits = cpu_to_be64(state->count << 3);
	336
	337	/* Pad out to 56 mod 64 */
	338	partial = state->count & 0x3f;
	339	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	340	padlock_sha1_update_nano(desc, padding, padlen);
	341
	342	/* Append length field bytes */
	343	padlock_sha1_update_nano(desc, (const u8 *)&bits, sizeof(bits));
	344
	345	/* Swap to output */
	346	padlock_output_block((uint32_t )(state->state), (uint32_t )out, 5);
	347
	348	return 0;
	349	}
	350
	351	static int padlock_sha256_init_nano(struct shash_desc *desc)
	352	{
	353	struct sha256_state *sctx = shash_desc_ctx(desc);
	354
	355	*sctx = (struct sha256_state){
	356	.state = { SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, \
	357	SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7},
	358	};
	359
	360	return 0;
	361	}
	362
	363	static int padlock_sha256_update_nano(struct shash_desc desc, const u8 data,
	364	unsigned int len)
	365	{
	366	struct sha256_state *sctx = shash_desc_ctx(desc);
	367	unsigned int partial, done;
	368	const u8 *src;
	369	/The PHE require the out buffer must 128 bytes and 16-bytes aligned/
	370	u8 buf[128 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
	371	((aligned(STACK_ALIGN)));
	372	u8 *dst = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0475add3 BW	373
	374	partial = sctx->count & 0x3f;
	375	sctx->count += len;
	376	done = 0;
	377	src = data;
	378	memcpy(dst, (u8 *)(sctx->state), SHA256_DIGEST_SIZE);
	379
	380	if ((partial + len) >= SHA256_BLOCK_SIZE) {
	381
	382	/* Append the bytes in state's buffer to a block to handle */
	383	if (partial) {
	384	done = -partial;
	385	memcpy(sctx->buf + partial, data,
	386	done + SHA256_BLOCK_SIZE);
	387	src = sctx->buf;
0475add3 BW	388	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
	389	: "+S"(src), "+D"(dst)
	390	: "a"((long)-1), "c"((unsigned long)1));
0475add3 BW	391	done += SHA256_BLOCK_SIZE;
	392	src = data + done;
	393	}
	394
	395	/* Process the left bytes from input data*/
	396	if (len - done >= SHA256_BLOCK_SIZE) {
0475add3 BW	397	asm volatile (".byte 0xf3,0x0f,0xa6,0xd0"
	398	: "+S"(src), "+D"(dst)
	399	: "a"((long)-1),
	400	"c"((unsigned long)((len - done) / 64)));
0475add3 BW	401	done += ((len - done) - (len - done) % 64);
	402	src = data + done;
	403	}
	404	partial = 0;
	405	}
	406	memcpy((u8 *)(sctx->state), dst, SHA256_DIGEST_SIZE);
	407	memcpy(sctx->buf + partial, src, len - done);
	408
	409	return 0;
	410	}
	411
	412	static int padlock_sha256_final_nano(struct shash_desc desc, u8 out)
	413	{
	414	struct sha256_state *state =
	415	(struct sha256_state *)shash_desc_ctx(desc);
	416	unsigned int partial, padlen;
	417	__be64 bits;
	418	static const u8 padding[64] = { 0x80, };
	419
	420	bits = cpu_to_be64(state->count << 3);
	421
	422	/* Pad out to 56 mod 64 */
	423	partial = state->count & 0x3f;
	424	padlen = (partial < 56) ? (56 - partial) : ((64+56) - partial);
	425	padlock_sha256_update_nano(desc, padding, padlen);
	426
	427	/* Append length field bytes */
	428	padlock_sha256_update_nano(desc, (const u8 *)&bits, sizeof(bits));
	429
	430	/* Swap to output */
	431	padlock_output_block((uint32_t )(state->state), (uint32_t )out, 8);
	432
	433	return 0;
	434	}
	435
	436	static int padlock_sha_export_nano(struct shash_desc *desc,
	437	void *out)
	438	{
	439	int statesize = crypto_shash_statesize(desc->tfm);
	440	void *sctx = shash_desc_ctx(desc);
	441
	442	memcpy(out, sctx, statesize);
	443	return 0;
	444	}
	445
	446	static int padlock_sha_import_nano(struct shash_desc *desc,
	447	const void *in)
	448	{
	449	int statesize = crypto_shash_statesize(desc->tfm);
	450	void *sctx = shash_desc_ctx(desc);
	451
	452	memcpy(sctx, in, statesize);
	453	return 0;
	454	}
	455
	456	static struct shash_alg sha1_alg_nano = {
	457	.digestsize = SHA1_DIGEST_SIZE,
	458	.init = padlock_sha1_init_nano,
	459	.update = padlock_sha1_update_nano,
	460	.final = padlock_sha1_final_nano,
	461	.export = padlock_sha_export_nano,
	462	.import = padlock_sha_import_nano,
	463	.descsize = sizeof(struct sha1_state),
	464	.statesize = sizeof(struct sha1_state),
465	.base = {
466	.cra_name = "sha1",
467	.cra_driver_name = "sha1-padlock-nano",
468	.cra_priority = PADLOCK_CRA_PRIORITY,
0475add3 BW	469	.cra_blocksize = SHA1_BLOCK_SIZE,
	470	.cra_module = THIS_MODULE,
	471	}
	472	};
	473
	474	static struct shash_alg sha256_alg_nano = {
	475	.digestsize = SHA256_DIGEST_SIZE,
	476	.init = padlock_sha256_init_nano,
	477	.update = padlock_sha256_update_nano,
	478	.final = padlock_sha256_final_nano,
	479	.export = padlock_sha_export_nano,
	480	.import = padlock_sha_import_nano,
	481	.descsize = sizeof(struct sha256_state),
	482	.statesize = sizeof(struct sha256_state),
	483	.base = {
	484	.cra_name = "sha256",
	485	.cra_driver_name = "sha256-padlock-nano",
	486	.cra_priority = PADLOCK_CRA_PRIORITY,
0475add3 BW	487	.cra_blocksize = SHA256_BLOCK_SIZE,
	488	.cra_module = THIS_MODULE,
	489	}
	490	};
	491
16d5cee5	492	static const struct x86_cpu_id padlock_sha_ids[] = {
f30cfaca	493	X86_MATCH_FEATURE(X86_FEATURE_PHE, NULL),
3bd391f0 AK	494	{}
	495	};
	496	MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);
	497
6c833275 ML	498	static int __init padlock_init(void)
	499	{
	500	int rc = -ENODEV;
0475add3 BW	501	struct cpuinfo_x86 *c = &cpu_data(0);
	502	struct shash_alg *sha1;
	503	struct shash_alg *sha256;
6c833275	504
362f924b	505	if (!x86_match_cpu(padlock_sha_ids) \|\| !boot_cpu_has(X86_FEATURE_PHE_EN))
6c833275	506	return -ENODEV;
6c833275	507
0475add3 BW	508	/* Register the newly added algorithm module if on *
	509	* VIA Nano processor, or else just do as before */
	510	if (c->x86_model < 0x0f) {
	511	sha1 = &sha1_alg;
	512	sha256 = &sha256_alg;
	513	} else {
	514	sha1 = &sha1_alg_nano;
	515	sha256 = &sha256_alg_nano;
	516	}
	517
	518	rc = crypto_register_shash(sha1);
6c833275 ML	519	if (rc)
	520	goto out;
	521
0475add3	522	rc = crypto_register_shash(sha256);
6c833275 ML	523	if (rc)
	524	goto out_unreg1;
	525
	526	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for SHA1/SHA256 algorithms.\n");
	527
	528	return 0;
	529
	530	out_unreg1:
0475add3 BW	531	crypto_unregister_shash(sha1);
0475add3 BW	532
6c833275 ML	533	out:
	534	printk(KERN_ERR PFX "VIA PadLock SHA1/SHA256 initialization failed.\n");
	535	return rc;
	536	}
	537
	538	static void __exit padlock_fini(void)
	539	{
0475add3 BW	540	struct cpuinfo_x86 *c = &cpu_data(0);
	541
	542	if (c->x86_model >= 0x0f) {
	543	crypto_unregister_shash(&sha1_alg_nano);
	544	crypto_unregister_shash(&sha256_alg_nano);
	545	} else {
	546	crypto_unregister_shash(&sha1_alg);
	547	crypto_unregister_shash(&sha256_alg);
	548	}
6c833275 ML	549	}
	550
	551	module_init(padlock_init);
	552	module_exit(padlock_fini);
	553
	554	MODULE_DESCRIPTION("VIA PadLock SHA1/SHA256 algorithms support.");
	555	MODULE_LICENSE("GPL");
	556	MODULE_AUTHOR("Michal Ludvig");
	557
5d26a105 KC	558	MODULE_ALIAS_CRYPTO("sha1-all");
	559	MODULE_ALIAS_CRYPTO("sha256-all");
	560	MODULE_ALIAS_CRYPTO("sha1-padlock");
	561	MODULE_ALIAS_CRYPTO("sha256-padlock");