Commit | Line | Data |
---|---|---|
09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Cryptographic API. | |
4 | * | |
5 | * Support for VIA PadLock hardware crypto engine. | |
6 | * | |
7 | * Copyright (c) 2004 Michal Ludvig <michal@logix.cz> | |
8 | * | |
1da177e4 LT |
9 | */ |
10 | ||
28ce728a | 11 | #include <crypto/algapi.h> |
89e12654 | 12 | #include <crypto/aes.h> |
21493088 | 13 | #include <crypto/padlock.h> |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/init.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/errno.h> | |
1da177e4 | 18 | #include <linux/interrupt.h> |
6789b2dc | 19 | #include <linux/kernel.h> |
420a4b20 HX |
20 | #include <linux/percpu.h> |
21 | #include <linux/smp.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
3bd391f0 | 23 | #include <asm/cpu_device_id.h> |
1da177e4 | 24 | #include <asm/byteorder.h> |
a76c1c23 | 25 | #include <asm/processor.h> |
df6b35f4 | 26 | #include <asm/fpu/api.h> |
1da177e4 | 27 | |
8d8409f7 CE |
28 | /* |
29 | * Number of data blocks actually fetched for each xcrypt insn. | |
30 | * Processors with prefetch errata will fetch extra blocks. | |
31 | */ | |
a76c1c23 | 32 | static unsigned int ecb_fetch_blocks = 2; |
8d8409f7 | 33 | #define MAX_ECB_FETCH_BLOCKS (8) |
a76c1c23 | 34 | #define ecb_fetch_bytes (ecb_fetch_blocks * AES_BLOCK_SIZE) |
8d8409f7 CE |
35 | |
36 | static unsigned int cbc_fetch_blocks = 1; | |
37 | #define MAX_CBC_FETCH_BLOCKS (4) | |
a76c1c23 CE |
38 | #define cbc_fetch_bytes (cbc_fetch_blocks * AES_BLOCK_SIZE) |
39 | ||
ccc17c34 ML |
40 | /* Control word. */ |
41 | struct cword { | |
42 | unsigned int __attribute__ ((__packed__)) | |
43 | rounds:4, | |
44 | algo:3, | |
45 | keygen:1, | |
46 | interm:1, | |
47 | encdec:1, | |
48 | ksize:2; | |
49 | } __attribute__ ((__aligned__(PADLOCK_ALIGNMENT))); | |
50 | ||
cc08632f ML |
51 | /* Whenever making any changes to the following |
52 | * structure *make sure* you keep E, d_data | |
7dc748e4 SS |
53 | * and cword aligned on 16 Bytes boundaries and |
54 | * the Hardware can access 16 * 16 bytes of E and d_data | |
55 | * (only the first 15 * 16 bytes matter but the HW reads | |
56 | * more). | |
57 | */ | |
1da177e4 | 58 | struct aes_ctx { |
7dc748e4 SS |
59 | u32 E[AES_MAX_KEYLENGTH_U32] |
60 | __attribute__ ((__aligned__(PADLOCK_ALIGNMENT))); | |
61 | u32 d_data[AES_MAX_KEYLENGTH_U32] | |
62 | __attribute__ ((__aligned__(PADLOCK_ALIGNMENT))); | |
6789b2dc HX |
63 | struct { |
64 | struct cword encrypt; | |
65 | struct cword decrypt; | |
66 | } cword; | |
82062c72 | 67 | u32 *D; |
1da177e4 LT |
68 | }; |
69 | ||
390dfd95 | 70 | static DEFINE_PER_CPU(struct cword *, paes_last_cword); |
420a4b20 | 71 | |
1da177e4 LT |
72 | /* Tells whether the ACE is capable to generate |
73 | the extended key for a given key_len. */ | |
74 | static inline int | |
75 | aes_hw_extkey_available(uint8_t key_len) | |
76 | { | |
77 | /* TODO: We should check the actual CPU model/stepping | |
78 | as it's possible that the capability will be | |
79 | added in the next CPU revisions. */ | |
80 | if (key_len == 16) | |
81 | return 1; | |
82 | return 0; | |
83 | } | |
84 | ||
28ce728a | 85 | static inline struct aes_ctx *aes_ctx_common(void *ctx) |
6789b2dc | 86 | { |
28ce728a | 87 | unsigned long addr = (unsigned long)ctx; |
f10b7897 HX |
88 | unsigned long align = PADLOCK_ALIGNMENT; |
89 | ||
90 | if (align <= crypto_tfm_ctx_alignment()) | |
91 | align = 1; | |
6c2bb98b | 92 | return (struct aes_ctx *)ALIGN(addr, align); |
6789b2dc HX |
93 | } |
94 | ||
28ce728a HX |
95 | static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm) |
96 | { | |
97 | return aes_ctx_common(crypto_tfm_ctx(tfm)); | |
98 | } | |
99 | ||
100 | static inline struct aes_ctx *blk_aes_ctx(struct crypto_blkcipher *tfm) | |
101 | { | |
102 | return aes_ctx_common(crypto_blkcipher_ctx(tfm)); | |
103 | } | |
104 | ||
6c2bb98b | 105 | static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key, |
560c06ae | 106 | unsigned int key_len) |
1da177e4 | 107 | { |
6c2bb98b | 108 | struct aes_ctx *ctx = aes_ctx(tfm); |
06ace7a9 | 109 | const __le32 *key = (const __le32 *)in_key; |
560c06ae | 110 | u32 *flags = &tfm->crt_flags; |
7dc748e4 | 111 | struct crypto_aes_ctx gen_aes; |
420a4b20 | 112 | int cpu; |
1da177e4 | 113 | |
560c06ae | 114 | if (key_len % 8) { |
1da177e4 LT |
115 | *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; |
116 | return -EINVAL; | |
117 | } | |
118 | ||
6789b2dc HX |
119 | /* |
120 | * If the hardware is capable of generating the extended key | |
121 | * itself we must supply the plain key for both encryption | |
122 | * and decryption. | |
123 | */ | |
82062c72 | 124 | ctx->D = ctx->E; |
1da177e4 | 125 | |
7dc748e4 SS |
126 | ctx->E[0] = le32_to_cpu(key[0]); |
127 | ctx->E[1] = le32_to_cpu(key[1]); | |
128 | ctx->E[2] = le32_to_cpu(key[2]); | |
129 | ctx->E[3] = le32_to_cpu(key[3]); | |
1da177e4 | 130 | |
6789b2dc HX |
131 | /* Prepare control words. */ |
132 | memset(&ctx->cword, 0, sizeof(ctx->cword)); | |
133 | ||
134 | ctx->cword.decrypt.encdec = 1; | |
135 | ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4; | |
136 | ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds; | |
137 | ctx->cword.encrypt.ksize = (key_len - 16) / 8; | |
138 | ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize; | |
139 | ||
1da177e4 LT |
140 | /* Don't generate extended keys if the hardware can do it. */ |
141 | if (aes_hw_extkey_available(key_len)) | |
420a4b20 | 142 | goto ok; |
1da177e4 | 143 | |
6789b2dc HX |
144 | ctx->D = ctx->d_data; |
145 | ctx->cword.encrypt.keygen = 1; | |
146 | ctx->cword.decrypt.keygen = 1; | |
147 | ||
8131878d | 148 | if (aes_expandkey(&gen_aes, in_key, key_len)) { |
7dc748e4 SS |
149 | *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; |
150 | return -EINVAL; | |
1da177e4 LT |
151 | } |
152 | ||
7dc748e4 SS |
153 | memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH); |
154 | memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH); | |
420a4b20 HX |
155 | |
156 | ok: | |
157 | for_each_online_cpu(cpu) | |
390dfd95 TH |
158 | if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) || |
159 | &ctx->cword.decrypt == per_cpu(paes_last_cword, cpu)) | |
160 | per_cpu(paes_last_cword, cpu) = NULL; | |
420a4b20 | 161 | |
1da177e4 LT |
162 | return 0; |
163 | } | |
164 | ||
165 | /* ====== Encryption/decryption routines ====== */ | |
166 | ||
28e8c3ad | 167 | /* These are the real call to PadLock. */ |
420a4b20 HX |
168 | static inline void padlock_reset_key(struct cword *cword) |
169 | { | |
170 | int cpu = raw_smp_processor_id(); | |
171 | ||
390dfd95 | 172 | if (cword != per_cpu(paes_last_cword, cpu)) |
d1c8b0a7 | 173 | #ifndef CONFIG_X86_64 |
420a4b20 | 174 | asm volatile ("pushfl; popfl"); |
d1c8b0a7 SAS |
175 | #else |
176 | asm volatile ("pushfq; popfq"); | |
177 | #endif | |
420a4b20 HX |
178 | } |
179 | ||
180 | static inline void padlock_store_cword(struct cword *cword) | |
866cd902 | 181 | { |
390dfd95 | 182 | per_cpu(paes_last_cword, raw_smp_processor_id()) = cword; |
866cd902 HX |
183 | } |
184 | ||
e4914012 SS |
185 | /* |
186 | * While the padlock instructions don't use FP/SSE registers, they | |
5a83d60c AL |
187 | * generate a spurious DNA fault when CR0.TS is '1'. Fortunately, |
188 | * the kernel doesn't use CR0.TS. | |
e4914012 SS |
189 | */ |
190 | ||
8d8409f7 | 191 | static inline void rep_xcrypt_ecb(const u8 *input, u8 *output, void *key, |
a76c1c23 | 192 | struct cword *control_word, int count) |
d4a7dd8e HX |
193 | { |
194 | asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */ | |
195 | : "+S"(input), "+D"(output) | |
a76c1c23 | 196 | : "d"(control_word), "b"(key), "c"(count)); |
d4a7dd8e HX |
197 | } |
198 | ||
8d8409f7 CE |
199 | static inline u8 *rep_xcrypt_cbc(const u8 *input, u8 *output, void *key, |
200 | u8 *iv, struct cword *control_word, int count) | |
201 | { | |
202 | asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */ | |
203 | : "+S" (input), "+D" (output), "+a" (iv) | |
204 | : "d" (control_word), "b" (key), "c" (count)); | |
205 | return iv; | |
206 | } | |
207 | ||
208 | static void ecb_crypt_copy(const u8 *in, u8 *out, u32 *key, | |
a76c1c23 | 209 | struct cword *cword, int count) |
d4a7dd8e | 210 | { |
a76c1c23 CE |
211 | /* |
212 | * Padlock prefetches extra data so we must provide mapped input buffers. | |
213 | * Assume there are at least 16 bytes of stack already in use. | |
214 | */ | |
8d8409f7 | 215 | u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1]; |
490fe3f0 | 216 | u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT); |
d4a7dd8e | 217 | |
a76c1c23 | 218 | memcpy(tmp, in, count * AES_BLOCK_SIZE); |
8d8409f7 | 219 | rep_xcrypt_ecb(tmp, out, key, cword, count); |
d4a7dd8e HX |
220 | } |
221 | ||
8d8409f7 CE |
222 | static u8 *cbc_crypt_copy(const u8 *in, u8 *out, u32 *key, |
223 | u8 *iv, struct cword *cword, int count) | |
224 | { | |
225 | /* | |
226 | * Padlock prefetches extra data so we must provide mapped input buffers. | |
227 | * Assume there are at least 16 bytes of stack already in use. | |
228 | */ | |
229 | u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1]; | |
230 | u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT); | |
231 | ||
232 | memcpy(tmp, in, count * AES_BLOCK_SIZE); | |
233 | return rep_xcrypt_cbc(tmp, out, key, iv, cword, count); | |
234 | } | |
235 | ||
236 | static inline void ecb_crypt(const u8 *in, u8 *out, u32 *key, | |
a76c1c23 | 237 | struct cword *cword, int count) |
d4a7dd8e | 238 | { |
a76c1c23 CE |
239 | /* Padlock in ECB mode fetches at least ecb_fetch_bytes of data. |
240 | * We could avoid some copying here but it's probably not worth it. | |
241 | */ | |
1d4bbc5a | 242 | if (unlikely(offset_in_page(in) + ecb_fetch_bytes > PAGE_SIZE)) { |
8d8409f7 | 243 | ecb_crypt_copy(in, out, key, cword, count); |
d4a7dd8e HX |
244 | return; |
245 | } | |
246 | ||
8d8409f7 CE |
247 | rep_xcrypt_ecb(in, out, key, cword, count); |
248 | } | |
249 | ||
250 | static inline u8 *cbc_crypt(const u8 *in, u8 *out, u32 *key, | |
251 | u8 *iv, struct cword *cword, int count) | |
252 | { | |
253 | /* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */ | |
1d4bbc5a | 254 | if (unlikely(offset_in_page(in) + cbc_fetch_bytes > PAGE_SIZE)) |
8d8409f7 CE |
255 | return cbc_crypt_copy(in, out, key, iv, cword, count); |
256 | ||
257 | return rep_xcrypt_cbc(in, out, key, iv, cword, count); | |
d4a7dd8e HX |
258 | } |
259 | ||
6789b2dc HX |
260 | static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key, |
261 | void *control_word, u32 count) | |
1da177e4 | 262 | { |
a76c1c23 CE |
263 | u32 initial = count & (ecb_fetch_blocks - 1); |
264 | ||
265 | if (count < ecb_fetch_blocks) { | |
8d8409f7 | 266 | ecb_crypt(input, output, key, control_word, count); |
d4a7dd8e HX |
267 | return; |
268 | } | |
269 | ||
46d8c4b2 HX |
270 | count -= initial; |
271 | ||
a76c1c23 CE |
272 | if (initial) |
273 | asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */ | |
274 | : "+S"(input), "+D"(output) | |
275 | : "d"(control_word), "b"(key), "c"(initial)); | |
276 | ||
277 | asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */ | |
1da177e4 | 278 | : "+S"(input), "+D"(output) |
46d8c4b2 | 279 | : "d"(control_word), "b"(key), "c"(count)); |
1da177e4 LT |
280 | } |
281 | ||
476df259 HX |
282 | static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key, |
283 | u8 *iv, void *control_word, u32 count) | |
28e8c3ad | 284 | { |
8d8409f7 CE |
285 | u32 initial = count & (cbc_fetch_blocks - 1); |
286 | ||
287 | if (count < cbc_fetch_blocks) | |
288 | return cbc_crypt(input, output, key, iv, control_word, count); | |
289 | ||
46d8c4b2 HX |
290 | count -= initial; |
291 | ||
8d8409f7 CE |
292 | if (initial) |
293 | asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */ | |
294 | : "+S" (input), "+D" (output), "+a" (iv) | |
c054a076 | 295 | : "d" (control_word), "b" (key), "c" (initial)); |
8d8409f7 CE |
296 | |
297 | asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */ | |
28e8c3ad | 298 | : "+S" (input), "+D" (output), "+a" (iv) |
46d8c4b2 | 299 | : "d" (control_word), "b" (key), "c" (count)); |
476df259 | 300 | return iv; |
28e8c3ad HX |
301 | } |
302 | ||
724ecd3c | 303 | static void padlock_aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) |
1da177e4 | 304 | { |
6c2bb98b | 305 | struct aes_ctx *ctx = aes_ctx(tfm); |
e4914012 | 306 | |
420a4b20 | 307 | padlock_reset_key(&ctx->cword.encrypt); |
8d8409f7 | 308 | ecb_crypt(in, out, ctx->E, &ctx->cword.encrypt, 1); |
420a4b20 | 309 | padlock_store_cword(&ctx->cword.encrypt); |
1da177e4 LT |
310 | } |
311 | ||
724ecd3c | 312 | static void padlock_aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) |
1da177e4 | 313 | { |
6c2bb98b | 314 | struct aes_ctx *ctx = aes_ctx(tfm); |
e4914012 | 315 | |
420a4b20 | 316 | padlock_reset_key(&ctx->cword.encrypt); |
8d8409f7 | 317 | ecb_crypt(in, out, ctx->D, &ctx->cword.decrypt, 1); |
420a4b20 | 318 | padlock_store_cword(&ctx->cword.encrypt); |
1da177e4 LT |
319 | } |
320 | ||
321 | static struct crypto_alg aes_alg = { | |
322 | .cra_name = "aes", | |
c8a19c91 | 323 | .cra_driver_name = "aes-padlock", |
ccc17c34 | 324 | .cra_priority = PADLOCK_CRA_PRIORITY, |
1da177e4 LT |
325 | .cra_flags = CRYPTO_ALG_TYPE_CIPHER, |
326 | .cra_blocksize = AES_BLOCK_SIZE, | |
fbdae9f3 | 327 | .cra_ctxsize = sizeof(struct aes_ctx), |
6789b2dc | 328 | .cra_alignmask = PADLOCK_ALIGNMENT - 1, |
1da177e4 | 329 | .cra_module = THIS_MODULE, |
1da177e4 LT |
330 | .cra_u = { |
331 | .cipher = { | |
332 | .cia_min_keysize = AES_MIN_KEY_SIZE, | |
333 | .cia_max_keysize = AES_MAX_KEY_SIZE, | |
334 | .cia_setkey = aes_set_key, | |
724ecd3c AB |
335 | .cia_encrypt = padlock_aes_encrypt, |
336 | .cia_decrypt = padlock_aes_decrypt, | |
1da177e4 LT |
337 | } |
338 | } | |
339 | }; | |
340 | ||
28ce728a HX |
341 | static int ecb_aes_encrypt(struct blkcipher_desc *desc, |
342 | struct scatterlist *dst, struct scatterlist *src, | |
343 | unsigned int nbytes) | |
344 | { | |
345 | struct aes_ctx *ctx = blk_aes_ctx(desc->tfm); | |
346 | struct blkcipher_walk walk; | |
347 | int err; | |
348 | ||
420a4b20 | 349 | padlock_reset_key(&ctx->cword.encrypt); |
866cd902 | 350 | |
28ce728a HX |
351 | blkcipher_walk_init(&walk, dst, src, nbytes); |
352 | err = blkcipher_walk_virt(desc, &walk); | |
353 | ||
354 | while ((nbytes = walk.nbytes)) { | |
355 | padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr, | |
356 | ctx->E, &ctx->cword.encrypt, | |
357 | nbytes / AES_BLOCK_SIZE); | |
358 | nbytes &= AES_BLOCK_SIZE - 1; | |
359 | err = blkcipher_walk_done(desc, &walk, nbytes); | |
360 | } | |
361 | ||
420a4b20 HX |
362 | padlock_store_cword(&ctx->cword.encrypt); |
363 | ||
28ce728a HX |
364 | return err; |
365 | } | |
366 | ||
367 | static int ecb_aes_decrypt(struct blkcipher_desc *desc, | |
368 | struct scatterlist *dst, struct scatterlist *src, | |
369 | unsigned int nbytes) | |
370 | { | |
371 | struct aes_ctx *ctx = blk_aes_ctx(desc->tfm); | |
372 | struct blkcipher_walk walk; | |
373 | int err; | |
374 | ||
420a4b20 | 375 | padlock_reset_key(&ctx->cword.decrypt); |
866cd902 | 376 | |
28ce728a HX |
377 | blkcipher_walk_init(&walk, dst, src, nbytes); |
378 | err = blkcipher_walk_virt(desc, &walk); | |
379 | ||
380 | while ((nbytes = walk.nbytes)) { | |
381 | padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr, | |
382 | ctx->D, &ctx->cword.decrypt, | |
383 | nbytes / AES_BLOCK_SIZE); | |
384 | nbytes &= AES_BLOCK_SIZE - 1; | |
385 | err = blkcipher_walk_done(desc, &walk, nbytes); | |
386 | } | |
420a4b20 HX |
387 | |
388 | padlock_store_cword(&ctx->cword.encrypt); | |
389 | ||
28ce728a HX |
390 | return err; |
391 | } | |
392 | ||
393 | static struct crypto_alg ecb_aes_alg = { | |
394 | .cra_name = "ecb(aes)", | |
395 | .cra_driver_name = "ecb-aes-padlock", | |
396 | .cra_priority = PADLOCK_COMPOSITE_PRIORITY, | |
397 | .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER, | |
398 | .cra_blocksize = AES_BLOCK_SIZE, | |
399 | .cra_ctxsize = sizeof(struct aes_ctx), | |
400 | .cra_alignmask = PADLOCK_ALIGNMENT - 1, | |
401 | .cra_type = &crypto_blkcipher_type, | |
402 | .cra_module = THIS_MODULE, | |
28ce728a HX |
403 | .cra_u = { |
404 | .blkcipher = { | |
405 | .min_keysize = AES_MIN_KEY_SIZE, | |
406 | .max_keysize = AES_MAX_KEY_SIZE, | |
407 | .setkey = aes_set_key, | |
408 | .encrypt = ecb_aes_encrypt, | |
409 | .decrypt = ecb_aes_decrypt, | |
410 | } | |
411 | } | |
412 | }; | |
413 | ||
414 | static int cbc_aes_encrypt(struct blkcipher_desc *desc, | |
415 | struct scatterlist *dst, struct scatterlist *src, | |
416 | unsigned int nbytes) | |
417 | { | |
418 | struct aes_ctx *ctx = blk_aes_ctx(desc->tfm); | |
419 | struct blkcipher_walk walk; | |
420 | int err; | |
421 | ||
420a4b20 | 422 | padlock_reset_key(&ctx->cword.encrypt); |
866cd902 | 423 | |
28ce728a HX |
424 | blkcipher_walk_init(&walk, dst, src, nbytes); |
425 | err = blkcipher_walk_virt(desc, &walk); | |
426 | ||
427 | while ((nbytes = walk.nbytes)) { | |
428 | u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr, | |
429 | walk.dst.virt.addr, ctx->E, | |
430 | walk.iv, &ctx->cword.encrypt, | |
431 | nbytes / AES_BLOCK_SIZE); | |
432 | memcpy(walk.iv, iv, AES_BLOCK_SIZE); | |
433 | nbytes &= AES_BLOCK_SIZE - 1; | |
434 | err = blkcipher_walk_done(desc, &walk, nbytes); | |
435 | } | |
436 | ||
420a4b20 HX |
437 | padlock_store_cword(&ctx->cword.decrypt); |
438 | ||
28ce728a HX |
439 | return err; |
440 | } | |
441 | ||
442 | static int cbc_aes_decrypt(struct blkcipher_desc *desc, | |
443 | struct scatterlist *dst, struct scatterlist *src, | |
444 | unsigned int nbytes) | |
445 | { | |
446 | struct aes_ctx *ctx = blk_aes_ctx(desc->tfm); | |
447 | struct blkcipher_walk walk; | |
448 | int err; | |
449 | ||
420a4b20 | 450 | padlock_reset_key(&ctx->cword.encrypt); |
866cd902 | 451 | |
28ce728a HX |
452 | blkcipher_walk_init(&walk, dst, src, nbytes); |
453 | err = blkcipher_walk_virt(desc, &walk); | |
454 | ||
455 | while ((nbytes = walk.nbytes)) { | |
456 | padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr, | |
457 | ctx->D, walk.iv, &ctx->cword.decrypt, | |
458 | nbytes / AES_BLOCK_SIZE); | |
459 | nbytes &= AES_BLOCK_SIZE - 1; | |
460 | err = blkcipher_walk_done(desc, &walk, nbytes); | |
461 | } | |
462 | ||
420a4b20 HX |
463 | padlock_store_cword(&ctx->cword.encrypt); |
464 | ||
28ce728a HX |
465 | return err; |
466 | } | |
467 | ||
468 | static struct crypto_alg cbc_aes_alg = { | |
469 | .cra_name = "cbc(aes)", | |
470 | .cra_driver_name = "cbc-aes-padlock", | |
471 | .cra_priority = PADLOCK_COMPOSITE_PRIORITY, | |
472 | .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER, | |
473 | .cra_blocksize = AES_BLOCK_SIZE, | |
474 | .cra_ctxsize = sizeof(struct aes_ctx), | |
475 | .cra_alignmask = PADLOCK_ALIGNMENT - 1, | |
476 | .cra_type = &crypto_blkcipher_type, | |
477 | .cra_module = THIS_MODULE, | |
28ce728a HX |
478 | .cra_u = { |
479 | .blkcipher = { | |
480 | .min_keysize = AES_MIN_KEY_SIZE, | |
481 | .max_keysize = AES_MAX_KEY_SIZE, | |
482 | .ivsize = AES_BLOCK_SIZE, | |
483 | .setkey = aes_set_key, | |
484 | .encrypt = cbc_aes_encrypt, | |
485 | .decrypt = cbc_aes_decrypt, | |
486 | } | |
487 | } | |
488 | }; | |
489 | ||
d9893645 | 490 | static const struct x86_cpu_id padlock_cpu_id[] = { |
3bd391f0 AK |
491 | X86_FEATURE_MATCH(X86_FEATURE_XCRYPT), |
492 | {} | |
493 | }; | |
494 | MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id); | |
495 | ||
1191f0a4 | 496 | static int __init padlock_init(void) |
1da177e4 | 497 | { |
1191f0a4 | 498 | int ret; |
a76c1c23 | 499 | struct cpuinfo_x86 *c = &cpu_data(0); |
1191f0a4 | 500 | |
3bd391f0 | 501 | if (!x86_match_cpu(padlock_cpu_id)) |
1191f0a4 | 502 | return -ENODEV; |
1191f0a4 | 503 | |
362f924b | 504 | if (!boot_cpu_has(X86_FEATURE_XCRYPT_EN)) { |
b43e726b | 505 | printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n"); |
1191f0a4 ML |
506 | return -ENODEV; |
507 | } | |
1da177e4 | 508 | |
28ce728a HX |
509 | if ((ret = crypto_register_alg(&aes_alg))) |
510 | goto aes_err; | |
511 | ||
512 | if ((ret = crypto_register_alg(&ecb_aes_alg))) | |
513 | goto ecb_aes_err; | |
514 | ||
515 | if ((ret = crypto_register_alg(&cbc_aes_alg))) | |
516 | goto cbc_aes_err; | |
1191f0a4 ML |
517 | |
518 | printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n"); | |
519 | ||
b399151c | 520 | if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) { |
8d8409f7 CE |
521 | ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS; |
522 | cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS; | |
a76c1c23 CE |
523 | printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n"); |
524 | } | |
525 | ||
28ce728a | 526 | out: |
1191f0a4 | 527 | return ret; |
28ce728a HX |
528 | |
529 | cbc_aes_err: | |
530 | crypto_unregister_alg(&ecb_aes_alg); | |
531 | ecb_aes_err: | |
532 | crypto_unregister_alg(&aes_alg); | |
533 | aes_err: | |
534 | printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n"); | |
535 | goto out; | |
1da177e4 LT |
536 | } |
537 | ||
1191f0a4 | 538 | static void __exit padlock_fini(void) |
1da177e4 | 539 | { |
28ce728a HX |
540 | crypto_unregister_alg(&cbc_aes_alg); |
541 | crypto_unregister_alg(&ecb_aes_alg); | |
1da177e4 LT |
542 | crypto_unregister_alg(&aes_alg); |
543 | } | |
1191f0a4 ML |
544 | |
545 | module_init(padlock_init); | |
546 | module_exit(padlock_fini); | |
547 | ||
548 | MODULE_DESCRIPTION("VIA PadLock AES algorithm support"); | |
549 | MODULE_LICENSE("GPL"); | |
550 | MODULE_AUTHOR("Michal Ludvig"); | |
551 | ||
5d26a105 | 552 | MODULE_ALIAS_CRYPTO("aes"); |