[linux-2.6-block.git] / drivers / crypto / padlock-aes.c

/* 
 * Cryptographic API.
 *
 * Support for VIA PadLock hardware crypto engine.
 *
 * Copyright (c) 2004  Michal Ludvig <michal@logix.cz>
 *
 */

#include <crypto/algapi.h>
#include <crypto/aes.h>
#include <crypto/padlock.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/slab.h>
#include <asm/cpu_device_id.h>
#include <asm/byteorder.h>
#include <asm/processor.h>
#include <asm/fpu/api.h>

/*
 * Number of data blocks actually fetched for each xcrypt insn.
 * Processors with prefetch errata will fetch extra blocks.
 */
static unsigned int ecb_fetch_blocks = 2;
#define MAX_ECB_FETCH_BLOCKS (8)
#define ecb_fetch_bytes (ecb_fetch_blocks * AES_BLOCK_SIZE)

static unsigned int cbc_fetch_blocks = 1;
#define MAX_CBC_FETCH_BLOCKS (4)
#define cbc_fetch_bytes (cbc_fetch_blocks * AES_BLOCK_SIZE)

/* Control word. */
struct cword {
	unsigned int __attribute__ ((__packed__))
		rounds:4,
		algo:3,
		keygen:1,
		interm:1,
		encdec:1,
		ksize:2;
} __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));

/* Whenever making any changes to the following
 * structure *make sure* you keep E, d_data
 * and cword aligned on 16 Bytes boundaries and
 * the Hardware can access 16 * 16 bytes of E and d_data
 * (only the first 15 * 16 bytes matter but the HW reads
 * more).
 */
struct aes_ctx {
	u32 E[AES_MAX_KEYLENGTH_U32]
		__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
	u32 d_data[AES_MAX_KEYLENGTH_U32]
		__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
	struct {
		struct cword encrypt;
		struct cword decrypt;
	} cword;
	u32 *D;
};

static DEFINE_PER_CPU(struct cword *, paes_last_cword);

/* Tells whether the ACE is capable to generate
   the extended key for a given key_len. */
static inline int
aes_hw_extkey_available(uint8_t key_len)
{
	/* TODO: We should check the actual CPU model/stepping
	         as it's possible that the capability will be
	         added in the next CPU revisions. */
	if (key_len == 16)
		return 1;
	return 0;
}

static inline struct aes_ctx *aes_ctx_common(void *ctx)
{
	unsigned long addr = (unsigned long)ctx;
	unsigned long align = PADLOCK_ALIGNMENT;

	if (align <= crypto_tfm_ctx_alignment())
		align = 1;
	return (struct aes_ctx *)ALIGN(addr, align);
}

static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm)
{
	return aes_ctx_common(crypto_tfm_ctx(tfm));
}

static inline struct aes_ctx *blk_aes_ctx(struct crypto_blkcipher *tfm)
{
	return aes_ctx_common(crypto_blkcipher_ctx(tfm));
}

static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
		       unsigned int key_len)
{
	struct aes_ctx *ctx = aes_ctx(tfm);
	const __le32 *key = (const __le32 *)in_key;
	u32 *flags = &tfm->crt_flags;
	struct crypto_aes_ctx gen_aes;
	int cpu;

	if (key_len % 8) {
		*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
		return -EINVAL;
	}

	/*
	 * If the hardware is capable of generating the extended key
	 * itself we must supply the plain key for both encryption
	 * and decryption.
	 */
	ctx->D = ctx->E;

	ctx->E[0] = le32_to_cpu(key[0]);
	ctx->E[1] = le32_to_cpu(key[1]);
	ctx->E[2] = le32_to_cpu(key[2]);
	ctx->E[3] = le32_to_cpu(key[3]);

	/* Prepare control words. */
	memset(&ctx->cword, 0, sizeof(ctx->cword));

	ctx->cword.decrypt.encdec = 1;
	ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4;
	ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds;
	ctx->cword.encrypt.ksize = (key_len - 16) / 8;
	ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize;

	/* Don't generate extended keys if the hardware can do it. */
	if (aes_hw_extkey_available(key_len))
		goto ok;

	ctx->D = ctx->d_data;
	ctx->cword.encrypt.keygen = 1;
	ctx->cword.decrypt.keygen = 1;

	if (crypto_aes_expand_key(&gen_aes, in_key, key_len)) {
		*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
		return -EINVAL;
	}

	memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH);
	memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH);

ok:
	for_each_online_cpu(cpu)
		if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) ||
		    &ctx->cword.decrypt == per_cpu(paes_last_cword, cpu))
			per_cpu(paes_last_cword, cpu) = NULL;

	return 0;
}

/* ====== Encryption/decryption routines ====== */

/* These are the real call to PadLock. */
static inline void padlock_reset_key(struct cword *cword)
{
	int cpu = raw_smp_processor_id();

	if (cword != per_cpu(paes_last_cword, cpu))
#ifndef CONFIG_X86_64
		asm volatile ("pushfl; popfl");
#else
		asm volatile ("pushfq; popfq");
#endif
}

static inline void padlock_store_cword(struct cword *cword)
{
	per_cpu(paes_last_cword, raw_smp_processor_id()) = cword;
}

/*
 * While the padlock instructions don't use FP/SSE registers, they
 * generate a spurious DNA fault when CR0.TS is '1'.  Fortunately,
 * the kernel doesn't use CR0.TS.
 */

static inline void rep_xcrypt_ecb(const u8 *input, u8 *output, void *key,
				  struct cword *control_word, int count)
{
	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"	/* rep xcryptecb */
		      : "+S"(input), "+D"(output)
		      : "d"(control_word), "b"(key), "c"(count));
}

static inline u8 *rep_xcrypt_cbc(const u8 *input, u8 *output, void *key,
				 u8 *iv, struct cword *control_word, int count)
{
	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"	/* rep xcryptcbc */
		      : "+S" (input), "+D" (output), "+a" (iv)
		      : "d" (control_word), "b" (key), "c" (count));
	return iv;
}

static void ecb_crypt_copy(const u8 *in, u8 *out, u32 *key,
			   struct cword *cword, int count)
{
	/*
	 * Padlock prefetches extra data so we must provide mapped input buffers.
	 * Assume there are at least 16 bytes of stack already in use.
	 */
	u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
	u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	memcpy(tmp, in, count * AES_BLOCK_SIZE);
	rep_xcrypt_ecb(tmp, out, key, cword, count);
}

static u8 *cbc_crypt_copy(const u8 *in, u8 *out, u32 *key,
			   u8 *iv, struct cword *cword, int count)
{
	/*
	 * Padlock prefetches extra data so we must provide mapped input buffers.
	 * Assume there are at least 16 bytes of stack already in use.
	 */
	u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
	u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);

	memcpy(tmp, in, count * AES_BLOCK_SIZE);
	return rep_xcrypt_cbc(tmp, out, key, iv, cword, count);
}

static inline void ecb_crypt(const u8 *in, u8 *out, u32 *key,
			     struct cword *cword, int count)
{
	/* Padlock in ECB mode fetches at least ecb_fetch_bytes of data.
	 * We could avoid some copying here but it's probably not worth it.
	 */
	if (unlikely(offset_in_page(in) + ecb_fetch_bytes > PAGE_SIZE)) {
		ecb_crypt_copy(in, out, key, cword, count);
		return;
	}

	rep_xcrypt_ecb(in, out, key, cword, count);
}

static inline u8 *cbc_crypt(const u8 *in, u8 *out, u32 *key,
			    u8 *iv, struct cword *cword, int count)
{
	/* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */
	if (unlikely(offset_in_page(in) + cbc_fetch_bytes > PAGE_SIZE))
		return cbc_crypt_copy(in, out, key, iv, cword, count);

	return rep_xcrypt_cbc(in, out, key, iv, cword, count);
}

static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key,
				      void *control_word, u32 count)
{
	u32 initial = count & (ecb_fetch_blocks - 1);

	if (count < ecb_fetch_blocks) {
		ecb_crypt(input, output, key, control_word, count);
		return;
	}

	count -= initial;

	if (initial)
		asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"	/* rep xcryptecb */
			      : "+S"(input), "+D"(output)
			      : "d"(control_word), "b"(key), "c"(initial));

	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"	/* rep xcryptecb */
		      : "+S"(input), "+D"(output)
		      : "d"(control_word), "b"(key), "c"(count));
}

static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key,
				     u8 *iv, void *control_word, u32 count)
{
	u32 initial = count & (cbc_fetch_blocks - 1);

	if (count < cbc_fetch_blocks)
		return cbc_crypt(input, output, key, iv, control_word, count);

	count -= initial;

	if (initial)
		asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"	/* rep xcryptcbc */
			      : "+S" (input), "+D" (output), "+a" (iv)
			      : "d" (control_word), "b" (key), "c" (initial));

	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"	/* rep xcryptcbc */
		      : "+S" (input), "+D" (output), "+a" (iv)
		      : "d" (control_word), "b" (key), "c" (count));
	return iv;
}

static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
{
	struct aes_ctx *ctx = aes_ctx(tfm);

	padlock_reset_key(&ctx->cword.encrypt);
	ecb_crypt(in, out, ctx->E, &ctx->cword.encrypt, 1);
	padlock_store_cword(&ctx->cword.encrypt);
}

static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
{
	struct aes_ctx *ctx = aes_ctx(tfm);

	padlock_reset_key(&ctx->cword.encrypt);
	ecb_crypt(in, out, ctx->D, &ctx->cword.decrypt, 1);
	padlock_store_cword(&ctx->cword.encrypt);
}

static struct crypto_alg aes_alg = {
	.cra_name		=	"aes",
	.cra_driver_name	=	"aes-padlock",
	.cra_priority		=	PADLOCK_CRA_PRIORITY,
	.cra_flags		=	CRYPTO_ALG_TYPE_CIPHER,
	.cra_blocksize		=	AES_BLOCK_SIZE,
	.cra_ctxsize		=	sizeof(struct aes_ctx),
	.cra_alignmask		=	PADLOCK_ALIGNMENT - 1,
	.cra_module		=	THIS_MODULE,
	.cra_u			=	{
		.cipher = {
			.cia_min_keysize	=	AES_MIN_KEY_SIZE,
			.cia_max_keysize	=	AES_MAX_KEY_SIZE,
			.cia_setkey	   	= 	aes_set_key,
			.cia_encrypt	 	=	aes_encrypt,
			.cia_decrypt	  	=	aes_decrypt,
		}
	}
};

static int ecb_aes_encrypt(struct blkcipher_desc *desc,
			   struct scatterlist *dst, struct scatterlist *src,
			   unsigned int nbytes)
{
	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	struct blkcipher_walk walk;
	int err;

	padlock_reset_key(&ctx->cword.encrypt);

	blkcipher_walk_init(&walk, dst, src, nbytes);
	err = blkcipher_walk_virt(desc, &walk);

	while ((nbytes = walk.nbytes)) {
		padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
				   ctx->E, &ctx->cword.encrypt,
				   nbytes / AES_BLOCK_SIZE);
		nbytes &= AES_BLOCK_SIZE - 1;
		err = blkcipher_walk_done(desc, &walk, nbytes);
	}

	padlock_store_cword(&ctx->cword.encrypt);

	return err;
}

static int ecb_aes_decrypt(struct blkcipher_desc *desc,
			   struct scatterlist *dst, struct scatterlist *src,
			   unsigned int nbytes)
{
	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	struct blkcipher_walk walk;
	int err;

	padlock_reset_key(&ctx->cword.decrypt);

	blkcipher_walk_init(&walk, dst, src, nbytes);
	err = blkcipher_walk_virt(desc, &walk);

	while ((nbytes = walk.nbytes)) {
		padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
				   ctx->D, &ctx->cword.decrypt,
				   nbytes / AES_BLOCK_SIZE);
		nbytes &= AES_BLOCK_SIZE - 1;
		err = blkcipher_walk_done(desc, &walk, nbytes);
	}

	padlock_store_cword(&ctx->cword.encrypt);

	return err;
}

static struct crypto_alg ecb_aes_alg = {
	.cra_name		=	"ecb(aes)",
	.cra_driver_name	=	"ecb-aes-padlock",
	.cra_priority		=	PADLOCK_COMPOSITE_PRIORITY,
	.cra_flags		=	CRYPTO_ALG_TYPE_BLKCIPHER,
	.cra_blocksize		=	AES_BLOCK_SIZE,
	.cra_ctxsize		=	sizeof(struct aes_ctx),
	.cra_alignmask		=	PADLOCK_ALIGNMENT - 1,
	.cra_type		=	&crypto_blkcipher_type,
	.cra_module		=	THIS_MODULE,
	.cra_u			=	{
		.blkcipher = {
			.min_keysize		=	AES_MIN_KEY_SIZE,
			.max_keysize		=	AES_MAX_KEY_SIZE,
			.setkey	   		= 	aes_set_key,
			.encrypt		=	ecb_aes_encrypt,
			.decrypt		=	ecb_aes_decrypt,
		}
	}
};

static int cbc_aes_encrypt(struct blkcipher_desc *desc,
			   struct scatterlist *dst, struct scatterlist *src,
			   unsigned int nbytes)
{
	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	struct blkcipher_walk walk;
	int err;

	padlock_reset_key(&ctx->cword.encrypt);

	blkcipher_walk_init(&walk, dst, src, nbytes);
	err = blkcipher_walk_virt(desc, &walk);

	while ((nbytes = walk.nbytes)) {
		u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr,
					    walk.dst.virt.addr, ctx->E,
					    walk.iv, &ctx->cword.encrypt,
					    nbytes / AES_BLOCK_SIZE);
		memcpy(walk.iv, iv, AES_BLOCK_SIZE);
		nbytes &= AES_BLOCK_SIZE - 1;
		err = blkcipher_walk_done(desc, &walk, nbytes);
	}

	padlock_store_cword(&ctx->cword.decrypt);

	return err;
}

static int cbc_aes_decrypt(struct blkcipher_desc *desc,
			   struct scatterlist *dst, struct scatterlist *src,
			   unsigned int nbytes)
{
	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	struct blkcipher_walk walk;
	int err;

	padlock_reset_key(&ctx->cword.encrypt);

	blkcipher_walk_init(&walk, dst, src, nbytes);
	err = blkcipher_walk_virt(desc, &walk);

	while ((nbytes = walk.nbytes)) {
		padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr,
				   ctx->D, walk.iv, &ctx->cword.decrypt,
				   nbytes / AES_BLOCK_SIZE);
		nbytes &= AES_BLOCK_SIZE - 1;
		err = blkcipher_walk_done(desc, &walk, nbytes);
	}

	padlock_store_cword(&ctx->cword.encrypt);

	return err;
}

static struct crypto_alg cbc_aes_alg = {
	.cra_name		=	"cbc(aes)",
	.cra_driver_name	=	"cbc-aes-padlock",
	.cra_priority		=	PADLOCK_COMPOSITE_PRIORITY,
	.cra_flags		=	CRYPTO_ALG_TYPE_BLKCIPHER,
	.cra_blocksize		=	AES_BLOCK_SIZE,
	.cra_ctxsize		=	sizeof(struct aes_ctx),
	.cra_alignmask		=	PADLOCK_ALIGNMENT - 1,
	.cra_type		=	&crypto_blkcipher_type,
	.cra_module		=	THIS_MODULE,
	.cra_u			=	{
		.blkcipher = {
			.min_keysize		=	AES_MIN_KEY_SIZE,
			.max_keysize		=	AES_MAX_KEY_SIZE,
			.ivsize			=	AES_BLOCK_SIZE,
			.setkey	   		= 	aes_set_key,
			.encrypt		=	cbc_aes_encrypt,
			.decrypt		=	cbc_aes_decrypt,
		}
	}
};

static const struct x86_cpu_id padlock_cpu_id[] = {
	X86_FEATURE_MATCH(X86_FEATURE_XCRYPT),
	{}
};
MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id);

static int __init padlock_init(void)
{
	int ret;
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (!x86_match_cpu(padlock_cpu_id))
		return -ENODEV;

	if (!boot_cpu_has(X86_FEATURE_XCRYPT_EN)) {
		printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
		return -ENODEV;
	}

	if ((ret = crypto_register_alg(&aes_alg)))
		goto aes_err;

	if ((ret = crypto_register_alg(&ecb_aes_alg)))
		goto ecb_aes_err;

	if ((ret = crypto_register_alg(&cbc_aes_alg)))
		goto cbc_aes_err;

	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");

	if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) {
		ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
		cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
		printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
	}

out:
	return ret;

cbc_aes_err:
	crypto_unregister_alg(&ecb_aes_alg);
ecb_aes_err:
	crypto_unregister_alg(&aes_alg);
aes_err:
	printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n");
	goto out;
}

static void __exit padlock_fini(void)
{
	crypto_unregister_alg(&cbc_aes_alg);
	crypto_unregister_alg(&ecb_aes_alg);
	crypto_unregister_alg(&aes_alg);
}

module_init(padlock_init);
module_exit(padlock_fini);

MODULE_DESCRIPTION("VIA PadLock AES algorithm support");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Michal Ludvig");

MODULE_ALIAS_CRYPTO("aes");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Cryptographic API.
	3	*
	4	* Support for VIA PadLock hardware crypto engine.
	5	*
	6	* Copyright (c) 2004 Michal Ludvig <michal@logix.cz>
	7	*
1da177e4 LT	8	*/
1da177e4 LT	9
28ce728a	10	#include <crypto/algapi.h>
89e12654	11	#include <crypto/aes.h>
21493088	12	#include <crypto/padlock.h>
1da177e4 LT	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/types.h>
	16	#include <linux/errno.h>
1da177e4	17	#include <linux/interrupt.h>
6789b2dc	18	#include <linux/kernel.h>
420a4b20 HX	19	#include <linux/percpu.h>
420a4b20 HX	20	#include <linux/smp.h>
5a0e3ad6	21	#include <linux/slab.h>
3bd391f0	22	#include <asm/cpu_device_id.h>
1da177e4	23	#include <asm/byteorder.h>
a76c1c23	24	#include <asm/processor.h>
df6b35f4	25	#include <asm/fpu/api.h>
1da177e4	26
8d8409f7 CE	27	/*
	28	* Number of data blocks actually fetched for each xcrypt insn.
	29	* Processors with prefetch errata will fetch extra blocks.
	30	*/
a76c1c23	31	static unsigned int ecb_fetch_blocks = 2;
8d8409f7	32	#define MAX_ECB_FETCH_BLOCKS (8)
a76c1c23	33	#define ecb_fetch_bytes (ecb_fetch_blocks * AES_BLOCK_SIZE)
8d8409f7 CE	34
	35	static unsigned int cbc_fetch_blocks = 1;
	36	#define MAX_CBC_FETCH_BLOCKS (4)
a76c1c23 CE	37	#define cbc_fetch_bytes (cbc_fetch_blocks * AES_BLOCK_SIZE)
a76c1c23 CE	38
ccc17c34 ML	39	/* Control word. */
	40	struct cword {
	41	unsigned int __attribute__ ((__packed__))
	42	rounds:4,
	43	algo:3,
	44	keygen:1,
	45	interm:1,
	46	encdec:1,
	47	ksize:2;
	48	} __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
	49
cc08632f ML	50	/* Whenever making any changes to the following
cc08632f ML	51	* structure make sure you keep E, d_data
7dc748e4 SS	52	* and cword aligned on 16 Bytes boundaries and
	53	* the Hardware can access 16 * 16 bytes of E and d_data
	54	* (only the first 15 * 16 bytes matter but the HW reads
	55	* more).
	56	*/
1da177e4	57	struct aes_ctx {
7dc748e4 SS	58	u32 E[AES_MAX_KEYLENGTH_U32]
	59	__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
	60	u32 d_data[AES_MAX_KEYLENGTH_U32]
	61	__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
6789b2dc HX	62	struct {
	63	struct cword encrypt;
	64	struct cword decrypt;
	65	} cword;
82062c72	66	u32 *D;
1da177e4 LT	67	};
1da177e4 LT	68
390dfd95	69	static DEFINE_PER_CPU(struct cword *, paes_last_cword);
420a4b20	70
1da177e4 LT	71	/* Tells whether the ACE is capable to generate
	72	the extended key for a given key_len. */
	73	static inline int
	74	aes_hw_extkey_available(uint8_t key_len)
	75	{
	76	/* TODO: We should check the actual CPU model/stepping
	77	as it's possible that the capability will be
	78	added in the next CPU revisions. */
	79	if (key_len == 16)
	80	return 1;
	81	return 0;
	82	}
	83
28ce728a	84	static inline struct aes_ctx aes_ctx_common(void ctx)
6789b2dc	85	{
28ce728a	86	unsigned long addr = (unsigned long)ctx;
f10b7897 HX	87	unsigned long align = PADLOCK_ALIGNMENT;
	88
	89	if (align <= crypto_tfm_ctx_alignment())
	90	align = 1;
6c2bb98b	91	return (struct aes_ctx *)ALIGN(addr, align);
6789b2dc HX	92	}
6789b2dc HX	93
28ce728a HX	94	static inline struct aes_ctx aes_ctx(struct crypto_tfm tfm)
	95	{
	96	return aes_ctx_common(crypto_tfm_ctx(tfm));
	97	}
	98
	99	static inline struct aes_ctx blk_aes_ctx(struct crypto_blkcipher tfm)
	100	{
	101	return aes_ctx_common(crypto_blkcipher_ctx(tfm));
	102	}
	103
6c2bb98b	104	static int aes_set_key(struct crypto_tfm tfm, const u8 in_key,
560c06ae	105	unsigned int key_len)
1da177e4	106	{
6c2bb98b	107	struct aes_ctx *ctx = aes_ctx(tfm);
06ace7a9	108	const __le32 key = (const __le32 )in_key;
560c06ae	109	u32 *flags = &tfm->crt_flags;
7dc748e4	110	struct crypto_aes_ctx gen_aes;
420a4b20	111	int cpu;
1da177e4	112
560c06ae	113	if (key_len % 8) {
1da177e4 LT	114	*flags \|= CRYPTO_TFM_RES_BAD_KEY_LEN;
	115	return -EINVAL;
	116	}
	117
6789b2dc HX	118	/*
	119	* If the hardware is capable of generating the extended key
	120	* itself we must supply the plain key for both encryption
	121	* and decryption.
	122	*/
82062c72	123	ctx->D = ctx->E;
1da177e4	124
7dc748e4 SS	125	ctx->E[0] = le32_to_cpu(key[0]);
	126	ctx->E[1] = le32_to_cpu(key[1]);
	127	ctx->E[2] = le32_to_cpu(key[2]);
	128	ctx->E[3] = le32_to_cpu(key[3]);
1da177e4	129
6789b2dc HX	130	/* Prepare control words. */
	131	memset(&ctx->cword, 0, sizeof(ctx->cword));
	132
	133	ctx->cword.decrypt.encdec = 1;
	134	ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4;
	135	ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds;
	136	ctx->cword.encrypt.ksize = (key_len - 16) / 8;
	137	ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize;
	138
1da177e4 LT	139	/* Don't generate extended keys if the hardware can do it. */
1da177e4 LT	140	if (aes_hw_extkey_available(key_len))
420a4b20	141	goto ok;
1da177e4	142
6789b2dc HX	143	ctx->D = ctx->d_data;
	144	ctx->cword.encrypt.keygen = 1;
	145	ctx->cword.decrypt.keygen = 1;
	146
7dc748e4 SS	147	if (crypto_aes_expand_key(&gen_aes, in_key, key_len)) {
	148	*flags \|= CRYPTO_TFM_RES_BAD_KEY_LEN;
	149	return -EINVAL;
1da177e4 LT	150	}
1da177e4 LT	151
7dc748e4 SS	152	memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH);
7dc748e4 SS	153	memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH);
420a4b20 HX	154
	155	ok:
	156	for_each_online_cpu(cpu)
390dfd95 TH	157	if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) \|\|
	158	&ctx->cword.decrypt == per_cpu(paes_last_cword, cpu))
	159	per_cpu(paes_last_cword, cpu) = NULL;
420a4b20	160
1da177e4 LT	161	return 0;
	162	}
	163
	164	/* ====== Encryption/decryption routines ====== */
	165
28e8c3ad	166	/* These are the real call to PadLock. */
420a4b20 HX	167	static inline void padlock_reset_key(struct cword *cword)
	168	{
	169	int cpu = raw_smp_processor_id();
	170
390dfd95	171	if (cword != per_cpu(paes_last_cword, cpu))
d1c8b0a7	172	#ifndef CONFIG_X86_64
420a4b20	173	asm volatile ("pushfl; popfl");
d1c8b0a7 SAS	174	#else
	175	asm volatile ("pushfq; popfq");
	176	#endif
420a4b20 HX	177	}
	178
	179	static inline void padlock_store_cword(struct cword *cword)
866cd902	180	{
390dfd95	181	per_cpu(paes_last_cword, raw_smp_processor_id()) = cword;
866cd902 HX	182	}
866cd902 HX	183
e4914012 SS	184	/*
e4914012 SS	185	* While the padlock instructions don't use FP/SSE registers, they
5a83d60c AL	186	* generate a spurious DNA fault when CR0.TS is '1'. Fortunately,
5a83d60c AL	187	* the kernel doesn't use CR0.TS.
e4914012 SS	188	*/
e4914012 SS	189
8d8409f7	190	static inline void rep_xcrypt_ecb(const u8 input, u8 output, void *key,
a76c1c23	191	struct cword *control_word, int count)
d4a7dd8e HX	192	{
	193	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
	194	: "+S"(input), "+D"(output)
a76c1c23	195	: "d"(control_word), "b"(key), "c"(count));
d4a7dd8e HX	196	}
d4a7dd8e HX	197
8d8409f7 CE	198	static inline u8 rep_xcrypt_cbc(const u8 input, u8 output, void key,
	199	u8 iv, struct cword control_word, int count)
	200	{
	201	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
	202	: "+S" (input), "+D" (output), "+a" (iv)
	203	: "d" (control_word), "b" (key), "c" (count));
	204	return iv;
	205	}
	206
	207	static void ecb_crypt_copy(const u8 in, u8 out, u32 *key,
a76c1c23	208	struct cword *cword, int count)
d4a7dd8e	209	{
a76c1c23 CE	210	/*
	211	* Padlock prefetches extra data so we must provide mapped input buffers.
	212	* Assume there are at least 16 bytes of stack already in use.
	213	*/
8d8409f7	214	u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
490fe3f0	215	u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
d4a7dd8e	216
a76c1c23	217	memcpy(tmp, in, count * AES_BLOCK_SIZE);
8d8409f7	218	rep_xcrypt_ecb(tmp, out, key, cword, count);
d4a7dd8e HX	219	}
d4a7dd8e HX	220
8d8409f7 CE	221	static u8 cbc_crypt_copy(const u8 in, u8 out, u32 key,
	222	u8 iv, struct cword cword, int count)
	223	{
	224	/*
	225	* Padlock prefetches extra data so we must provide mapped input buffers.
	226	* Assume there are at least 16 bytes of stack already in use.
	227	*/
	228	u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
	229	u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
	230
	231	memcpy(tmp, in, count * AES_BLOCK_SIZE);
	232	return rep_xcrypt_cbc(tmp, out, key, iv, cword, count);
	233	}
	234
	235	static inline void ecb_crypt(const u8 in, u8 out, u32 *key,
a76c1c23	236	struct cword *cword, int count)
d4a7dd8e	237	{
a76c1c23 CE	238	/* Padlock in ECB mode fetches at least ecb_fetch_bytes of data.
	239	* We could avoid some copying here but it's probably not worth it.
	240	*/
1d4bbc5a	241	if (unlikely(offset_in_page(in) + ecb_fetch_bytes > PAGE_SIZE)) {
8d8409f7	242	ecb_crypt_copy(in, out, key, cword, count);
d4a7dd8e HX	243	return;
	244	}
	245
8d8409f7 CE	246	rep_xcrypt_ecb(in, out, key, cword, count);
	247	}
	248
	249	static inline u8 cbc_crypt(const u8 in, u8 out, u32 key,
	250	u8 iv, struct cword cword, int count)
	251	{
	252	/* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */
1d4bbc5a	253	if (unlikely(offset_in_page(in) + cbc_fetch_bytes > PAGE_SIZE))
8d8409f7 CE	254	return cbc_crypt_copy(in, out, key, iv, cword, count);
	255
	256	return rep_xcrypt_cbc(in, out, key, iv, cword, count);
d4a7dd8e HX	257	}
d4a7dd8e HX	258
6789b2dc HX	259	static inline void padlock_xcrypt_ecb(const u8 input, u8 output, void *key,
6789b2dc HX	260	void *control_word, u32 count)
1da177e4	261	{
a76c1c23 CE	262	u32 initial = count & (ecb_fetch_blocks - 1);
	263
	264	if (count < ecb_fetch_blocks) {
8d8409f7	265	ecb_crypt(input, output, key, control_word, count);
d4a7dd8e HX	266	return;
	267	}
	268
46d8c4b2 HX	269	count -= initial;
46d8c4b2 HX	270
a76c1c23 CE	271	if (initial)
	272	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
	273	: "+S"(input), "+D"(output)
	274	: "d"(control_word), "b"(key), "c"(initial));
	275
	276	asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
1da177e4	277	: "+S"(input), "+D"(output)
46d8c4b2	278	: "d"(control_word), "b"(key), "c"(count));
1da177e4 LT	279	}
1da177e4 LT	280
476df259 HX	281	static inline u8 padlock_xcrypt_cbc(const u8 input, u8 output, void key,
476df259 HX	282	u8 iv, void control_word, u32 count)
28e8c3ad	283	{
8d8409f7 CE	284	u32 initial = count & (cbc_fetch_blocks - 1);
	285
	286	if (count < cbc_fetch_blocks)
	287	return cbc_crypt(input, output, key, iv, control_word, count);
	288
46d8c4b2 HX	289	count -= initial;
46d8c4b2 HX	290
8d8409f7 CE	291	if (initial)
	292	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
	293	: "+S" (input), "+D" (output), "+a" (iv)
c054a076	294	: "d" (control_word), "b" (key), "c" (initial));
8d8409f7 CE	295
8d8409f7 CE	296	asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
28e8c3ad	297	: "+S" (input), "+D" (output), "+a" (iv)
46d8c4b2	298	: "d" (control_word), "b" (key), "c" (count));
476df259	299	return iv;
28e8c3ad HX	300	}
28e8c3ad HX	301
6c2bb98b	302	static void aes_encrypt(struct crypto_tfm tfm, u8 out, const u8 *in)
1da177e4	303	{
6c2bb98b	304	struct aes_ctx *ctx = aes_ctx(tfm);
e4914012	305
420a4b20	306	padlock_reset_key(&ctx->cword.encrypt);
8d8409f7	307	ecb_crypt(in, out, ctx->E, &ctx->cword.encrypt, 1);
420a4b20	308	padlock_store_cword(&ctx->cword.encrypt);
1da177e4 LT	309	}
1da177e4 LT	310
6c2bb98b	311	static void aes_decrypt(struct crypto_tfm tfm, u8 out, const u8 *in)
1da177e4	312	{
6c2bb98b	313	struct aes_ctx *ctx = aes_ctx(tfm);
e4914012	314
420a4b20	315	padlock_reset_key(&ctx->cword.encrypt);
8d8409f7	316	ecb_crypt(in, out, ctx->D, &ctx->cword.decrypt, 1);
420a4b20	317	padlock_store_cword(&ctx->cword.encrypt);
1da177e4 LT	318	}
	319
	320	static struct crypto_alg aes_alg = {
	321	.cra_name = "aes",
c8a19c91	322	.cra_driver_name = "aes-padlock",
ccc17c34	323	.cra_priority = PADLOCK_CRA_PRIORITY,
1da177e4 LT	324	.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
1da177e4 LT	325	.cra_blocksize = AES_BLOCK_SIZE,
fbdae9f3	326	.cra_ctxsize = sizeof(struct aes_ctx),
6789b2dc	327	.cra_alignmask = PADLOCK_ALIGNMENT - 1,
1da177e4	328	.cra_module = THIS_MODULE,
1da177e4 LT	329	.cra_u = {
	330	.cipher = {
	331	.cia_min_keysize = AES_MIN_KEY_SIZE,
	332	.cia_max_keysize = AES_MAX_KEY_SIZE,
	333	.cia_setkey = aes_set_key,
	334	.cia_encrypt = aes_encrypt,
28e8c3ad	335	.cia_decrypt = aes_decrypt,
1da177e4 LT	336	}
	337	}
	338	};
	339
28ce728a HX	340	static int ecb_aes_encrypt(struct blkcipher_desc *desc,
	341	struct scatterlist dst, struct scatterlist src,
	342	unsigned int nbytes)
	343	{
	344	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	345	struct blkcipher_walk walk;
	346	int err;
	347
420a4b20	348	padlock_reset_key(&ctx->cword.encrypt);
866cd902	349
28ce728a HX	350	blkcipher_walk_init(&walk, dst, src, nbytes);
	351	err = blkcipher_walk_virt(desc, &walk);
	352
	353	while ((nbytes = walk.nbytes)) {
	354	padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
	355	ctx->E, &ctx->cword.encrypt,
	356	nbytes / AES_BLOCK_SIZE);
	357	nbytes &= AES_BLOCK_SIZE - 1;
	358	err = blkcipher_walk_done(desc, &walk, nbytes);
	359	}
	360
420a4b20 HX	361	padlock_store_cword(&ctx->cword.encrypt);
420a4b20 HX	362
28ce728a HX	363	return err;
	364	}
	365
	366	static int ecb_aes_decrypt(struct blkcipher_desc *desc,
	367	struct scatterlist dst, struct scatterlist src,
	368	unsigned int nbytes)
	369	{
	370	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	371	struct blkcipher_walk walk;
	372	int err;
	373
420a4b20	374	padlock_reset_key(&ctx->cword.decrypt);
866cd902	375
28ce728a HX	376	blkcipher_walk_init(&walk, dst, src, nbytes);
	377	err = blkcipher_walk_virt(desc, &walk);
	378
	379	while ((nbytes = walk.nbytes)) {
	380	padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
	381	ctx->D, &ctx->cword.decrypt,
	382	nbytes / AES_BLOCK_SIZE);
	383	nbytes &= AES_BLOCK_SIZE - 1;
	384	err = blkcipher_walk_done(desc, &walk, nbytes);
	385	}
420a4b20 HX	386
	387	padlock_store_cword(&ctx->cword.encrypt);
	388
28ce728a HX	389	return err;
	390	}
	391
	392	static struct crypto_alg ecb_aes_alg = {
	393	.cra_name = "ecb(aes)",
	394	.cra_driver_name = "ecb-aes-padlock",
	395	.cra_priority = PADLOCK_COMPOSITE_PRIORITY,
	396	.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
	397	.cra_blocksize = AES_BLOCK_SIZE,
	398	.cra_ctxsize = sizeof(struct aes_ctx),
	399	.cra_alignmask = PADLOCK_ALIGNMENT - 1,
	400	.cra_type = &crypto_blkcipher_type,
	401	.cra_module = THIS_MODULE,
28ce728a HX	402	.cra_u = {
	403	.blkcipher = {
	404	.min_keysize = AES_MIN_KEY_SIZE,
	405	.max_keysize = AES_MAX_KEY_SIZE,
	406	.setkey = aes_set_key,
	407	.encrypt = ecb_aes_encrypt,
	408	.decrypt = ecb_aes_decrypt,
	409	}
	410	}
	411	};
	412
	413	static int cbc_aes_encrypt(struct blkcipher_desc *desc,
	414	struct scatterlist dst, struct scatterlist src,
	415	unsigned int nbytes)
	416	{
	417	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	418	struct blkcipher_walk walk;
	419	int err;
	420
420a4b20	421	padlock_reset_key(&ctx->cword.encrypt);
866cd902	422
28ce728a HX	423	blkcipher_walk_init(&walk, dst, src, nbytes);
	424	err = blkcipher_walk_virt(desc, &walk);
	425
	426	while ((nbytes = walk.nbytes)) {
	427	u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr,
	428	walk.dst.virt.addr, ctx->E,
	429	walk.iv, &ctx->cword.encrypt,
	430	nbytes / AES_BLOCK_SIZE);
	431	memcpy(walk.iv, iv, AES_BLOCK_SIZE);
	432	nbytes &= AES_BLOCK_SIZE - 1;
	433	err = blkcipher_walk_done(desc, &walk, nbytes);
	434	}
	435
420a4b20 HX	436	padlock_store_cword(&ctx->cword.decrypt);
420a4b20 HX	437
28ce728a HX	438	return err;
	439	}
	440
	441	static int cbc_aes_decrypt(struct blkcipher_desc *desc,
	442	struct scatterlist dst, struct scatterlist src,
	443	unsigned int nbytes)
	444	{
	445	struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
	446	struct blkcipher_walk walk;
	447	int err;
	448
420a4b20	449	padlock_reset_key(&ctx->cword.encrypt);
866cd902	450
28ce728a HX	451	blkcipher_walk_init(&walk, dst, src, nbytes);
	452	err = blkcipher_walk_virt(desc, &walk);
	453
	454	while ((nbytes = walk.nbytes)) {
	455	padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr,
	456	ctx->D, walk.iv, &ctx->cword.decrypt,
	457	nbytes / AES_BLOCK_SIZE);
	458	nbytes &= AES_BLOCK_SIZE - 1;
	459	err = blkcipher_walk_done(desc, &walk, nbytes);
	460	}
	461
420a4b20 HX	462	padlock_store_cword(&ctx->cword.encrypt);
420a4b20 HX	463
28ce728a HX	464	return err;
	465	}
	466
	467	static struct crypto_alg cbc_aes_alg = {
	468	.cra_name = "cbc(aes)",
	469	.cra_driver_name = "cbc-aes-padlock",
	470	.cra_priority = PADLOCK_COMPOSITE_PRIORITY,
	471	.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
	472	.cra_blocksize = AES_BLOCK_SIZE,
	473	.cra_ctxsize = sizeof(struct aes_ctx),
	474	.cra_alignmask = PADLOCK_ALIGNMENT - 1,
	475	.cra_type = &crypto_blkcipher_type,
	476	.cra_module = THIS_MODULE,
28ce728a HX	477	.cra_u = {
	478	.blkcipher = {
	479	.min_keysize = AES_MIN_KEY_SIZE,
	480	.max_keysize = AES_MAX_KEY_SIZE,
	481	.ivsize = AES_BLOCK_SIZE,
	482	.setkey = aes_set_key,
	483	.encrypt = cbc_aes_encrypt,
	484	.decrypt = cbc_aes_decrypt,
	485	}
	486	}
	487	};
	488
d9893645	489	static const struct x86_cpu_id padlock_cpu_id[] = {
3bd391f0 AK	490	X86_FEATURE_MATCH(X86_FEATURE_XCRYPT),
	491	{}
	492	};
	493	MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id);
	494
1191f0a4	495	static int __init padlock_init(void)
1da177e4	496	{
1191f0a4	497	int ret;
a76c1c23	498	struct cpuinfo_x86 *c = &cpu_data(0);
1191f0a4	499
3bd391f0	500	if (!x86_match_cpu(padlock_cpu_id))
1191f0a4	501	return -ENODEV;
1191f0a4	502
362f924b	503	if (!boot_cpu_has(X86_FEATURE_XCRYPT_EN)) {
b43e726b	504	printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
1191f0a4 ML	505	return -ENODEV;
1191f0a4 ML	506	}
1da177e4	507
28ce728a HX	508	if ((ret = crypto_register_alg(&aes_alg)))
	509	goto aes_err;
	510
	511	if ((ret = crypto_register_alg(&ecb_aes_alg)))
	512	goto ecb_aes_err;
	513
	514	if ((ret = crypto_register_alg(&cbc_aes_alg)))
	515	goto cbc_aes_err;
1191f0a4 ML	516
	517	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
	518
b399151c	519	if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) {
8d8409f7 CE	520	ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
8d8409f7 CE	521	cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
a76c1c23 CE	522	printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
	523	}
	524
28ce728a	525	out:
1191f0a4	526	return ret;
28ce728a HX	527
	528	cbc_aes_err:
	529	crypto_unregister_alg(&ecb_aes_alg);
	530	ecb_aes_err:
	531	crypto_unregister_alg(&aes_alg);
	532	aes_err:
	533	printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n");
	534	goto out;
1da177e4 LT	535	}
1da177e4 LT	536
1191f0a4	537	static void __exit padlock_fini(void)
1da177e4	538	{
28ce728a HX	539	crypto_unregister_alg(&cbc_aes_alg);
28ce728a HX	540	crypto_unregister_alg(&ecb_aes_alg);
1da177e4 LT	541	crypto_unregister_alg(&aes_alg);
1da177e4 LT	542	}
1191f0a4 ML	543
	544	module_init(padlock_init);
	545	module_exit(padlock_fini);
	546
	547	MODULE_DESCRIPTION("VIA PadLock AES algorithm support");
	548	MODULE_LICENSE("GPL");
	549	MODULE_AUTHOR("Michal Ludvig");
	550
5d26a105	551	MODULE_ALIAS_CRYPTO("aes");