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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
8628e7c8 DK |
2 | /* |
3 | * Cryptographic API. | |
4 | * | |
5 | * Support for OMAP SHA1/MD5 HW acceleration. | |
6 | * | |
7 | * Copyright (c) 2010 Nokia Corporation | |
8 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
0d373d60 | 9 | * Copyright (c) 2011 Texas Instruments Incorporated |
8628e7c8 | 10 | * |
8628e7c8 DK |
11 | * Some ideas are from old omap-sha1-md5.c driver. |
12 | */ | |
13 | ||
14 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
15 | ||
8628e7c8 DK |
16 | #include <linux/err.h> |
17 | #include <linux/device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
8628e7c8 DK |
23 | #include <linux/irq.h> |
24 | #include <linux/io.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/scatterlist.h> | |
27 | #include <linux/dma-mapping.h> | |
dfd061d5 | 28 | #include <linux/dmaengine.h> |
b359f034 | 29 | #include <linux/pm_runtime.h> |
03feec9c MG |
30 | #include <linux/of.h> |
31 | #include <linux/of_device.h> | |
32 | #include <linux/of_address.h> | |
33 | #include <linux/of_irq.h> | |
8628e7c8 DK |
34 | #include <linux/delay.h> |
35 | #include <linux/crypto.h> | |
8628e7c8 DK |
36 | #include <crypto/scatterwalk.h> |
37 | #include <crypto/algapi.h> | |
a24d22b2 EB |
38 | #include <crypto/sha1.h> |
39 | #include <crypto/sha2.h> | |
8628e7c8 | 40 | #include <crypto/hash.h> |
ebd401e7 | 41 | #include <crypto/hmac.h> |
8628e7c8 | 42 | #include <crypto/internal/hash.h> |
133c3d43 | 43 | #include <crypto/engine.h> |
8628e7c8 | 44 | |
8628e7c8 DK |
45 | #define MD5_DIGEST_SIZE 16 |
46 | ||
0d373d60 MG |
47 | #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) |
48 | #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) | |
49 | #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) | |
50 | ||
eaef7e3f | 51 | #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) |
8628e7c8 DK |
52 | |
53 | #define SHA_REG_CTRL 0x18 | |
54 | #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) | |
55 | #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) | |
56 | #define SHA_REG_CTRL_ALGO_CONST (1 << 3) | |
57 | #define SHA_REG_CTRL_ALGO (1 << 2) | |
58 | #define SHA_REG_CTRL_INPUT_READY (1 << 1) | |
59 | #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) | |
60 | ||
0d373d60 | 61 | #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) |
8628e7c8 | 62 | |
0d373d60 | 63 | #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) |
8628e7c8 DK |
64 | #define SHA_REG_MASK_DMA_EN (1 << 3) |
65 | #define SHA_REG_MASK_IT_EN (1 << 2) | |
66 | #define SHA_REG_MASK_SOFTRESET (1 << 1) | |
67 | #define SHA_REG_AUTOIDLE (1 << 0) | |
68 | ||
0d373d60 | 69 | #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) |
8628e7c8 DK |
70 | #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) |
71 | ||
eaef7e3f | 72 | #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) |
0d373d60 MG |
73 | #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) |
74 | #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) | |
75 | #define SHA_REG_MODE_CLOSE_HASH (1 << 4) | |
76 | #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) | |
0d373d60 | 77 | |
eaef7e3f LV |
78 | #define SHA_REG_MODE_ALGO_MASK (7 << 0) |
79 | #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) | |
80 | #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) | |
81 | #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) | |
82 | #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) | |
83 | #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) | |
84 | #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) | |
85 | ||
86 | #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) | |
0d373d60 MG |
87 | |
88 | #define SHA_REG_IRQSTATUS 0x118 | |
89 | #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) | |
90 | #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) | |
91 | #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) | |
92 | #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) | |
93 | ||
94 | #define SHA_REG_IRQENA 0x11C | |
95 | #define SHA_REG_IRQENA_CTX_RDY (1 << 3) | |
96 | #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) | |
97 | #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) | |
98 | #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) | |
99 | ||
8628e7c8 DK |
100 | #define DEFAULT_TIMEOUT_INTERVAL HZ |
101 | ||
e93f767b TK |
102 | #define DEFAULT_AUTOSUSPEND_DELAY 1000 |
103 | ||
ea1fd224 | 104 | /* mostly device flags */ |
ea1fd224 DK |
105 | #define FLAGS_FINAL 1 |
106 | #define FLAGS_DMA_ACTIVE 2 | |
107 | #define FLAGS_OUTPUT_READY 3 | |
ea1fd224 | 108 | #define FLAGS_CPU 5 |
6c63db82 | 109 | #define FLAGS_DMA_READY 6 |
0d373d60 MG |
110 | #define FLAGS_AUTO_XOR 7 |
111 | #define FLAGS_BE32_SHA1 8 | |
f19de1bc TK |
112 | #define FLAGS_SGS_COPIED 9 |
113 | #define FLAGS_SGS_ALLOCED 10 | |
462519fc TK |
114 | #define FLAGS_HUGE 11 |
115 | ||
ea1fd224 DK |
116 | /* context flags */ |
117 | #define FLAGS_FINUP 16 | |
8628e7c8 | 118 | |
0d373d60 | 119 | #define FLAGS_MODE_SHIFT 18 |
eaef7e3f LV |
120 | #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) |
121 | #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) | |
122 | #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) | |
123 | #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) | |
124 | #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) | |
125 | #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) | |
126 | #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) | |
127 | ||
128 | #define FLAGS_HMAC 21 | |
129 | #define FLAGS_ERROR 22 | |
0d373d60 MG |
130 | |
131 | #define OP_UPDATE 1 | |
132 | #define OP_FINAL 2 | |
8628e7c8 | 133 | |
798eed5d DK |
134 | #define OMAP_ALIGN_MASK (sizeof(u32)-1) |
135 | #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) | |
136 | ||
182e283f | 137 | #define BUFLEN SHA512_BLOCK_SIZE |
2c5bd1ef | 138 | #define OMAP_SHA_DMA_THRESHOLD 256 |
798eed5d | 139 | |
462519fc TK |
140 | #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048) |
141 | ||
8628e7c8 DK |
142 | struct omap_sham_dev; |
143 | ||
144 | struct omap_sham_reqctx { | |
145 | struct omap_sham_dev *dd; | |
146 | unsigned long flags; | |
133c3d43 | 147 | u8 op; |
8628e7c8 | 148 | |
eaef7e3f | 149 | u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; |
8628e7c8 | 150 | size_t digcnt; |
8628e7c8 DK |
151 | size_t bufcnt; |
152 | size_t buflen; | |
8628e7c8 DK |
153 | |
154 | /* walk state */ | |
155 | struct scatterlist *sg; | |
f19de1bc | 156 | struct scatterlist sgl[2]; |
8043bb1a | 157 | int offset; /* offset in current sg */ |
f19de1bc | 158 | int sg_len; |
8628e7c8 | 159 | unsigned int total; /* total request */ |
798eed5d | 160 | |
5a8a0765 | 161 | u8 buffer[] OMAP_ALIGNED; |
8628e7c8 DK |
162 | }; |
163 | ||
164 | struct omap_sham_hmac_ctx { | |
165 | struct crypto_shash *shash; | |
eaef7e3f LV |
166 | u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; |
167 | u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; | |
8628e7c8 DK |
168 | }; |
169 | ||
170 | struct omap_sham_ctx { | |
133c3d43 | 171 | struct crypto_engine_ctx enginectx; |
8628e7c8 DK |
172 | unsigned long flags; |
173 | ||
174 | /* fallback stuff */ | |
175 | struct crypto_shash *fallback; | |
176 | ||
5a8a0765 | 177 | struct omap_sham_hmac_ctx base[]; |
8628e7c8 DK |
178 | }; |
179 | ||
65e7a549 | 180 | #define OMAP_SHAM_QUEUE_LENGTH 10 |
8628e7c8 | 181 | |
d20fb18b MG |
182 | struct omap_sham_algs_info { |
183 | struct ahash_alg *algs_list; | |
184 | unsigned int size; | |
185 | unsigned int registered; | |
186 | }; | |
187 | ||
0d373d60 | 188 | struct omap_sham_pdata { |
d20fb18b MG |
189 | struct omap_sham_algs_info *algs_info; |
190 | unsigned int algs_info_size; | |
0d373d60 MG |
191 | unsigned long flags; |
192 | int digest_size; | |
193 | ||
194 | void (*copy_hash)(struct ahash_request *req, int out); | |
195 | void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, | |
196 | int final, int dma); | |
197 | void (*trigger)(struct omap_sham_dev *dd, size_t length); | |
198 | int (*poll_irq)(struct omap_sham_dev *dd); | |
199 | irqreturn_t (*intr_hdlr)(int irq, void *dev_id); | |
200 | ||
201 | u32 odigest_ofs; | |
202 | u32 idigest_ofs; | |
203 | u32 din_ofs; | |
204 | u32 digcnt_ofs; | |
205 | u32 rev_ofs; | |
206 | u32 mask_ofs; | |
207 | u32 sysstatus_ofs; | |
eaef7e3f LV |
208 | u32 mode_ofs; |
209 | u32 length_ofs; | |
0d373d60 MG |
210 | |
211 | u32 major_mask; | |
212 | u32 major_shift; | |
213 | u32 minor_mask; | |
214 | u32 minor_shift; | |
215 | }; | |
216 | ||
8628e7c8 DK |
217 | struct omap_sham_dev { |
218 | struct list_head list; | |
219 | unsigned long phys_base; | |
220 | struct device *dev; | |
221 | void __iomem *io_base; | |
222 | int irq; | |
3e133c8b | 223 | int err; |
dfd061d5 | 224 | struct dma_chan *dma_lch; |
8628e7c8 | 225 | struct tasklet_struct done_task; |
b8411ccd | 226 | u8 polling_mode; |
c28e8f21 | 227 | u8 xmit_buf[BUFLEN] OMAP_ALIGNED; |
8628e7c8 DK |
228 | |
229 | unsigned long flags; | |
c9af5995 | 230 | int fallback_sz; |
8628e7c8 DK |
231 | struct crypto_queue queue; |
232 | struct ahash_request *req; | |
133c3d43 | 233 | struct crypto_engine *engine; |
0d373d60 MG |
234 | |
235 | const struct omap_sham_pdata *pdata; | |
8628e7c8 DK |
236 | }; |
237 | ||
238 | struct omap_sham_drv { | |
239 | struct list_head dev_list; | |
240 | spinlock_t lock; | |
241 | unsigned long flags; | |
242 | }; | |
243 | ||
244 | static struct omap_sham_drv sham = { | |
245 | .dev_list = LIST_HEAD_INIT(sham.dev_list), | |
246 | .lock = __SPIN_LOCK_UNLOCKED(sham.lock), | |
247 | }; | |
248 | ||
133c3d43 TK |
249 | static int omap_sham_enqueue(struct ahash_request *req, unsigned int op); |
250 | static void omap_sham_finish_req(struct ahash_request *req, int err); | |
251 | ||
8628e7c8 DK |
252 | static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) |
253 | { | |
254 | return __raw_readl(dd->io_base + offset); | |
255 | } | |
256 | ||
257 | static inline void omap_sham_write(struct omap_sham_dev *dd, | |
258 | u32 offset, u32 value) | |
259 | { | |
260 | __raw_writel(value, dd->io_base + offset); | |
261 | } | |
262 | ||
263 | static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, | |
264 | u32 value, u32 mask) | |
265 | { | |
266 | u32 val; | |
267 | ||
268 | val = omap_sham_read(dd, address); | |
269 | val &= ~mask; | |
270 | val |= value; | |
271 | omap_sham_write(dd, address, val); | |
272 | } | |
273 | ||
274 | static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) | |
275 | { | |
276 | unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; | |
277 | ||
278 | while (!(omap_sham_read(dd, offset) & bit)) { | |
279 | if (time_is_before_jiffies(timeout)) | |
280 | return -ETIMEDOUT; | |
281 | } | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
0d373d60 | 286 | static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) |
8628e7c8 DK |
287 | { |
288 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
0d373d60 | 289 | struct omap_sham_dev *dd = ctx->dd; |
0c3cf4cc | 290 | u32 *hash = (u32 *)ctx->digest; |
8628e7c8 DK |
291 | int i; |
292 | ||
0d373d60 | 293 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { |
3c8d758a | 294 | if (out) |
0d373d60 | 295 | hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); |
3c8d758a | 296 | else |
0d373d60 MG |
297 | omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); |
298 | } | |
299 | } | |
300 | ||
301 | static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) | |
302 | { | |
303 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
304 | struct omap_sham_dev *dd = ctx->dd; | |
305 | int i; | |
306 | ||
307 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
308 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
309 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
310 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
311 | u32 *opad = (u32 *)bctx->opad; | |
312 | ||
313 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { | |
314 | if (out) | |
315 | opad[i] = omap_sham_read(dd, | |
eaef7e3f | 316 | SHA_REG_ODIGEST(dd, i)); |
0d373d60 | 317 | else |
eaef7e3f | 318 | omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), |
0d373d60 MG |
319 | opad[i]); |
320 | } | |
3c8d758a | 321 | } |
0d373d60 MG |
322 | |
323 | omap_sham_copy_hash_omap2(req, out); | |
3c8d758a DK |
324 | } |
325 | ||
326 | static void omap_sham_copy_ready_hash(struct ahash_request *req) | |
327 | { | |
328 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
329 | u32 *in = (u32 *)ctx->digest; | |
330 | u32 *hash = (u32 *)req->result; | |
0d373d60 | 331 | int i, d, big_endian = 0; |
3c8d758a DK |
332 | |
333 | if (!hash) | |
334 | return; | |
335 | ||
0d373d60 MG |
336 | switch (ctx->flags & FLAGS_MODE_MASK) { |
337 | case FLAGS_MODE_MD5: | |
338 | d = MD5_DIGEST_SIZE / sizeof(u32); | |
339 | break; | |
340 | case FLAGS_MODE_SHA1: | |
341 | /* OMAP2 SHA1 is big endian */ | |
342 | if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) | |
343 | big_endian = 1; | |
344 | d = SHA1_DIGEST_SIZE / sizeof(u32); | |
345 | break; | |
d20fb18b MG |
346 | case FLAGS_MODE_SHA224: |
347 | d = SHA224_DIGEST_SIZE / sizeof(u32); | |
348 | break; | |
349 | case FLAGS_MODE_SHA256: | |
350 | d = SHA256_DIGEST_SIZE / sizeof(u32); | |
351 | break; | |
eaef7e3f LV |
352 | case FLAGS_MODE_SHA384: |
353 | d = SHA384_DIGEST_SIZE / sizeof(u32); | |
354 | break; | |
355 | case FLAGS_MODE_SHA512: | |
356 | d = SHA512_DIGEST_SIZE / sizeof(u32); | |
357 | break; | |
0d373d60 MG |
358 | default: |
359 | d = 0; | |
360 | } | |
361 | ||
362 | if (big_endian) | |
363 | for (i = 0; i < d; i++) | |
758f4879 | 364 | hash[i] = be32_to_cpup((__be32 *)in + i); |
0d373d60 MG |
365 | else |
366 | for (i = 0; i < d; i++) | |
758f4879 | 367 | hash[i] = le32_to_cpup((__le32 *)in + i); |
8628e7c8 DK |
368 | } |
369 | ||
0d373d60 | 370 | static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, |
798eed5d DK |
371 | int final, int dma) |
372 | { | |
373 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
374 | u32 val = length << 5, mask; | |
375 | ||
376 | if (likely(ctx->digcnt)) | |
0d373d60 | 377 | omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); |
8628e7c8 | 378 | |
0d373d60 | 379 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), |
8628e7c8 DK |
380 | SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), |
381 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
382 | /* | |
383 | * Setting ALGO_CONST only for the first iteration | |
384 | * and CLOSE_HASH only for the last one. | |
385 | */ | |
0d373d60 | 386 | if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) |
8628e7c8 DK |
387 | val |= SHA_REG_CTRL_ALGO; |
388 | if (!ctx->digcnt) | |
389 | val |= SHA_REG_CTRL_ALGO_CONST; | |
390 | if (final) | |
391 | val |= SHA_REG_CTRL_CLOSE_HASH; | |
392 | ||
393 | mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | | |
394 | SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; | |
395 | ||
396 | omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); | |
8628e7c8 DK |
397 | } |
398 | ||
0d373d60 MG |
399 | static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) |
400 | { | |
401 | } | |
402 | ||
403 | static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) | |
404 | { | |
405 | return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); | |
406 | } | |
407 | ||
eaef7e3f LV |
408 | static int get_block_size(struct omap_sham_reqctx *ctx) |
409 | { | |
410 | int d; | |
411 | ||
412 | switch (ctx->flags & FLAGS_MODE_MASK) { | |
413 | case FLAGS_MODE_MD5: | |
414 | case FLAGS_MODE_SHA1: | |
415 | d = SHA1_BLOCK_SIZE; | |
416 | break; | |
417 | case FLAGS_MODE_SHA224: | |
418 | case FLAGS_MODE_SHA256: | |
419 | d = SHA256_BLOCK_SIZE; | |
420 | break; | |
421 | case FLAGS_MODE_SHA384: | |
422 | case FLAGS_MODE_SHA512: | |
423 | d = SHA512_BLOCK_SIZE; | |
424 | break; | |
425 | default: | |
426 | d = 0; | |
427 | } | |
428 | ||
429 | return d; | |
430 | } | |
431 | ||
0d373d60 MG |
432 | static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, |
433 | u32 *value, int count) | |
434 | { | |
435 | for (; count--; value++, offset += 4) | |
436 | omap_sham_write(dd, offset, *value); | |
437 | } | |
438 | ||
439 | static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, | |
440 | int final, int dma) | |
441 | { | |
442 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
443 | u32 val, mask; | |
444 | ||
3faf757b TK |
445 | if (likely(ctx->digcnt)) |
446 | omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); | |
447 | ||
0d373d60 MG |
448 | /* |
449 | * Setting ALGO_CONST only for the first iteration and | |
450 | * CLOSE_HASH only for the last one. Note that flags mode bits | |
451 | * correspond to algorithm encoding in mode register. | |
452 | */ | |
eaef7e3f | 453 | val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); |
0d373d60 MG |
454 | if (!ctx->digcnt) { |
455 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
456 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
457 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
eaef7e3f | 458 | int bs, nr_dr; |
0d373d60 MG |
459 | |
460 | val |= SHA_REG_MODE_ALGO_CONSTANT; | |
461 | ||
462 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
eaef7e3f LV |
463 | bs = get_block_size(ctx); |
464 | nr_dr = bs / (2 * sizeof(u32)); | |
0d373d60 | 465 | val |= SHA_REG_MODE_HMAC_KEY_PROC; |
eaef7e3f LV |
466 | omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), |
467 | (u32 *)bctx->ipad, nr_dr); | |
468 | omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), | |
469 | (u32 *)bctx->ipad + nr_dr, nr_dr); | |
470 | ctx->digcnt += bs; | |
0d373d60 MG |
471 | } |
472 | } | |
473 | ||
474 | if (final) { | |
475 | val |= SHA_REG_MODE_CLOSE_HASH; | |
476 | ||
477 | if (ctx->flags & BIT(FLAGS_HMAC)) | |
478 | val |= SHA_REG_MODE_HMAC_OUTER_HASH; | |
479 | } | |
480 | ||
481 | mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | | |
482 | SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | | |
483 | SHA_REG_MODE_HMAC_KEY_PROC; | |
484 | ||
485 | dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); | |
eaef7e3f | 486 | omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); |
0d373d60 MG |
487 | omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); |
488 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), | |
489 | SHA_REG_MASK_IT_EN | | |
490 | (dma ? SHA_REG_MASK_DMA_EN : 0), | |
491 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
492 | } | |
493 | ||
494 | static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) | |
495 | { | |
eaef7e3f | 496 | omap_sham_write(dd, SHA_REG_LENGTH(dd), length); |
0d373d60 MG |
497 | } |
498 | ||
499 | static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) | |
500 | { | |
501 | return omap_sham_wait(dd, SHA_REG_IRQSTATUS, | |
502 | SHA_REG_IRQSTATUS_INPUT_RDY); | |
503 | } | |
504 | ||
8043bb1a TK |
505 | static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length, |
506 | int final) | |
8628e7c8 DK |
507 | { |
508 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
b8411ccd | 509 | int count, len32, bs32, offset = 0; |
8043bb1a TK |
510 | const u32 *buffer; |
511 | int mlen; | |
512 | struct sg_mapping_iter mi; | |
8628e7c8 | 513 | |
758f4879 | 514 | dev_dbg(dd->dev, "xmit_cpu: digcnt: %zd, length: %zd, final: %d\n", |
8628e7c8 DK |
515 | ctx->digcnt, length, final); |
516 | ||
0d373d60 MG |
517 | dd->pdata->write_ctrl(dd, length, final, 0); |
518 | dd->pdata->trigger(dd, length); | |
8628e7c8 | 519 | |
3e133c8b DK |
520 | /* should be non-zero before next lines to disable clocks later */ |
521 | ctx->digcnt += length; | |
8043bb1a | 522 | ctx->total -= length; |
3e133c8b | 523 | |
8628e7c8 | 524 | if (final) |
ed3ea9a8 | 525 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 526 | |
6c63db82 DK |
527 | set_bit(FLAGS_CPU, &dd->flags); |
528 | ||
8628e7c8 | 529 | len32 = DIV_ROUND_UP(length, sizeof(u32)); |
b8411ccd LV |
530 | bs32 = get_block_size(ctx) / sizeof(u32); |
531 | ||
8043bb1a TK |
532 | sg_miter_start(&mi, ctx->sg, ctx->sg_len, |
533 | SG_MITER_FROM_SG | SG_MITER_ATOMIC); | |
534 | ||
535 | mlen = 0; | |
536 | ||
b8411ccd LV |
537 | while (len32) { |
538 | if (dd->pdata->poll_irq(dd)) | |
539 | return -ETIMEDOUT; | |
8628e7c8 | 540 | |
8043bb1a TK |
541 | for (count = 0; count < min(len32, bs32); count++, offset++) { |
542 | if (!mlen) { | |
543 | sg_miter_next(&mi); | |
544 | mlen = mi.length; | |
545 | if (!mlen) { | |
546 | pr_err("sg miter failure.\n"); | |
547 | return -EINVAL; | |
548 | } | |
549 | offset = 0; | |
550 | buffer = mi.addr; | |
551 | } | |
b8411ccd LV |
552 | omap_sham_write(dd, SHA_REG_DIN(dd, count), |
553 | buffer[offset]); | |
8043bb1a TK |
554 | mlen -= 4; |
555 | } | |
b8411ccd LV |
556 | len32 -= min(len32, bs32); |
557 | } | |
8628e7c8 | 558 | |
8043bb1a TK |
559 | sg_miter_stop(&mi); |
560 | ||
8628e7c8 DK |
561 | return -EINPROGRESS; |
562 | } | |
563 | ||
dfd061d5 MG |
564 | static void omap_sham_dma_callback(void *param) |
565 | { | |
566 | struct omap_sham_dev *dd = param; | |
567 | ||
568 | set_bit(FLAGS_DMA_READY, &dd->flags); | |
569 | tasklet_schedule(&dd->done_task); | |
570 | } | |
dfd061d5 | 571 | |
8043bb1a TK |
572 | static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length, |
573 | int final) | |
8628e7c8 DK |
574 | { |
575 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
dfd061d5 MG |
576 | struct dma_async_tx_descriptor *tx; |
577 | struct dma_slave_config cfg; | |
8043bb1a | 578 | int ret; |
8628e7c8 | 579 | |
758f4879 | 580 | dev_dbg(dd->dev, "xmit_dma: digcnt: %zd, length: %zd, final: %d\n", |
8628e7c8 | 581 | ctx->digcnt, length, final); |
8628e7c8 | 582 | |
8043bb1a TK |
583 | if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) { |
584 | dev_err(dd->dev, "dma_map_sg error\n"); | |
585 | return -EINVAL; | |
586 | } | |
587 | ||
dfd061d5 MG |
588 | memset(&cfg, 0, sizeof(cfg)); |
589 | ||
0d373d60 | 590 | cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); |
dfd061d5 | 591 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
8043bb1a | 592 | cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES; |
dfd061d5 MG |
593 | |
594 | ret = dmaengine_slave_config(dd->dma_lch, &cfg); | |
595 | if (ret) { | |
596 | pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); | |
597 | return ret; | |
598 | } | |
599 | ||
8043bb1a TK |
600 | tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len, |
601 | DMA_MEM_TO_DEV, | |
602 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
8628e7c8 | 603 | |
dfd061d5 | 604 | if (!tx) { |
8043bb1a | 605 | dev_err(dd->dev, "prep_slave_sg failed\n"); |
dfd061d5 MG |
606 | return -EINVAL; |
607 | } | |
8628e7c8 | 608 | |
dfd061d5 MG |
609 | tx->callback = omap_sham_dma_callback; |
610 | tx->callback_param = dd; | |
8628e7c8 | 611 | |
0d373d60 | 612 | dd->pdata->write_ctrl(dd, length, final, 1); |
8628e7c8 DK |
613 | |
614 | ctx->digcnt += length; | |
8043bb1a | 615 | ctx->total -= length; |
8628e7c8 DK |
616 | |
617 | if (final) | |
ed3ea9a8 | 618 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 619 | |
a929cbee | 620 | set_bit(FLAGS_DMA_ACTIVE, &dd->flags); |
8628e7c8 | 621 | |
dfd061d5 MG |
622 | dmaengine_submit(tx); |
623 | dma_async_issue_pending(dd->dma_lch); | |
8628e7c8 | 624 | |
0d373d60 | 625 | dd->pdata->trigger(dd, length); |
8628e7c8 DK |
626 | |
627 | return -EINPROGRESS; | |
628 | } | |
629 | ||
f19de1bc TK |
630 | static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx, |
631 | struct scatterlist *sg, int bs, int new_len) | |
632 | { | |
633 | int n = sg_nents(sg); | |
634 | struct scatterlist *tmp; | |
635 | int offset = ctx->offset; | |
636 | ||
60a0894c TK |
637 | ctx->total = new_len; |
638 | ||
f19de1bc TK |
639 | if (ctx->bufcnt) |
640 | n++; | |
641 | ||
642 | ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); | |
643 | if (!ctx->sg) | |
644 | return -ENOMEM; | |
645 | ||
646 | sg_init_table(ctx->sg, n); | |
647 | ||
648 | tmp = ctx->sg; | |
649 | ||
650 | ctx->sg_len = 0; | |
651 | ||
652 | if (ctx->bufcnt) { | |
653 | sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); | |
654 | tmp = sg_next(tmp); | |
655 | ctx->sg_len++; | |
60a0894c | 656 | new_len -= ctx->bufcnt; |
f19de1bc TK |
657 | } |
658 | ||
659 | while (sg && new_len) { | |
660 | int len = sg->length - offset; | |
661 | ||
1cfd9f3f | 662 | if (len <= 0) { |
f19de1bc | 663 | offset -= sg->length; |
1cfd9f3f TK |
664 | sg = sg_next(sg); |
665 | continue; | |
f19de1bc TK |
666 | } |
667 | ||
668 | if (new_len < len) | |
669 | len = new_len; | |
670 | ||
671 | if (len > 0) { | |
672 | new_len -= len; | |
1cfd9f3f TK |
673 | sg_set_page(tmp, sg_page(sg), len, sg->offset + offset); |
674 | offset = 0; | |
675 | ctx->offset = 0; | |
60a0894c | 676 | ctx->sg_len++; |
f19de1bc | 677 | if (new_len <= 0) |
60a0894c | 678 | break; |
f19de1bc | 679 | tmp = sg_next(tmp); |
f19de1bc TK |
680 | } |
681 | ||
682 | sg = sg_next(sg); | |
683 | } | |
684 | ||
60a0894c TK |
685 | if (tmp) |
686 | sg_mark_end(tmp); | |
687 | ||
f19de1bc TK |
688 | set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags); |
689 | ||
462519fc | 690 | ctx->offset += new_len - ctx->bufcnt; |
f19de1bc TK |
691 | ctx->bufcnt = 0; |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
696 | static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx, | |
462519fc TK |
697 | struct scatterlist *sg, int bs, |
698 | unsigned int new_len) | |
f19de1bc TK |
699 | { |
700 | int pages; | |
701 | void *buf; | |
f19de1bc | 702 | |
462519fc | 703 | pages = get_order(new_len); |
f19de1bc TK |
704 | |
705 | buf = (void *)__get_free_pages(GFP_ATOMIC, pages); | |
706 | if (!buf) { | |
707 | pr_err("Couldn't allocate pages for unaligned cases.\n"); | |
708 | return -ENOMEM; | |
709 | } | |
710 | ||
711 | if (ctx->bufcnt) | |
712 | memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); | |
713 | ||
714 | scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset, | |
462519fc | 715 | min(new_len, ctx->total) - ctx->bufcnt, 0); |
f19de1bc | 716 | sg_init_table(ctx->sgl, 1); |
462519fc | 717 | sg_set_buf(ctx->sgl, buf, new_len); |
f19de1bc TK |
718 | ctx->sg = ctx->sgl; |
719 | set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags); | |
720 | ctx->sg_len = 1; | |
462519fc | 721 | ctx->offset += new_len - ctx->bufcnt; |
f19de1bc | 722 | ctx->bufcnt = 0; |
60a0894c | 723 | ctx->total = new_len; |
f19de1bc TK |
724 | |
725 | return 0; | |
726 | } | |
727 | ||
728 | static int omap_sham_align_sgs(struct scatterlist *sg, | |
729 | int nbytes, int bs, bool final, | |
730 | struct omap_sham_reqctx *rctx) | |
731 | { | |
732 | int n = 0; | |
733 | bool aligned = true; | |
734 | bool list_ok = true; | |
735 | struct scatterlist *sg_tmp = sg; | |
736 | int new_len; | |
737 | int offset = rctx->offset; | |
2b352489 | 738 | int bufcnt = rctx->bufcnt; |
f19de1bc | 739 | |
6395166d TK |
740 | if (!sg || !sg->length || !nbytes) { |
741 | if (bufcnt) { | |
63832a0c | 742 | bufcnt = DIV_ROUND_UP(bufcnt, bs) * bs; |
6395166d TK |
743 | sg_init_table(rctx->sgl, 1); |
744 | sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, bufcnt); | |
745 | rctx->sg = rctx->sgl; | |
63832a0c | 746 | rctx->sg_len = 1; |
6395166d TK |
747 | } |
748 | ||
f19de1bc | 749 | return 0; |
6395166d | 750 | } |
f19de1bc | 751 | |
2b352489 | 752 | new_len = nbytes; |
f19de1bc TK |
753 | |
754 | if (offset) | |
755 | list_ok = false; | |
756 | ||
757 | if (final) | |
758 | new_len = DIV_ROUND_UP(new_len, bs) * bs; | |
759 | else | |
898d86a5 TK |
760 | new_len = (new_len - 1) / bs * bs; |
761 | ||
462519fc TK |
762 | if (!new_len) |
763 | return 0; | |
764 | ||
898d86a5 TK |
765 | if (nbytes != new_len) |
766 | list_ok = false; | |
f19de1bc TK |
767 | |
768 | while (nbytes > 0 && sg_tmp) { | |
769 | n++; | |
770 | ||
2b352489 TK |
771 | if (bufcnt) { |
772 | if (!IS_ALIGNED(bufcnt, bs)) { | |
773 | aligned = false; | |
774 | break; | |
775 | } | |
776 | nbytes -= bufcnt; | |
777 | bufcnt = 0; | |
60a0894c TK |
778 | if (!nbytes) |
779 | list_ok = false; | |
780 | ||
2b352489 TK |
781 | continue; |
782 | } | |
783 | ||
4c219855 TK |
784 | #ifdef CONFIG_ZONE_DMA |
785 | if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) { | |
786 | aligned = false; | |
787 | break; | |
788 | } | |
789 | #endif | |
790 | ||
f19de1bc TK |
791 | if (offset < sg_tmp->length) { |
792 | if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) { | |
793 | aligned = false; | |
794 | break; | |
795 | } | |
796 | ||
797 | if (!IS_ALIGNED(sg_tmp->length - offset, bs)) { | |
798 | aligned = false; | |
799 | break; | |
800 | } | |
801 | } | |
802 | ||
803 | if (offset) { | |
804 | offset -= sg_tmp->length; | |
805 | if (offset < 0) { | |
806 | nbytes += offset; | |
807 | offset = 0; | |
808 | } | |
809 | } else { | |
810 | nbytes -= sg_tmp->length; | |
811 | } | |
812 | ||
813 | sg_tmp = sg_next(sg_tmp); | |
814 | ||
815 | if (nbytes < 0) { | |
816 | list_ok = false; | |
817 | break; | |
818 | } | |
819 | } | |
820 | ||
462519fc TK |
821 | if (new_len > OMAP_SHA_MAX_DMA_LEN) { |
822 | new_len = OMAP_SHA_MAX_DMA_LEN; | |
823 | aligned = false; | |
824 | } | |
825 | ||
f19de1bc TK |
826 | if (!aligned) |
827 | return omap_sham_copy_sgs(rctx, sg, bs, new_len); | |
828 | else if (!list_ok) | |
829 | return omap_sham_copy_sg_lists(rctx, sg, bs, new_len); | |
830 | ||
60a0894c TK |
831 | rctx->total = new_len; |
832 | rctx->offset += new_len; | |
f19de1bc | 833 | rctx->sg_len = n; |
1cfd9f3f TK |
834 | if (rctx->bufcnt) { |
835 | sg_init_table(rctx->sgl, 2); | |
836 | sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt); | |
837 | sg_chain(rctx->sgl, 2, sg); | |
838 | rctx->sg = rctx->sgl; | |
839 | } else { | |
840 | rctx->sg = sg; | |
841 | } | |
f19de1bc TK |
842 | |
843 | return 0; | |
844 | } | |
845 | ||
133c3d43 | 846 | static int omap_sham_prepare_request(struct crypto_engine *engine, void *areq) |
f19de1bc | 847 | { |
133c3d43 TK |
848 | struct ahash_request *req = container_of(areq, struct ahash_request, |
849 | base); | |
f19de1bc TK |
850 | struct omap_sham_reqctx *rctx = ahash_request_ctx(req); |
851 | int bs; | |
852 | int ret; | |
60a0894c | 853 | unsigned int nbytes; |
f19de1bc | 854 | bool final = rctx->flags & BIT(FLAGS_FINUP); |
133c3d43 | 855 | bool update = rctx->op == OP_UPDATE; |
60a0894c | 856 | int hash_later; |
f19de1bc | 857 | |
f19de1bc TK |
858 | bs = get_block_size(rctx); |
859 | ||
60a0894c | 860 | nbytes = rctx->bufcnt; |
f19de1bc | 861 | |
60a0894c TK |
862 | if (update) |
863 | nbytes += req->nbytes - rctx->offset; | |
462519fc TK |
864 | |
865 | dev_dbg(rctx->dd->dev, | |
758f4879 | 866 | "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%zd\n", |
462519fc TK |
867 | __func__, nbytes, bs, rctx->total, rctx->offset, |
868 | rctx->bufcnt); | |
f19de1bc | 869 | |
60a0894c | 870 | if (!nbytes) |
f19de1bc TK |
871 | return 0; |
872 | ||
60a0894c TK |
873 | rctx->total = nbytes; |
874 | ||
875 | if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) { | |
f19de1bc TK |
876 | int len = bs - rctx->bufcnt % bs; |
877 | ||
60a0894c TK |
878 | if (len > req->nbytes) |
879 | len = req->nbytes; | |
f19de1bc TK |
880 | scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src, |
881 | 0, len, 0); | |
882 | rctx->bufcnt += len; | |
f19de1bc TK |
883 | rctx->offset = len; |
884 | } | |
885 | ||
886 | if (rctx->bufcnt) | |
887 | memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt); | |
888 | ||
60a0894c | 889 | ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx); |
f19de1bc TK |
890 | if (ret) |
891 | return ret; | |
892 | ||
60a0894c | 893 | hash_later = nbytes - rctx->total; |
f19de1bc TK |
894 | if (hash_later < 0) |
895 | hash_later = 0; | |
896 | ||
6395166d | 897 | if (hash_later && hash_later <= rctx->buflen) { |
60a0894c TK |
898 | scatterwalk_map_and_copy(rctx->buffer, |
899 | req->src, | |
900 | req->nbytes - hash_later, | |
901 | hash_later, 0); | |
5d78d57e | 902 | |
f19de1bc TK |
903 | rctx->bufcnt = hash_later; |
904 | } else { | |
905 | rctx->bufcnt = 0; | |
906 | } | |
907 | ||
462519fc TK |
908 | if (hash_later > rctx->buflen) |
909 | set_bit(FLAGS_HUGE, &rctx->dd->flags); | |
910 | ||
60a0894c | 911 | rctx->total = min(nbytes, rctx->total); |
f19de1bc TK |
912 | |
913 | return 0; | |
914 | } | |
915 | ||
8628e7c8 DK |
916 | static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) |
917 | { | |
918 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
919 | ||
8043bb1a | 920 | dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); |
dfd061d5 | 921 | |
8043bb1a | 922 | clear_bit(FLAGS_DMA_ACTIVE, &dd->flags); |
8628e7c8 DK |
923 | |
924 | return 0; | |
925 | } | |
926 | ||
758f4879 | 927 | static struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx) |
281c3778 TK |
928 | { |
929 | struct omap_sham_dev *dd; | |
930 | ||
931 | if (ctx->dd) | |
932 | return ctx->dd; | |
933 | ||
934 | spin_lock_bh(&sham.lock); | |
935 | dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list); | |
936 | list_move_tail(&dd->list, &sham.dev_list); | |
937 | ctx->dd = dd; | |
938 | spin_unlock_bh(&sham.lock); | |
939 | ||
940 | return dd; | |
941 | } | |
942 | ||
8628e7c8 DK |
943 | static int omap_sham_init(struct ahash_request *req) |
944 | { | |
945 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
946 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
947 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
281c3778 | 948 | struct omap_sham_dev *dd; |
eaef7e3f | 949 | int bs = 0; |
8628e7c8 | 950 | |
281c3778 | 951 | ctx->dd = NULL; |
8628e7c8 | 952 | |
281c3778 TK |
953 | dd = omap_sham_find_dev(ctx); |
954 | if (!dd) | |
955 | return -ENODEV; | |
8628e7c8 DK |
956 | |
957 | ctx->flags = 0; | |
958 | ||
8628e7c8 DK |
959 | dev_dbg(dd->dev, "init: digest size: %d\n", |
960 | crypto_ahash_digestsize(tfm)); | |
961 | ||
0d373d60 MG |
962 | switch (crypto_ahash_digestsize(tfm)) { |
963 | case MD5_DIGEST_SIZE: | |
964 | ctx->flags |= FLAGS_MODE_MD5; | |
eaef7e3f | 965 | bs = SHA1_BLOCK_SIZE; |
0d373d60 MG |
966 | break; |
967 | case SHA1_DIGEST_SIZE: | |
968 | ctx->flags |= FLAGS_MODE_SHA1; | |
eaef7e3f | 969 | bs = SHA1_BLOCK_SIZE; |
0d373d60 | 970 | break; |
d20fb18b MG |
971 | case SHA224_DIGEST_SIZE: |
972 | ctx->flags |= FLAGS_MODE_SHA224; | |
eaef7e3f | 973 | bs = SHA224_BLOCK_SIZE; |
d20fb18b MG |
974 | break; |
975 | case SHA256_DIGEST_SIZE: | |
976 | ctx->flags |= FLAGS_MODE_SHA256; | |
eaef7e3f LV |
977 | bs = SHA256_BLOCK_SIZE; |
978 | break; | |
979 | case SHA384_DIGEST_SIZE: | |
980 | ctx->flags |= FLAGS_MODE_SHA384; | |
981 | bs = SHA384_BLOCK_SIZE; | |
982 | break; | |
983 | case SHA512_DIGEST_SIZE: | |
984 | ctx->flags |= FLAGS_MODE_SHA512; | |
985 | bs = SHA512_BLOCK_SIZE; | |
d20fb18b | 986 | break; |
0d373d60 | 987 | } |
8628e7c8 DK |
988 | |
989 | ctx->bufcnt = 0; | |
990 | ctx->digcnt = 0; | |
8043bb1a TK |
991 | ctx->total = 0; |
992 | ctx->offset = 0; | |
798eed5d | 993 | ctx->buflen = BUFLEN; |
8628e7c8 | 994 | |
ea1fd224 | 995 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
0d373d60 MG |
996 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
997 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
998 | ||
eaef7e3f LV |
999 | memcpy(ctx->buffer, bctx->ipad, bs); |
1000 | ctx->bufcnt = bs; | |
0d373d60 | 1001 | } |
8628e7c8 | 1002 | |
ea1fd224 | 1003 | ctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
1004 | } |
1005 | ||
1006 | return 0; | |
1007 | ||
1008 | } | |
1009 | ||
1010 | static int omap_sham_update_req(struct omap_sham_dev *dd) | |
1011 | { | |
1012 | struct ahash_request *req = dd->req; | |
1013 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1014 | int err; | |
462519fc | 1015 | bool final = (ctx->flags & BIT(FLAGS_FINUP)) && |
133c3d43 | 1016 | !(dd->flags & BIT(FLAGS_HUGE)); |
8628e7c8 | 1017 | |
758f4879 | 1018 | dev_dbg(dd->dev, "update_req: total: %u, digcnt: %zd, final: %d", |
462519fc | 1019 | ctx->total, ctx->digcnt, final); |
8628e7c8 | 1020 | |
8043bb1a | 1021 | if (ctx->total < get_block_size(ctx) || |
c9af5995 | 1022 | ctx->total < dd->fallback_sz) |
8043bb1a TK |
1023 | ctx->flags |= BIT(FLAGS_CPU); |
1024 | ||
ea1fd224 | 1025 | if (ctx->flags & BIT(FLAGS_CPU)) |
8043bb1a | 1026 | err = omap_sham_xmit_cpu(dd, ctx->total, final); |
8628e7c8 | 1027 | else |
8043bb1a | 1028 | err = omap_sham_xmit_dma(dd, ctx->total, final); |
8628e7c8 DK |
1029 | |
1030 | /* wait for dma completion before can take more data */ | |
758f4879 | 1031 | dev_dbg(dd->dev, "update: err: %d, digcnt: %zd\n", err, ctx->digcnt); |
8628e7c8 DK |
1032 | |
1033 | return err; | |
1034 | } | |
1035 | ||
1036 | static int omap_sham_final_req(struct omap_sham_dev *dd) | |
1037 | { | |
1038 | struct ahash_request *req = dd->req; | |
1039 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1040 | int err = 0, use_dma = 1; | |
1041 | ||
462519fc TK |
1042 | if (dd->flags & BIT(FLAGS_HUGE)) |
1043 | return 0; | |
1044 | ||
8043bb1a | 1045 | if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode) |
b8411ccd LV |
1046 | /* |
1047 | * faster to handle last block with cpu or | |
1048 | * use cpu when dma is not present. | |
1049 | */ | |
8628e7c8 DK |
1050 | use_dma = 0; |
1051 | ||
1052 | if (use_dma) | |
8043bb1a | 1053 | err = omap_sham_xmit_dma(dd, ctx->total, 1); |
8628e7c8 | 1054 | else |
8043bb1a | 1055 | err = omap_sham_xmit_cpu(dd, ctx->total, 1); |
8628e7c8 DK |
1056 | |
1057 | ctx->bufcnt = 0; | |
1058 | ||
8628e7c8 DK |
1059 | dev_dbg(dd->dev, "final_req: err: %d\n", err); |
1060 | ||
1061 | return err; | |
1062 | } | |
1063 | ||
133c3d43 TK |
1064 | static int omap_sham_hash_one_req(struct crypto_engine *engine, void *areq) |
1065 | { | |
1066 | struct ahash_request *req = container_of(areq, struct ahash_request, | |
1067 | base); | |
1068 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1069 | struct omap_sham_dev *dd = ctx->dd; | |
1070 | int err; | |
1071 | bool final = (ctx->flags & BIT(FLAGS_FINUP)) && | |
1072 | !(dd->flags & BIT(FLAGS_HUGE)); | |
1073 | ||
1074 | dev_dbg(dd->dev, "hash-one: op: %u, total: %u, digcnt: %zd, final: %d", | |
1075 | ctx->op, ctx->total, ctx->digcnt, final); | |
1076 | ||
f23f2186 TL |
1077 | err = pm_runtime_resume_and_get(dd->dev); |
1078 | if (err < 0) { | |
1079 | dev_err(dd->dev, "failed to get sync: %d\n", err); | |
133c3d43 | 1080 | return err; |
f23f2186 | 1081 | } |
133c3d43 | 1082 | |
f23f2186 | 1083 | dd->err = 0; |
6a1ec89f TL |
1084 | dd->req = req; |
1085 | ||
133c3d43 TK |
1086 | if (ctx->digcnt) |
1087 | dd->pdata->copy_hash(req, 0); | |
1088 | ||
1089 | if (ctx->op == OP_UPDATE) | |
1090 | err = omap_sham_update_req(dd); | |
1091 | else if (ctx->op == OP_FINAL) | |
1092 | err = omap_sham_final_req(dd); | |
1093 | ||
1094 | if (err != -EINPROGRESS) | |
1095 | omap_sham_finish_req(req, err); | |
1096 | ||
1097 | return 0; | |
1098 | } | |
1099 | ||
bf362759 | 1100 | static int omap_sham_finish_hmac(struct ahash_request *req) |
8628e7c8 DK |
1101 | { |
1102 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1103 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1104 | int bs = crypto_shash_blocksize(bctx->shash); | |
1105 | int ds = crypto_shash_digestsize(bctx->shash); | |
7bc53c3f | 1106 | SHASH_DESC_ON_STACK(shash, bctx->shash); |
8628e7c8 | 1107 | |
7bc53c3f | 1108 | shash->tfm = bctx->shash; |
8628e7c8 | 1109 | |
7bc53c3f BW |
1110 | return crypto_shash_init(shash) ?: |
1111 | crypto_shash_update(shash, bctx->opad, bs) ?: | |
1112 | crypto_shash_finup(shash, req->result, ds, req->result); | |
bf362759 DK |
1113 | } |
1114 | ||
1115 | static int omap_sham_finish(struct ahash_request *req) | |
1116 | { | |
1117 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1118 | struct omap_sham_dev *dd = ctx->dd; | |
1119 | int err = 0; | |
1120 | ||
1121 | if (ctx->digcnt) { | |
1122 | omap_sham_copy_ready_hash(req); | |
0d373d60 MG |
1123 | if ((ctx->flags & BIT(FLAGS_HMAC)) && |
1124 | !test_bit(FLAGS_AUTO_XOR, &dd->flags)) | |
bf362759 DK |
1125 | err = omap_sham_finish_hmac(req); |
1126 | } | |
1127 | ||
758f4879 | 1128 | dev_dbg(dd->dev, "digcnt: %zd, bufcnt: %zd\n", ctx->digcnt, ctx->bufcnt); |
bf362759 DK |
1129 | |
1130 | return err; | |
8628e7c8 DK |
1131 | } |
1132 | ||
1133 | static void omap_sham_finish_req(struct ahash_request *req, int err) | |
1134 | { | |
1135 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
798eed5d | 1136 | struct omap_sham_dev *dd = ctx->dd; |
8628e7c8 | 1137 | |
8043bb1a TK |
1138 | if (test_bit(FLAGS_SGS_COPIED, &dd->flags)) |
1139 | free_pages((unsigned long)sg_virt(ctx->sg), | |
462519fc | 1140 | get_order(ctx->sg->length)); |
8043bb1a TK |
1141 | |
1142 | if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags)) | |
1143 | kfree(ctx->sg); | |
1144 | ||
1145 | ctx->sg = NULL; | |
1146 | ||
133c3d43 TK |
1147 | dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED) | |
1148 | BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) | | |
1149 | BIT(FLAGS_OUTPUT_READY)); | |
1150 | ||
1151 | if (!err) | |
1152 | dd->pdata->copy_hash(req, 1); | |
8043bb1a | 1153 | |
462519fc | 1154 | if (dd->flags & BIT(FLAGS_HUGE)) { |
133c3d43 TK |
1155 | /* Re-enqueue the request */ |
1156 | omap_sham_enqueue(req, ctx->op); | |
462519fc TK |
1157 | return; |
1158 | } | |
1159 | ||
8628e7c8 | 1160 | if (!err) { |
ed3ea9a8 | 1161 | if (test_bit(FLAGS_FINAL, &dd->flags)) |
bf362759 | 1162 | err = omap_sham_finish(req); |
3e133c8b | 1163 | } else { |
ea1fd224 | 1164 | ctx->flags |= BIT(FLAGS_ERROR); |
8628e7c8 DK |
1165 | } |
1166 | ||
0efd4d8a | 1167 | /* atomic operation is not needed here */ |
133c3d43 | 1168 | dd->flags &= ~(BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | |
0efd4d8a | 1169 | BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); |
b359f034 | 1170 | |
e93f767b TK |
1171 | pm_runtime_mark_last_busy(dd->dev); |
1172 | pm_runtime_put_autosuspend(dd->dev); | |
8628e7c8 | 1173 | |
462519fc TK |
1174 | ctx->offset = 0; |
1175 | ||
133c3d43 | 1176 | crypto_finalize_hash_request(dd->engine, req, err); |
8628e7c8 DK |
1177 | } |
1178 | ||
a5d87237 DK |
1179 | static int omap_sham_handle_queue(struct omap_sham_dev *dd, |
1180 | struct ahash_request *req) | |
8628e7c8 | 1181 | { |
133c3d43 | 1182 | return crypto_transfer_hash_request_to_engine(dd->engine, req); |
8628e7c8 DK |
1183 | } |
1184 | ||
1185 | static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) | |
1186 | { | |
1187 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
281c3778 | 1188 | struct omap_sham_dev *dd = ctx->dd; |
8628e7c8 DK |
1189 | |
1190 | ctx->op = op; | |
1191 | ||
a5d87237 | 1192 | return omap_sham_handle_queue(dd, req); |
8628e7c8 DK |
1193 | } |
1194 | ||
1195 | static int omap_sham_update(struct ahash_request *req) | |
1196 | { | |
1197 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
281c3778 | 1198 | struct omap_sham_dev *dd = omap_sham_find_dev(ctx); |
8628e7c8 DK |
1199 | |
1200 | if (!req->nbytes) | |
1201 | return 0; | |
1202 | ||
5d78d57e | 1203 | if (ctx->bufcnt + req->nbytes <= ctx->buflen) { |
8043bb1a TK |
1204 | scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, |
1205 | 0, req->nbytes, 0); | |
1206 | ctx->bufcnt += req->nbytes; | |
8628e7c8 DK |
1207 | return 0; |
1208 | } | |
1209 | ||
acef7b0f LV |
1210 | if (dd->polling_mode) |
1211 | ctx->flags |= BIT(FLAGS_CPU); | |
1212 | ||
8628e7c8 DK |
1213 | return omap_sham_enqueue(req, OP_UPDATE); |
1214 | } | |
1215 | ||
8628e7c8 DK |
1216 | static int omap_sham_final_shash(struct ahash_request *req) |
1217 | { | |
1218 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1219 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
cb8d5c83 TK |
1220 | int offset = 0; |
1221 | ||
1222 | /* | |
1223 | * If we are running HMAC on limited hardware support, skip | |
1224 | * the ipad in the beginning of the buffer if we are going for | |
1225 | * software fallback algorithm. | |
1226 | */ | |
1227 | if (test_bit(FLAGS_HMAC, &ctx->flags) && | |
1228 | !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags)) | |
1229 | offset = get_block_size(ctx); | |
8628e7c8 | 1230 | |
e29ba412 EB |
1231 | return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset, |
1232 | ctx->bufcnt - offset, req->result); | |
8628e7c8 DK |
1233 | } |
1234 | ||
1235 | static int omap_sham_final(struct ahash_request *req) | |
1236 | { | |
1237 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
8628e7c8 | 1238 | |
ea1fd224 | 1239 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 | 1240 | |
ea1fd224 | 1241 | if (ctx->flags & BIT(FLAGS_ERROR)) |
bf362759 | 1242 | return 0; /* uncompleted hash is not needed */ |
8628e7c8 | 1243 | |
85e0687f BL |
1244 | /* |
1245 | * OMAP HW accel works only with buffers >= 9. | |
1246 | * HMAC is always >= 9 because ipad == block size. | |
c9af5995 | 1247 | * If buffersize is less than fallback_sz, we use fallback |
2c5bd1ef TK |
1248 | * SW encoding, as using DMA + HW in this case doesn't provide |
1249 | * any benefit. | |
85e0687f | 1250 | */ |
c9af5995 | 1251 | if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz) |
bf362759 DK |
1252 | return omap_sham_final_shash(req); |
1253 | else if (ctx->bufcnt) | |
1254 | return omap_sham_enqueue(req, OP_FINAL); | |
8628e7c8 | 1255 | |
bf362759 DK |
1256 | /* copy ready hash (+ finalize hmac) */ |
1257 | return omap_sham_finish(req); | |
8628e7c8 DK |
1258 | } |
1259 | ||
1260 | static int omap_sham_finup(struct ahash_request *req) | |
1261 | { | |
1262 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1263 | int err1, err2; | |
1264 | ||
ea1fd224 | 1265 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 DK |
1266 | |
1267 | err1 = omap_sham_update(req); | |
455e3389 | 1268 | if (err1 == -EINPROGRESS || err1 == -EBUSY) |
8628e7c8 DK |
1269 | return err1; |
1270 | /* | |
1271 | * final() has to be always called to cleanup resources | |
1272 | * even if udpate() failed, except EINPROGRESS | |
1273 | */ | |
1274 | err2 = omap_sham_final(req); | |
1275 | ||
1276 | return err1 ?: err2; | |
1277 | } | |
1278 | ||
1279 | static int omap_sham_digest(struct ahash_request *req) | |
1280 | { | |
1281 | return omap_sham_init(req) ?: omap_sham_finup(req); | |
1282 | } | |
1283 | ||
1284 | static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1285 | unsigned int keylen) | |
1286 | { | |
1287 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
1288 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1289 | int bs = crypto_shash_blocksize(bctx->shash); | |
1290 | int ds = crypto_shash_digestsize(bctx->shash); | |
1291 | int err, i; | |
0d373d60 | 1292 | |
8628e7c8 DK |
1293 | err = crypto_shash_setkey(tctx->fallback, key, keylen); |
1294 | if (err) | |
1295 | return err; | |
1296 | ||
1297 | if (keylen > bs) { | |
e29ba412 EB |
1298 | err = crypto_shash_tfm_digest(bctx->shash, key, keylen, |
1299 | bctx->ipad); | |
8628e7c8 DK |
1300 | if (err) |
1301 | return err; | |
1302 | keylen = ds; | |
1303 | } else { | |
1304 | memcpy(bctx->ipad, key, keylen); | |
1305 | } | |
1306 | ||
1307 | memset(bctx->ipad + keylen, 0, bs - keylen); | |
8628e7c8 | 1308 | |
281c3778 | 1309 | if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) { |
0d373d60 MG |
1310 | memcpy(bctx->opad, bctx->ipad, bs); |
1311 | ||
1312 | for (i = 0; i < bs; i++) { | |
ebd401e7 CL |
1313 | bctx->ipad[i] ^= HMAC_IPAD_VALUE; |
1314 | bctx->opad[i] ^= HMAC_OPAD_VALUE; | |
0d373d60 | 1315 | } |
8628e7c8 DK |
1316 | } |
1317 | ||
1318 | return err; | |
1319 | } | |
1320 | ||
1321 | static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) | |
1322 | { | |
1323 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1324 | const char *alg_name = crypto_tfm_alg_name(tfm); | |
1325 | ||
1326 | /* Allocate a fallback and abort if it failed. */ | |
1327 | tctx->fallback = crypto_alloc_shash(alg_name, 0, | |
1328 | CRYPTO_ALG_NEED_FALLBACK); | |
1329 | if (IS_ERR(tctx->fallback)) { | |
1330 | pr_err("omap-sham: fallback driver '%s' " | |
1331 | "could not be loaded.\n", alg_name); | |
1332 | return PTR_ERR(tctx->fallback); | |
1333 | } | |
1334 | ||
1335 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
798eed5d | 1336 | sizeof(struct omap_sham_reqctx) + BUFLEN); |
8628e7c8 DK |
1337 | |
1338 | if (alg_base) { | |
1339 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
ea1fd224 | 1340 | tctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
1341 | bctx->shash = crypto_alloc_shash(alg_base, 0, |
1342 | CRYPTO_ALG_NEED_FALLBACK); | |
1343 | if (IS_ERR(bctx->shash)) { | |
1344 | pr_err("omap-sham: base driver '%s' " | |
1345 | "could not be loaded.\n", alg_base); | |
1346 | crypto_free_shash(tctx->fallback); | |
1347 | return PTR_ERR(bctx->shash); | |
1348 | } | |
1349 | ||
1350 | } | |
1351 | ||
133c3d43 TK |
1352 | tctx->enginectx.op.do_one_request = omap_sham_hash_one_req; |
1353 | tctx->enginectx.op.prepare_request = omap_sham_prepare_request; | |
1354 | tctx->enginectx.op.unprepare_request = NULL; | |
1355 | ||
8628e7c8 DK |
1356 | return 0; |
1357 | } | |
1358 | ||
1359 | static int omap_sham_cra_init(struct crypto_tfm *tfm) | |
1360 | { | |
1361 | return omap_sham_cra_init_alg(tfm, NULL); | |
1362 | } | |
1363 | ||
1364 | static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) | |
1365 | { | |
1366 | return omap_sham_cra_init_alg(tfm, "sha1"); | |
1367 | } | |
1368 | ||
d20fb18b MG |
1369 | static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) |
1370 | { | |
1371 | return omap_sham_cra_init_alg(tfm, "sha224"); | |
1372 | } | |
1373 | ||
1374 | static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) | |
1375 | { | |
1376 | return omap_sham_cra_init_alg(tfm, "sha256"); | |
1377 | } | |
1378 | ||
8628e7c8 DK |
1379 | static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) |
1380 | { | |
1381 | return omap_sham_cra_init_alg(tfm, "md5"); | |
1382 | } | |
1383 | ||
eaef7e3f LV |
1384 | static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) |
1385 | { | |
1386 | return omap_sham_cra_init_alg(tfm, "sha384"); | |
1387 | } | |
1388 | ||
1389 | static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) | |
1390 | { | |
1391 | return omap_sham_cra_init_alg(tfm, "sha512"); | |
1392 | } | |
1393 | ||
8628e7c8 DK |
1394 | static void omap_sham_cra_exit(struct crypto_tfm *tfm) |
1395 | { | |
1396 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1397 | ||
1398 | crypto_free_shash(tctx->fallback); | |
1399 | tctx->fallback = NULL; | |
1400 | ||
ea1fd224 | 1401 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
8628e7c8 DK |
1402 | struct omap_sham_hmac_ctx *bctx = tctx->base; |
1403 | crypto_free_shash(bctx->shash); | |
1404 | } | |
1405 | } | |
1406 | ||
99a7ffff TK |
1407 | static int omap_sham_export(struct ahash_request *req, void *out) |
1408 | { | |
a84d351f TK |
1409 | struct omap_sham_reqctx *rctx = ahash_request_ctx(req); |
1410 | ||
1411 | memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt); | |
1412 | ||
1413 | return 0; | |
99a7ffff TK |
1414 | } |
1415 | ||
1416 | static int omap_sham_import(struct ahash_request *req, const void *in) | |
1417 | { | |
a84d351f TK |
1418 | struct omap_sham_reqctx *rctx = ahash_request_ctx(req); |
1419 | const struct omap_sham_reqctx *ctx_in = in; | |
1420 | ||
1421 | memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt); | |
1422 | ||
1423 | return 0; | |
99a7ffff TK |
1424 | } |
1425 | ||
d20fb18b | 1426 | static struct ahash_alg algs_sha1_md5[] = { |
8628e7c8 DK |
1427 | { |
1428 | .init = omap_sham_init, | |
1429 | .update = omap_sham_update, | |
1430 | .final = omap_sham_final, | |
1431 | .finup = omap_sham_finup, | |
1432 | .digest = omap_sham_digest, | |
1433 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1434 | .halg.base = { | |
1435 | .cra_name = "sha1", | |
1436 | .cra_driver_name = "omap-sha1", | |
eb354785 | 1437 | .cra_priority = 400, |
6a38f622 | 1438 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1439 | CRYPTO_ALG_ASYNC | |
1440 | CRYPTO_ALG_NEED_FALLBACK, | |
1441 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1442 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1443 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1444 | .cra_module = THIS_MODULE, |
1445 | .cra_init = omap_sham_cra_init, | |
1446 | .cra_exit = omap_sham_cra_exit, | |
1447 | } | |
1448 | }, | |
1449 | { | |
1450 | .init = omap_sham_init, | |
1451 | .update = omap_sham_update, | |
1452 | .final = omap_sham_final, | |
1453 | .finup = omap_sham_finup, | |
1454 | .digest = omap_sham_digest, | |
1455 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1456 | .halg.base = { | |
1457 | .cra_name = "md5", | |
1458 | .cra_driver_name = "omap-md5", | |
eb354785 | 1459 | .cra_priority = 400, |
6a38f622 | 1460 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1461 | CRYPTO_ALG_ASYNC | |
1462 | CRYPTO_ALG_NEED_FALLBACK, | |
1463 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1464 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
798eed5d | 1465 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1466 | .cra_module = THIS_MODULE, |
1467 | .cra_init = omap_sham_cra_init, | |
1468 | .cra_exit = omap_sham_cra_exit, | |
1469 | } | |
1470 | }, | |
1471 | { | |
1472 | .init = omap_sham_init, | |
1473 | .update = omap_sham_update, | |
1474 | .final = omap_sham_final, | |
1475 | .finup = omap_sham_finup, | |
1476 | .digest = omap_sham_digest, | |
1477 | .setkey = omap_sham_setkey, | |
1478 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1479 | .halg.base = { | |
1480 | .cra_name = "hmac(sha1)", | |
1481 | .cra_driver_name = "omap-hmac-sha1", | |
eb354785 | 1482 | .cra_priority = 400, |
6a38f622 | 1483 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1484 | CRYPTO_ALG_ASYNC | |
1485 | CRYPTO_ALG_NEED_FALLBACK, | |
1486 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1487 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1488 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1489 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1490 | .cra_module = THIS_MODULE, |
1491 | .cra_init = omap_sham_cra_sha1_init, | |
1492 | .cra_exit = omap_sham_cra_exit, | |
1493 | } | |
1494 | }, | |
1495 | { | |
1496 | .init = omap_sham_init, | |
1497 | .update = omap_sham_update, | |
1498 | .final = omap_sham_final, | |
1499 | .finup = omap_sham_finup, | |
1500 | .digest = omap_sham_digest, | |
1501 | .setkey = omap_sham_setkey, | |
1502 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1503 | .halg.base = { | |
1504 | .cra_name = "hmac(md5)", | |
1505 | .cra_driver_name = "omap-hmac-md5", | |
eb354785 | 1506 | .cra_priority = 400, |
6a38f622 | 1507 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1508 | CRYPTO_ALG_ASYNC | |
1509 | CRYPTO_ALG_NEED_FALLBACK, | |
1510 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1511 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1512 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1513 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1514 | .cra_module = THIS_MODULE, |
1515 | .cra_init = omap_sham_cra_md5_init, | |
1516 | .cra_exit = omap_sham_cra_exit, | |
1517 | } | |
1518 | } | |
1519 | }; | |
1520 | ||
d20fb18b MG |
1521 | /* OMAP4 has some algs in addition to what OMAP2 has */ |
1522 | static struct ahash_alg algs_sha224_sha256[] = { | |
1523 | { | |
1524 | .init = omap_sham_init, | |
1525 | .update = omap_sham_update, | |
1526 | .final = omap_sham_final, | |
1527 | .finup = omap_sham_finup, | |
1528 | .digest = omap_sham_digest, | |
1529 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
1530 | .halg.base = { | |
1531 | .cra_name = "sha224", | |
1532 | .cra_driver_name = "omap-sha224", | |
eb354785 | 1533 | .cra_priority = 400, |
8dc43636 TK |
1534 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1535 | CRYPTO_ALG_ASYNC | | |
d20fb18b MG |
1536 | CRYPTO_ALG_NEED_FALLBACK, |
1537 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
1538 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1539 | .cra_alignmask = OMAP_ALIGN_MASK, |
d20fb18b MG |
1540 | .cra_module = THIS_MODULE, |
1541 | .cra_init = omap_sham_cra_init, | |
1542 | .cra_exit = omap_sham_cra_exit, | |
1543 | } | |
1544 | }, | |
1545 | { | |
1546 | .init = omap_sham_init, | |
1547 | .update = omap_sham_update, | |
1548 | .final = omap_sham_final, | |
1549 | .finup = omap_sham_finup, | |
1550 | .digest = omap_sham_digest, | |
1551 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
1552 | .halg.base = { | |
1553 | .cra_name = "sha256", | |
1554 | .cra_driver_name = "omap-sha256", | |
eb354785 | 1555 | .cra_priority = 400, |
8dc43636 TK |
1556 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1557 | CRYPTO_ALG_ASYNC | | |
d20fb18b MG |
1558 | CRYPTO_ALG_NEED_FALLBACK, |
1559 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1560 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1561 | .cra_alignmask = OMAP_ALIGN_MASK, |
d20fb18b MG |
1562 | .cra_module = THIS_MODULE, |
1563 | .cra_init = omap_sham_cra_init, | |
1564 | .cra_exit = omap_sham_cra_exit, | |
1565 | } | |
1566 | }, | |
1567 | { | |
1568 | .init = omap_sham_init, | |
1569 | .update = omap_sham_update, | |
1570 | .final = omap_sham_final, | |
1571 | .finup = omap_sham_finup, | |
1572 | .digest = omap_sham_digest, | |
1573 | .setkey = omap_sham_setkey, | |
1574 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
1575 | .halg.base = { | |
1576 | .cra_name = "hmac(sha224)", | |
1577 | .cra_driver_name = "omap-hmac-sha224", | |
eb354785 | 1578 | .cra_priority = 400, |
8dc43636 TK |
1579 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1580 | CRYPTO_ALG_ASYNC | | |
d20fb18b MG |
1581 | CRYPTO_ALG_NEED_FALLBACK, |
1582 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
1583 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1584 | sizeof(struct omap_sham_hmac_ctx), | |
1585 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1586 | .cra_module = THIS_MODULE, | |
1587 | .cra_init = omap_sham_cra_sha224_init, | |
1588 | .cra_exit = omap_sham_cra_exit, | |
1589 | } | |
1590 | }, | |
1591 | { | |
1592 | .init = omap_sham_init, | |
1593 | .update = omap_sham_update, | |
1594 | .final = omap_sham_final, | |
1595 | .finup = omap_sham_finup, | |
1596 | .digest = omap_sham_digest, | |
1597 | .setkey = omap_sham_setkey, | |
1598 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
1599 | .halg.base = { | |
1600 | .cra_name = "hmac(sha256)", | |
1601 | .cra_driver_name = "omap-hmac-sha256", | |
eb354785 | 1602 | .cra_priority = 400, |
8dc43636 TK |
1603 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1604 | CRYPTO_ALG_ASYNC | | |
d20fb18b MG |
1605 | CRYPTO_ALG_NEED_FALLBACK, |
1606 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1607 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1608 | sizeof(struct omap_sham_hmac_ctx), | |
1609 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1610 | .cra_module = THIS_MODULE, | |
1611 | .cra_init = omap_sham_cra_sha256_init, | |
1612 | .cra_exit = omap_sham_cra_exit, | |
1613 | } | |
1614 | }, | |
1615 | }; | |
1616 | ||
eaef7e3f LV |
1617 | static struct ahash_alg algs_sha384_sha512[] = { |
1618 | { | |
1619 | .init = omap_sham_init, | |
1620 | .update = omap_sham_update, | |
1621 | .final = omap_sham_final, | |
1622 | .finup = omap_sham_finup, | |
1623 | .digest = omap_sham_digest, | |
1624 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
1625 | .halg.base = { | |
1626 | .cra_name = "sha384", | |
1627 | .cra_driver_name = "omap-sha384", | |
eb354785 | 1628 | .cra_priority = 400, |
8dc43636 TK |
1629 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1630 | CRYPTO_ALG_ASYNC | | |
eaef7e3f LV |
1631 | CRYPTO_ALG_NEED_FALLBACK, |
1632 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
1633 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1634 | .cra_alignmask = OMAP_ALIGN_MASK, |
eaef7e3f LV |
1635 | .cra_module = THIS_MODULE, |
1636 | .cra_init = omap_sham_cra_init, | |
1637 | .cra_exit = omap_sham_cra_exit, | |
1638 | } | |
1639 | }, | |
1640 | { | |
1641 | .init = omap_sham_init, | |
1642 | .update = omap_sham_update, | |
1643 | .final = omap_sham_final, | |
1644 | .finup = omap_sham_finup, | |
1645 | .digest = omap_sham_digest, | |
1646 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
1647 | .halg.base = { | |
1648 | .cra_name = "sha512", | |
1649 | .cra_driver_name = "omap-sha512", | |
eb354785 | 1650 | .cra_priority = 400, |
8dc43636 TK |
1651 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1652 | CRYPTO_ALG_ASYNC | | |
eaef7e3f LV |
1653 | CRYPTO_ALG_NEED_FALLBACK, |
1654 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
1655 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1656 | .cra_alignmask = OMAP_ALIGN_MASK, |
eaef7e3f LV |
1657 | .cra_module = THIS_MODULE, |
1658 | .cra_init = omap_sham_cra_init, | |
1659 | .cra_exit = omap_sham_cra_exit, | |
1660 | } | |
1661 | }, | |
1662 | { | |
1663 | .init = omap_sham_init, | |
1664 | .update = omap_sham_update, | |
1665 | .final = omap_sham_final, | |
1666 | .finup = omap_sham_finup, | |
1667 | .digest = omap_sham_digest, | |
1668 | .setkey = omap_sham_setkey, | |
1669 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
1670 | .halg.base = { | |
1671 | .cra_name = "hmac(sha384)", | |
1672 | .cra_driver_name = "omap-hmac-sha384", | |
eb354785 | 1673 | .cra_priority = 400, |
8dc43636 TK |
1674 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1675 | CRYPTO_ALG_ASYNC | | |
eaef7e3f LV |
1676 | CRYPTO_ALG_NEED_FALLBACK, |
1677 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
1678 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1679 | sizeof(struct omap_sham_hmac_ctx), | |
1680 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1681 | .cra_module = THIS_MODULE, | |
1682 | .cra_init = omap_sham_cra_sha384_init, | |
1683 | .cra_exit = omap_sham_cra_exit, | |
1684 | } | |
1685 | }, | |
1686 | { | |
1687 | .init = omap_sham_init, | |
1688 | .update = omap_sham_update, | |
1689 | .final = omap_sham_final, | |
1690 | .finup = omap_sham_finup, | |
1691 | .digest = omap_sham_digest, | |
1692 | .setkey = omap_sham_setkey, | |
1693 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
1694 | .halg.base = { | |
1695 | .cra_name = "hmac(sha512)", | |
1696 | .cra_driver_name = "omap-hmac-sha512", | |
eb354785 | 1697 | .cra_priority = 400, |
8dc43636 TK |
1698 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1699 | CRYPTO_ALG_ASYNC | | |
eaef7e3f LV |
1700 | CRYPTO_ALG_NEED_FALLBACK, |
1701 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
1702 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1703 | sizeof(struct omap_sham_hmac_ctx), | |
1704 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1705 | .cra_module = THIS_MODULE, | |
1706 | .cra_init = omap_sham_cra_sha512_init, | |
1707 | .cra_exit = omap_sham_cra_exit, | |
1708 | } | |
1709 | }, | |
1710 | }; | |
1711 | ||
8628e7c8 DK |
1712 | static void omap_sham_done_task(unsigned long data) |
1713 | { | |
1714 | struct omap_sham_dev *dd = (struct omap_sham_dev *)data; | |
6c63db82 | 1715 | int err = 0; |
8628e7c8 | 1716 | |
462519fc TK |
1717 | dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags); |
1718 | ||
6c63db82 | 1719 | if (test_bit(FLAGS_CPU, &dd->flags)) { |
8043bb1a TK |
1720 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) |
1721 | goto finish; | |
6c63db82 | 1722 | } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { |
fe28140b | 1723 | if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { |
6c63db82 DK |
1724 | omap_sham_update_dma_stop(dd); |
1725 | if (dd->err) { | |
1726 | err = dd->err; | |
1727 | goto finish; | |
1728 | } | |
1729 | } | |
1730 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { | |
1731 | /* hash or semi-hash ready */ | |
1732 | clear_bit(FLAGS_DMA_READY, &dd->flags); | |
17f5b199 | 1733 | goto finish; |
6c63db82 | 1734 | } |
8628e7c8 DK |
1735 | } |
1736 | ||
6c63db82 | 1737 | return; |
3e133c8b | 1738 | |
6c63db82 DK |
1739 | finish: |
1740 | dev_dbg(dd->dev, "update done: err: %d\n", err); | |
1741 | /* finish curent request */ | |
1742 | omap_sham_finish_req(dd->req, err); | |
8628e7c8 DK |
1743 | } |
1744 | ||
0d373d60 MG |
1745 | static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) |
1746 | { | |
133c3d43 TK |
1747 | set_bit(FLAGS_OUTPUT_READY, &dd->flags); |
1748 | tasklet_schedule(&dd->done_task); | |
0d373d60 MG |
1749 | |
1750 | return IRQ_HANDLED; | |
1751 | } | |
1752 | ||
1753 | static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) | |
8628e7c8 DK |
1754 | { |
1755 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1756 | |
ed3ea9a8 | 1757 | if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) |
8628e7c8 DK |
1758 | /* final -> allow device to go to power-saving mode */ |
1759 | omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); | |
1760 | ||
1761 | omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, | |
1762 | SHA_REG_CTRL_OUTPUT_READY); | |
1763 | omap_sham_read(dd, SHA_REG_CTRL); | |
1764 | ||
0d373d60 MG |
1765 | return omap_sham_irq_common(dd); |
1766 | } | |
cd3f1d54 | 1767 | |
0d373d60 MG |
1768 | static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) |
1769 | { | |
1770 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1771 | |
0d373d60 MG |
1772 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); |
1773 | ||
1774 | return omap_sham_irq_common(dd); | |
8628e7c8 DK |
1775 | } |
1776 | ||
d20fb18b MG |
1777 | static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { |
1778 | { | |
1779 | .algs_list = algs_sha1_md5, | |
1780 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1781 | }, | |
1782 | }; | |
1783 | ||
0d373d60 | 1784 | static const struct omap_sham_pdata omap_sham_pdata_omap2 = { |
d20fb18b MG |
1785 | .algs_info = omap_sham_algs_info_omap2, |
1786 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), | |
0d373d60 MG |
1787 | .flags = BIT(FLAGS_BE32_SHA1), |
1788 | .digest_size = SHA1_DIGEST_SIZE, | |
1789 | .copy_hash = omap_sham_copy_hash_omap2, | |
1790 | .write_ctrl = omap_sham_write_ctrl_omap2, | |
1791 | .trigger = omap_sham_trigger_omap2, | |
1792 | .poll_irq = omap_sham_poll_irq_omap2, | |
1793 | .intr_hdlr = omap_sham_irq_omap2, | |
1794 | .idigest_ofs = 0x00, | |
1795 | .din_ofs = 0x1c, | |
1796 | .digcnt_ofs = 0x14, | |
1797 | .rev_ofs = 0x5c, | |
1798 | .mask_ofs = 0x60, | |
1799 | .sysstatus_ofs = 0x64, | |
1800 | .major_mask = 0xf0, | |
1801 | .major_shift = 4, | |
1802 | .minor_mask = 0x0f, | |
1803 | .minor_shift = 0, | |
1804 | }; | |
1805 | ||
03feec9c | 1806 | #ifdef CONFIG_OF |
d20fb18b MG |
1807 | static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { |
1808 | { | |
1809 | .algs_list = algs_sha1_md5, | |
1810 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1811 | }, | |
1812 | { | |
1813 | .algs_list = algs_sha224_sha256, | |
1814 | .size = ARRAY_SIZE(algs_sha224_sha256), | |
1815 | }, | |
1816 | }; | |
1817 | ||
0d373d60 | 1818 | static const struct omap_sham_pdata omap_sham_pdata_omap4 = { |
d20fb18b MG |
1819 | .algs_info = omap_sham_algs_info_omap4, |
1820 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), | |
0d373d60 MG |
1821 | .flags = BIT(FLAGS_AUTO_XOR), |
1822 | .digest_size = SHA256_DIGEST_SIZE, | |
1823 | .copy_hash = omap_sham_copy_hash_omap4, | |
1824 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
1825 | .trigger = omap_sham_trigger_omap4, | |
1826 | .poll_irq = omap_sham_poll_irq_omap4, | |
1827 | .intr_hdlr = omap_sham_irq_omap4, | |
1828 | .idigest_ofs = 0x020, | |
eaef7e3f | 1829 | .odigest_ofs = 0x0, |
0d373d60 MG |
1830 | .din_ofs = 0x080, |
1831 | .digcnt_ofs = 0x040, | |
1832 | .rev_ofs = 0x100, | |
1833 | .mask_ofs = 0x110, | |
1834 | .sysstatus_ofs = 0x114, | |
eaef7e3f LV |
1835 | .mode_ofs = 0x44, |
1836 | .length_ofs = 0x48, | |
0d373d60 MG |
1837 | .major_mask = 0x0700, |
1838 | .major_shift = 8, | |
1839 | .minor_mask = 0x003f, | |
1840 | .minor_shift = 0, | |
1841 | }; | |
1842 | ||
7d7c704d LV |
1843 | static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { |
1844 | { | |
1845 | .algs_list = algs_sha1_md5, | |
1846 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1847 | }, | |
1848 | { | |
1849 | .algs_list = algs_sha224_sha256, | |
1850 | .size = ARRAY_SIZE(algs_sha224_sha256), | |
1851 | }, | |
1852 | { | |
1853 | .algs_list = algs_sha384_sha512, | |
1854 | .size = ARRAY_SIZE(algs_sha384_sha512), | |
1855 | }, | |
1856 | }; | |
1857 | ||
1858 | static const struct omap_sham_pdata omap_sham_pdata_omap5 = { | |
1859 | .algs_info = omap_sham_algs_info_omap5, | |
1860 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), | |
1861 | .flags = BIT(FLAGS_AUTO_XOR), | |
1862 | .digest_size = SHA512_DIGEST_SIZE, | |
1863 | .copy_hash = omap_sham_copy_hash_omap4, | |
1864 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
1865 | .trigger = omap_sham_trigger_omap4, | |
1866 | .poll_irq = omap_sham_poll_irq_omap4, | |
1867 | .intr_hdlr = omap_sham_irq_omap4, | |
1868 | .idigest_ofs = 0x240, | |
1869 | .odigest_ofs = 0x200, | |
1870 | .din_ofs = 0x080, | |
1871 | .digcnt_ofs = 0x280, | |
1872 | .rev_ofs = 0x100, | |
1873 | .mask_ofs = 0x110, | |
1874 | .sysstatus_ofs = 0x114, | |
1875 | .mode_ofs = 0x284, | |
1876 | .length_ofs = 0x288, | |
1877 | .major_mask = 0x0700, | |
1878 | .major_shift = 8, | |
1879 | .minor_mask = 0x003f, | |
1880 | .minor_shift = 0, | |
1881 | }; | |
1882 | ||
03feec9c MG |
1883 | static const struct of_device_id omap_sham_of_match[] = { |
1884 | { | |
1885 | .compatible = "ti,omap2-sham", | |
0d373d60 MG |
1886 | .data = &omap_sham_pdata_omap2, |
1887 | }, | |
eddca85b PR |
1888 | { |
1889 | .compatible = "ti,omap3-sham", | |
1890 | .data = &omap_sham_pdata_omap2, | |
1891 | }, | |
0d373d60 MG |
1892 | { |
1893 | .compatible = "ti,omap4-sham", | |
1894 | .data = &omap_sham_pdata_omap4, | |
03feec9c | 1895 | }, |
7d7c704d LV |
1896 | { |
1897 | .compatible = "ti,omap5-sham", | |
1898 | .data = &omap_sham_pdata_omap5, | |
1899 | }, | |
03feec9c MG |
1900 | {}, |
1901 | }; | |
1902 | MODULE_DEVICE_TABLE(of, omap_sham_of_match); | |
1903 | ||
1904 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, | |
1905 | struct device *dev, struct resource *res) | |
8628e7c8 | 1906 | { |
03feec9c | 1907 | struct device_node *node = dev->of_node; |
03feec9c | 1908 | int err = 0; |
8628e7c8 | 1909 | |
7d556931 CL |
1910 | dd->pdata = of_device_get_match_data(dev); |
1911 | if (!dd->pdata) { | |
03feec9c MG |
1912 | dev_err(dev, "no compatible OF match\n"); |
1913 | err = -EINVAL; | |
1914 | goto err; | |
3e133c8b DK |
1915 | } |
1916 | ||
03feec9c MG |
1917 | err = of_address_to_resource(node, 0, res); |
1918 | if (err < 0) { | |
1919 | dev_err(dev, "can't translate OF node address\n"); | |
1920 | err = -EINVAL; | |
1921 | goto err; | |
1922 | } | |
1923 | ||
f7578496 | 1924 | dd->irq = irq_of_parse_and_map(node, 0); |
03feec9c MG |
1925 | if (!dd->irq) { |
1926 | dev_err(dev, "can't translate OF irq value\n"); | |
1927 | err = -EINVAL; | |
1928 | goto err; | |
1929 | } | |
1930 | ||
03feec9c MG |
1931 | err: |
1932 | return err; | |
8628e7c8 | 1933 | } |
03feec9c | 1934 | #else |
c3c3b329 MG |
1935 | static const struct of_device_id omap_sham_of_match[] = { |
1936 | {}, | |
1937 | }; | |
8628e7c8 | 1938 | |
c3c3b329 | 1939 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, |
03feec9c | 1940 | struct device *dev, struct resource *res) |
8628e7c8 | 1941 | { |
03feec9c MG |
1942 | return -EINVAL; |
1943 | } | |
1944 | #endif | |
8628e7c8 | 1945 | |
03feec9c MG |
1946 | static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, |
1947 | struct platform_device *pdev, struct resource *res) | |
1948 | { | |
1949 | struct device *dev = &pdev->dev; | |
1950 | struct resource *r; | |
1951 | int err = 0; | |
8628e7c8 | 1952 | |
03feec9c MG |
1953 | /* Get the base address */ |
1954 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1955 | if (!r) { | |
1956 | dev_err(dev, "no MEM resource info\n"); | |
1957 | err = -ENODEV; | |
1958 | goto err; | |
8628e7c8 | 1959 | } |
03feec9c | 1960 | memcpy(res, r, sizeof(*res)); |
584db6a1 | 1961 | |
03feec9c MG |
1962 | /* Get the IRQ */ |
1963 | dd->irq = platform_get_irq(pdev, 0); | |
1964 | if (dd->irq < 0) { | |
03feec9c MG |
1965 | err = dd->irq; |
1966 | goto err; | |
1967 | } | |
8628e7c8 | 1968 | |
0d373d60 MG |
1969 | /* Only OMAP2/3 can be non-DT */ |
1970 | dd->pdata = &omap_sham_pdata_omap2; | |
1971 | ||
03feec9c MG |
1972 | err: |
1973 | return err; | |
8628e7c8 DK |
1974 | } |
1975 | ||
c9af5995 TK |
1976 | static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, |
1977 | char *buf) | |
1978 | { | |
1979 | struct omap_sham_dev *dd = dev_get_drvdata(dev); | |
1980 | ||
1981 | return sprintf(buf, "%d\n", dd->fallback_sz); | |
1982 | } | |
1983 | ||
1984 | static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, | |
1985 | const char *buf, size_t size) | |
1986 | { | |
1987 | struct omap_sham_dev *dd = dev_get_drvdata(dev); | |
1988 | ssize_t status; | |
1989 | long value; | |
1990 | ||
1991 | status = kstrtol(buf, 0, &value); | |
1992 | if (status) | |
1993 | return status; | |
1994 | ||
1995 | /* HW accelerator only works with buffers > 9 */ | |
1996 | if (value < 9) { | |
1997 | dev_err(dev, "minimum fallback size 9\n"); | |
1998 | return -EINVAL; | |
1999 | } | |
2000 | ||
2001 | dd->fallback_sz = value; | |
2002 | ||
2003 | return size; | |
2004 | } | |
2005 | ||
62f7c708 TK |
2006 | static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, |
2007 | char *buf) | |
2008 | { | |
2009 | struct omap_sham_dev *dd = dev_get_drvdata(dev); | |
2010 | ||
2011 | return sprintf(buf, "%d\n", dd->queue.max_qlen); | |
2012 | } | |
2013 | ||
2014 | static ssize_t queue_len_store(struct device *dev, | |
2015 | struct device_attribute *attr, const char *buf, | |
2016 | size_t size) | |
2017 | { | |
2018 | struct omap_sham_dev *dd = dev_get_drvdata(dev); | |
2019 | ssize_t status; | |
2020 | long value; | |
62f7c708 TK |
2021 | |
2022 | status = kstrtol(buf, 0, &value); | |
2023 | if (status) | |
2024 | return status; | |
2025 | ||
2026 | if (value < 1) | |
2027 | return -EINVAL; | |
2028 | ||
2029 | /* | |
2030 | * Changing the queue size in fly is safe, if size becomes smaller | |
2031 | * than current size, it will just not accept new entries until | |
2032 | * it has shrank enough. | |
2033 | */ | |
62f7c708 | 2034 | dd->queue.max_qlen = value; |
62f7c708 TK |
2035 | |
2036 | return size; | |
2037 | } | |
2038 | ||
2039 | static DEVICE_ATTR_RW(queue_len); | |
c9af5995 TK |
2040 | static DEVICE_ATTR_RW(fallback); |
2041 | ||
2042 | static struct attribute *omap_sham_attrs[] = { | |
62f7c708 | 2043 | &dev_attr_queue_len.attr, |
c9af5995 TK |
2044 | &dev_attr_fallback.attr, |
2045 | NULL, | |
2046 | }; | |
2047 | ||
83b5a23b | 2048 | static const struct attribute_group omap_sham_attr_group = { |
c9af5995 TK |
2049 | .attrs = omap_sham_attrs, |
2050 | }; | |
2051 | ||
49cfe4db | 2052 | static int omap_sham_probe(struct platform_device *pdev) |
8628e7c8 DK |
2053 | { |
2054 | struct omap_sham_dev *dd; | |
2055 | struct device *dev = &pdev->dev; | |
03feec9c | 2056 | struct resource res; |
dfd061d5 | 2057 | dma_cap_mask_t mask; |
8628e7c8 | 2058 | int err, i, j; |
0d373d60 | 2059 | u32 rev; |
8628e7c8 | 2060 | |
7a7e4b73 | 2061 | dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); |
8628e7c8 DK |
2062 | if (dd == NULL) { |
2063 | dev_err(dev, "unable to alloc data struct.\n"); | |
2064 | err = -ENOMEM; | |
2065 | goto data_err; | |
2066 | } | |
2067 | dd->dev = dev; | |
2068 | platform_set_drvdata(pdev, dd); | |
2069 | ||
2070 | INIT_LIST_HEAD(&dd->list); | |
8628e7c8 | 2071 | tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); |
8628e7c8 DK |
2072 | crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); |
2073 | ||
03feec9c MG |
2074 | err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : |
2075 | omap_sham_get_res_pdev(dd, pdev, &res); | |
2076 | if (err) | |
7a7e4b73 | 2077 | goto data_err; |
8628e7c8 | 2078 | |
30862281 LN |
2079 | dd->io_base = devm_ioremap_resource(dev, &res); |
2080 | if (IS_ERR(dd->io_base)) { | |
2081 | err = PTR_ERR(dd->io_base); | |
7a7e4b73 | 2082 | goto data_err; |
8628e7c8 | 2083 | } |
03feec9c | 2084 | dd->phys_base = res.start; |
8628e7c8 | 2085 | |
0de9c387 LV |
2086 | err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, |
2087 | IRQF_TRIGGER_NONE, dev_name(dev), dd); | |
8628e7c8 | 2088 | if (err) { |
0de9c387 LV |
2089 | dev_err(dev, "unable to request irq %d, err = %d\n", |
2090 | dd->irq, err); | |
7a7e4b73 | 2091 | goto data_err; |
8628e7c8 DK |
2092 | } |
2093 | ||
dfd061d5 MG |
2094 | dma_cap_zero(mask); |
2095 | dma_cap_set(DMA_SLAVE, mask); | |
8628e7c8 | 2096 | |
dbe24620 PU |
2097 | dd->dma_lch = dma_request_chan(dev, "rx"); |
2098 | if (IS_ERR(dd->dma_lch)) { | |
2099 | err = PTR_ERR(dd->dma_lch); | |
2100 | if (err == -EPROBE_DEFER) | |
2101 | goto data_err; | |
2102 | ||
b8411ccd LV |
2103 | dd->polling_mode = 1; |
2104 | dev_dbg(dev, "using polling mode instead of dma\n"); | |
8628e7c8 DK |
2105 | } |
2106 | ||
0d373d60 | 2107 | dd->flags |= dd->pdata->flags; |
281c3778 | 2108 | sham.flags |= dd->pdata->flags; |
8628e7c8 | 2109 | |
e93f767b TK |
2110 | pm_runtime_use_autosuspend(dev); |
2111 | pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); | |
2112 | ||
c9af5995 TK |
2113 | dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD; |
2114 | ||
b359f034 | 2115 | pm_runtime_enable(dev); |
604c3103 PR |
2116 | |
2117 | err = pm_runtime_get_sync(dev); | |
2118 | if (err < 0) { | |
2119 | dev_err(dev, "failed to get sync: %d\n", err); | |
2120 | goto err_pm; | |
2121 | } | |
2122 | ||
0d373d60 MG |
2123 | rev = omap_sham_read(dd, SHA_REG_REV(dd)); |
2124 | pm_runtime_put_sync(&pdev->dev); | |
8628e7c8 | 2125 | |
8628e7c8 | 2126 | dev_info(dev, "hw accel on OMAP rev %u.%u\n", |
0d373d60 MG |
2127 | (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, |
2128 | (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); | |
8628e7c8 | 2129 | |
fe4d5577 | 2130 | spin_lock_bh(&sham.lock); |
8628e7c8 | 2131 | list_add_tail(&dd->list, &sham.dev_list); |
fe4d5577 | 2132 | spin_unlock_bh(&sham.lock); |
8628e7c8 | 2133 | |
133c3d43 TK |
2134 | dd->engine = crypto_engine_alloc_init(dev, 1); |
2135 | if (!dd->engine) { | |
2136 | err = -ENOMEM; | |
2137 | goto err_engine; | |
2138 | } | |
2139 | ||
2140 | err = crypto_engine_start(dd->engine); | |
2141 | if (err) | |
2142 | goto err_engine_start; | |
2143 | ||
d20fb18b | 2144 | for (i = 0; i < dd->pdata->algs_info_size; i++) { |
281c3778 TK |
2145 | if (dd->pdata->algs_info[i].registered) |
2146 | break; | |
2147 | ||
d20fb18b | 2148 | for (j = 0; j < dd->pdata->algs_info[i].size; j++) { |
99a7ffff TK |
2149 | struct ahash_alg *alg; |
2150 | ||
2151 | alg = &dd->pdata->algs_info[i].algs_list[j]; | |
2152 | alg->export = omap_sham_export; | |
2153 | alg->import = omap_sham_import; | |
a84d351f TK |
2154 | alg->halg.statesize = sizeof(struct omap_sham_reqctx) + |
2155 | BUFLEN; | |
99a7ffff | 2156 | err = crypto_register_ahash(alg); |
d20fb18b MG |
2157 | if (err) |
2158 | goto err_algs; | |
2159 | ||
2160 | dd->pdata->algs_info[i].registered++; | |
2161 | } | |
8628e7c8 DK |
2162 | } |
2163 | ||
c9af5995 TK |
2164 | err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group); |
2165 | if (err) { | |
2166 | dev_err(dev, "could not create sysfs device attrs\n"); | |
2167 | goto err_algs; | |
2168 | } | |
2169 | ||
8628e7c8 DK |
2170 | return 0; |
2171 | ||
2172 | err_algs: | |
d20fb18b MG |
2173 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
2174 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
2175 | crypto_unregister_ahash( | |
2176 | &dd->pdata->algs_info[i].algs_list[j]); | |
133c3d43 TK |
2177 | err_engine_start: |
2178 | crypto_engine_exit(dd->engine); | |
2179 | err_engine: | |
fe4d5577 | 2180 | spin_lock_bh(&sham.lock); |
133c3d43 | 2181 | list_del(&dd->list); |
fe4d5577 | 2182 | spin_unlock_bh(&sham.lock); |
604c3103 | 2183 | err_pm: |
f83fc1a0 | 2184 | pm_runtime_dont_use_autosuspend(dev); |
b359f034 | 2185 | pm_runtime_disable(dev); |
d462e322 | 2186 | if (!dd->polling_mode) |
f13ab86a | 2187 | dma_release_channel(dd->dma_lch); |
8628e7c8 DK |
2188 | data_err: |
2189 | dev_err(dev, "initialization failed.\n"); | |
2190 | ||
2191 | return err; | |
2192 | } | |
2193 | ||
49cfe4db | 2194 | static int omap_sham_remove(struct platform_device *pdev) |
8628e7c8 | 2195 | { |
0588d850 | 2196 | struct omap_sham_dev *dd; |
d20fb18b | 2197 | int i, j; |
8628e7c8 DK |
2198 | |
2199 | dd = platform_get_drvdata(pdev); | |
2200 | if (!dd) | |
2201 | return -ENODEV; | |
fe4d5577 | 2202 | spin_lock_bh(&sham.lock); |
8628e7c8 | 2203 | list_del(&dd->list); |
fe4d5577 | 2204 | spin_unlock_bh(&sham.lock); |
d20fb18b | 2205 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
281c3778 | 2206 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) { |
d20fb18b MG |
2207 | crypto_unregister_ahash( |
2208 | &dd->pdata->algs_info[i].algs_list[j]); | |
281c3778 TK |
2209 | dd->pdata->algs_info[i].registered--; |
2210 | } | |
8628e7c8 | 2211 | tasklet_kill(&dd->done_task); |
f83fc1a0 | 2212 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
b359f034 | 2213 | pm_runtime_disable(&pdev->dev); |
f13ab86a | 2214 | |
dbe24620 | 2215 | if (!dd->polling_mode) |
f13ab86a | 2216 | dma_release_channel(dd->dma_lch); |
8628e7c8 | 2217 | |
b82fc91e TK |
2218 | sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group); |
2219 | ||
8628e7c8 DK |
2220 | return 0; |
2221 | } | |
2222 | ||
2223 | static struct platform_driver omap_sham_driver = { | |
2224 | .probe = omap_sham_probe, | |
2225 | .remove = omap_sham_remove, | |
2226 | .driver = { | |
2227 | .name = "omap-sham", | |
03feec9c | 2228 | .of_match_table = omap_sham_of_match, |
8628e7c8 DK |
2229 | }, |
2230 | }; | |
2231 | ||
02613702 | 2232 | module_platform_driver(omap_sham_driver); |
8628e7c8 DK |
2233 | |
2234 | MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); | |
2235 | MODULE_LICENSE("GPL v2"); | |
2236 | MODULE_AUTHOR("Dmitry Kasatkin"); | |
718249d7 | 2237 | MODULE_ALIAS("platform:omap-sham"); |