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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
8628e7c8 DK |
2 | /* |
3 | * Cryptographic API. | |
4 | * | |
5 | * Support for OMAP SHA1/MD5 HW acceleration. | |
6 | * | |
7 | * Copyright (c) 2010 Nokia Corporation | |
8 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
0d373d60 | 9 | * Copyright (c) 2011 Texas Instruments Incorporated |
8628e7c8 | 10 | * |
8628e7c8 DK |
11 | * Some ideas are from old omap-sha1-md5.c driver. |
12 | */ | |
13 | ||
14 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
15 | ||
8628e7c8 DK |
16 | #include <linux/err.h> |
17 | #include <linux/device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
8628e7c8 DK |
23 | #include <linux/irq.h> |
24 | #include <linux/io.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/scatterlist.h> | |
27 | #include <linux/dma-mapping.h> | |
dfd061d5 | 28 | #include <linux/dmaengine.h> |
b359f034 | 29 | #include <linux/pm_runtime.h> |
03feec9c MG |
30 | #include <linux/of.h> |
31 | #include <linux/of_device.h> | |
32 | #include <linux/of_address.h> | |
33 | #include <linux/of_irq.h> | |
8628e7c8 DK |
34 | #include <linux/delay.h> |
35 | #include <linux/crypto.h> | |
8628e7c8 DK |
36 | #include <crypto/scatterwalk.h> |
37 | #include <crypto/algapi.h> | |
38 | #include <crypto/sha.h> | |
39 | #include <crypto/hash.h> | |
ebd401e7 | 40 | #include <crypto/hmac.h> |
8628e7c8 DK |
41 | #include <crypto/internal/hash.h> |
42 | ||
8628e7c8 DK |
43 | #define MD5_DIGEST_SIZE 16 |
44 | ||
0d373d60 MG |
45 | #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) |
46 | #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) | |
47 | #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) | |
48 | ||
eaef7e3f | 49 | #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) |
8628e7c8 DK |
50 | |
51 | #define SHA_REG_CTRL 0x18 | |
52 | #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) | |
53 | #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) | |
54 | #define SHA_REG_CTRL_ALGO_CONST (1 << 3) | |
55 | #define SHA_REG_CTRL_ALGO (1 << 2) | |
56 | #define SHA_REG_CTRL_INPUT_READY (1 << 1) | |
57 | #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) | |
58 | ||
0d373d60 | 59 | #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) |
8628e7c8 | 60 | |
0d373d60 | 61 | #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) |
8628e7c8 DK |
62 | #define SHA_REG_MASK_DMA_EN (1 << 3) |
63 | #define SHA_REG_MASK_IT_EN (1 << 2) | |
64 | #define SHA_REG_MASK_SOFTRESET (1 << 1) | |
65 | #define SHA_REG_AUTOIDLE (1 << 0) | |
66 | ||
0d373d60 | 67 | #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) |
8628e7c8 DK |
68 | #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) |
69 | ||
eaef7e3f | 70 | #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) |
0d373d60 MG |
71 | #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) |
72 | #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) | |
73 | #define SHA_REG_MODE_CLOSE_HASH (1 << 4) | |
74 | #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) | |
0d373d60 | 75 | |
eaef7e3f LV |
76 | #define SHA_REG_MODE_ALGO_MASK (7 << 0) |
77 | #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) | |
78 | #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) | |
79 | #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) | |
80 | #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) | |
81 | #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) | |
82 | #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) | |
83 | ||
84 | #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) | |
0d373d60 MG |
85 | |
86 | #define SHA_REG_IRQSTATUS 0x118 | |
87 | #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) | |
88 | #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) | |
89 | #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) | |
90 | #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) | |
91 | ||
92 | #define SHA_REG_IRQENA 0x11C | |
93 | #define SHA_REG_IRQENA_CTX_RDY (1 << 3) | |
94 | #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) | |
95 | #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) | |
96 | #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) | |
97 | ||
8628e7c8 DK |
98 | #define DEFAULT_TIMEOUT_INTERVAL HZ |
99 | ||
e93f767b TK |
100 | #define DEFAULT_AUTOSUSPEND_DELAY 1000 |
101 | ||
ea1fd224 DK |
102 | /* mostly device flags */ |
103 | #define FLAGS_BUSY 0 | |
104 | #define FLAGS_FINAL 1 | |
105 | #define FLAGS_DMA_ACTIVE 2 | |
106 | #define FLAGS_OUTPUT_READY 3 | |
107 | #define FLAGS_INIT 4 | |
108 | #define FLAGS_CPU 5 | |
6c63db82 | 109 | #define FLAGS_DMA_READY 6 |
0d373d60 MG |
110 | #define FLAGS_AUTO_XOR 7 |
111 | #define FLAGS_BE32_SHA1 8 | |
f19de1bc TK |
112 | #define FLAGS_SGS_COPIED 9 |
113 | #define FLAGS_SGS_ALLOCED 10 | |
462519fc TK |
114 | #define FLAGS_HUGE 11 |
115 | ||
ea1fd224 DK |
116 | /* context flags */ |
117 | #define FLAGS_FINUP 16 | |
8628e7c8 | 118 | |
0d373d60 | 119 | #define FLAGS_MODE_SHIFT 18 |
eaef7e3f LV |
120 | #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) |
121 | #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) | |
122 | #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) | |
123 | #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) | |
124 | #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) | |
125 | #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) | |
126 | #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) | |
127 | ||
128 | #define FLAGS_HMAC 21 | |
129 | #define FLAGS_ERROR 22 | |
0d373d60 MG |
130 | |
131 | #define OP_UPDATE 1 | |
132 | #define OP_FINAL 2 | |
8628e7c8 | 133 | |
798eed5d DK |
134 | #define OMAP_ALIGN_MASK (sizeof(u32)-1) |
135 | #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) | |
136 | ||
182e283f | 137 | #define BUFLEN SHA512_BLOCK_SIZE |
2c5bd1ef | 138 | #define OMAP_SHA_DMA_THRESHOLD 256 |
798eed5d | 139 | |
462519fc TK |
140 | #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048) |
141 | ||
8628e7c8 DK |
142 | struct omap_sham_dev; |
143 | ||
144 | struct omap_sham_reqctx { | |
145 | struct omap_sham_dev *dd; | |
146 | unsigned long flags; | |
147 | unsigned long op; | |
148 | ||
eaef7e3f | 149 | u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; |
8628e7c8 | 150 | size_t digcnt; |
8628e7c8 DK |
151 | size_t bufcnt; |
152 | size_t buflen; | |
8628e7c8 DK |
153 | |
154 | /* walk state */ | |
155 | struct scatterlist *sg; | |
f19de1bc | 156 | struct scatterlist sgl[2]; |
8043bb1a | 157 | int offset; /* offset in current sg */ |
f19de1bc | 158 | int sg_len; |
8628e7c8 | 159 | unsigned int total; /* total request */ |
798eed5d | 160 | |
5a8a0765 | 161 | u8 buffer[] OMAP_ALIGNED; |
8628e7c8 DK |
162 | }; |
163 | ||
164 | struct omap_sham_hmac_ctx { | |
165 | struct crypto_shash *shash; | |
eaef7e3f LV |
166 | u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; |
167 | u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; | |
8628e7c8 DK |
168 | }; |
169 | ||
170 | struct omap_sham_ctx { | |
171 | struct omap_sham_dev *dd; | |
172 | ||
173 | unsigned long flags; | |
174 | ||
175 | /* fallback stuff */ | |
176 | struct crypto_shash *fallback; | |
177 | ||
5a8a0765 | 178 | struct omap_sham_hmac_ctx base[]; |
8628e7c8 DK |
179 | }; |
180 | ||
65e7a549 | 181 | #define OMAP_SHAM_QUEUE_LENGTH 10 |
8628e7c8 | 182 | |
d20fb18b MG |
183 | struct omap_sham_algs_info { |
184 | struct ahash_alg *algs_list; | |
185 | unsigned int size; | |
186 | unsigned int registered; | |
187 | }; | |
188 | ||
0d373d60 | 189 | struct omap_sham_pdata { |
d20fb18b MG |
190 | struct omap_sham_algs_info *algs_info; |
191 | unsigned int algs_info_size; | |
0d373d60 MG |
192 | unsigned long flags; |
193 | int digest_size; | |
194 | ||
195 | void (*copy_hash)(struct ahash_request *req, int out); | |
196 | void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, | |
197 | int final, int dma); | |
198 | void (*trigger)(struct omap_sham_dev *dd, size_t length); | |
199 | int (*poll_irq)(struct omap_sham_dev *dd); | |
200 | irqreturn_t (*intr_hdlr)(int irq, void *dev_id); | |
201 | ||
202 | u32 odigest_ofs; | |
203 | u32 idigest_ofs; | |
204 | u32 din_ofs; | |
205 | u32 digcnt_ofs; | |
206 | u32 rev_ofs; | |
207 | u32 mask_ofs; | |
208 | u32 sysstatus_ofs; | |
eaef7e3f LV |
209 | u32 mode_ofs; |
210 | u32 length_ofs; | |
0d373d60 MG |
211 | |
212 | u32 major_mask; | |
213 | u32 major_shift; | |
214 | u32 minor_mask; | |
215 | u32 minor_shift; | |
216 | }; | |
217 | ||
8628e7c8 DK |
218 | struct omap_sham_dev { |
219 | struct list_head list; | |
220 | unsigned long phys_base; | |
221 | struct device *dev; | |
222 | void __iomem *io_base; | |
223 | int irq; | |
8628e7c8 | 224 | spinlock_t lock; |
3e133c8b | 225 | int err; |
dfd061d5 | 226 | struct dma_chan *dma_lch; |
8628e7c8 | 227 | struct tasklet_struct done_task; |
b8411ccd | 228 | u8 polling_mode; |
c28e8f21 | 229 | u8 xmit_buf[BUFLEN] OMAP_ALIGNED; |
8628e7c8 DK |
230 | |
231 | unsigned long flags; | |
c9af5995 | 232 | int fallback_sz; |
8628e7c8 DK |
233 | struct crypto_queue queue; |
234 | struct ahash_request *req; | |
0d373d60 MG |
235 | |
236 | const struct omap_sham_pdata *pdata; | |
8628e7c8 DK |
237 | }; |
238 | ||
239 | struct omap_sham_drv { | |
240 | struct list_head dev_list; | |
241 | spinlock_t lock; | |
242 | unsigned long flags; | |
243 | }; | |
244 | ||
245 | static struct omap_sham_drv sham = { | |
246 | .dev_list = LIST_HEAD_INIT(sham.dev_list), | |
247 | .lock = __SPIN_LOCK_UNLOCKED(sham.lock), | |
248 | }; | |
249 | ||
250 | static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) | |
251 | { | |
252 | return __raw_readl(dd->io_base + offset); | |
253 | } | |
254 | ||
255 | static inline void omap_sham_write(struct omap_sham_dev *dd, | |
256 | u32 offset, u32 value) | |
257 | { | |
258 | __raw_writel(value, dd->io_base + offset); | |
259 | } | |
260 | ||
261 | static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, | |
262 | u32 value, u32 mask) | |
263 | { | |
264 | u32 val; | |
265 | ||
266 | val = omap_sham_read(dd, address); | |
267 | val &= ~mask; | |
268 | val |= value; | |
269 | omap_sham_write(dd, address, val); | |
270 | } | |
271 | ||
272 | static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) | |
273 | { | |
274 | unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; | |
275 | ||
276 | while (!(omap_sham_read(dd, offset) & bit)) { | |
277 | if (time_is_before_jiffies(timeout)) | |
278 | return -ETIMEDOUT; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
0d373d60 | 284 | static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) |
8628e7c8 DK |
285 | { |
286 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
0d373d60 | 287 | struct omap_sham_dev *dd = ctx->dd; |
0c3cf4cc | 288 | u32 *hash = (u32 *)ctx->digest; |
8628e7c8 DK |
289 | int i; |
290 | ||
0d373d60 | 291 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { |
3c8d758a | 292 | if (out) |
0d373d60 | 293 | hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); |
3c8d758a | 294 | else |
0d373d60 MG |
295 | omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); |
296 | } | |
297 | } | |
298 | ||
299 | static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) | |
300 | { | |
301 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
302 | struct omap_sham_dev *dd = ctx->dd; | |
303 | int i; | |
304 | ||
305 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
306 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
307 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
308 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
309 | u32 *opad = (u32 *)bctx->opad; | |
310 | ||
311 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { | |
312 | if (out) | |
313 | opad[i] = omap_sham_read(dd, | |
eaef7e3f | 314 | SHA_REG_ODIGEST(dd, i)); |
0d373d60 | 315 | else |
eaef7e3f | 316 | omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), |
0d373d60 MG |
317 | opad[i]); |
318 | } | |
3c8d758a | 319 | } |
0d373d60 MG |
320 | |
321 | omap_sham_copy_hash_omap2(req, out); | |
3c8d758a DK |
322 | } |
323 | ||
324 | static void omap_sham_copy_ready_hash(struct ahash_request *req) | |
325 | { | |
326 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
327 | u32 *in = (u32 *)ctx->digest; | |
328 | u32 *hash = (u32 *)req->result; | |
0d373d60 | 329 | int i, d, big_endian = 0; |
3c8d758a DK |
330 | |
331 | if (!hash) | |
332 | return; | |
333 | ||
0d373d60 MG |
334 | switch (ctx->flags & FLAGS_MODE_MASK) { |
335 | case FLAGS_MODE_MD5: | |
336 | d = MD5_DIGEST_SIZE / sizeof(u32); | |
337 | break; | |
338 | case FLAGS_MODE_SHA1: | |
339 | /* OMAP2 SHA1 is big endian */ | |
340 | if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) | |
341 | big_endian = 1; | |
342 | d = SHA1_DIGEST_SIZE / sizeof(u32); | |
343 | break; | |
d20fb18b MG |
344 | case FLAGS_MODE_SHA224: |
345 | d = SHA224_DIGEST_SIZE / sizeof(u32); | |
346 | break; | |
347 | case FLAGS_MODE_SHA256: | |
348 | d = SHA256_DIGEST_SIZE / sizeof(u32); | |
349 | break; | |
eaef7e3f LV |
350 | case FLAGS_MODE_SHA384: |
351 | d = SHA384_DIGEST_SIZE / sizeof(u32); | |
352 | break; | |
353 | case FLAGS_MODE_SHA512: | |
354 | d = SHA512_DIGEST_SIZE / sizeof(u32); | |
355 | break; | |
0d373d60 MG |
356 | default: |
357 | d = 0; | |
358 | } | |
359 | ||
360 | if (big_endian) | |
361 | for (i = 0; i < d; i++) | |
3c8d758a | 362 | hash[i] = be32_to_cpu(in[i]); |
0d373d60 MG |
363 | else |
364 | for (i = 0; i < d; i++) | |
3c8d758a | 365 | hash[i] = le32_to_cpu(in[i]); |
8628e7c8 DK |
366 | } |
367 | ||
798eed5d | 368 | static int omap_sham_hw_init(struct omap_sham_dev *dd) |
8628e7c8 | 369 | { |
604c3103 PR |
370 | int err; |
371 | ||
372 | err = pm_runtime_get_sync(dd->dev); | |
373 | if (err < 0) { | |
374 | dev_err(dd->dev, "failed to get sync: %d\n", err); | |
375 | return err; | |
376 | } | |
8628e7c8 | 377 | |
a929cbee | 378 | if (!test_bit(FLAGS_INIT, &dd->flags)) { |
a929cbee | 379 | set_bit(FLAGS_INIT, &dd->flags); |
798eed5d DK |
380 | dd->err = 0; |
381 | } | |
8628e7c8 | 382 | |
798eed5d DK |
383 | return 0; |
384 | } | |
385 | ||
0d373d60 | 386 | static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, |
798eed5d DK |
387 | int final, int dma) |
388 | { | |
389 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
390 | u32 val = length << 5, mask; | |
391 | ||
392 | if (likely(ctx->digcnt)) | |
0d373d60 | 393 | omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); |
8628e7c8 | 394 | |
0d373d60 | 395 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), |
8628e7c8 DK |
396 | SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), |
397 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
398 | /* | |
399 | * Setting ALGO_CONST only for the first iteration | |
400 | * and CLOSE_HASH only for the last one. | |
401 | */ | |
0d373d60 | 402 | if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) |
8628e7c8 DK |
403 | val |= SHA_REG_CTRL_ALGO; |
404 | if (!ctx->digcnt) | |
405 | val |= SHA_REG_CTRL_ALGO_CONST; | |
406 | if (final) | |
407 | val |= SHA_REG_CTRL_CLOSE_HASH; | |
408 | ||
409 | mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | | |
410 | SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; | |
411 | ||
412 | omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); | |
8628e7c8 DK |
413 | } |
414 | ||
0d373d60 MG |
415 | static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) |
416 | { | |
417 | } | |
418 | ||
419 | static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) | |
420 | { | |
421 | return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); | |
422 | } | |
423 | ||
eaef7e3f LV |
424 | static int get_block_size(struct omap_sham_reqctx *ctx) |
425 | { | |
426 | int d; | |
427 | ||
428 | switch (ctx->flags & FLAGS_MODE_MASK) { | |
429 | case FLAGS_MODE_MD5: | |
430 | case FLAGS_MODE_SHA1: | |
431 | d = SHA1_BLOCK_SIZE; | |
432 | break; | |
433 | case FLAGS_MODE_SHA224: | |
434 | case FLAGS_MODE_SHA256: | |
435 | d = SHA256_BLOCK_SIZE; | |
436 | break; | |
437 | case FLAGS_MODE_SHA384: | |
438 | case FLAGS_MODE_SHA512: | |
439 | d = SHA512_BLOCK_SIZE; | |
440 | break; | |
441 | default: | |
442 | d = 0; | |
443 | } | |
444 | ||
445 | return d; | |
446 | } | |
447 | ||
0d373d60 MG |
448 | static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, |
449 | u32 *value, int count) | |
450 | { | |
451 | for (; count--; value++, offset += 4) | |
452 | omap_sham_write(dd, offset, *value); | |
453 | } | |
454 | ||
455 | static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, | |
456 | int final, int dma) | |
457 | { | |
458 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
459 | u32 val, mask; | |
460 | ||
461 | /* | |
462 | * Setting ALGO_CONST only for the first iteration and | |
463 | * CLOSE_HASH only for the last one. Note that flags mode bits | |
464 | * correspond to algorithm encoding in mode register. | |
465 | */ | |
eaef7e3f | 466 | val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); |
0d373d60 MG |
467 | if (!ctx->digcnt) { |
468 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
469 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
470 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
eaef7e3f | 471 | int bs, nr_dr; |
0d373d60 MG |
472 | |
473 | val |= SHA_REG_MODE_ALGO_CONSTANT; | |
474 | ||
475 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
eaef7e3f LV |
476 | bs = get_block_size(ctx); |
477 | nr_dr = bs / (2 * sizeof(u32)); | |
0d373d60 | 478 | val |= SHA_REG_MODE_HMAC_KEY_PROC; |
eaef7e3f LV |
479 | omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), |
480 | (u32 *)bctx->ipad, nr_dr); | |
481 | omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), | |
482 | (u32 *)bctx->ipad + nr_dr, nr_dr); | |
483 | ctx->digcnt += bs; | |
0d373d60 MG |
484 | } |
485 | } | |
486 | ||
487 | if (final) { | |
488 | val |= SHA_REG_MODE_CLOSE_HASH; | |
489 | ||
490 | if (ctx->flags & BIT(FLAGS_HMAC)) | |
491 | val |= SHA_REG_MODE_HMAC_OUTER_HASH; | |
492 | } | |
493 | ||
494 | mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | | |
495 | SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | | |
496 | SHA_REG_MODE_HMAC_KEY_PROC; | |
497 | ||
498 | dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); | |
eaef7e3f | 499 | omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); |
0d373d60 MG |
500 | omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); |
501 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), | |
502 | SHA_REG_MASK_IT_EN | | |
503 | (dma ? SHA_REG_MASK_DMA_EN : 0), | |
504 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
505 | } | |
506 | ||
507 | static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) | |
508 | { | |
eaef7e3f | 509 | omap_sham_write(dd, SHA_REG_LENGTH(dd), length); |
0d373d60 MG |
510 | } |
511 | ||
512 | static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) | |
513 | { | |
514 | return omap_sham_wait(dd, SHA_REG_IRQSTATUS, | |
515 | SHA_REG_IRQSTATUS_INPUT_RDY); | |
516 | } | |
517 | ||
8043bb1a TK |
518 | static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length, |
519 | int final) | |
8628e7c8 DK |
520 | { |
521 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
b8411ccd | 522 | int count, len32, bs32, offset = 0; |
8043bb1a TK |
523 | const u32 *buffer; |
524 | int mlen; | |
525 | struct sg_mapping_iter mi; | |
8628e7c8 DK |
526 | |
527 | dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", | |
528 | ctx->digcnt, length, final); | |
529 | ||
0d373d60 MG |
530 | dd->pdata->write_ctrl(dd, length, final, 0); |
531 | dd->pdata->trigger(dd, length); | |
8628e7c8 | 532 | |
3e133c8b DK |
533 | /* should be non-zero before next lines to disable clocks later */ |
534 | ctx->digcnt += length; | |
8043bb1a | 535 | ctx->total -= length; |
3e133c8b | 536 | |
8628e7c8 | 537 | if (final) |
ed3ea9a8 | 538 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 539 | |
6c63db82 DK |
540 | set_bit(FLAGS_CPU, &dd->flags); |
541 | ||
8628e7c8 | 542 | len32 = DIV_ROUND_UP(length, sizeof(u32)); |
b8411ccd LV |
543 | bs32 = get_block_size(ctx) / sizeof(u32); |
544 | ||
8043bb1a TK |
545 | sg_miter_start(&mi, ctx->sg, ctx->sg_len, |
546 | SG_MITER_FROM_SG | SG_MITER_ATOMIC); | |
547 | ||
548 | mlen = 0; | |
549 | ||
b8411ccd LV |
550 | while (len32) { |
551 | if (dd->pdata->poll_irq(dd)) | |
552 | return -ETIMEDOUT; | |
8628e7c8 | 553 | |
8043bb1a TK |
554 | for (count = 0; count < min(len32, bs32); count++, offset++) { |
555 | if (!mlen) { | |
556 | sg_miter_next(&mi); | |
557 | mlen = mi.length; | |
558 | if (!mlen) { | |
559 | pr_err("sg miter failure.\n"); | |
560 | return -EINVAL; | |
561 | } | |
562 | offset = 0; | |
563 | buffer = mi.addr; | |
564 | } | |
b8411ccd LV |
565 | omap_sham_write(dd, SHA_REG_DIN(dd, count), |
566 | buffer[offset]); | |
8043bb1a TK |
567 | mlen -= 4; |
568 | } | |
b8411ccd LV |
569 | len32 -= min(len32, bs32); |
570 | } | |
8628e7c8 | 571 | |
8043bb1a TK |
572 | sg_miter_stop(&mi); |
573 | ||
8628e7c8 DK |
574 | return -EINPROGRESS; |
575 | } | |
576 | ||
dfd061d5 MG |
577 | static void omap_sham_dma_callback(void *param) |
578 | { | |
579 | struct omap_sham_dev *dd = param; | |
580 | ||
581 | set_bit(FLAGS_DMA_READY, &dd->flags); | |
582 | tasklet_schedule(&dd->done_task); | |
583 | } | |
dfd061d5 | 584 | |
8043bb1a TK |
585 | static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length, |
586 | int final) | |
8628e7c8 DK |
587 | { |
588 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
dfd061d5 MG |
589 | struct dma_async_tx_descriptor *tx; |
590 | struct dma_slave_config cfg; | |
8043bb1a | 591 | int ret; |
8628e7c8 DK |
592 | |
593 | dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", | |
594 | ctx->digcnt, length, final); | |
8628e7c8 | 595 | |
8043bb1a TK |
596 | if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) { |
597 | dev_err(dd->dev, "dma_map_sg error\n"); | |
598 | return -EINVAL; | |
599 | } | |
600 | ||
dfd061d5 MG |
601 | memset(&cfg, 0, sizeof(cfg)); |
602 | ||
0d373d60 | 603 | cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); |
dfd061d5 | 604 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
8043bb1a | 605 | cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES; |
dfd061d5 MG |
606 | |
607 | ret = dmaengine_slave_config(dd->dma_lch, &cfg); | |
608 | if (ret) { | |
609 | pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); | |
610 | return ret; | |
611 | } | |
612 | ||
8043bb1a TK |
613 | tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len, |
614 | DMA_MEM_TO_DEV, | |
615 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
8628e7c8 | 616 | |
dfd061d5 | 617 | if (!tx) { |
8043bb1a | 618 | dev_err(dd->dev, "prep_slave_sg failed\n"); |
dfd061d5 MG |
619 | return -EINVAL; |
620 | } | |
8628e7c8 | 621 | |
dfd061d5 MG |
622 | tx->callback = omap_sham_dma_callback; |
623 | tx->callback_param = dd; | |
8628e7c8 | 624 | |
0d373d60 | 625 | dd->pdata->write_ctrl(dd, length, final, 1); |
8628e7c8 DK |
626 | |
627 | ctx->digcnt += length; | |
8043bb1a | 628 | ctx->total -= length; |
8628e7c8 DK |
629 | |
630 | if (final) | |
ed3ea9a8 | 631 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 632 | |
a929cbee | 633 | set_bit(FLAGS_DMA_ACTIVE, &dd->flags); |
8628e7c8 | 634 | |
dfd061d5 MG |
635 | dmaengine_submit(tx); |
636 | dma_async_issue_pending(dd->dma_lch); | |
8628e7c8 | 637 | |
0d373d60 | 638 | dd->pdata->trigger(dd, length); |
8628e7c8 DK |
639 | |
640 | return -EINPROGRESS; | |
641 | } | |
642 | ||
f19de1bc TK |
643 | static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx, |
644 | struct scatterlist *sg, int bs, int new_len) | |
645 | { | |
646 | int n = sg_nents(sg); | |
647 | struct scatterlist *tmp; | |
648 | int offset = ctx->offset; | |
649 | ||
60a0894c TK |
650 | ctx->total = new_len; |
651 | ||
f19de1bc TK |
652 | if (ctx->bufcnt) |
653 | n++; | |
654 | ||
655 | ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); | |
656 | if (!ctx->sg) | |
657 | return -ENOMEM; | |
658 | ||
659 | sg_init_table(ctx->sg, n); | |
660 | ||
661 | tmp = ctx->sg; | |
662 | ||
663 | ctx->sg_len = 0; | |
664 | ||
665 | if (ctx->bufcnt) { | |
666 | sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); | |
667 | tmp = sg_next(tmp); | |
668 | ctx->sg_len++; | |
60a0894c | 669 | new_len -= ctx->bufcnt; |
f19de1bc TK |
670 | } |
671 | ||
672 | while (sg && new_len) { | |
673 | int len = sg->length - offset; | |
674 | ||
1cfd9f3f | 675 | if (len <= 0) { |
f19de1bc | 676 | offset -= sg->length; |
1cfd9f3f TK |
677 | sg = sg_next(sg); |
678 | continue; | |
f19de1bc TK |
679 | } |
680 | ||
681 | if (new_len < len) | |
682 | len = new_len; | |
683 | ||
684 | if (len > 0) { | |
685 | new_len -= len; | |
1cfd9f3f TK |
686 | sg_set_page(tmp, sg_page(sg), len, sg->offset + offset); |
687 | offset = 0; | |
688 | ctx->offset = 0; | |
60a0894c | 689 | ctx->sg_len++; |
f19de1bc | 690 | if (new_len <= 0) |
60a0894c | 691 | break; |
f19de1bc | 692 | tmp = sg_next(tmp); |
f19de1bc TK |
693 | } |
694 | ||
695 | sg = sg_next(sg); | |
696 | } | |
697 | ||
60a0894c TK |
698 | if (tmp) |
699 | sg_mark_end(tmp); | |
700 | ||
f19de1bc TK |
701 | set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags); |
702 | ||
462519fc | 703 | ctx->offset += new_len - ctx->bufcnt; |
f19de1bc TK |
704 | ctx->bufcnt = 0; |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx, | |
462519fc TK |
710 | struct scatterlist *sg, int bs, |
711 | unsigned int new_len) | |
f19de1bc TK |
712 | { |
713 | int pages; | |
714 | void *buf; | |
f19de1bc | 715 | |
462519fc | 716 | pages = get_order(new_len); |
f19de1bc TK |
717 | |
718 | buf = (void *)__get_free_pages(GFP_ATOMIC, pages); | |
719 | if (!buf) { | |
720 | pr_err("Couldn't allocate pages for unaligned cases.\n"); | |
721 | return -ENOMEM; | |
722 | } | |
723 | ||
724 | if (ctx->bufcnt) | |
725 | memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); | |
726 | ||
727 | scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset, | |
462519fc | 728 | min(new_len, ctx->total) - ctx->bufcnt, 0); |
f19de1bc | 729 | sg_init_table(ctx->sgl, 1); |
462519fc | 730 | sg_set_buf(ctx->sgl, buf, new_len); |
f19de1bc TK |
731 | ctx->sg = ctx->sgl; |
732 | set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags); | |
733 | ctx->sg_len = 1; | |
462519fc | 734 | ctx->offset += new_len - ctx->bufcnt; |
f19de1bc | 735 | ctx->bufcnt = 0; |
60a0894c | 736 | ctx->total = new_len; |
f19de1bc TK |
737 | |
738 | return 0; | |
739 | } | |
740 | ||
741 | static int omap_sham_align_sgs(struct scatterlist *sg, | |
742 | int nbytes, int bs, bool final, | |
743 | struct omap_sham_reqctx *rctx) | |
744 | { | |
745 | int n = 0; | |
746 | bool aligned = true; | |
747 | bool list_ok = true; | |
748 | struct scatterlist *sg_tmp = sg; | |
749 | int new_len; | |
750 | int offset = rctx->offset; | |
2b352489 | 751 | int bufcnt = rctx->bufcnt; |
f19de1bc TK |
752 | |
753 | if (!sg || !sg->length || !nbytes) | |
754 | return 0; | |
755 | ||
2b352489 | 756 | new_len = nbytes; |
f19de1bc TK |
757 | |
758 | if (offset) | |
759 | list_ok = false; | |
760 | ||
761 | if (final) | |
762 | new_len = DIV_ROUND_UP(new_len, bs) * bs; | |
763 | else | |
898d86a5 TK |
764 | new_len = (new_len - 1) / bs * bs; |
765 | ||
462519fc TK |
766 | if (!new_len) |
767 | return 0; | |
768 | ||
898d86a5 TK |
769 | if (nbytes != new_len) |
770 | list_ok = false; | |
f19de1bc TK |
771 | |
772 | while (nbytes > 0 && sg_tmp) { | |
773 | n++; | |
774 | ||
2b352489 TK |
775 | if (bufcnt) { |
776 | if (!IS_ALIGNED(bufcnt, bs)) { | |
777 | aligned = false; | |
778 | break; | |
779 | } | |
780 | nbytes -= bufcnt; | |
781 | bufcnt = 0; | |
60a0894c TK |
782 | if (!nbytes) |
783 | list_ok = false; | |
784 | ||
2b352489 TK |
785 | continue; |
786 | } | |
787 | ||
4c219855 TK |
788 | #ifdef CONFIG_ZONE_DMA |
789 | if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) { | |
790 | aligned = false; | |
791 | break; | |
792 | } | |
793 | #endif | |
794 | ||
f19de1bc TK |
795 | if (offset < sg_tmp->length) { |
796 | if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) { | |
797 | aligned = false; | |
798 | break; | |
799 | } | |
800 | ||
801 | if (!IS_ALIGNED(sg_tmp->length - offset, bs)) { | |
802 | aligned = false; | |
803 | break; | |
804 | } | |
805 | } | |
806 | ||
807 | if (offset) { | |
808 | offset -= sg_tmp->length; | |
809 | if (offset < 0) { | |
810 | nbytes += offset; | |
811 | offset = 0; | |
812 | } | |
813 | } else { | |
814 | nbytes -= sg_tmp->length; | |
815 | } | |
816 | ||
817 | sg_tmp = sg_next(sg_tmp); | |
818 | ||
819 | if (nbytes < 0) { | |
820 | list_ok = false; | |
821 | break; | |
822 | } | |
823 | } | |
824 | ||
462519fc TK |
825 | if (new_len > OMAP_SHA_MAX_DMA_LEN) { |
826 | new_len = OMAP_SHA_MAX_DMA_LEN; | |
827 | aligned = false; | |
828 | } | |
829 | ||
f19de1bc TK |
830 | if (!aligned) |
831 | return omap_sham_copy_sgs(rctx, sg, bs, new_len); | |
832 | else if (!list_ok) | |
833 | return omap_sham_copy_sg_lists(rctx, sg, bs, new_len); | |
834 | ||
60a0894c TK |
835 | rctx->total = new_len; |
836 | rctx->offset += new_len; | |
f19de1bc | 837 | rctx->sg_len = n; |
1cfd9f3f TK |
838 | if (rctx->bufcnt) { |
839 | sg_init_table(rctx->sgl, 2); | |
840 | sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt); | |
841 | sg_chain(rctx->sgl, 2, sg); | |
842 | rctx->sg = rctx->sgl; | |
843 | } else { | |
844 | rctx->sg = sg; | |
845 | } | |
f19de1bc TK |
846 | |
847 | return 0; | |
848 | } | |
849 | ||
850 | static int omap_sham_prepare_request(struct ahash_request *req, bool update) | |
851 | { | |
852 | struct omap_sham_reqctx *rctx = ahash_request_ctx(req); | |
853 | int bs; | |
854 | int ret; | |
60a0894c | 855 | unsigned int nbytes; |
f19de1bc | 856 | bool final = rctx->flags & BIT(FLAGS_FINUP); |
60a0894c | 857 | int hash_later; |
f19de1bc | 858 | |
f19de1bc TK |
859 | bs = get_block_size(rctx); |
860 | ||
60a0894c | 861 | nbytes = rctx->bufcnt; |
f19de1bc | 862 | |
60a0894c TK |
863 | if (update) |
864 | nbytes += req->nbytes - rctx->offset; | |
462519fc TK |
865 | |
866 | dev_dbg(rctx->dd->dev, | |
867 | "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%d\n", | |
868 | __func__, nbytes, bs, rctx->total, rctx->offset, | |
869 | rctx->bufcnt); | |
f19de1bc | 870 | |
60a0894c | 871 | if (!nbytes) |
f19de1bc TK |
872 | return 0; |
873 | ||
60a0894c TK |
874 | rctx->total = nbytes; |
875 | ||
876 | if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) { | |
f19de1bc TK |
877 | int len = bs - rctx->bufcnt % bs; |
878 | ||
60a0894c TK |
879 | if (len > req->nbytes) |
880 | len = req->nbytes; | |
f19de1bc TK |
881 | scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src, |
882 | 0, len, 0); | |
883 | rctx->bufcnt += len; | |
f19de1bc TK |
884 | rctx->offset = len; |
885 | } | |
886 | ||
887 | if (rctx->bufcnt) | |
888 | memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt); | |
889 | ||
60a0894c | 890 | ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx); |
f19de1bc TK |
891 | if (ret) |
892 | return ret; | |
893 | ||
60a0894c | 894 | hash_later = nbytes - rctx->total; |
f19de1bc TK |
895 | if (hash_later < 0) |
896 | hash_later = 0; | |
897 | ||
60a0894c TK |
898 | if (hash_later) { |
899 | scatterwalk_map_and_copy(rctx->buffer, | |
900 | req->src, | |
901 | req->nbytes - hash_later, | |
902 | hash_later, 0); | |
5d78d57e | 903 | |
f19de1bc TK |
904 | rctx->bufcnt = hash_later; |
905 | } else { | |
906 | rctx->bufcnt = 0; | |
907 | } | |
908 | ||
462519fc TK |
909 | if (hash_later > rctx->buflen) |
910 | set_bit(FLAGS_HUGE, &rctx->dd->flags); | |
911 | ||
60a0894c | 912 | rctx->total = min(nbytes, rctx->total); |
f19de1bc TK |
913 | |
914 | return 0; | |
915 | } | |
916 | ||
8628e7c8 DK |
917 | static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) |
918 | { | |
919 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
920 | ||
8043bb1a | 921 | dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); |
dfd061d5 | 922 | |
8043bb1a | 923 | clear_bit(FLAGS_DMA_ACTIVE, &dd->flags); |
8628e7c8 DK |
924 | |
925 | return 0; | |
926 | } | |
927 | ||
8628e7c8 DK |
928 | static int omap_sham_init(struct ahash_request *req) |
929 | { | |
930 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
931 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
932 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
933 | struct omap_sham_dev *dd = NULL, *tmp; | |
eaef7e3f | 934 | int bs = 0; |
8628e7c8 DK |
935 | |
936 | spin_lock_bh(&sham.lock); | |
937 | if (!tctx->dd) { | |
938 | list_for_each_entry(tmp, &sham.dev_list, list) { | |
939 | dd = tmp; | |
940 | break; | |
941 | } | |
942 | tctx->dd = dd; | |
943 | } else { | |
944 | dd = tctx->dd; | |
945 | } | |
946 | spin_unlock_bh(&sham.lock); | |
947 | ||
948 | ctx->dd = dd; | |
949 | ||
950 | ctx->flags = 0; | |
951 | ||
8628e7c8 DK |
952 | dev_dbg(dd->dev, "init: digest size: %d\n", |
953 | crypto_ahash_digestsize(tfm)); | |
954 | ||
0d373d60 MG |
955 | switch (crypto_ahash_digestsize(tfm)) { |
956 | case MD5_DIGEST_SIZE: | |
957 | ctx->flags |= FLAGS_MODE_MD5; | |
eaef7e3f | 958 | bs = SHA1_BLOCK_SIZE; |
0d373d60 MG |
959 | break; |
960 | case SHA1_DIGEST_SIZE: | |
961 | ctx->flags |= FLAGS_MODE_SHA1; | |
eaef7e3f | 962 | bs = SHA1_BLOCK_SIZE; |
0d373d60 | 963 | break; |
d20fb18b MG |
964 | case SHA224_DIGEST_SIZE: |
965 | ctx->flags |= FLAGS_MODE_SHA224; | |
eaef7e3f | 966 | bs = SHA224_BLOCK_SIZE; |
d20fb18b MG |
967 | break; |
968 | case SHA256_DIGEST_SIZE: | |
969 | ctx->flags |= FLAGS_MODE_SHA256; | |
eaef7e3f LV |
970 | bs = SHA256_BLOCK_SIZE; |
971 | break; | |
972 | case SHA384_DIGEST_SIZE: | |
973 | ctx->flags |= FLAGS_MODE_SHA384; | |
974 | bs = SHA384_BLOCK_SIZE; | |
975 | break; | |
976 | case SHA512_DIGEST_SIZE: | |
977 | ctx->flags |= FLAGS_MODE_SHA512; | |
978 | bs = SHA512_BLOCK_SIZE; | |
d20fb18b | 979 | break; |
0d373d60 | 980 | } |
8628e7c8 DK |
981 | |
982 | ctx->bufcnt = 0; | |
983 | ctx->digcnt = 0; | |
8043bb1a TK |
984 | ctx->total = 0; |
985 | ctx->offset = 0; | |
798eed5d | 986 | ctx->buflen = BUFLEN; |
8628e7c8 | 987 | |
ea1fd224 | 988 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
0d373d60 MG |
989 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
990 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
991 | ||
eaef7e3f LV |
992 | memcpy(ctx->buffer, bctx->ipad, bs); |
993 | ctx->bufcnt = bs; | |
0d373d60 | 994 | } |
8628e7c8 | 995 | |
ea1fd224 | 996 | ctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
997 | } |
998 | ||
999 | return 0; | |
1000 | ||
1001 | } | |
1002 | ||
1003 | static int omap_sham_update_req(struct omap_sham_dev *dd) | |
1004 | { | |
1005 | struct ahash_request *req = dd->req; | |
1006 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1007 | int err; | |
462519fc TK |
1008 | bool final = (ctx->flags & BIT(FLAGS_FINUP)) && |
1009 | !(dd->flags & BIT(FLAGS_HUGE)); | |
8628e7c8 | 1010 | |
462519fc TK |
1011 | dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, final: %d", |
1012 | ctx->total, ctx->digcnt, final); | |
8628e7c8 | 1013 | |
8043bb1a | 1014 | if (ctx->total < get_block_size(ctx) || |
c9af5995 | 1015 | ctx->total < dd->fallback_sz) |
8043bb1a TK |
1016 | ctx->flags |= BIT(FLAGS_CPU); |
1017 | ||
ea1fd224 | 1018 | if (ctx->flags & BIT(FLAGS_CPU)) |
8043bb1a | 1019 | err = omap_sham_xmit_cpu(dd, ctx->total, final); |
8628e7c8 | 1020 | else |
8043bb1a | 1021 | err = omap_sham_xmit_dma(dd, ctx->total, final); |
8628e7c8 DK |
1022 | |
1023 | /* wait for dma completion before can take more data */ | |
1024 | dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); | |
1025 | ||
1026 | return err; | |
1027 | } | |
1028 | ||
1029 | static int omap_sham_final_req(struct omap_sham_dev *dd) | |
1030 | { | |
1031 | struct ahash_request *req = dd->req; | |
1032 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1033 | int err = 0, use_dma = 1; | |
1034 | ||
462519fc TK |
1035 | if (dd->flags & BIT(FLAGS_HUGE)) |
1036 | return 0; | |
1037 | ||
8043bb1a | 1038 | if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode) |
b8411ccd LV |
1039 | /* |
1040 | * faster to handle last block with cpu or | |
1041 | * use cpu when dma is not present. | |
1042 | */ | |
8628e7c8 DK |
1043 | use_dma = 0; |
1044 | ||
1045 | if (use_dma) | |
8043bb1a | 1046 | err = omap_sham_xmit_dma(dd, ctx->total, 1); |
8628e7c8 | 1047 | else |
8043bb1a | 1048 | err = omap_sham_xmit_cpu(dd, ctx->total, 1); |
8628e7c8 DK |
1049 | |
1050 | ctx->bufcnt = 0; | |
1051 | ||
8628e7c8 DK |
1052 | dev_dbg(dd->dev, "final_req: err: %d\n", err); |
1053 | ||
1054 | return err; | |
1055 | } | |
1056 | ||
bf362759 | 1057 | static int omap_sham_finish_hmac(struct ahash_request *req) |
8628e7c8 DK |
1058 | { |
1059 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1060 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1061 | int bs = crypto_shash_blocksize(bctx->shash); | |
1062 | int ds = crypto_shash_digestsize(bctx->shash); | |
7bc53c3f | 1063 | SHASH_DESC_ON_STACK(shash, bctx->shash); |
8628e7c8 | 1064 | |
7bc53c3f | 1065 | shash->tfm = bctx->shash; |
8628e7c8 | 1066 | |
7bc53c3f BW |
1067 | return crypto_shash_init(shash) ?: |
1068 | crypto_shash_update(shash, bctx->opad, bs) ?: | |
1069 | crypto_shash_finup(shash, req->result, ds, req->result); | |
bf362759 DK |
1070 | } |
1071 | ||
1072 | static int omap_sham_finish(struct ahash_request *req) | |
1073 | { | |
1074 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1075 | struct omap_sham_dev *dd = ctx->dd; | |
1076 | int err = 0; | |
1077 | ||
1078 | if (ctx->digcnt) { | |
1079 | omap_sham_copy_ready_hash(req); | |
0d373d60 MG |
1080 | if ((ctx->flags & BIT(FLAGS_HMAC)) && |
1081 | !test_bit(FLAGS_AUTO_XOR, &dd->flags)) | |
bf362759 DK |
1082 | err = omap_sham_finish_hmac(req); |
1083 | } | |
1084 | ||
1085 | dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); | |
1086 | ||
1087 | return err; | |
8628e7c8 DK |
1088 | } |
1089 | ||
1090 | static void omap_sham_finish_req(struct ahash_request *req, int err) | |
1091 | { | |
1092 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
798eed5d | 1093 | struct omap_sham_dev *dd = ctx->dd; |
8628e7c8 | 1094 | |
8043bb1a TK |
1095 | if (test_bit(FLAGS_SGS_COPIED, &dd->flags)) |
1096 | free_pages((unsigned long)sg_virt(ctx->sg), | |
462519fc | 1097 | get_order(ctx->sg->length)); |
8043bb1a TK |
1098 | |
1099 | if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags)) | |
1100 | kfree(ctx->sg); | |
1101 | ||
1102 | ctx->sg = NULL; | |
1103 | ||
1104 | dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED)); | |
1105 | ||
462519fc TK |
1106 | if (dd->flags & BIT(FLAGS_HUGE)) { |
1107 | dd->flags &= ~(BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) | | |
1108 | BIT(FLAGS_OUTPUT_READY) | BIT(FLAGS_HUGE)); | |
1109 | omap_sham_prepare_request(req, ctx->op == OP_UPDATE); | |
1110 | if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) { | |
1111 | err = omap_sham_update_req(dd); | |
1112 | if (err != -EINPROGRESS && | |
1113 | (ctx->flags & BIT(FLAGS_FINUP))) | |
1114 | err = omap_sham_final_req(dd); | |
1115 | } else if (ctx->op == OP_FINAL) { | |
1116 | omap_sham_final_req(dd); | |
1117 | } | |
1118 | return; | |
1119 | } | |
1120 | ||
8628e7c8 | 1121 | if (!err) { |
0d373d60 | 1122 | dd->pdata->copy_hash(req, 1); |
ed3ea9a8 | 1123 | if (test_bit(FLAGS_FINAL, &dd->flags)) |
bf362759 | 1124 | err = omap_sham_finish(req); |
3e133c8b | 1125 | } else { |
ea1fd224 | 1126 | ctx->flags |= BIT(FLAGS_ERROR); |
8628e7c8 DK |
1127 | } |
1128 | ||
0efd4d8a DK |
1129 | /* atomic operation is not needed here */ |
1130 | dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | | |
1131 | BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); | |
b359f034 | 1132 | |
e93f767b TK |
1133 | pm_runtime_mark_last_busy(dd->dev); |
1134 | pm_runtime_put_autosuspend(dd->dev); | |
8628e7c8 | 1135 | |
462519fc TK |
1136 | ctx->offset = 0; |
1137 | ||
8628e7c8 DK |
1138 | if (req->base.complete) |
1139 | req->base.complete(&req->base, err); | |
1140 | } | |
1141 | ||
a5d87237 DK |
1142 | static int omap_sham_handle_queue(struct omap_sham_dev *dd, |
1143 | struct ahash_request *req) | |
8628e7c8 | 1144 | { |
6c39d116 | 1145 | struct crypto_async_request *async_req, *backlog; |
8628e7c8 | 1146 | struct omap_sham_reqctx *ctx; |
8628e7c8 | 1147 | unsigned long flags; |
a5d87237 | 1148 | int err = 0, ret = 0; |
8628e7c8 | 1149 | |
4e7813a0 | 1150 | retry: |
8628e7c8 | 1151 | spin_lock_irqsave(&dd->lock, flags); |
a5d87237 DK |
1152 | if (req) |
1153 | ret = ahash_enqueue_request(&dd->queue, req); | |
a929cbee | 1154 | if (test_bit(FLAGS_BUSY, &dd->flags)) { |
a5d87237 DK |
1155 | spin_unlock_irqrestore(&dd->lock, flags); |
1156 | return ret; | |
1157 | } | |
6c39d116 | 1158 | backlog = crypto_get_backlog(&dd->queue); |
8628e7c8 | 1159 | async_req = crypto_dequeue_request(&dd->queue); |
6c39d116 | 1160 | if (async_req) |
a929cbee | 1161 | set_bit(FLAGS_BUSY, &dd->flags); |
8628e7c8 DK |
1162 | spin_unlock_irqrestore(&dd->lock, flags); |
1163 | ||
1164 | if (!async_req) | |
a5d87237 | 1165 | return ret; |
8628e7c8 DK |
1166 | |
1167 | if (backlog) | |
1168 | backlog->complete(backlog, -EINPROGRESS); | |
1169 | ||
1170 | req = ahash_request_cast(async_req); | |
8628e7c8 | 1171 | dd->req = req; |
8628e7c8 DK |
1172 | ctx = ahash_request_ctx(req); |
1173 | ||
8043bb1a | 1174 | err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE); |
898d86a5 | 1175 | if (err || !ctx->total) |
f19de1bc TK |
1176 | goto err1; |
1177 | ||
8628e7c8 DK |
1178 | dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", |
1179 | ctx->op, req->nbytes); | |
1180 | ||
798eed5d DK |
1181 | err = omap_sham_hw_init(dd); |
1182 | if (err) | |
1183 | goto err1; | |
1184 | ||
798eed5d | 1185 | if (ctx->digcnt) |
8628e7c8 | 1186 | /* request has changed - restore hash */ |
0d373d60 | 1187 | dd->pdata->copy_hash(req, 0); |
8628e7c8 | 1188 | |
462519fc | 1189 | if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) { |
8628e7c8 | 1190 | err = omap_sham_update_req(dd); |
ea1fd224 | 1191 | if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) |
8628e7c8 DK |
1192 | /* no final() after finup() */ |
1193 | err = omap_sham_final_req(dd); | |
1194 | } else if (ctx->op == OP_FINAL) { | |
1195 | err = omap_sham_final_req(dd); | |
1196 | } | |
798eed5d | 1197 | err1: |
4e7813a0 TK |
1198 | dev_dbg(dd->dev, "exit, err: %d\n", err); |
1199 | ||
1200 | if (err != -EINPROGRESS) { | |
8628e7c8 DK |
1201 | /* done_task will not finish it, so do it here */ |
1202 | omap_sham_finish_req(req, err); | |
4e7813a0 | 1203 | req = NULL; |
8628e7c8 | 1204 | |
4e7813a0 TK |
1205 | /* |
1206 | * Execute next request immediately if there is anything | |
1207 | * in queue. | |
1208 | */ | |
1209 | goto retry; | |
1210 | } | |
8628e7c8 | 1211 | |
a5d87237 | 1212 | return ret; |
8628e7c8 DK |
1213 | } |
1214 | ||
1215 | static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) | |
1216 | { | |
1217 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1218 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1219 | struct omap_sham_dev *dd = tctx->dd; | |
8628e7c8 DK |
1220 | |
1221 | ctx->op = op; | |
1222 | ||
a5d87237 | 1223 | return omap_sham_handle_queue(dd, req); |
8628e7c8 DK |
1224 | } |
1225 | ||
1226 | static int omap_sham_update(struct ahash_request *req) | |
1227 | { | |
1228 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
b8411ccd | 1229 | struct omap_sham_dev *dd = ctx->dd; |
8628e7c8 DK |
1230 | |
1231 | if (!req->nbytes) | |
1232 | return 0; | |
1233 | ||
5d78d57e | 1234 | if (ctx->bufcnt + req->nbytes <= ctx->buflen) { |
8043bb1a TK |
1235 | scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, |
1236 | 0, req->nbytes, 0); | |
1237 | ctx->bufcnt += req->nbytes; | |
8628e7c8 DK |
1238 | return 0; |
1239 | } | |
1240 | ||
acef7b0f LV |
1241 | if (dd->polling_mode) |
1242 | ctx->flags |= BIT(FLAGS_CPU); | |
1243 | ||
8628e7c8 DK |
1244 | return omap_sham_enqueue(req, OP_UPDATE); |
1245 | } | |
1246 | ||
8628e7c8 DK |
1247 | static int omap_sham_final_shash(struct ahash_request *req) |
1248 | { | |
1249 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1250 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
cb8d5c83 TK |
1251 | int offset = 0; |
1252 | ||
1253 | /* | |
1254 | * If we are running HMAC on limited hardware support, skip | |
1255 | * the ipad in the beginning of the buffer if we are going for | |
1256 | * software fallback algorithm. | |
1257 | */ | |
1258 | if (test_bit(FLAGS_HMAC, &ctx->flags) && | |
1259 | !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags)) | |
1260 | offset = get_block_size(ctx); | |
8628e7c8 | 1261 | |
e29ba412 EB |
1262 | return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset, |
1263 | ctx->bufcnt - offset, req->result); | |
8628e7c8 DK |
1264 | } |
1265 | ||
1266 | static int omap_sham_final(struct ahash_request *req) | |
1267 | { | |
1268 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
8628e7c8 | 1269 | |
ea1fd224 | 1270 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 | 1271 | |
ea1fd224 | 1272 | if (ctx->flags & BIT(FLAGS_ERROR)) |
bf362759 | 1273 | return 0; /* uncompleted hash is not needed */ |
8628e7c8 | 1274 | |
85e0687f BL |
1275 | /* |
1276 | * OMAP HW accel works only with buffers >= 9. | |
1277 | * HMAC is always >= 9 because ipad == block size. | |
c9af5995 | 1278 | * If buffersize is less than fallback_sz, we use fallback |
2c5bd1ef TK |
1279 | * SW encoding, as using DMA + HW in this case doesn't provide |
1280 | * any benefit. | |
85e0687f | 1281 | */ |
c9af5995 | 1282 | if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz) |
bf362759 DK |
1283 | return omap_sham_final_shash(req); |
1284 | else if (ctx->bufcnt) | |
1285 | return omap_sham_enqueue(req, OP_FINAL); | |
8628e7c8 | 1286 | |
bf362759 DK |
1287 | /* copy ready hash (+ finalize hmac) */ |
1288 | return omap_sham_finish(req); | |
8628e7c8 DK |
1289 | } |
1290 | ||
1291 | static int omap_sham_finup(struct ahash_request *req) | |
1292 | { | |
1293 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1294 | int err1, err2; | |
1295 | ||
ea1fd224 | 1296 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 DK |
1297 | |
1298 | err1 = omap_sham_update(req); | |
455e3389 | 1299 | if (err1 == -EINPROGRESS || err1 == -EBUSY) |
8628e7c8 DK |
1300 | return err1; |
1301 | /* | |
1302 | * final() has to be always called to cleanup resources | |
1303 | * even if udpate() failed, except EINPROGRESS | |
1304 | */ | |
1305 | err2 = omap_sham_final(req); | |
1306 | ||
1307 | return err1 ?: err2; | |
1308 | } | |
1309 | ||
1310 | static int omap_sham_digest(struct ahash_request *req) | |
1311 | { | |
1312 | return omap_sham_init(req) ?: omap_sham_finup(req); | |
1313 | } | |
1314 | ||
1315 | static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1316 | unsigned int keylen) | |
1317 | { | |
1318 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
1319 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1320 | int bs = crypto_shash_blocksize(bctx->shash); | |
1321 | int ds = crypto_shash_digestsize(bctx->shash); | |
0d373d60 | 1322 | struct omap_sham_dev *dd = NULL, *tmp; |
8628e7c8 | 1323 | int err, i; |
0d373d60 MG |
1324 | |
1325 | spin_lock_bh(&sham.lock); | |
1326 | if (!tctx->dd) { | |
1327 | list_for_each_entry(tmp, &sham.dev_list, list) { | |
1328 | dd = tmp; | |
1329 | break; | |
1330 | } | |
1331 | tctx->dd = dd; | |
1332 | } else { | |
1333 | dd = tctx->dd; | |
1334 | } | |
1335 | spin_unlock_bh(&sham.lock); | |
1336 | ||
8628e7c8 DK |
1337 | err = crypto_shash_setkey(tctx->fallback, key, keylen); |
1338 | if (err) | |
1339 | return err; | |
1340 | ||
1341 | if (keylen > bs) { | |
e29ba412 EB |
1342 | err = crypto_shash_tfm_digest(bctx->shash, key, keylen, |
1343 | bctx->ipad); | |
8628e7c8 DK |
1344 | if (err) |
1345 | return err; | |
1346 | keylen = ds; | |
1347 | } else { | |
1348 | memcpy(bctx->ipad, key, keylen); | |
1349 | } | |
1350 | ||
1351 | memset(bctx->ipad + keylen, 0, bs - keylen); | |
8628e7c8 | 1352 | |
0d373d60 MG |
1353 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
1354 | memcpy(bctx->opad, bctx->ipad, bs); | |
1355 | ||
1356 | for (i = 0; i < bs; i++) { | |
ebd401e7 CL |
1357 | bctx->ipad[i] ^= HMAC_IPAD_VALUE; |
1358 | bctx->opad[i] ^= HMAC_OPAD_VALUE; | |
0d373d60 | 1359 | } |
8628e7c8 DK |
1360 | } |
1361 | ||
1362 | return err; | |
1363 | } | |
1364 | ||
1365 | static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) | |
1366 | { | |
1367 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1368 | const char *alg_name = crypto_tfm_alg_name(tfm); | |
1369 | ||
1370 | /* Allocate a fallback and abort if it failed. */ | |
1371 | tctx->fallback = crypto_alloc_shash(alg_name, 0, | |
1372 | CRYPTO_ALG_NEED_FALLBACK); | |
1373 | if (IS_ERR(tctx->fallback)) { | |
1374 | pr_err("omap-sham: fallback driver '%s' " | |
1375 | "could not be loaded.\n", alg_name); | |
1376 | return PTR_ERR(tctx->fallback); | |
1377 | } | |
1378 | ||
1379 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
798eed5d | 1380 | sizeof(struct omap_sham_reqctx) + BUFLEN); |
8628e7c8 DK |
1381 | |
1382 | if (alg_base) { | |
1383 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
ea1fd224 | 1384 | tctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
1385 | bctx->shash = crypto_alloc_shash(alg_base, 0, |
1386 | CRYPTO_ALG_NEED_FALLBACK); | |
1387 | if (IS_ERR(bctx->shash)) { | |
1388 | pr_err("omap-sham: base driver '%s' " | |
1389 | "could not be loaded.\n", alg_base); | |
1390 | crypto_free_shash(tctx->fallback); | |
1391 | return PTR_ERR(bctx->shash); | |
1392 | } | |
1393 | ||
1394 | } | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | static int omap_sham_cra_init(struct crypto_tfm *tfm) | |
1400 | { | |
1401 | return omap_sham_cra_init_alg(tfm, NULL); | |
1402 | } | |
1403 | ||
1404 | static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) | |
1405 | { | |
1406 | return omap_sham_cra_init_alg(tfm, "sha1"); | |
1407 | } | |
1408 | ||
d20fb18b MG |
1409 | static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) |
1410 | { | |
1411 | return omap_sham_cra_init_alg(tfm, "sha224"); | |
1412 | } | |
1413 | ||
1414 | static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) | |
1415 | { | |
1416 | return omap_sham_cra_init_alg(tfm, "sha256"); | |
1417 | } | |
1418 | ||
8628e7c8 DK |
1419 | static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) |
1420 | { | |
1421 | return omap_sham_cra_init_alg(tfm, "md5"); | |
1422 | } | |
1423 | ||
eaef7e3f LV |
1424 | static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) |
1425 | { | |
1426 | return omap_sham_cra_init_alg(tfm, "sha384"); | |
1427 | } | |
1428 | ||
1429 | static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) | |
1430 | { | |
1431 | return omap_sham_cra_init_alg(tfm, "sha512"); | |
1432 | } | |
1433 | ||
8628e7c8 DK |
1434 | static void omap_sham_cra_exit(struct crypto_tfm *tfm) |
1435 | { | |
1436 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1437 | ||
1438 | crypto_free_shash(tctx->fallback); | |
1439 | tctx->fallback = NULL; | |
1440 | ||
ea1fd224 | 1441 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
8628e7c8 DK |
1442 | struct omap_sham_hmac_ctx *bctx = tctx->base; |
1443 | crypto_free_shash(bctx->shash); | |
1444 | } | |
1445 | } | |
1446 | ||
99a7ffff TK |
1447 | static int omap_sham_export(struct ahash_request *req, void *out) |
1448 | { | |
a84d351f TK |
1449 | struct omap_sham_reqctx *rctx = ahash_request_ctx(req); |
1450 | ||
1451 | memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt); | |
1452 | ||
1453 | return 0; | |
99a7ffff TK |
1454 | } |
1455 | ||
1456 | static int omap_sham_import(struct ahash_request *req, const void *in) | |
1457 | { | |
a84d351f TK |
1458 | struct omap_sham_reqctx *rctx = ahash_request_ctx(req); |
1459 | const struct omap_sham_reqctx *ctx_in = in; | |
1460 | ||
1461 | memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt); | |
1462 | ||
1463 | return 0; | |
99a7ffff TK |
1464 | } |
1465 | ||
d20fb18b | 1466 | static struct ahash_alg algs_sha1_md5[] = { |
8628e7c8 DK |
1467 | { |
1468 | .init = omap_sham_init, | |
1469 | .update = omap_sham_update, | |
1470 | .final = omap_sham_final, | |
1471 | .finup = omap_sham_finup, | |
1472 | .digest = omap_sham_digest, | |
1473 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1474 | .halg.base = { | |
1475 | .cra_name = "sha1", | |
1476 | .cra_driver_name = "omap-sha1", | |
eb354785 | 1477 | .cra_priority = 400, |
6a38f622 | 1478 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1479 | CRYPTO_ALG_ASYNC | |
1480 | CRYPTO_ALG_NEED_FALLBACK, | |
1481 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1482 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1483 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1484 | .cra_module = THIS_MODULE, |
1485 | .cra_init = omap_sham_cra_init, | |
1486 | .cra_exit = omap_sham_cra_exit, | |
1487 | } | |
1488 | }, | |
1489 | { | |
1490 | .init = omap_sham_init, | |
1491 | .update = omap_sham_update, | |
1492 | .final = omap_sham_final, | |
1493 | .finup = omap_sham_finup, | |
1494 | .digest = omap_sham_digest, | |
1495 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1496 | .halg.base = { | |
1497 | .cra_name = "md5", | |
1498 | .cra_driver_name = "omap-md5", | |
eb354785 | 1499 | .cra_priority = 400, |
6a38f622 | 1500 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1501 | CRYPTO_ALG_ASYNC | |
1502 | CRYPTO_ALG_NEED_FALLBACK, | |
1503 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1504 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
798eed5d | 1505 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1506 | .cra_module = THIS_MODULE, |
1507 | .cra_init = omap_sham_cra_init, | |
1508 | .cra_exit = omap_sham_cra_exit, | |
1509 | } | |
1510 | }, | |
1511 | { | |
1512 | .init = omap_sham_init, | |
1513 | .update = omap_sham_update, | |
1514 | .final = omap_sham_final, | |
1515 | .finup = omap_sham_finup, | |
1516 | .digest = omap_sham_digest, | |
1517 | .setkey = omap_sham_setkey, | |
1518 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1519 | .halg.base = { | |
1520 | .cra_name = "hmac(sha1)", | |
1521 | .cra_driver_name = "omap-hmac-sha1", | |
eb354785 | 1522 | .cra_priority = 400, |
6a38f622 | 1523 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1524 | CRYPTO_ALG_ASYNC | |
1525 | CRYPTO_ALG_NEED_FALLBACK, | |
1526 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1527 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1528 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1529 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1530 | .cra_module = THIS_MODULE, |
1531 | .cra_init = omap_sham_cra_sha1_init, | |
1532 | .cra_exit = omap_sham_cra_exit, | |
1533 | } | |
1534 | }, | |
1535 | { | |
1536 | .init = omap_sham_init, | |
1537 | .update = omap_sham_update, | |
1538 | .final = omap_sham_final, | |
1539 | .finup = omap_sham_finup, | |
1540 | .digest = omap_sham_digest, | |
1541 | .setkey = omap_sham_setkey, | |
1542 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1543 | .halg.base = { | |
1544 | .cra_name = "hmac(md5)", | |
1545 | .cra_driver_name = "omap-hmac-md5", | |
eb354785 | 1546 | .cra_priority = 400, |
6a38f622 | 1547 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1548 | CRYPTO_ALG_ASYNC | |
1549 | CRYPTO_ALG_NEED_FALLBACK, | |
1550 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1551 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1552 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1553 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1554 | .cra_module = THIS_MODULE, |
1555 | .cra_init = omap_sham_cra_md5_init, | |
1556 | .cra_exit = omap_sham_cra_exit, | |
1557 | } | |
1558 | } | |
1559 | }; | |
1560 | ||
d20fb18b MG |
1561 | /* OMAP4 has some algs in addition to what OMAP2 has */ |
1562 | static struct ahash_alg algs_sha224_sha256[] = { | |
1563 | { | |
1564 | .init = omap_sham_init, | |
1565 | .update = omap_sham_update, | |
1566 | .final = omap_sham_final, | |
1567 | .finup = omap_sham_finup, | |
1568 | .digest = omap_sham_digest, | |
1569 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
1570 | .halg.base = { | |
1571 | .cra_name = "sha224", | |
1572 | .cra_driver_name = "omap-sha224", | |
eb354785 | 1573 | .cra_priority = 400, |
8dc43636 TK |
1574 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1575 | CRYPTO_ALG_ASYNC | | |
d20fb18b MG |
1576 | CRYPTO_ALG_NEED_FALLBACK, |
1577 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
1578 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1579 | .cra_alignmask = OMAP_ALIGN_MASK, |
d20fb18b MG |
1580 | .cra_module = THIS_MODULE, |
1581 | .cra_init = omap_sham_cra_init, | |
1582 | .cra_exit = omap_sham_cra_exit, | |
1583 | } | |
1584 | }, | |
1585 | { | |
1586 | .init = omap_sham_init, | |
1587 | .update = omap_sham_update, | |
1588 | .final = omap_sham_final, | |
1589 | .finup = omap_sham_finup, | |
1590 | .digest = omap_sham_digest, | |
1591 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
1592 | .halg.base = { | |
1593 | .cra_name = "sha256", | |
1594 | .cra_driver_name = "omap-sha256", | |
eb354785 | 1595 | .cra_priority = 400, |
8dc43636 TK |
1596 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1597 | CRYPTO_ALG_ASYNC | | |
d20fb18b MG |
1598 | CRYPTO_ALG_NEED_FALLBACK, |
1599 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1600 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1601 | .cra_alignmask = OMAP_ALIGN_MASK, |
d20fb18b MG |
1602 | .cra_module = THIS_MODULE, |
1603 | .cra_init = omap_sham_cra_init, | |
1604 | .cra_exit = omap_sham_cra_exit, | |
1605 | } | |
1606 | }, | |
1607 | { | |
1608 | .init = omap_sham_init, | |
1609 | .update = omap_sham_update, | |
1610 | .final = omap_sham_final, | |
1611 | .finup = omap_sham_finup, | |
1612 | .digest = omap_sham_digest, | |
1613 | .setkey = omap_sham_setkey, | |
1614 | .halg.digestsize = SHA224_DIGEST_SIZE, | |
1615 | .halg.base = { | |
1616 | .cra_name = "hmac(sha224)", | |
1617 | .cra_driver_name = "omap-hmac-sha224", | |
eb354785 | 1618 | .cra_priority = 400, |
8dc43636 TK |
1619 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1620 | CRYPTO_ALG_ASYNC | | |
d20fb18b MG |
1621 | CRYPTO_ALG_NEED_FALLBACK, |
1622 | .cra_blocksize = SHA224_BLOCK_SIZE, | |
1623 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1624 | sizeof(struct omap_sham_hmac_ctx), | |
1625 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1626 | .cra_module = THIS_MODULE, | |
1627 | .cra_init = omap_sham_cra_sha224_init, | |
1628 | .cra_exit = omap_sham_cra_exit, | |
1629 | } | |
1630 | }, | |
1631 | { | |
1632 | .init = omap_sham_init, | |
1633 | .update = omap_sham_update, | |
1634 | .final = omap_sham_final, | |
1635 | .finup = omap_sham_finup, | |
1636 | .digest = omap_sham_digest, | |
1637 | .setkey = omap_sham_setkey, | |
1638 | .halg.digestsize = SHA256_DIGEST_SIZE, | |
1639 | .halg.base = { | |
1640 | .cra_name = "hmac(sha256)", | |
1641 | .cra_driver_name = "omap-hmac-sha256", | |
eb354785 | 1642 | .cra_priority = 400, |
8dc43636 TK |
1643 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1644 | CRYPTO_ALG_ASYNC | | |
d20fb18b MG |
1645 | CRYPTO_ALG_NEED_FALLBACK, |
1646 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1647 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1648 | sizeof(struct omap_sham_hmac_ctx), | |
1649 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1650 | .cra_module = THIS_MODULE, | |
1651 | .cra_init = omap_sham_cra_sha256_init, | |
1652 | .cra_exit = omap_sham_cra_exit, | |
1653 | } | |
1654 | }, | |
1655 | }; | |
1656 | ||
eaef7e3f LV |
1657 | static struct ahash_alg algs_sha384_sha512[] = { |
1658 | { | |
1659 | .init = omap_sham_init, | |
1660 | .update = omap_sham_update, | |
1661 | .final = omap_sham_final, | |
1662 | .finup = omap_sham_finup, | |
1663 | .digest = omap_sham_digest, | |
1664 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
1665 | .halg.base = { | |
1666 | .cra_name = "sha384", | |
1667 | .cra_driver_name = "omap-sha384", | |
eb354785 | 1668 | .cra_priority = 400, |
8dc43636 TK |
1669 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1670 | CRYPTO_ALG_ASYNC | | |
eaef7e3f LV |
1671 | CRYPTO_ALG_NEED_FALLBACK, |
1672 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
1673 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1674 | .cra_alignmask = OMAP_ALIGN_MASK, |
eaef7e3f LV |
1675 | .cra_module = THIS_MODULE, |
1676 | .cra_init = omap_sham_cra_init, | |
1677 | .cra_exit = omap_sham_cra_exit, | |
1678 | } | |
1679 | }, | |
1680 | { | |
1681 | .init = omap_sham_init, | |
1682 | .update = omap_sham_update, | |
1683 | .final = omap_sham_final, | |
1684 | .finup = omap_sham_finup, | |
1685 | .digest = omap_sham_digest, | |
1686 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
1687 | .halg.base = { | |
1688 | .cra_name = "sha512", | |
1689 | .cra_driver_name = "omap-sha512", | |
eb354785 | 1690 | .cra_priority = 400, |
8dc43636 TK |
1691 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1692 | CRYPTO_ALG_ASYNC | | |
eaef7e3f LV |
1693 | CRYPTO_ALG_NEED_FALLBACK, |
1694 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
1695 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
744e686a | 1696 | .cra_alignmask = OMAP_ALIGN_MASK, |
eaef7e3f LV |
1697 | .cra_module = THIS_MODULE, |
1698 | .cra_init = omap_sham_cra_init, | |
1699 | .cra_exit = omap_sham_cra_exit, | |
1700 | } | |
1701 | }, | |
1702 | { | |
1703 | .init = omap_sham_init, | |
1704 | .update = omap_sham_update, | |
1705 | .final = omap_sham_final, | |
1706 | .finup = omap_sham_finup, | |
1707 | .digest = omap_sham_digest, | |
1708 | .setkey = omap_sham_setkey, | |
1709 | .halg.digestsize = SHA384_DIGEST_SIZE, | |
1710 | .halg.base = { | |
1711 | .cra_name = "hmac(sha384)", | |
1712 | .cra_driver_name = "omap-hmac-sha384", | |
eb354785 | 1713 | .cra_priority = 400, |
8dc43636 TK |
1714 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1715 | CRYPTO_ALG_ASYNC | | |
eaef7e3f LV |
1716 | CRYPTO_ALG_NEED_FALLBACK, |
1717 | .cra_blocksize = SHA384_BLOCK_SIZE, | |
1718 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1719 | sizeof(struct omap_sham_hmac_ctx), | |
1720 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1721 | .cra_module = THIS_MODULE, | |
1722 | .cra_init = omap_sham_cra_sha384_init, | |
1723 | .cra_exit = omap_sham_cra_exit, | |
1724 | } | |
1725 | }, | |
1726 | { | |
1727 | .init = omap_sham_init, | |
1728 | .update = omap_sham_update, | |
1729 | .final = omap_sham_final, | |
1730 | .finup = omap_sham_finup, | |
1731 | .digest = omap_sham_digest, | |
1732 | .setkey = omap_sham_setkey, | |
1733 | .halg.digestsize = SHA512_DIGEST_SIZE, | |
1734 | .halg.base = { | |
1735 | .cra_name = "hmac(sha512)", | |
1736 | .cra_driver_name = "omap-hmac-sha512", | |
eb354785 | 1737 | .cra_priority = 400, |
8dc43636 TK |
1738 | .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | |
1739 | CRYPTO_ALG_ASYNC | | |
eaef7e3f LV |
1740 | CRYPTO_ALG_NEED_FALLBACK, |
1741 | .cra_blocksize = SHA512_BLOCK_SIZE, | |
1742 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1743 | sizeof(struct omap_sham_hmac_ctx), | |
1744 | .cra_alignmask = OMAP_ALIGN_MASK, | |
1745 | .cra_module = THIS_MODULE, | |
1746 | .cra_init = omap_sham_cra_sha512_init, | |
1747 | .cra_exit = omap_sham_cra_exit, | |
1748 | } | |
1749 | }, | |
1750 | }; | |
1751 | ||
8628e7c8 DK |
1752 | static void omap_sham_done_task(unsigned long data) |
1753 | { | |
1754 | struct omap_sham_dev *dd = (struct omap_sham_dev *)data; | |
6c63db82 | 1755 | int err = 0; |
8628e7c8 | 1756 | |
462519fc TK |
1757 | dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags); |
1758 | ||
6cb3ffe1 DK |
1759 | if (!test_bit(FLAGS_BUSY, &dd->flags)) { |
1760 | omap_sham_handle_queue(dd, NULL); | |
1761 | return; | |
1762 | } | |
1763 | ||
6c63db82 | 1764 | if (test_bit(FLAGS_CPU, &dd->flags)) { |
8043bb1a TK |
1765 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) |
1766 | goto finish; | |
6c63db82 DK |
1767 | } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { |
1768 | if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { | |
1769 | omap_sham_update_dma_stop(dd); | |
1770 | if (dd->err) { | |
1771 | err = dd->err; | |
1772 | goto finish; | |
1773 | } | |
1774 | } | |
1775 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { | |
1776 | /* hash or semi-hash ready */ | |
1777 | clear_bit(FLAGS_DMA_READY, &dd->flags); | |
17f5b199 | 1778 | goto finish; |
6c63db82 | 1779 | } |
8628e7c8 DK |
1780 | } |
1781 | ||
6c63db82 | 1782 | return; |
3e133c8b | 1783 | |
6c63db82 DK |
1784 | finish: |
1785 | dev_dbg(dd->dev, "update done: err: %d\n", err); | |
1786 | /* finish curent request */ | |
1787 | omap_sham_finish_req(dd->req, err); | |
4e7813a0 TK |
1788 | |
1789 | /* If we are not busy, process next req */ | |
1790 | if (!test_bit(FLAGS_BUSY, &dd->flags)) | |
1791 | omap_sham_handle_queue(dd, NULL); | |
8628e7c8 DK |
1792 | } |
1793 | ||
0d373d60 MG |
1794 | static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) |
1795 | { | |
1796 | if (!test_bit(FLAGS_BUSY, &dd->flags)) { | |
1797 | dev_warn(dd->dev, "Interrupt when no active requests.\n"); | |
1798 | } else { | |
1799 | set_bit(FLAGS_OUTPUT_READY, &dd->flags); | |
1800 | tasklet_schedule(&dd->done_task); | |
1801 | } | |
1802 | ||
1803 | return IRQ_HANDLED; | |
1804 | } | |
1805 | ||
1806 | static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) | |
8628e7c8 DK |
1807 | { |
1808 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1809 | |
ed3ea9a8 | 1810 | if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) |
8628e7c8 DK |
1811 | /* final -> allow device to go to power-saving mode */ |
1812 | omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); | |
1813 | ||
1814 | omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, | |
1815 | SHA_REG_CTRL_OUTPUT_READY); | |
1816 | omap_sham_read(dd, SHA_REG_CTRL); | |
1817 | ||
0d373d60 MG |
1818 | return omap_sham_irq_common(dd); |
1819 | } | |
cd3f1d54 | 1820 | |
0d373d60 MG |
1821 | static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) |
1822 | { | |
1823 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1824 | |
0d373d60 MG |
1825 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); |
1826 | ||
1827 | return omap_sham_irq_common(dd); | |
8628e7c8 DK |
1828 | } |
1829 | ||
d20fb18b MG |
1830 | static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { |
1831 | { | |
1832 | .algs_list = algs_sha1_md5, | |
1833 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1834 | }, | |
1835 | }; | |
1836 | ||
0d373d60 | 1837 | static const struct omap_sham_pdata omap_sham_pdata_omap2 = { |
d20fb18b MG |
1838 | .algs_info = omap_sham_algs_info_omap2, |
1839 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), | |
0d373d60 MG |
1840 | .flags = BIT(FLAGS_BE32_SHA1), |
1841 | .digest_size = SHA1_DIGEST_SIZE, | |
1842 | .copy_hash = omap_sham_copy_hash_omap2, | |
1843 | .write_ctrl = omap_sham_write_ctrl_omap2, | |
1844 | .trigger = omap_sham_trigger_omap2, | |
1845 | .poll_irq = omap_sham_poll_irq_omap2, | |
1846 | .intr_hdlr = omap_sham_irq_omap2, | |
1847 | .idigest_ofs = 0x00, | |
1848 | .din_ofs = 0x1c, | |
1849 | .digcnt_ofs = 0x14, | |
1850 | .rev_ofs = 0x5c, | |
1851 | .mask_ofs = 0x60, | |
1852 | .sysstatus_ofs = 0x64, | |
1853 | .major_mask = 0xf0, | |
1854 | .major_shift = 4, | |
1855 | .minor_mask = 0x0f, | |
1856 | .minor_shift = 0, | |
1857 | }; | |
1858 | ||
03feec9c | 1859 | #ifdef CONFIG_OF |
d20fb18b MG |
1860 | static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { |
1861 | { | |
1862 | .algs_list = algs_sha1_md5, | |
1863 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1864 | }, | |
1865 | { | |
1866 | .algs_list = algs_sha224_sha256, | |
1867 | .size = ARRAY_SIZE(algs_sha224_sha256), | |
1868 | }, | |
1869 | }; | |
1870 | ||
0d373d60 | 1871 | static const struct omap_sham_pdata omap_sham_pdata_omap4 = { |
d20fb18b MG |
1872 | .algs_info = omap_sham_algs_info_omap4, |
1873 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), | |
0d373d60 MG |
1874 | .flags = BIT(FLAGS_AUTO_XOR), |
1875 | .digest_size = SHA256_DIGEST_SIZE, | |
1876 | .copy_hash = omap_sham_copy_hash_omap4, | |
1877 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
1878 | .trigger = omap_sham_trigger_omap4, | |
1879 | .poll_irq = omap_sham_poll_irq_omap4, | |
1880 | .intr_hdlr = omap_sham_irq_omap4, | |
1881 | .idigest_ofs = 0x020, | |
eaef7e3f | 1882 | .odigest_ofs = 0x0, |
0d373d60 MG |
1883 | .din_ofs = 0x080, |
1884 | .digcnt_ofs = 0x040, | |
1885 | .rev_ofs = 0x100, | |
1886 | .mask_ofs = 0x110, | |
1887 | .sysstatus_ofs = 0x114, | |
eaef7e3f LV |
1888 | .mode_ofs = 0x44, |
1889 | .length_ofs = 0x48, | |
0d373d60 MG |
1890 | .major_mask = 0x0700, |
1891 | .major_shift = 8, | |
1892 | .minor_mask = 0x003f, | |
1893 | .minor_shift = 0, | |
1894 | }; | |
1895 | ||
7d7c704d LV |
1896 | static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { |
1897 | { | |
1898 | .algs_list = algs_sha1_md5, | |
1899 | .size = ARRAY_SIZE(algs_sha1_md5), | |
1900 | }, | |
1901 | { | |
1902 | .algs_list = algs_sha224_sha256, | |
1903 | .size = ARRAY_SIZE(algs_sha224_sha256), | |
1904 | }, | |
1905 | { | |
1906 | .algs_list = algs_sha384_sha512, | |
1907 | .size = ARRAY_SIZE(algs_sha384_sha512), | |
1908 | }, | |
1909 | }; | |
1910 | ||
1911 | static const struct omap_sham_pdata omap_sham_pdata_omap5 = { | |
1912 | .algs_info = omap_sham_algs_info_omap5, | |
1913 | .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), | |
1914 | .flags = BIT(FLAGS_AUTO_XOR), | |
1915 | .digest_size = SHA512_DIGEST_SIZE, | |
1916 | .copy_hash = omap_sham_copy_hash_omap4, | |
1917 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
1918 | .trigger = omap_sham_trigger_omap4, | |
1919 | .poll_irq = omap_sham_poll_irq_omap4, | |
1920 | .intr_hdlr = omap_sham_irq_omap4, | |
1921 | .idigest_ofs = 0x240, | |
1922 | .odigest_ofs = 0x200, | |
1923 | .din_ofs = 0x080, | |
1924 | .digcnt_ofs = 0x280, | |
1925 | .rev_ofs = 0x100, | |
1926 | .mask_ofs = 0x110, | |
1927 | .sysstatus_ofs = 0x114, | |
1928 | .mode_ofs = 0x284, | |
1929 | .length_ofs = 0x288, | |
1930 | .major_mask = 0x0700, | |
1931 | .major_shift = 8, | |
1932 | .minor_mask = 0x003f, | |
1933 | .minor_shift = 0, | |
1934 | }; | |
1935 | ||
03feec9c MG |
1936 | static const struct of_device_id omap_sham_of_match[] = { |
1937 | { | |
1938 | .compatible = "ti,omap2-sham", | |
0d373d60 MG |
1939 | .data = &omap_sham_pdata_omap2, |
1940 | }, | |
eddca85b PR |
1941 | { |
1942 | .compatible = "ti,omap3-sham", | |
1943 | .data = &omap_sham_pdata_omap2, | |
1944 | }, | |
0d373d60 MG |
1945 | { |
1946 | .compatible = "ti,omap4-sham", | |
1947 | .data = &omap_sham_pdata_omap4, | |
03feec9c | 1948 | }, |
7d7c704d LV |
1949 | { |
1950 | .compatible = "ti,omap5-sham", | |
1951 | .data = &omap_sham_pdata_omap5, | |
1952 | }, | |
03feec9c MG |
1953 | {}, |
1954 | }; | |
1955 | MODULE_DEVICE_TABLE(of, omap_sham_of_match); | |
1956 | ||
1957 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, | |
1958 | struct device *dev, struct resource *res) | |
8628e7c8 | 1959 | { |
03feec9c | 1960 | struct device_node *node = dev->of_node; |
03feec9c | 1961 | int err = 0; |
8628e7c8 | 1962 | |
7d556931 CL |
1963 | dd->pdata = of_device_get_match_data(dev); |
1964 | if (!dd->pdata) { | |
03feec9c MG |
1965 | dev_err(dev, "no compatible OF match\n"); |
1966 | err = -EINVAL; | |
1967 | goto err; | |
3e133c8b DK |
1968 | } |
1969 | ||
03feec9c MG |
1970 | err = of_address_to_resource(node, 0, res); |
1971 | if (err < 0) { | |
1972 | dev_err(dev, "can't translate OF node address\n"); | |
1973 | err = -EINVAL; | |
1974 | goto err; | |
1975 | } | |
1976 | ||
f7578496 | 1977 | dd->irq = irq_of_parse_and_map(node, 0); |
03feec9c MG |
1978 | if (!dd->irq) { |
1979 | dev_err(dev, "can't translate OF irq value\n"); | |
1980 | err = -EINVAL; | |
1981 | goto err; | |
1982 | } | |
1983 | ||
03feec9c MG |
1984 | err: |
1985 | return err; | |
8628e7c8 | 1986 | } |
03feec9c | 1987 | #else |
c3c3b329 MG |
1988 | static const struct of_device_id omap_sham_of_match[] = { |
1989 | {}, | |
1990 | }; | |
8628e7c8 | 1991 | |
c3c3b329 | 1992 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, |
03feec9c | 1993 | struct device *dev, struct resource *res) |
8628e7c8 | 1994 | { |
03feec9c MG |
1995 | return -EINVAL; |
1996 | } | |
1997 | #endif | |
8628e7c8 | 1998 | |
03feec9c MG |
1999 | static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, |
2000 | struct platform_device *pdev, struct resource *res) | |
2001 | { | |
2002 | struct device *dev = &pdev->dev; | |
2003 | struct resource *r; | |
2004 | int err = 0; | |
8628e7c8 | 2005 | |
03feec9c MG |
2006 | /* Get the base address */ |
2007 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2008 | if (!r) { | |
2009 | dev_err(dev, "no MEM resource info\n"); | |
2010 | err = -ENODEV; | |
2011 | goto err; | |
8628e7c8 | 2012 | } |
03feec9c | 2013 | memcpy(res, r, sizeof(*res)); |
584db6a1 | 2014 | |
03feec9c MG |
2015 | /* Get the IRQ */ |
2016 | dd->irq = platform_get_irq(pdev, 0); | |
2017 | if (dd->irq < 0) { | |
03feec9c MG |
2018 | err = dd->irq; |
2019 | goto err; | |
2020 | } | |
8628e7c8 | 2021 | |
0d373d60 MG |
2022 | /* Only OMAP2/3 can be non-DT */ |
2023 | dd->pdata = &omap_sham_pdata_omap2; | |
2024 | ||
03feec9c MG |
2025 | err: |
2026 | return err; | |
8628e7c8 DK |
2027 | } |
2028 | ||
c9af5995 TK |
2029 | static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, |
2030 | char *buf) | |
2031 | { | |
2032 | struct omap_sham_dev *dd = dev_get_drvdata(dev); | |
2033 | ||
2034 | return sprintf(buf, "%d\n", dd->fallback_sz); | |
2035 | } | |
2036 | ||
2037 | static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, | |
2038 | const char *buf, size_t size) | |
2039 | { | |
2040 | struct omap_sham_dev *dd = dev_get_drvdata(dev); | |
2041 | ssize_t status; | |
2042 | long value; | |
2043 | ||
2044 | status = kstrtol(buf, 0, &value); | |
2045 | if (status) | |
2046 | return status; | |
2047 | ||
2048 | /* HW accelerator only works with buffers > 9 */ | |
2049 | if (value < 9) { | |
2050 | dev_err(dev, "minimum fallback size 9\n"); | |
2051 | return -EINVAL; | |
2052 | } | |
2053 | ||
2054 | dd->fallback_sz = value; | |
2055 | ||
2056 | return size; | |
2057 | } | |
2058 | ||
62f7c708 TK |
2059 | static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, |
2060 | char *buf) | |
2061 | { | |
2062 | struct omap_sham_dev *dd = dev_get_drvdata(dev); | |
2063 | ||
2064 | return sprintf(buf, "%d\n", dd->queue.max_qlen); | |
2065 | } | |
2066 | ||
2067 | static ssize_t queue_len_store(struct device *dev, | |
2068 | struct device_attribute *attr, const char *buf, | |
2069 | size_t size) | |
2070 | { | |
2071 | struct omap_sham_dev *dd = dev_get_drvdata(dev); | |
2072 | ssize_t status; | |
2073 | long value; | |
2074 | unsigned long flags; | |
2075 | ||
2076 | status = kstrtol(buf, 0, &value); | |
2077 | if (status) | |
2078 | return status; | |
2079 | ||
2080 | if (value < 1) | |
2081 | return -EINVAL; | |
2082 | ||
2083 | /* | |
2084 | * Changing the queue size in fly is safe, if size becomes smaller | |
2085 | * than current size, it will just not accept new entries until | |
2086 | * it has shrank enough. | |
2087 | */ | |
2088 | spin_lock_irqsave(&dd->lock, flags); | |
2089 | dd->queue.max_qlen = value; | |
2090 | spin_unlock_irqrestore(&dd->lock, flags); | |
2091 | ||
2092 | return size; | |
2093 | } | |
2094 | ||
2095 | static DEVICE_ATTR_RW(queue_len); | |
c9af5995 TK |
2096 | static DEVICE_ATTR_RW(fallback); |
2097 | ||
2098 | static struct attribute *omap_sham_attrs[] = { | |
62f7c708 | 2099 | &dev_attr_queue_len.attr, |
c9af5995 TK |
2100 | &dev_attr_fallback.attr, |
2101 | NULL, | |
2102 | }; | |
2103 | ||
2104 | static struct attribute_group omap_sham_attr_group = { | |
2105 | .attrs = omap_sham_attrs, | |
2106 | }; | |
2107 | ||
49cfe4db | 2108 | static int omap_sham_probe(struct platform_device *pdev) |
8628e7c8 DK |
2109 | { |
2110 | struct omap_sham_dev *dd; | |
2111 | struct device *dev = &pdev->dev; | |
03feec9c | 2112 | struct resource res; |
dfd061d5 | 2113 | dma_cap_mask_t mask; |
8628e7c8 | 2114 | int err, i, j; |
0d373d60 | 2115 | u32 rev; |
8628e7c8 | 2116 | |
7a7e4b73 | 2117 | dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); |
8628e7c8 DK |
2118 | if (dd == NULL) { |
2119 | dev_err(dev, "unable to alloc data struct.\n"); | |
2120 | err = -ENOMEM; | |
2121 | goto data_err; | |
2122 | } | |
2123 | dd->dev = dev; | |
2124 | platform_set_drvdata(pdev, dd); | |
2125 | ||
2126 | INIT_LIST_HEAD(&dd->list); | |
2127 | spin_lock_init(&dd->lock); | |
2128 | tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); | |
8628e7c8 DK |
2129 | crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); |
2130 | ||
03feec9c MG |
2131 | err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : |
2132 | omap_sham_get_res_pdev(dd, pdev, &res); | |
2133 | if (err) | |
7a7e4b73 | 2134 | goto data_err; |
8628e7c8 | 2135 | |
30862281 LN |
2136 | dd->io_base = devm_ioremap_resource(dev, &res); |
2137 | if (IS_ERR(dd->io_base)) { | |
2138 | err = PTR_ERR(dd->io_base); | |
7a7e4b73 | 2139 | goto data_err; |
8628e7c8 | 2140 | } |
03feec9c | 2141 | dd->phys_base = res.start; |
8628e7c8 | 2142 | |
0de9c387 LV |
2143 | err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, |
2144 | IRQF_TRIGGER_NONE, dev_name(dev), dd); | |
8628e7c8 | 2145 | if (err) { |
0de9c387 LV |
2146 | dev_err(dev, "unable to request irq %d, err = %d\n", |
2147 | dd->irq, err); | |
7a7e4b73 | 2148 | goto data_err; |
8628e7c8 DK |
2149 | } |
2150 | ||
dfd061d5 MG |
2151 | dma_cap_zero(mask); |
2152 | dma_cap_set(DMA_SLAVE, mask); | |
8628e7c8 | 2153 | |
dbe24620 PU |
2154 | dd->dma_lch = dma_request_chan(dev, "rx"); |
2155 | if (IS_ERR(dd->dma_lch)) { | |
2156 | err = PTR_ERR(dd->dma_lch); | |
2157 | if (err == -EPROBE_DEFER) | |
2158 | goto data_err; | |
2159 | ||
b8411ccd LV |
2160 | dd->polling_mode = 1; |
2161 | dev_dbg(dev, "using polling mode instead of dma\n"); | |
8628e7c8 DK |
2162 | } |
2163 | ||
0d373d60 | 2164 | dd->flags |= dd->pdata->flags; |
8628e7c8 | 2165 | |
e93f767b TK |
2166 | pm_runtime_use_autosuspend(dev); |
2167 | pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); | |
2168 | ||
c9af5995 TK |
2169 | dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD; |
2170 | ||
b359f034 | 2171 | pm_runtime_enable(dev); |
b0a3d898 | 2172 | pm_runtime_irq_safe(dev); |
604c3103 PR |
2173 | |
2174 | err = pm_runtime_get_sync(dev); | |
2175 | if (err < 0) { | |
2176 | dev_err(dev, "failed to get sync: %d\n", err); | |
2177 | goto err_pm; | |
2178 | } | |
2179 | ||
0d373d60 MG |
2180 | rev = omap_sham_read(dd, SHA_REG_REV(dd)); |
2181 | pm_runtime_put_sync(&pdev->dev); | |
8628e7c8 | 2182 | |
8628e7c8 | 2183 | dev_info(dev, "hw accel on OMAP rev %u.%u\n", |
0d373d60 MG |
2184 | (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, |
2185 | (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); | |
8628e7c8 DK |
2186 | |
2187 | spin_lock(&sham.lock); | |
2188 | list_add_tail(&dd->list, &sham.dev_list); | |
2189 | spin_unlock(&sham.lock); | |
2190 | ||
d20fb18b MG |
2191 | for (i = 0; i < dd->pdata->algs_info_size; i++) { |
2192 | for (j = 0; j < dd->pdata->algs_info[i].size; j++) { | |
99a7ffff TK |
2193 | struct ahash_alg *alg; |
2194 | ||
2195 | alg = &dd->pdata->algs_info[i].algs_list[j]; | |
2196 | alg->export = omap_sham_export; | |
2197 | alg->import = omap_sham_import; | |
a84d351f TK |
2198 | alg->halg.statesize = sizeof(struct omap_sham_reqctx) + |
2199 | BUFLEN; | |
99a7ffff | 2200 | err = crypto_register_ahash(alg); |
d20fb18b MG |
2201 | if (err) |
2202 | goto err_algs; | |
2203 | ||
2204 | dd->pdata->algs_info[i].registered++; | |
2205 | } | |
8628e7c8 DK |
2206 | } |
2207 | ||
c9af5995 TK |
2208 | err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group); |
2209 | if (err) { | |
2210 | dev_err(dev, "could not create sysfs device attrs\n"); | |
2211 | goto err_algs; | |
2212 | } | |
2213 | ||
8628e7c8 DK |
2214 | return 0; |
2215 | ||
2216 | err_algs: | |
d20fb18b MG |
2217 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
2218 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
2219 | crypto_unregister_ahash( | |
2220 | &dd->pdata->algs_info[i].algs_list[j]); | |
604c3103 | 2221 | err_pm: |
b359f034 | 2222 | pm_runtime_disable(dev); |
d462e322 | 2223 | if (!dd->polling_mode) |
f13ab86a | 2224 | dma_release_channel(dd->dma_lch); |
8628e7c8 DK |
2225 | data_err: |
2226 | dev_err(dev, "initialization failed.\n"); | |
2227 | ||
2228 | return err; | |
2229 | } | |
2230 | ||
49cfe4db | 2231 | static int omap_sham_remove(struct platform_device *pdev) |
8628e7c8 | 2232 | { |
0588d850 | 2233 | struct omap_sham_dev *dd; |
d20fb18b | 2234 | int i, j; |
8628e7c8 DK |
2235 | |
2236 | dd = platform_get_drvdata(pdev); | |
2237 | if (!dd) | |
2238 | return -ENODEV; | |
2239 | spin_lock(&sham.lock); | |
2240 | list_del(&dd->list); | |
2241 | spin_unlock(&sham.lock); | |
d20fb18b MG |
2242 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
2243 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
2244 | crypto_unregister_ahash( | |
2245 | &dd->pdata->algs_info[i].algs_list[j]); | |
8628e7c8 | 2246 | tasklet_kill(&dd->done_task); |
b359f034 | 2247 | pm_runtime_disable(&pdev->dev); |
f13ab86a | 2248 | |
dbe24620 | 2249 | if (!dd->polling_mode) |
f13ab86a | 2250 | dma_release_channel(dd->dma_lch); |
8628e7c8 | 2251 | |
b82fc91e TK |
2252 | sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group); |
2253 | ||
8628e7c8 DK |
2254 | return 0; |
2255 | } | |
2256 | ||
3b3f4400 MG |
2257 | #ifdef CONFIG_PM_SLEEP |
2258 | static int omap_sham_suspend(struct device *dev) | |
2259 | { | |
2260 | pm_runtime_put_sync(dev); | |
2261 | return 0; | |
2262 | } | |
2263 | ||
2264 | static int omap_sham_resume(struct device *dev) | |
2265 | { | |
604c3103 PR |
2266 | int err = pm_runtime_get_sync(dev); |
2267 | if (err < 0) { | |
2268 | dev_err(dev, "failed to get sync: %d\n", err); | |
2269 | return err; | |
2270 | } | |
3b3f4400 MG |
2271 | return 0; |
2272 | } | |
2273 | #endif | |
2274 | ||
ae12fe28 | 2275 | static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume); |
3b3f4400 | 2276 | |
8628e7c8 DK |
2277 | static struct platform_driver omap_sham_driver = { |
2278 | .probe = omap_sham_probe, | |
2279 | .remove = omap_sham_remove, | |
2280 | .driver = { | |
2281 | .name = "omap-sham", | |
3b3f4400 | 2282 | .pm = &omap_sham_pm_ops, |
03feec9c | 2283 | .of_match_table = omap_sham_of_match, |
8628e7c8 DK |
2284 | }, |
2285 | }; | |
2286 | ||
02613702 | 2287 | module_platform_driver(omap_sham_driver); |
8628e7c8 DK |
2288 | |
2289 | MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); | |
2290 | MODULE_LICENSE("GPL v2"); | |
2291 | MODULE_AUTHOR("Dmitry Kasatkin"); | |
718249d7 | 2292 | MODULE_ALIAS("platform:omap-sham"); |