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libnvdimm/altmap: Track namespace boundaries in altmap
[linux-2.6-block.git] / drivers / crypto / omap-des.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
e91aa9d5
JF		 2/*
3 * Support for OMAP DES and Triple DES HW acceleration.
4 *
5 * Copyright (c) 2013 Texas Instruments Incorporated
6 * Author: Joel Fernandes <joelf@ti.com>
e91aa9d5
JF		 7 */
8
9#define pr_fmt(fmt) "%s: " fmt, __func__
10
11#ifdef DEBUG
12#define prn(num) printk(#num "=%d\n", num)
13#define prx(num) printk(#num "=%x\n", num)
14#else
15#define prn(num) do { } while (0)
16#define prx(num) do { } while (0)
17#endif
18
19#include <linux/err.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/kernel.h>
24#include <linux/platform_device.h>
25#include <linux/scatterlist.h>
26#include <linux/dma-mapping.h>
27#include <linux/dmaengine.h>
e91aa9d5
JF		 28#include <linux/pm_runtime.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/of_address.h>
32#include <linux/io.h>
33#include <linux/crypto.h>
34#include <linux/interrupt.h>
35#include <crypto/scatterwalk.h>
36#include <crypto/des.h>
f1b77aac 37#include <crypto/algapi.h>
2589ad84 38#include <crypto/engine.h>
e91aa9d5 39
9765e768
TK		 40#include "omap-crypto.h"
41
e91aa9d5
JF		 42#define DST_MAXBURST 2
43
44#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
45
46#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
47
48#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
49 ((x ^ 0x01) * 0x04))
50
51#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
52
53#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
54#define DES_REG_CTRL_CBC BIT(4)
55#define DES_REG_CTRL_TDES BIT(3)
56#define DES_REG_CTRL_DIRECTION BIT(2)
57#define DES_REG_CTRL_INPUT_READY BIT(1)
58#define DES_REG_CTRL_OUTPUT_READY BIT(0)
59
60#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
61
62#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
63
64#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
65
66#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
67
68#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
69#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
70#define DES_REG_IRQ_DATA_IN BIT(1)
71#define DES_REG_IRQ_DATA_OUT BIT(2)
72
73#define FLAGS_MODE_MASK 0x000f
74#define FLAGS_ENCRYPT BIT(0)
75#define FLAGS_CBC BIT(1)
76#define FLAGS_INIT BIT(4)
77#define FLAGS_BUSY BIT(6)
78
418f2a8c
TK		 79#define DEFAULT_AUTOSUSPEND_DELAY 1000
80
9765e768
TK		 81#define FLAGS_IN_DATA_ST_SHIFT 8
82#define FLAGS_OUT_DATA_ST_SHIFT 10
83
e91aa9d5 84struct omap_des_ctx {
c21c8b89 85 struct crypto_engine_ctx enginectx;
e91aa9d5
JF		 86 struct omap_des_dev *dd;
87
88 int keylen;
89 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
90 unsigned long flags;
91};
92
93struct omap_des_reqctx {
94 unsigned long mode;
95};
96
97#define OMAP_DES_QUEUE_LENGTH 1
98#define OMAP_DES_CACHE_SIZE 0
99
100struct omap_des_algs_info {
101 struct crypto_alg *algs_list;
102 unsigned int size;
103 unsigned int registered;
104};
105
106struct omap_des_pdata {
107 struct omap_des_algs_info *algs_info;
108 unsigned int algs_info_size;
109
110 void (*trigger)(struct omap_des_dev *dd, int length);
111
112 u32 key_ofs;
113 u32 iv_ofs;
114 u32 ctrl_ofs;
115 u32 data_ofs;
116 u32 rev_ofs;
117 u32 mask_ofs;
118 u32 irq_enable_ofs;
119 u32 irq_status_ofs;
120
121 u32 dma_enable_in;
122 u32 dma_enable_out;
123 u32 dma_start;
124
125 u32 major_mask;
126 u32 major_shift;
127 u32 minor_mask;
128 u32 minor_shift;
129};
130
131struct omap_des_dev {
132 struct list_head list;
133 unsigned long phys_base;
134 void __iomem *io_base;
135 struct omap_des_ctx *ctx;
136 struct device *dev;
137 unsigned long flags;
138 int err;
139
e91aa9d5 140 struct tasklet_struct done_task;
e91aa9d5
JF		 141
142 struct ablkcipher_request *req;
f1b77aac 143 struct crypto_engine *engine;
e91aa9d5
JF		 144 /*
145 * total is used by PIO mode for book keeping so introduce
146 * variable total_save as need it to calc page_order
147 */
148 size_t total;
149 size_t total_save;
150
151 struct scatterlist *in_sg;
152 struct scatterlist *out_sg;
153
154 /* Buffers for copying for unaligned cases */
155 struct scatterlist in_sgl;
156 struct scatterlist out_sgl;
157 struct scatterlist *orig_out;
e91aa9d5
JF		 158
159 struct scatter_walk in_walk;
160 struct scatter_walk out_walk;
e91aa9d5 161 struct dma_chan *dma_lch_in;
e91aa9d5
JF		 162 struct dma_chan *dma_lch_out;
163 int in_sg_len;
164 int out_sg_len;
165 int pio_only;
166 const struct omap_des_pdata *pdata;
167};
168
169/* keep registered devices data here */
170static LIST_HEAD(dev_list);
171static DEFINE_SPINLOCK(list_lock);
172
173#ifdef DEBUG
174#define omap_des_read(dd, offset) \
175 ({ \
176 int _read_ret; \
177 _read_ret = __raw_readl(dd->io_base + offset); \
178 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
179 offset, _read_ret); \
180 _read_ret; \
181 })
182#else
183static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
184{
185 return __raw_readl(dd->io_base + offset);
186}
187#endif
188
189#ifdef DEBUG
190#define omap_des_write(dd, offset, value) \
191 do { \
192 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
193 offset, value); \
194 __raw_writel(value, dd->io_base + offset); \
195 } while (0)
196#else
197static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
198 u32 value)
199{
200 __raw_writel(value, dd->io_base + offset);
201}
202#endif
203
204static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
205 u32 value, u32 mask)
206{
207 u32 val;
208
209 val = omap_des_read(dd, offset);
210 val &= ~mask;
211 val |= value;
212 omap_des_write(dd, offset, val);
213}
214
215static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
216 u32 *value, int count)
217{
218 for (; count--; value++, offset += 4)
219 omap_des_write(dd, offset, *value);
220}
221
222static int omap_des_hw_init(struct omap_des_dev *dd)
223{
f51f593b
NM		 224 int err;
225
e91aa9d5
JF		 226 /*
227 * clocks are enabled when request starts and disabled when finished.
228 * It may be long delays between requests.
229 * Device might go to off mode to save power.
230 */
f51f593b
NM		 231 err = pm_runtime_get_sync(dd->dev);
232 if (err < 0) {
233 pm_runtime_put_noidle(dd->dev);
234 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
235 return err;
236 }
e91aa9d5
JF		 237
238 if (!(dd->flags & FLAGS_INIT)) {
239 dd->flags |= FLAGS_INIT;
240 dd->err = 0;
241 }
242
243 return 0;
244}
245
246static int omap_des_write_ctrl(struct omap_des_dev *dd)
247{
248 unsigned int key32;
249 int i, err;
250 u32 val = 0, mask = 0;
251
252 err = omap_des_hw_init(dd);
253 if (err)
254 return err;
255
256 key32 = dd->ctx->keylen / sizeof(u32);
257
258 /* it seems a key should always be set even if it has not changed */
259 for (i = 0; i < key32; i++) {
260 omap_des_write(dd, DES_REG_KEY(dd, i),
261 __le32_to_cpu(dd->ctx->key[i]));
262 }
263
264 if ((dd->flags & FLAGS_CBC) && dd->req->info)
265 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
266
267 if (dd->flags & FLAGS_CBC)
268 val |= DES_REG_CTRL_CBC;
269 if (dd->flags & FLAGS_ENCRYPT)
270 val |= DES_REG_CTRL_DIRECTION;
271 if (key32 == 6)
272 val |= DES_REG_CTRL_TDES;
273
274 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
275
276 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
277
278 return 0;
279}
280
281static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
282{
283 u32 mask, val;
284
285 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
286
287 val = dd->pdata->dma_start;
288
289 if (dd->dma_lch_out != NULL)
290 val |= dd->pdata->dma_enable_out;
291 if (dd->dma_lch_in != NULL)
292 val |= dd->pdata->dma_enable_in;
293
294 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
295 dd->pdata->dma_start;
296
297 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
298}
299
300static void omap_des_dma_stop(struct omap_des_dev *dd)
301{
302 u32 mask;
303
304 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
305 dd->pdata->dma_start;
306
307 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
308}
309
310static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
311{
312 struct omap_des_dev *dd = NULL, *tmp;
313
314 spin_lock_bh(&list_lock);
315 if (!ctx->dd) {
316 list_for_each_entry(tmp, &dev_list, list) {
317 /* FIXME: take fist available des core */
318 dd = tmp;
319 break;
320 }
321 ctx->dd = dd;
322 } else {
323 /* already found before */
324 dd = ctx->dd;
325 }
326 spin_unlock_bh(&list_lock);
327
328 return dd;
329}
330
331static void omap_des_dma_out_callback(void *data)
332{
333 struct omap_des_dev *dd = data;
334
335 /* dma_lch_out - completed */
336 tasklet_schedule(&dd->done_task);
337}
338
339static int omap_des_dma_init(struct omap_des_dev *dd)
340{
2f6f0680 341 int err;
e91aa9d5
JF		 342
343 dd->dma_lch_out = NULL;
344 dd->dma_lch_in = NULL;
345
2f6f0680
PU		 346 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
347 if (IS_ERR(dd->dma_lch_in)) {
e91aa9d5 348 dev_err(dd->dev, "Unable to request in DMA channel\n");
2f6f0680 349 return PTR_ERR(dd->dma_lch_in);
e91aa9d5
JF		 350 }
351
2f6f0680
PU		 352 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
353 if (IS_ERR(dd->dma_lch_out)) {
e91aa9d5 354 dev_err(dd->dev, "Unable to request out DMA channel\n");
2f6f0680 355 err = PTR_ERR(dd->dma_lch_out);
e91aa9d5
JF		 356 goto err_dma_out;
357 }
358
359 return 0;
360
361err_dma_out:
362 dma_release_channel(dd->dma_lch_in);
2f6f0680 363
e91aa9d5
JF		 364 return err;
365}
366
367static void omap_des_dma_cleanup(struct omap_des_dev *dd)
368{
2f6f0680
PU		 369 if (dd->pio_only)
370 return;
371
e91aa9d5
JF		 372 dma_release_channel(dd->dma_lch_out);
373 dma_release_channel(dd->dma_lch_in);
374}
375
e91aa9d5
JF		 376static int omap_des_crypt_dma(struct crypto_tfm *tfm,
377 struct scatterlist *in_sg, struct scatterlist *out_sg,
378 int in_sg_len, int out_sg_len)
379{
380 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
381 struct omap_des_dev *dd = ctx->dd;
382 struct dma_async_tx_descriptor *tx_in, *tx_out;
383 struct dma_slave_config cfg;
384 int ret;
385
386 if (dd->pio_only) {
387 scatterwalk_start(&dd->in_walk, dd->in_sg);
388 scatterwalk_start(&dd->out_walk, dd->out_sg);
389
390 /* Enable DATAIN interrupt and let it take
391 care of the rest */
392 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
393 return 0;
394 }
395
396 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
397
398 memset(&cfg, 0, sizeof(cfg));
399
400 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
401 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
402 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
403 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
404 cfg.src_maxburst = DST_MAXBURST;
405 cfg.dst_maxburst = DST_MAXBURST;
406
407 /* IN */
408 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
409 if (ret) {
410 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
411 ret);
412 return ret;
413 }
414
415 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
416 DMA_MEM_TO_DEV,
417 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
418 if (!tx_in) {
419 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
420 return -EINVAL;
421 }
422
423 /* No callback necessary */
424 tx_in->callback_param = dd;
425
426 /* OUT */
427 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
428 if (ret) {
429 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
430 ret);
431 return ret;
432 }
433
434 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
435 DMA_DEV_TO_MEM,
436 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
437 if (!tx_out) {
438 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
439 return -EINVAL;
440 }
441
442 tx_out->callback = omap_des_dma_out_callback;
443 tx_out->callback_param = dd;
444
445 dmaengine_submit(tx_in);
446 dmaengine_submit(tx_out);
447
448 dma_async_issue_pending(dd->dma_lch_in);
449 dma_async_issue_pending(dd->dma_lch_out);
450
451 /* start DMA */
452 dd->pdata->trigger(dd, dd->total);
453
454 return 0;
455}
456
457static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
458{
459 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
460 crypto_ablkcipher_reqtfm(dd->req));
461 int err;
462
463 pr_debug("total: %d\n", dd->total);
464
465 if (!dd->pio_only) {
466 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
467 DMA_TO_DEVICE);
468 if (!err) {
469 dev_err(dd->dev, "dma_map_sg() error\n");
470 return -EINVAL;
471 }
472
473 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
474 DMA_FROM_DEVICE);
475 if (!err) {
476 dev_err(dd->dev, "dma_map_sg() error\n");
477 return -EINVAL;
478 }
479 }
480
481 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
482 dd->out_sg_len);
483 if (err && !dd->pio_only) {
484 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
485 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
486 DMA_FROM_DEVICE);
487 }
488
489 return err;
490}
491
492static void omap_des_finish_req(struct omap_des_dev *dd, int err)
493{
494 struct ablkcipher_request *req = dd->req;
495
496 pr_debug("err: %d\n", err);
497
c21c8b89 498 crypto_finalize_ablkcipher_request(dd->engine, req, err);
418f2a8c
TK		 499
500 pm_runtime_mark_last_busy(dd->dev);
501 pm_runtime_put_autosuspend(dd->dev);
e91aa9d5
JF		 502}
503
504static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
505{
e91aa9d5
JF		 506 pr_debug("total: %d\n", dd->total);
507
508 omap_des_dma_stop(dd);
509
510 dmaengine_terminate_all(dd->dma_lch_in);
511 dmaengine_terminate_all(dd->dma_lch_out);
512
16f080aa 513 return 0;
e91aa9d5
JF		 514}
515
e91aa9d5 516static int omap_des_handle_queue(struct omap_des_dev *dd,
f1b77aac 517 struct ablkcipher_request *req)
e91aa9d5 518{
e91aa9d5 519 if (req)
c21c8b89 520 return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
e91aa9d5 521
f1b77aac
BW		 522 return 0;
523}
e91aa9d5 524
f1b77aac 525static int omap_des_prepare_req(struct crypto_engine *engine,
c21c8b89 526 void *areq)
f1b77aac 527{
c21c8b89 528 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
f1b77aac
BW		 529 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
530 crypto_ablkcipher_reqtfm(req));
531 struct omap_des_dev *dd = omap_des_find_dev(ctx);
532 struct omap_des_reqctx *rctx;
9765e768
TK		 533 int ret;
534 u16 flags;
e91aa9d5 535
f1b77aac
BW		 536 if (!dd)
537 return -ENODEV;
e91aa9d5
JF		 538
539 /* assign new request to device */
540 dd->req = req;
541 dd->total = req->nbytes;
542 dd->total_save = req->nbytes;
543 dd->in_sg = req->src;
544 dd->out_sg = req->dst;
9765e768
TK		 545 dd->orig_out = req->dst;
546
547 flags = OMAP_CRYPTO_COPY_DATA;
548 if (req->src == req->dst)
549 flags |= OMAP_CRYPTO_FORCE_COPY;
550
551 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
552 &dd->in_sgl, flags,
553 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
554 if (ret)
555 return ret;
556
557 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
558 &dd->out_sgl, 0,
559 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
560 if (ret)
561 return ret;
e91aa9d5 562
7c001a86
HX		 563 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
564 if (dd->in_sg_len < 0)
565 return dd->in_sg_len;
566
567 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
568 if (dd->out_sg_len < 0)
569 return dd->out_sg_len;
570
e91aa9d5
JF		 571 rctx = ablkcipher_request_ctx(req);
572 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
573 rctx->mode &= FLAGS_MODE_MASK;
574 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
575
576 dd->ctx = ctx;
577 ctx->dd = dd;
578
f1b77aac
BW		 579 return omap_des_write_ctrl(dd);
580}
e91aa9d5 581
f1b77aac 582static int omap_des_crypt_req(struct crypto_engine *engine,
c21c8b89 583 void *areq)
f1b77aac 584{
c21c8b89 585 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
f1b77aac
BW		 586 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
587 crypto_ablkcipher_reqtfm(req));
588 struct omap_des_dev *dd = omap_des_find_dev(ctx);
589
590 if (!dd)
591 return -ENODEV;
592
593 return omap_des_crypt_dma_start(dd);
e91aa9d5
JF		 594}
595
596static void omap_des_done_task(unsigned long data)
597{
598 struct omap_des_dev *dd = (struct omap_des_dev *)data;
e91aa9d5
JF		 599
600 pr_debug("enter done_task\n");
601
602 if (!dd->pio_only) {
603 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
604 DMA_FROM_DEVICE);
605 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
606 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
607 DMA_FROM_DEVICE);
608 omap_des_crypt_dma_stop(dd);
609 }
610
9765e768
TK		 611 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
612 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
e91aa9d5 613
9765e768
TK		 614 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
615 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
e91aa9d5
JF		 616
617 omap_des_finish_req(dd, 0);
e91aa9d5
JF		 618
619 pr_debug("exit\n");
620}
621
e91aa9d5
JF		 622static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
623{
624 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
625 crypto_ablkcipher_reqtfm(req));
626 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
627 struct omap_des_dev *dd;
628
629 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
630 !!(mode & FLAGS_ENCRYPT),
631 !!(mode & FLAGS_CBC));
632
633 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
634 pr_err("request size is not exact amount of DES blocks\n");
635 return -EINVAL;
636 }
637
638 dd = omap_des_find_dev(ctx);
639 if (!dd)
640 return -ENODEV;
641
642 rctx->mode = mode;
643
644 return omap_des_handle_queue(dd, req);
645}
646
647/* ********************** ALG API ************************************ */
648
a636fdce 649static int omap_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
e91aa9d5
JF		 650 unsigned int keylen)
651{
a636fdce
TK		 652 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher);
653 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
e91aa9d5 654
e91aa9d5
JF		 655 pr_debug("enter, keylen: %d\n", keylen);
656
a636fdce 657 /* Do we need to test against weak key? */
231baecd 658 if (tfm->crt_flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
a636fdce
TK		 659 u32 tmp[DES_EXPKEY_WORDS];
660 int ret = des_ekey(tmp, key);
661
662 if (!ret) {
663 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
664 return -EINVAL;
665 }
666 }
667
e91aa9d5
JF		 668 memcpy(ctx->key, key, keylen);
669 ctx->keylen = keylen;
670
671 return 0;
672}
673
7f88c4d7
HX		 674static int omap_des3_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
675 unsigned int keylen)
676{
677 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher);
678 u32 flags;
679 int err;
680
681 pr_debug("enter, keylen: %d\n", keylen);
682
683 flags = crypto_ablkcipher_get_flags(cipher);
684 err = __des3_verify_key(&flags, key);
685 if (unlikely(err)) {
686 crypto_ablkcipher_set_flags(cipher, flags);
687 return err;
688 }
689
690 memcpy(ctx->key, key, keylen);
691 ctx->keylen = keylen;
692
693 return 0;
694}
695
e91aa9d5
JF		 696static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
697{
698 return omap_des_crypt(req, FLAGS_ENCRYPT);
699}
700
701static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
702{
703 return omap_des_crypt(req, 0);
704}
705
706static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
707{
708 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
709}
710
711static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
712{
713 return omap_des_crypt(req, FLAGS_CBC);
714}
715
c21c8b89
CL		 716static int omap_des_prepare_req(struct crypto_engine *engine,
717 void *areq);
718static int omap_des_crypt_req(struct crypto_engine *engine,
719 void *areq);
720
e91aa9d5
JF		 721static int omap_des_cra_init(struct crypto_tfm *tfm)
722{
c21c8b89
CL		 723 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
724
e91aa9d5
JF		 725 pr_debug("enter\n");
726
727 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
728
c21c8b89
CL		 729 ctx->enginectx.op.prepare_request = omap_des_prepare_req;
730 ctx->enginectx.op.unprepare_request = NULL;
731 ctx->enginectx.op.do_one_request = omap_des_crypt_req;
732
e91aa9d5
JF		 733 return 0;
734}
735
736static void omap_des_cra_exit(struct crypto_tfm *tfm)
737{
738 pr_debug("enter\n");
739}
740
741/* ********************** ALGS ************************************ */
742
743static struct crypto_alg algs_ecb_cbc[] = {
744{
745 .cra_name = "ecb(des)",
746 .cra_driver_name = "ecb-des-omap",
747 .cra_priority = 100,
748 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
749 CRYPTO_ALG_KERN_DRIVER_ONLY |
750 CRYPTO_ALG_ASYNC,
751 .cra_blocksize = DES_BLOCK_SIZE,
752 .cra_ctxsize = sizeof(struct omap_des_ctx),
753 .cra_alignmask = 0,
754 .cra_type = &crypto_ablkcipher_type,
755 .cra_module = THIS_MODULE,
756 .cra_init = omap_des_cra_init,
757 .cra_exit = omap_des_cra_exit,
758 .cra_u.ablkcipher = {
759 .min_keysize = DES_KEY_SIZE,
760 .max_keysize = DES_KEY_SIZE,
761 .setkey = omap_des_setkey,
762 .encrypt = omap_des_ecb_encrypt,
763 .decrypt = omap_des_ecb_decrypt,
764 }
765},
766{
767 .cra_name = "cbc(des)",
768 .cra_driver_name = "cbc-des-omap",
769 .cra_priority = 100,
770 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
771 CRYPTO_ALG_KERN_DRIVER_ONLY |
772 CRYPTO_ALG_ASYNC,
773 .cra_blocksize = DES_BLOCK_SIZE,
774 .cra_ctxsize = sizeof(struct omap_des_ctx),
775 .cra_alignmask = 0,
776 .cra_type = &crypto_ablkcipher_type,
777 .cra_module = THIS_MODULE,
778 .cra_init = omap_des_cra_init,
779 .cra_exit = omap_des_cra_exit,
780 .cra_u.ablkcipher = {
781 .min_keysize = DES_KEY_SIZE,
782 .max_keysize = DES_KEY_SIZE,
783 .ivsize = DES_BLOCK_SIZE,
784 .setkey = omap_des_setkey,
785 .encrypt = omap_des_cbc_encrypt,
786 .decrypt = omap_des_cbc_decrypt,
787 }
788},
789{
790 .cra_name = "ecb(des3_ede)",
791 .cra_driver_name = "ecb-des3-omap",
792 .cra_priority = 100,
793 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
794 CRYPTO_ALG_KERN_DRIVER_ONLY |
795 CRYPTO_ALG_ASYNC,
796 .cra_blocksize = DES_BLOCK_SIZE,
797 .cra_ctxsize = sizeof(struct omap_des_ctx),
798 .cra_alignmask = 0,
799 .cra_type = &crypto_ablkcipher_type,
800 .cra_module = THIS_MODULE,
801 .cra_init = omap_des_cra_init,
802 .cra_exit = omap_des_cra_exit,
803 .cra_u.ablkcipher = {
804 .min_keysize = 3*DES_KEY_SIZE,
805 .max_keysize = 3*DES_KEY_SIZE,
7f88c4d7 806 .setkey = omap_des3_setkey,
e91aa9d5
JF		 807 .encrypt = omap_des_ecb_encrypt,
808 .decrypt = omap_des_ecb_decrypt,
809 }
810},
811{
812 .cra_name = "cbc(des3_ede)",
813 .cra_driver_name = "cbc-des3-omap",
814 .cra_priority = 100,
815 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
816 CRYPTO_ALG_KERN_DRIVER_ONLY |
817 CRYPTO_ALG_ASYNC,
818 .cra_blocksize = DES_BLOCK_SIZE,
819 .cra_ctxsize = sizeof(struct omap_des_ctx),
820 .cra_alignmask = 0,
821 .cra_type = &crypto_ablkcipher_type,
822 .cra_module = THIS_MODULE,
823 .cra_init = omap_des_cra_init,
824 .cra_exit = omap_des_cra_exit,
825 .cra_u.ablkcipher = {
826 .min_keysize = 3*DES_KEY_SIZE,
827 .max_keysize = 3*DES_KEY_SIZE,
828 .ivsize = DES_BLOCK_SIZE,
7f88c4d7 829 .setkey = omap_des3_setkey,
e91aa9d5
JF		 830 .encrypt = omap_des_cbc_encrypt,
831 .decrypt = omap_des_cbc_decrypt,
832 }
833}
834};
835
836static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
837 {
838 .algs_list = algs_ecb_cbc,
839 .size = ARRAY_SIZE(algs_ecb_cbc),
840 },
841};
842
843#ifdef CONFIG_OF
844static const struct omap_des_pdata omap_des_pdata_omap4 = {
845 .algs_info = omap_des_algs_info_ecb_cbc,
846 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
847 .trigger = omap_des_dma_trigger_omap4,
848 .key_ofs = 0x14,
849 .iv_ofs = 0x18,
850 .ctrl_ofs = 0x20,
851 .data_ofs = 0x28,
852 .rev_ofs = 0x30,
853 .mask_ofs = 0x34,
854 .irq_status_ofs = 0x3c,
855 .irq_enable_ofs = 0x40,
856 .dma_enable_in = BIT(5),
857 .dma_enable_out = BIT(6),
858 .major_mask = 0x0700,
859 .major_shift = 8,
860 .minor_mask = 0x003f,
861 .minor_shift = 0,
862};
863
864static irqreturn_t omap_des_irq(int irq, void *dev_id)
865{
866 struct omap_des_dev *dd = dev_id;
867 u32 status, i;
868 u32 *src, *dst;
869
870 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
871 if (status & DES_REG_IRQ_DATA_IN) {
872 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
873
874 BUG_ON(!dd->in_sg);
875
876 BUG_ON(_calc_walked(in) > dd->in_sg->length);
877
878 src = sg_virt(dd->in_sg) + _calc_walked(in);
879
880 for (i = 0; i < DES_BLOCK_WORDS; i++) {
881 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
882
883 scatterwalk_advance(&dd->in_walk, 4);
884 if (dd->in_sg->length == _calc_walked(in)) {
5be4d4c9 885 dd->in_sg = sg_next(dd->in_sg);
e91aa9d5
JF		 886 if (dd->in_sg) {
887 scatterwalk_start(&dd->in_walk,
888 dd->in_sg);
889 src = sg_virt(dd->in_sg) +
890 _calc_walked(in);
891 }
892 } else {
893 src++;
894 }
895 }
896
897 /* Clear IRQ status */
898 status &= ~DES_REG_IRQ_DATA_IN;
899 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
900
901 /* Enable DATA_OUT interrupt */
902 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
903
904 } else if (status & DES_REG_IRQ_DATA_OUT) {
905 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
906
907 BUG_ON(!dd->out_sg);
908
909 BUG_ON(_calc_walked(out) > dd->out_sg->length);
910
911 dst = sg_virt(dd->out_sg) + _calc_walked(out);
912
913 for (i = 0; i < DES_BLOCK_WORDS; i++) {
914 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
915 scatterwalk_advance(&dd->out_walk, 4);
916 if (dd->out_sg->length == _calc_walked(out)) {
5be4d4c9 917 dd->out_sg = sg_next(dd->out_sg);
e91aa9d5
JF		 918 if (dd->out_sg) {
919 scatterwalk_start(&dd->out_walk,
920 dd->out_sg);
921 dst = sg_virt(dd->out_sg) +
922 _calc_walked(out);
923 }
924 } else {
925 dst++;
926 }
927 }
928
42d2e780 929 BUG_ON(dd->total < DES_BLOCK_SIZE);
e91aa9d5 930
42d2e780 931 dd->total -= DES_BLOCK_SIZE;
e91aa9d5
JF		 932
933 /* Clear IRQ status */
934 status &= ~DES_REG_IRQ_DATA_OUT;
935 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
936
937 if (!dd->total)
938 /* All bytes read! */
939 tasklet_schedule(&dd->done_task);
940 else
941 /* Enable DATA_IN interrupt for next block */
942 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
943 }
944
945 return IRQ_HANDLED;
946}
947
948static const struct of_device_id omap_des_of_match[] = {
949 {
950 .compatible = "ti,omap4-des",
951 .data = &omap_des_pdata_omap4,
952 },
953 {},
954};
955MODULE_DEVICE_TABLE(of, omap_des_of_match);
956
957static int omap_des_get_of(struct omap_des_dev *dd,
958 struct platform_device *pdev)
959{
e91aa9d5 960
7d556931
CL		 961 dd->pdata = of_device_get_match_data(&pdev->dev);
962 if (!dd->pdata) {
e91aa9d5
JF		 963 dev_err(&pdev->dev, "no compatible OF match\n");
964 return -EINVAL;
965 }
966
e91aa9d5
JF		 967 return 0;
968}
969#else
970static int omap_des_get_of(struct omap_des_dev *dd,
971 struct device *dev)
972{
973 return -EINVAL;
974}
975#endif
976
977static int omap_des_get_pdev(struct omap_des_dev *dd,
978 struct platform_device *pdev)
979{
e91aa9d5
JF		 980 /* non-DT devices get pdata from pdev */
981 dd->pdata = pdev->dev.platform_data;
982
2f6f0680 983 return 0;
e91aa9d5
JF		 984}
985
986static int omap_des_probe(struct platform_device *pdev)
987{
988 struct device *dev = &pdev->dev;
989 struct omap_des_dev *dd;
990 struct crypto_alg *algp;
991 struct resource *res;
992 int err = -ENOMEM, i, j, irq = -1;
993 u32 reg;
994
995 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
996 if (dd == NULL) {
997 dev_err(dev, "unable to alloc data struct.\n");
998 goto err_data;
999 }
1000 dd->dev = dev;
1001 platform_set_drvdata(pdev, dd);
1002
e91aa9d5
JF		 1003 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004 if (!res) {
1005 dev_err(dev, "no MEM resource info\n");
1006 goto err_res;
1007 }
1008
1009 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
1010 omap_des_get_pdev(dd, pdev);
1011 if (err)
1012 goto err_res;
1013
2496be2e
JH		 1014 dd->io_base = devm_ioremap_resource(dev, res);
1015 if (IS_ERR(dd->io_base)) {
1016 err = PTR_ERR(dd->io_base);
e91aa9d5
JF		 1017 goto err_res;
1018 }
1019 dd->phys_base = res->start;
1020
418f2a8c
TK		 1021 pm_runtime_use_autosuspend(dev);
1022 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1023
e91aa9d5 1024 pm_runtime_enable(dev);
f51f593b
NM		 1025 err = pm_runtime_get_sync(dev);
1026 if (err < 0) {
1027 pm_runtime_put_noidle(dev);
1028 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
1029 goto err_get;
1030 }
e91aa9d5
JF		 1031
1032 omap_des_dma_stop(dd);
1033
1034 reg = omap_des_read(dd, DES_REG_REV(dd));
1035
1036 pm_runtime_put_sync(dev);
1037
1038 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1039 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1040 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1041
1042 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
e91aa9d5
JF		 1043
1044 err = omap_des_dma_init(dd);
2f6f0680
PU		 1045 if (err == -EPROBE_DEFER) {
1046 goto err_irq;
1047 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
e91aa9d5
JF		 1048 dd->pio_only = 1;
1049
1050 irq = platform_get_irq(pdev, 0);
1051 if (irq < 0) {
3822c331
GS		 1052 dev_err(dev, "can't get IRQ resource: %d\n", irq);
1053 err = irq;
e91aa9d5
JF		 1054 goto err_irq;
1055 }
1056
1057 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1058 dev_name(dev), dd);
1059 if (err) {
1060 dev_err(dev, "Unable to grab omap-des IRQ\n");
1061 goto err_irq;
1062 }
1063 }
1064
1065
1066 INIT_LIST_HEAD(&dd->list);
1067 spin_lock(&list_lock);
1068 list_add_tail(&dd->list, &dev_list);
1069 spin_unlock(&list_lock);
1070
1d1f98d1
TK		 1071 /* Initialize des crypto engine */
1072 dd->engine = crypto_engine_alloc_init(dev, 1);
59af1566
WY		 1073 if (!dd->engine) {
1074 err = -ENOMEM;
1d1f98d1 1075 goto err_engine;
59af1566 1076 }
1d1f98d1 1077
1d1f98d1
TK		 1078 err = crypto_engine_start(dd->engine);
1079 if (err)
1080 goto err_engine;
1081
e91aa9d5
JF		 1082 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1083 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1084 algp = &dd->pdata->algs_info[i].algs_list[j];
1085
1086 pr_debug("reg alg: %s\n", algp->cra_name);
e91aa9d5
JF		 1087
1088 err = crypto_register_alg(algp);
1089 if (err)
1090 goto err_algs;
1091
1092 dd->pdata->algs_info[i].registered++;
1093 }
1094 }
1095
1096 return 0;
f1b77aac 1097
e91aa9d5
JF		 1098err_algs:
1099 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1100 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1101 crypto_unregister_alg(
1102 &dd->pdata->algs_info[i].algs_list[j]);
2f6f0680 1103
1d1f98d1
TK		 1104err_engine:
1105 if (dd->engine)
1106 crypto_engine_exit(dd->engine);
1107
2f6f0680 1108 omap_des_dma_cleanup(dd);
e91aa9d5
JF		 1109err_irq:
1110 tasklet_kill(&dd->done_task);
f51f593b 1111err_get:
e91aa9d5
JF		 1112 pm_runtime_disable(dev);
1113err_res:
1114 dd = NULL;
1115err_data:
1116 dev_err(dev, "initialization failed.\n");
1117 return err;
1118}
1119
1120static int omap_des_remove(struct platform_device *pdev)
1121{
1122 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1123 int i, j;
1124
1125 if (!dd)
1126 return -ENODEV;
1127
1128 spin_lock(&list_lock);
1129 list_del(&dd->list);
1130 spin_unlock(&list_lock);
1131
1132 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1133 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1134 crypto_unregister_alg(
1135 &dd->pdata->algs_info[i].algs_list[j]);
1136
1137 tasklet_kill(&dd->done_task);
e91aa9d5
JF		 1138 omap_des_dma_cleanup(dd);
1139 pm_runtime_disable(dd->dev);
1140 dd = NULL;
1141
1142 return 0;
1143}
1144
1145#ifdef CONFIG_PM_SLEEP
1146static int omap_des_suspend(struct device *dev)
1147{
1148 pm_runtime_put_sync(dev);
1149 return 0;
1150}
1151
1152static int omap_des_resume(struct device *dev)
1153{
f51f593b
NM		 1154 int err;
1155
1156 err = pm_runtime_get_sync(dev);
1157 if (err < 0) {
1158 pm_runtime_put_noidle(dev);
1159 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1160 return err;
1161 }
e91aa9d5
JF		 1162 return 0;
1163}
1164#endif
1165
e78f9193 1166static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
e91aa9d5
JF		 1167
1168static struct platform_driver omap_des_driver = {
1169 .probe = omap_des_probe,
1170 .remove = omap_des_remove,
1171 .driver = {
1172 .name = "omap-des",
e91aa9d5
JF		 1173 .pm = &omap_des_pm_ops,
1174 .of_match_table = of_match_ptr(omap_des_of_match),
1175 },
1176};
1177
1178module_platform_driver(omap_des_driver);
1179
1180MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1181MODULE_LICENSE("GPL v2");
1182MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");
Linux 6.x block layer and io_uring tree(s)