Commit | Line | Data |
---|---|---|
537559a5 DK |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for OMAP AES HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2010 Nokia Corporation | |
7 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
0d35583a | 8 | * Copyright (c) 2011 Texas Instruments Incorporated |
537559a5 DK |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as published | |
12 | * by the Free Software Foundation. | |
13 | * | |
14 | */ | |
15 | ||
016af9b5 JF |
16 | #define pr_fmt(fmt) "%20s: " fmt, __func__ |
17 | #define prn(num) pr_debug(#num "=%d\n", num) | |
18 | #define prx(num) pr_debug(#num "=%x\n", num) | |
537559a5 DK |
19 | |
20 | #include <linux/err.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/kernel.h> | |
537559a5 DK |
25 | #include <linux/platform_device.h> |
26 | #include <linux/scatterlist.h> | |
27 | #include <linux/dma-mapping.h> | |
ebedbf79 | 28 | #include <linux/dmaengine.h> |
5946c4a5 | 29 | #include <linux/pm_runtime.h> |
bc69d124 MG |
30 | #include <linux/of.h> |
31 | #include <linux/of_device.h> | |
32 | #include <linux/of_address.h> | |
537559a5 DK |
33 | #include <linux/io.h> |
34 | #include <linux/crypto.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <crypto/scatterwalk.h> | |
37 | #include <crypto/aes.h> | |
cb3f3817 | 38 | #include <crypto/gcm.h> |
2589ad84 | 39 | #include <crypto/engine.h> |
9fcb191a | 40 | #include <crypto/internal/skcipher.h> |
ad18cc9d | 41 | #include <crypto/internal/aead.h> |
537559a5 | 42 | |
afc2dc13 | 43 | #include "omap-crypto.h" |
5b3d4d2e | 44 | #include "omap-aes.h" |
537559a5 DK |
45 | |
46 | /* keep registered devices data here */ | |
47 | static LIST_HEAD(dev_list); | |
48 | static DEFINE_SPINLOCK(list_lock); | |
49 | ||
537c62ca TK |
50 | static int aes_fallback_sz = 200; |
51 | ||
016af9b5 JF |
52 | #ifdef DEBUG |
53 | #define omap_aes_read(dd, offset) \ | |
54 | ({ \ | |
55 | int _read_ret; \ | |
56 | _read_ret = __raw_readl(dd->io_base + offset); \ | |
57 | pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ | |
58 | offset, _read_ret); \ | |
59 | _read_ret; \ | |
60 | }) | |
61 | #else | |
d695bfd6 | 62 | inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) |
537559a5 DK |
63 | { |
64 | return __raw_readl(dd->io_base + offset); | |
65 | } | |
016af9b5 JF |
66 | #endif |
67 | ||
68 | #ifdef DEBUG | |
69 | #define omap_aes_write(dd, offset, value) \ | |
70 | do { \ | |
71 | pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ | |
72 | offset, value); \ | |
73 | __raw_writel(value, dd->io_base + offset); \ | |
74 | } while (0) | |
75 | #else | |
d695bfd6 | 76 | inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, |
537559a5 DK |
77 | u32 value) |
78 | { | |
79 | __raw_writel(value, dd->io_base + offset); | |
80 | } | |
016af9b5 | 81 | #endif |
537559a5 DK |
82 | |
83 | static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, | |
84 | u32 value, u32 mask) | |
85 | { | |
86 | u32 val; | |
87 | ||
88 | val = omap_aes_read(dd, offset); | |
89 | val &= ~mask; | |
90 | val |= value; | |
91 | omap_aes_write(dd, offset, val); | |
92 | } | |
93 | ||
94 | static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, | |
95 | u32 *value, int count) | |
96 | { | |
97 | for (; count--; value++, offset += 4) | |
98 | omap_aes_write(dd, offset, *value); | |
99 | } | |
100 | ||
537559a5 DK |
101 | static int omap_aes_hw_init(struct omap_aes_dev *dd) |
102 | { | |
f303b455 TK |
103 | int err; |
104 | ||
537559a5 | 105 | if (!(dd->flags & FLAGS_INIT)) { |
eeb2b202 | 106 | dd->flags |= FLAGS_INIT; |
21fe9767 | 107 | dd->err = 0; |
537559a5 DK |
108 | } |
109 | ||
f303b455 TK |
110 | err = pm_runtime_get_sync(dd->dev); |
111 | if (err < 0) { | |
112 | dev_err(dd->dev, "failed to get sync: %d\n", err); | |
113 | return err; | |
114 | } | |
115 | ||
eeb2b202 | 116 | return 0; |
537559a5 DK |
117 | } |
118 | ||
ad18cc9d TK |
119 | void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) |
120 | { | |
121 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); | |
122 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); | |
123 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); | |
124 | } | |
125 | ||
d695bfd6 | 126 | int omap_aes_write_ctrl(struct omap_aes_dev *dd) |
537559a5 | 127 | { |
ad18cc9d | 128 | struct omap_aes_reqctx *rctx; |
537559a5 | 129 | unsigned int key32; |
67a730ce | 130 | int i, err; |
5396c6c0 | 131 | u32 val; |
537559a5 | 132 | |
21fe9767 DK |
133 | err = omap_aes_hw_init(dd); |
134 | if (err) | |
135 | return err; | |
136 | ||
537559a5 | 137 | key32 = dd->ctx->keylen / sizeof(u32); |
67a730ce | 138 | |
ad18cc9d TK |
139 | /* RESET the key as previous HASH keys should not get affected*/ |
140 | if (dd->flags & FLAGS_GCM) | |
141 | for (i = 0; i < 0x40; i = i + 4) | |
142 | omap_aes_write(dd, i, 0x0); | |
143 | ||
537559a5 | 144 | for (i = 0; i < key32; i++) { |
0d35583a | 145 | omap_aes_write(dd, AES_REG_KEY(dd, i), |
537559a5 DK |
146 | __le32_to_cpu(dd->ctx->key[i])); |
147 | } | |
537559a5 | 148 | |
f9fb69e7 | 149 | if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info) |
0d35583a | 150 | omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4); |
67a730ce | 151 | |
ad18cc9d TK |
152 | if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { |
153 | rctx = aead_request_ctx(dd->aead_req); | |
154 | omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); | |
155 | } | |
156 | ||
67a730ce DK |
157 | val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); |
158 | if (dd->flags & FLAGS_CBC) | |
159 | val |= AES_REG_CTRL_CBC; | |
ad18cc9d TK |
160 | |
161 | if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) | |
8ed49c76 | 162 | val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; |
5396c6c0 | 163 | |
ad18cc9d TK |
164 | if (dd->flags & FLAGS_GCM) |
165 | val |= AES_REG_CTRL_GCM; | |
166 | ||
67a730ce DK |
167 | if (dd->flags & FLAGS_ENCRYPT) |
168 | val |= AES_REG_CTRL_DIRECTION; | |
537559a5 | 169 | |
5396c6c0 | 170 | omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); |
537559a5 | 171 | |
21fe9767 | 172 | return 0; |
537559a5 DK |
173 | } |
174 | ||
0d35583a MG |
175 | static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) |
176 | { | |
177 | u32 mask, val; | |
178 | ||
179 | val = dd->pdata->dma_start; | |
180 | ||
181 | if (dd->dma_lch_out != NULL) | |
182 | val |= dd->pdata->dma_enable_out; | |
183 | if (dd->dma_lch_in != NULL) | |
184 | val |= dd->pdata->dma_enable_in; | |
185 | ||
186 | mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | | |
187 | dd->pdata->dma_start; | |
188 | ||
189 | omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); | |
190 | ||
191 | } | |
192 | ||
193 | static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) | |
194 | { | |
195 | omap_aes_write(dd, AES_REG_LENGTH_N(0), length); | |
196 | omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); | |
ad18cc9d TK |
197 | if (dd->flags & FLAGS_GCM) |
198 | omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); | |
0d35583a MG |
199 | |
200 | omap_aes_dma_trigger_omap2(dd, length); | |
201 | } | |
202 | ||
203 | static void omap_aes_dma_stop(struct omap_aes_dev *dd) | |
204 | { | |
205 | u32 mask; | |
206 | ||
207 | mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | | |
208 | dd->pdata->dma_start; | |
209 | ||
210 | omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); | |
211 | } | |
212 | ||
d695bfd6 | 213 | struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) |
537559a5 | 214 | { |
164f3ef3 | 215 | struct omap_aes_dev *dd; |
537559a5 DK |
216 | |
217 | spin_lock_bh(&list_lock); | |
164f3ef3 LV |
218 | dd = list_first_entry(&dev_list, struct omap_aes_dev, list); |
219 | list_move_tail(&dd->list, &dev_list); | |
619ce700 | 220 | rctx->dd = dd; |
537559a5 DK |
221 | spin_unlock_bh(&list_lock); |
222 | ||
223 | return dd; | |
224 | } | |
225 | ||
ebedbf79 MG |
226 | static void omap_aes_dma_out_callback(void *data) |
227 | { | |
228 | struct omap_aes_dev *dd = data; | |
229 | ||
230 | /* dma_lch_out - completed */ | |
231 | tasklet_schedule(&dd->done_task); | |
232 | } | |
537559a5 DK |
233 | |
234 | static int omap_aes_dma_init(struct omap_aes_dev *dd) | |
235 | { | |
da8b29a6 | 236 | int err; |
537559a5 | 237 | |
ebedbf79 MG |
238 | dd->dma_lch_out = NULL; |
239 | dd->dma_lch_in = NULL; | |
537559a5 | 240 | |
da8b29a6 PU |
241 | dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); |
242 | if (IS_ERR(dd->dma_lch_in)) { | |
ebedbf79 | 243 | dev_err(dd->dev, "Unable to request in DMA channel\n"); |
da8b29a6 | 244 | return PTR_ERR(dd->dma_lch_in); |
ebedbf79 MG |
245 | } |
246 | ||
da8b29a6 PU |
247 | dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); |
248 | if (IS_ERR(dd->dma_lch_out)) { | |
ebedbf79 | 249 | dev_err(dd->dev, "Unable to request out DMA channel\n"); |
da8b29a6 | 250 | err = PTR_ERR(dd->dma_lch_out); |
ebedbf79 MG |
251 | goto err_dma_out; |
252 | } | |
537559a5 | 253 | |
537559a5 DK |
254 | return 0; |
255 | ||
256 | err_dma_out: | |
ebedbf79 | 257 | dma_release_channel(dd->dma_lch_in); |
da8b29a6 | 258 | |
537559a5 DK |
259 | return err; |
260 | } | |
261 | ||
262 | static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) | |
263 | { | |
da8b29a6 PU |
264 | if (dd->pio_only) |
265 | return; | |
266 | ||
ebedbf79 MG |
267 | dma_release_channel(dd->dma_lch_out); |
268 | dma_release_channel(dd->dma_lch_in); | |
537559a5 DK |
269 | } |
270 | ||
619ce700 TK |
271 | static int omap_aes_crypt_dma(struct omap_aes_dev *dd, |
272 | struct scatterlist *in_sg, | |
273 | struct scatterlist *out_sg, | |
274 | int in_sg_len, int out_sg_len) | |
537559a5 | 275 | { |
ebedbf79 MG |
276 | struct dma_async_tx_descriptor *tx_in, *tx_out; |
277 | struct dma_slave_config cfg; | |
4b645c94 | 278 | int ret; |
537559a5 | 279 | |
98837abc JF |
280 | if (dd->pio_only) { |
281 | scatterwalk_start(&dd->in_walk, dd->in_sg); | |
282 | scatterwalk_start(&dd->out_walk, dd->out_sg); | |
283 | ||
284 | /* Enable DATAIN interrupt and let it take | |
285 | care of the rest */ | |
286 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); | |
287 | return 0; | |
288 | } | |
289 | ||
0a641712 JF |
290 | dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); |
291 | ||
ebedbf79 MG |
292 | memset(&cfg, 0, sizeof(cfg)); |
293 | ||
0d35583a MG |
294 | cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); |
295 | cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); | |
ebedbf79 MG |
296 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
297 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
298 | cfg.src_maxburst = DST_MAXBURST; | |
299 | cfg.dst_maxburst = DST_MAXBURST; | |
300 | ||
301 | /* IN */ | |
302 | ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); | |
303 | if (ret) { | |
304 | dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", | |
305 | ret); | |
306 | return ret; | |
307 | } | |
308 | ||
4b645c94 | 309 | tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, |
ebedbf79 MG |
310 | DMA_MEM_TO_DEV, |
311 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
312 | if (!tx_in) { | |
313 | dev_err(dd->dev, "IN prep_slave_sg() failed\n"); | |
314 | return -EINVAL; | |
315 | } | |
316 | ||
317 | /* No callback necessary */ | |
318 | tx_in->callback_param = dd; | |
319 | ||
320 | /* OUT */ | |
321 | ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); | |
322 | if (ret) { | |
323 | dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", | |
324 | ret); | |
325 | return ret; | |
326 | } | |
327 | ||
4b645c94 | 328 | tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, |
ebedbf79 MG |
329 | DMA_DEV_TO_MEM, |
330 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
331 | if (!tx_out) { | |
332 | dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); | |
333 | return -EINVAL; | |
334 | } | |
335 | ||
ad18cc9d TK |
336 | if (dd->flags & FLAGS_GCM) |
337 | tx_out->callback = omap_aes_gcm_dma_out_callback; | |
338 | else | |
339 | tx_out->callback = omap_aes_dma_out_callback; | |
ebedbf79 MG |
340 | tx_out->callback_param = dd; |
341 | ||
342 | dmaengine_submit(tx_in); | |
343 | dmaengine_submit(tx_out); | |
344 | ||
345 | dma_async_issue_pending(dd->dma_lch_in); | |
346 | dma_async_issue_pending(dd->dma_lch_out); | |
537559a5 | 347 | |
0d35583a | 348 | /* start DMA */ |
4b645c94 | 349 | dd->pdata->trigger(dd, dd->total); |
83ea7e0f | 350 | |
537559a5 DK |
351 | return 0; |
352 | } | |
353 | ||
d695bfd6 | 354 | int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) |
537559a5 | 355 | { |
4b645c94 | 356 | int err; |
537559a5 DK |
357 | |
358 | pr_debug("total: %d\n", dd->total); | |
359 | ||
98837abc JF |
360 | if (!dd->pio_only) { |
361 | err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, | |
362 | DMA_TO_DEVICE); | |
363 | if (!err) { | |
364 | dev_err(dd->dev, "dma_map_sg() error\n"); | |
365 | return -EINVAL; | |
366 | } | |
537559a5 | 367 | |
98837abc JF |
368 | err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, |
369 | DMA_FROM_DEVICE); | |
370 | if (!err) { | |
371 | dev_err(dd->dev, "dma_map_sg() error\n"); | |
372 | return -EINVAL; | |
373 | } | |
537559a5 DK |
374 | } |
375 | ||
619ce700 | 376 | err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, |
4b645c94 | 377 | dd->out_sg_len); |
98837abc | 378 | if (err && !dd->pio_only) { |
4b645c94 JF |
379 | dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
380 | dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, | |
381 | DMA_FROM_DEVICE); | |
21fe9767 | 382 | } |
537559a5 DK |
383 | |
384 | return err; | |
385 | } | |
386 | ||
387 | static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) | |
388 | { | |
21fe9767 | 389 | struct ablkcipher_request *req = dd->req; |
537559a5 DK |
390 | |
391 | pr_debug("err: %d\n", err); | |
392 | ||
c21c8b89 | 393 | crypto_finalize_ablkcipher_request(dd->engine, req, err); |
f303b455 TK |
394 | |
395 | pm_runtime_mark_last_busy(dd->dev); | |
396 | pm_runtime_put_autosuspend(dd->dev); | |
537559a5 DK |
397 | } |
398 | ||
d695bfd6 | 399 | int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) |
537559a5 | 400 | { |
537559a5 DK |
401 | pr_debug("total: %d\n", dd->total); |
402 | ||
0d35583a | 403 | omap_aes_dma_stop(dd); |
537559a5 | 404 | |
537559a5 | 405 | |
16f080aa | 406 | return 0; |
537559a5 DK |
407 | } |
408 | ||
21fe9767 | 409 | static int omap_aes_handle_queue(struct omap_aes_dev *dd, |
0529900a | 410 | struct ablkcipher_request *req) |
537559a5 | 411 | { |
eeb2b202 | 412 | if (req) |
c21c8b89 | 413 | return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req); |
537559a5 | 414 | |
0529900a BW |
415 | return 0; |
416 | } | |
537559a5 | 417 | |
0529900a | 418 | static int omap_aes_prepare_req(struct crypto_engine *engine, |
c21c8b89 | 419 | void *areq) |
0529900a | 420 | { |
c21c8b89 | 421 | struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base); |
0529900a BW |
422 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( |
423 | crypto_ablkcipher_reqtfm(req)); | |
619ce700 TK |
424 | struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); |
425 | struct omap_aes_dev *dd = rctx->dd; | |
afc2dc13 TK |
426 | int ret; |
427 | u16 flags; | |
537559a5 | 428 | |
0529900a BW |
429 | if (!dd) |
430 | return -ENODEV; | |
537559a5 | 431 | |
537559a5 DK |
432 | /* assign new request to device */ |
433 | dd->req = req; | |
434 | dd->total = req->nbytes; | |
6242332f | 435 | dd->total_save = req->nbytes; |
537559a5 | 436 | dd->in_sg = req->src; |
537559a5 | 437 | dd->out_sg = req->dst; |
afc2dc13 TK |
438 | dd->orig_out = req->dst; |
439 | ||
440 | flags = OMAP_CRYPTO_COPY_DATA; | |
441 | if (req->src == req->dst) | |
442 | flags |= OMAP_CRYPTO_FORCE_COPY; | |
443 | ||
444 | ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, | |
ad18cc9d | 445 | dd->in_sgl, flags, |
afc2dc13 TK |
446 | FLAGS_IN_DATA_ST_SHIFT, &dd->flags); |
447 | if (ret) | |
448 | return ret; | |
449 | ||
450 | ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, | |
451 | &dd->out_sgl, 0, | |
452 | FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); | |
453 | if (ret) | |
454 | return ret; | |
537559a5 | 455 | |
7c001a86 HX |
456 | dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); |
457 | if (dd->in_sg_len < 0) | |
458 | return dd->in_sg_len; | |
459 | ||
460 | dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); | |
461 | if (dd->out_sg_len < 0) | |
462 | return dd->out_sg_len; | |
463 | ||
537559a5 DK |
464 | rctx->mode &= FLAGS_MODE_MASK; |
465 | dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; | |
466 | ||
67a730ce | 467 | dd->ctx = ctx; |
619ce700 | 468 | rctx->dd = dd; |
537559a5 | 469 | |
0529900a BW |
470 | return omap_aes_write_ctrl(dd); |
471 | } | |
eeb2b202 | 472 | |
0529900a | 473 | static int omap_aes_crypt_req(struct crypto_engine *engine, |
c21c8b89 | 474 | void *areq) |
0529900a | 475 | { |
c21c8b89 | 476 | struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base); |
619ce700 TK |
477 | struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); |
478 | struct omap_aes_dev *dd = rctx->dd; | |
0529900a BW |
479 | |
480 | if (!dd) | |
481 | return -ENODEV; | |
482 | ||
483 | return omap_aes_crypt_dma_start(dd); | |
537559a5 DK |
484 | } |
485 | ||
21fe9767 | 486 | static void omap_aes_done_task(unsigned long data) |
537559a5 DK |
487 | { |
488 | struct omap_aes_dev *dd = (struct omap_aes_dev *)data; | |
537559a5 | 489 | |
4b645c94 | 490 | pr_debug("enter done_task\n"); |
21fe9767 | 491 | |
98837abc JF |
492 | if (!dd->pio_only) { |
493 | dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, | |
494 | DMA_FROM_DEVICE); | |
6242332f JF |
495 | dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
496 | dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, | |
497 | DMA_FROM_DEVICE); | |
98837abc JF |
498 | omap_aes_crypt_dma_stop(dd); |
499 | } | |
6242332f | 500 | |
ad18cc9d | 501 | omap_crypto_cleanup(dd->in_sgl, NULL, 0, dd->total_save, |
afc2dc13 | 502 | FLAGS_IN_DATA_ST_SHIFT, dd->flags); |
6242332f | 503 | |
afc2dc13 TK |
504 | omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save, |
505 | FLAGS_OUT_DATA_ST_SHIFT, dd->flags); | |
6242332f | 506 | |
4b645c94 | 507 | omap_aes_finish_req(dd, 0); |
537559a5 DK |
508 | |
509 | pr_debug("exit\n"); | |
510 | } | |
511 | ||
512 | static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) | |
513 | { | |
514 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( | |
515 | crypto_ablkcipher_reqtfm(req)); | |
516 | struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); | |
517 | struct omap_aes_dev *dd; | |
9fcb191a | 518 | int ret; |
537559a5 DK |
519 | |
520 | pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, | |
521 | !!(mode & FLAGS_ENCRYPT), | |
522 | !!(mode & FLAGS_CBC)); | |
523 | ||
537c62ca | 524 | if (req->nbytes < aes_fallback_sz) { |
9fcb191a LV |
525 | SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); |
526 | ||
527 | skcipher_request_set_tfm(subreq, ctx->fallback); | |
528 | skcipher_request_set_callback(subreq, req->base.flags, NULL, | |
529 | NULL); | |
530 | skcipher_request_set_crypt(subreq, req->src, req->dst, | |
531 | req->nbytes, req->info); | |
532 | ||
533 | if (mode & FLAGS_ENCRYPT) | |
534 | ret = crypto_skcipher_encrypt(subreq); | |
535 | else | |
536 | ret = crypto_skcipher_decrypt(subreq); | |
537 | ||
538 | skcipher_request_zero(subreq); | |
539 | return ret; | |
540 | } | |
619ce700 | 541 | dd = omap_aes_find_dev(rctx); |
537559a5 DK |
542 | if (!dd) |
543 | return -ENODEV; | |
544 | ||
545 | rctx->mode = mode; | |
546 | ||
21fe9767 | 547 | return omap_aes_handle_queue(dd, req); |
537559a5 DK |
548 | } |
549 | ||
550 | /* ********************** ALG API ************************************ */ | |
551 | ||
552 | static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, | |
553 | unsigned int keylen) | |
554 | { | |
555 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); | |
9fcb191a | 556 | int ret; |
537559a5 DK |
557 | |
558 | if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && | |
559 | keylen != AES_KEYSIZE_256) | |
560 | return -EINVAL; | |
561 | ||
562 | pr_debug("enter, keylen: %d\n", keylen); | |
563 | ||
564 | memcpy(ctx->key, key, keylen); | |
565 | ctx->keylen = keylen; | |
537559a5 | 566 | |
9fcb191a LV |
567 | crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); |
568 | crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & | |
569 | CRYPTO_TFM_REQ_MASK); | |
570 | ||
571 | ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); | |
572 | if (!ret) | |
573 | return 0; | |
574 | ||
537559a5 DK |
575 | return 0; |
576 | } | |
577 | ||
578 | static int omap_aes_ecb_encrypt(struct ablkcipher_request *req) | |
579 | { | |
580 | return omap_aes_crypt(req, FLAGS_ENCRYPT); | |
581 | } | |
582 | ||
583 | static int omap_aes_ecb_decrypt(struct ablkcipher_request *req) | |
584 | { | |
585 | return omap_aes_crypt(req, 0); | |
586 | } | |
587 | ||
588 | static int omap_aes_cbc_encrypt(struct ablkcipher_request *req) | |
589 | { | |
590 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); | |
591 | } | |
592 | ||
593 | static int omap_aes_cbc_decrypt(struct ablkcipher_request *req) | |
594 | { | |
595 | return omap_aes_crypt(req, FLAGS_CBC); | |
596 | } | |
597 | ||
f9fb69e7 MG |
598 | static int omap_aes_ctr_encrypt(struct ablkcipher_request *req) |
599 | { | |
600 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); | |
601 | } | |
602 | ||
603 | static int omap_aes_ctr_decrypt(struct ablkcipher_request *req) | |
604 | { | |
605 | return omap_aes_crypt(req, FLAGS_CTR); | |
606 | } | |
607 | ||
c21c8b89 CL |
608 | static int omap_aes_prepare_req(struct crypto_engine *engine, |
609 | void *req); | |
610 | static int omap_aes_crypt_req(struct crypto_engine *engine, | |
611 | void *req); | |
612 | ||
537559a5 DK |
613 | static int omap_aes_cra_init(struct crypto_tfm *tfm) |
614 | { | |
9fcb191a LV |
615 | const char *name = crypto_tfm_alg_name(tfm); |
616 | const u32 flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK; | |
617 | struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
618 | struct crypto_skcipher *blk; | |
619 | ||
620 | blk = crypto_alloc_skcipher(name, 0, flags); | |
621 | if (IS_ERR(blk)) | |
622 | return PTR_ERR(blk); | |
623 | ||
624 | ctx->fallback = blk; | |
625 | ||
537559a5 DK |
626 | tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); |
627 | ||
c21c8b89 CL |
628 | ctx->enginectx.op.prepare_request = omap_aes_prepare_req; |
629 | ctx->enginectx.op.unprepare_request = NULL; | |
630 | ctx->enginectx.op.do_one_request = omap_aes_crypt_req; | |
631 | ||
537559a5 DK |
632 | return 0; |
633 | } | |
634 | ||
ad18cc9d TK |
635 | static int omap_aes_gcm_cra_init(struct crypto_aead *tfm) |
636 | { | |
637 | struct omap_aes_dev *dd = NULL; | |
638 | struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); | |
639 | int err; | |
640 | ||
641 | /* Find AES device, currently picks the first device */ | |
642 | spin_lock_bh(&list_lock); | |
643 | list_for_each_entry(dd, &dev_list, list) { | |
644 | break; | |
645 | } | |
646 | spin_unlock_bh(&list_lock); | |
647 | ||
648 | err = pm_runtime_get_sync(dd->dev); | |
649 | if (err < 0) { | |
650 | dev_err(dd->dev, "%s: failed to get_sync(%d)\n", | |
651 | __func__, err); | |
652 | return err; | |
653 | } | |
654 | ||
655 | tfm->reqsize = sizeof(struct omap_aes_reqctx); | |
656 | ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0); | |
657 | if (IS_ERR(ctx->ctr)) { | |
658 | pr_warn("could not load aes driver for encrypting IV\n"); | |
659 | return PTR_ERR(ctx->ctr); | |
660 | } | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
537559a5 DK |
665 | static void omap_aes_cra_exit(struct crypto_tfm *tfm) |
666 | { | |
9fcb191a LV |
667 | struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); |
668 | ||
669 | if (ctx->fallback) | |
670 | crypto_free_skcipher(ctx->fallback); | |
671 | ||
672 | ctx->fallback = NULL; | |
537559a5 DK |
673 | } |
674 | ||
ad18cc9d TK |
675 | static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm) |
676 | { | |
677 | struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); | |
678 | ||
679 | omap_aes_cra_exit(crypto_aead_tfm(tfm)); | |
680 | ||
681 | if (ctx->ctr) | |
682 | crypto_free_skcipher(ctx->ctr); | |
683 | } | |
684 | ||
537559a5 DK |
685 | /* ********************** ALGS ************************************ */ |
686 | ||
f9fb69e7 | 687 | static struct crypto_alg algs_ecb_cbc[] = { |
537559a5 DK |
688 | { |
689 | .cra_name = "ecb(aes)", | |
690 | .cra_driver_name = "ecb-aes-omap", | |
6e2e3d1d | 691 | .cra_priority = 300, |
d912bb76 NM |
692 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
693 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
9fcb191a | 694 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, |
537559a5 DK |
695 | .cra_blocksize = AES_BLOCK_SIZE, |
696 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
efce41b6 | 697 | .cra_alignmask = 0, |
537559a5 DK |
698 | .cra_type = &crypto_ablkcipher_type, |
699 | .cra_module = THIS_MODULE, | |
700 | .cra_init = omap_aes_cra_init, | |
701 | .cra_exit = omap_aes_cra_exit, | |
702 | .cra_u.ablkcipher = { | |
703 | .min_keysize = AES_MIN_KEY_SIZE, | |
704 | .max_keysize = AES_MAX_KEY_SIZE, | |
705 | .setkey = omap_aes_setkey, | |
706 | .encrypt = omap_aes_ecb_encrypt, | |
707 | .decrypt = omap_aes_ecb_decrypt, | |
708 | } | |
709 | }, | |
710 | { | |
711 | .cra_name = "cbc(aes)", | |
712 | .cra_driver_name = "cbc-aes-omap", | |
6e2e3d1d | 713 | .cra_priority = 300, |
d912bb76 NM |
714 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
715 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
9fcb191a | 716 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, |
537559a5 DK |
717 | .cra_blocksize = AES_BLOCK_SIZE, |
718 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
efce41b6 | 719 | .cra_alignmask = 0, |
537559a5 DK |
720 | .cra_type = &crypto_ablkcipher_type, |
721 | .cra_module = THIS_MODULE, | |
722 | .cra_init = omap_aes_cra_init, | |
723 | .cra_exit = omap_aes_cra_exit, | |
724 | .cra_u.ablkcipher = { | |
725 | .min_keysize = AES_MIN_KEY_SIZE, | |
726 | .max_keysize = AES_MAX_KEY_SIZE, | |
727 | .ivsize = AES_BLOCK_SIZE, | |
728 | .setkey = omap_aes_setkey, | |
729 | .encrypt = omap_aes_cbc_encrypt, | |
730 | .decrypt = omap_aes_cbc_decrypt, | |
731 | } | |
732 | } | |
733 | }; | |
734 | ||
f9fb69e7 MG |
735 | static struct crypto_alg algs_ctr[] = { |
736 | { | |
737 | .cra_name = "ctr(aes)", | |
738 | .cra_driver_name = "ctr-aes-omap", | |
6e2e3d1d | 739 | .cra_priority = 300, |
f9fb69e7 MG |
740 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
741 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
9fcb191a | 742 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, |
f9fb69e7 MG |
743 | .cra_blocksize = AES_BLOCK_SIZE, |
744 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
745 | .cra_alignmask = 0, | |
746 | .cra_type = &crypto_ablkcipher_type, | |
747 | .cra_module = THIS_MODULE, | |
748 | .cra_init = omap_aes_cra_init, | |
749 | .cra_exit = omap_aes_cra_exit, | |
750 | .cra_u.ablkcipher = { | |
751 | .min_keysize = AES_MIN_KEY_SIZE, | |
752 | .max_keysize = AES_MAX_KEY_SIZE, | |
753 | .geniv = "eseqiv", | |
754 | .ivsize = AES_BLOCK_SIZE, | |
755 | .setkey = omap_aes_setkey, | |
756 | .encrypt = omap_aes_ctr_encrypt, | |
757 | .decrypt = omap_aes_ctr_decrypt, | |
758 | } | |
759 | } , | |
760 | }; | |
761 | ||
762 | static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { | |
763 | { | |
764 | .algs_list = algs_ecb_cbc, | |
765 | .size = ARRAY_SIZE(algs_ecb_cbc), | |
766 | }, | |
767 | }; | |
768 | ||
ad18cc9d TK |
769 | static struct aead_alg algs_aead_gcm[] = { |
770 | { | |
771 | .base = { | |
772 | .cra_name = "gcm(aes)", | |
773 | .cra_driver_name = "gcm-aes-omap", | |
774 | .cra_priority = 300, | |
775 | .cra_flags = CRYPTO_ALG_ASYNC | | |
776 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
777 | .cra_blocksize = 1, | |
778 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
779 | .cra_alignmask = 0xf, | |
780 | .cra_module = THIS_MODULE, | |
781 | }, | |
782 | .init = omap_aes_gcm_cra_init, | |
783 | .exit = omap_aes_gcm_cra_exit, | |
cb3f3817 | 784 | .ivsize = GCM_AES_IV_SIZE, |
ad18cc9d TK |
785 | .maxauthsize = AES_BLOCK_SIZE, |
786 | .setkey = omap_aes_gcm_setkey, | |
787 | .encrypt = omap_aes_gcm_encrypt, | |
788 | .decrypt = omap_aes_gcm_decrypt, | |
789 | }, | |
790 | { | |
791 | .base = { | |
792 | .cra_name = "rfc4106(gcm(aes))", | |
793 | .cra_driver_name = "rfc4106-gcm-aes-omap", | |
794 | .cra_priority = 300, | |
795 | .cra_flags = CRYPTO_ALG_ASYNC | | |
796 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
797 | .cra_blocksize = 1, | |
798 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
799 | .cra_alignmask = 0xf, | |
800 | .cra_module = THIS_MODULE, | |
801 | }, | |
802 | .init = omap_aes_gcm_cra_init, | |
803 | .exit = omap_aes_gcm_cra_exit, | |
804 | .maxauthsize = AES_BLOCK_SIZE, | |
cb3f3817 | 805 | .ivsize = GCM_RFC4106_IV_SIZE, |
ad18cc9d TK |
806 | .setkey = omap_aes_4106gcm_setkey, |
807 | .encrypt = omap_aes_4106gcm_encrypt, | |
808 | .decrypt = omap_aes_4106gcm_decrypt, | |
809 | }, | |
810 | }; | |
811 | ||
812 | static struct omap_aes_aead_algs omap_aes_aead_info = { | |
813 | .algs_list = algs_aead_gcm, | |
814 | .size = ARRAY_SIZE(algs_aead_gcm), | |
815 | }; | |
816 | ||
0d35583a | 817 | static const struct omap_aes_pdata omap_aes_pdata_omap2 = { |
f9fb69e7 MG |
818 | .algs_info = omap_aes_algs_info_ecb_cbc, |
819 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), | |
0d35583a MG |
820 | .trigger = omap_aes_dma_trigger_omap2, |
821 | .key_ofs = 0x1c, | |
822 | .iv_ofs = 0x20, | |
823 | .ctrl_ofs = 0x30, | |
824 | .data_ofs = 0x34, | |
825 | .rev_ofs = 0x44, | |
826 | .mask_ofs = 0x48, | |
827 | .dma_enable_in = BIT(2), | |
828 | .dma_enable_out = BIT(3), | |
829 | .dma_start = BIT(5), | |
830 | .major_mask = 0xf0, | |
831 | .major_shift = 4, | |
832 | .minor_mask = 0x0f, | |
833 | .minor_shift = 0, | |
834 | }; | |
835 | ||
bc69d124 | 836 | #ifdef CONFIG_OF |
f9fb69e7 MG |
837 | static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { |
838 | { | |
839 | .algs_list = algs_ecb_cbc, | |
840 | .size = ARRAY_SIZE(algs_ecb_cbc), | |
841 | }, | |
842 | { | |
843 | .algs_list = algs_ctr, | |
844 | .size = ARRAY_SIZE(algs_ctr), | |
845 | }, | |
846 | }; | |
847 | ||
848 | static const struct omap_aes_pdata omap_aes_pdata_omap3 = { | |
849 | .algs_info = omap_aes_algs_info_ecb_cbc_ctr, | |
850 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), | |
851 | .trigger = omap_aes_dma_trigger_omap2, | |
852 | .key_ofs = 0x1c, | |
853 | .iv_ofs = 0x20, | |
854 | .ctrl_ofs = 0x30, | |
855 | .data_ofs = 0x34, | |
856 | .rev_ofs = 0x44, | |
857 | .mask_ofs = 0x48, | |
858 | .dma_enable_in = BIT(2), | |
859 | .dma_enable_out = BIT(3), | |
860 | .dma_start = BIT(5), | |
861 | .major_mask = 0xf0, | |
862 | .major_shift = 4, | |
863 | .minor_mask = 0x0f, | |
864 | .minor_shift = 0, | |
865 | }; | |
866 | ||
0d35583a | 867 | static const struct omap_aes_pdata omap_aes_pdata_omap4 = { |
f9fb69e7 MG |
868 | .algs_info = omap_aes_algs_info_ecb_cbc_ctr, |
869 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), | |
ad18cc9d | 870 | .aead_algs_info = &omap_aes_aead_info, |
0d35583a MG |
871 | .trigger = omap_aes_dma_trigger_omap4, |
872 | .key_ofs = 0x3c, | |
873 | .iv_ofs = 0x40, | |
874 | .ctrl_ofs = 0x50, | |
875 | .data_ofs = 0x60, | |
876 | .rev_ofs = 0x80, | |
877 | .mask_ofs = 0x84, | |
67216756 JF |
878 | .irq_status_ofs = 0x8c, |
879 | .irq_enable_ofs = 0x90, | |
0d35583a MG |
880 | .dma_enable_in = BIT(5), |
881 | .dma_enable_out = BIT(6), | |
882 | .major_mask = 0x0700, | |
883 | .major_shift = 8, | |
884 | .minor_mask = 0x003f, | |
885 | .minor_shift = 0, | |
886 | }; | |
887 | ||
1bf95cca JF |
888 | static irqreturn_t omap_aes_irq(int irq, void *dev_id) |
889 | { | |
890 | struct omap_aes_dev *dd = dev_id; | |
891 | u32 status, i; | |
892 | u32 *src, *dst; | |
893 | ||
894 | status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); | |
895 | if (status & AES_REG_IRQ_DATA_IN) { | |
896 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); | |
897 | ||
898 | BUG_ON(!dd->in_sg); | |
899 | ||
900 | BUG_ON(_calc_walked(in) > dd->in_sg->length); | |
901 | ||
902 | src = sg_virt(dd->in_sg) + _calc_walked(in); | |
903 | ||
904 | for (i = 0; i < AES_BLOCK_WORDS; i++) { | |
905 | omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); | |
906 | ||
907 | scatterwalk_advance(&dd->in_walk, 4); | |
908 | if (dd->in_sg->length == _calc_walked(in)) { | |
5be4d4c9 | 909 | dd->in_sg = sg_next(dd->in_sg); |
1bf95cca JF |
910 | if (dd->in_sg) { |
911 | scatterwalk_start(&dd->in_walk, | |
912 | dd->in_sg); | |
913 | src = sg_virt(dd->in_sg) + | |
914 | _calc_walked(in); | |
915 | } | |
916 | } else { | |
917 | src++; | |
918 | } | |
919 | } | |
920 | ||
921 | /* Clear IRQ status */ | |
922 | status &= ~AES_REG_IRQ_DATA_IN; | |
923 | omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); | |
924 | ||
925 | /* Enable DATA_OUT interrupt */ | |
926 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); | |
927 | ||
928 | } else if (status & AES_REG_IRQ_DATA_OUT) { | |
929 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); | |
930 | ||
931 | BUG_ON(!dd->out_sg); | |
932 | ||
933 | BUG_ON(_calc_walked(out) > dd->out_sg->length); | |
934 | ||
935 | dst = sg_virt(dd->out_sg) + _calc_walked(out); | |
936 | ||
937 | for (i = 0; i < AES_BLOCK_WORDS; i++) { | |
938 | *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); | |
939 | scatterwalk_advance(&dd->out_walk, 4); | |
940 | if (dd->out_sg->length == _calc_walked(out)) { | |
5be4d4c9 | 941 | dd->out_sg = sg_next(dd->out_sg); |
1bf95cca JF |
942 | if (dd->out_sg) { |
943 | scatterwalk_start(&dd->out_walk, | |
944 | dd->out_sg); | |
945 | dst = sg_virt(dd->out_sg) + | |
946 | _calc_walked(out); | |
947 | } | |
948 | } else { | |
949 | dst++; | |
950 | } | |
951 | } | |
952 | ||
310b0d55 | 953 | dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); |
1bf95cca JF |
954 | |
955 | /* Clear IRQ status */ | |
956 | status &= ~AES_REG_IRQ_DATA_OUT; | |
957 | omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); | |
958 | ||
959 | if (!dd->total) | |
960 | /* All bytes read! */ | |
961 | tasklet_schedule(&dd->done_task); | |
962 | else | |
963 | /* Enable DATA_IN interrupt for next block */ | |
964 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); | |
965 | } | |
966 | ||
967 | return IRQ_HANDLED; | |
968 | } | |
969 | ||
bc69d124 MG |
970 | static const struct of_device_id omap_aes_of_match[] = { |
971 | { | |
972 | .compatible = "ti,omap2-aes", | |
0d35583a MG |
973 | .data = &omap_aes_pdata_omap2, |
974 | }, | |
f9fb69e7 MG |
975 | { |
976 | .compatible = "ti,omap3-aes", | |
977 | .data = &omap_aes_pdata_omap3, | |
978 | }, | |
0d35583a MG |
979 | { |
980 | .compatible = "ti,omap4-aes", | |
981 | .data = &omap_aes_pdata_omap4, | |
bc69d124 MG |
982 | }, |
983 | {}, | |
984 | }; | |
985 | MODULE_DEVICE_TABLE(of, omap_aes_of_match); | |
986 | ||
987 | static int omap_aes_get_res_of(struct omap_aes_dev *dd, | |
988 | struct device *dev, struct resource *res) | |
989 | { | |
990 | struct device_node *node = dev->of_node; | |
bc69d124 MG |
991 | int err = 0; |
992 | ||
7d556931 CL |
993 | dd->pdata = of_device_get_match_data(dev); |
994 | if (!dd->pdata) { | |
bc69d124 MG |
995 | dev_err(dev, "no compatible OF match\n"); |
996 | err = -EINVAL; | |
997 | goto err; | |
998 | } | |
999 | ||
1000 | err = of_address_to_resource(node, 0, res); | |
1001 | if (err < 0) { | |
1002 | dev_err(dev, "can't translate OF node address\n"); | |
1003 | err = -EINVAL; | |
1004 | goto err; | |
1005 | } | |
1006 | ||
bc69d124 MG |
1007 | err: |
1008 | return err; | |
1009 | } | |
1010 | #else | |
1011 | static const struct of_device_id omap_aes_of_match[] = { | |
1012 | {}, | |
1013 | }; | |
1014 | ||
1015 | static int omap_aes_get_res_of(struct omap_aes_dev *dd, | |
1016 | struct device *dev, struct resource *res) | |
1017 | { | |
1018 | return -EINVAL; | |
1019 | } | |
1020 | #endif | |
1021 | ||
1022 | static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, | |
1023 | struct platform_device *pdev, struct resource *res) | |
1024 | { | |
1025 | struct device *dev = &pdev->dev; | |
1026 | struct resource *r; | |
1027 | int err = 0; | |
1028 | ||
1029 | /* Get the base address */ | |
1030 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1031 | if (!r) { | |
1032 | dev_err(dev, "no MEM resource info\n"); | |
1033 | err = -ENODEV; | |
1034 | goto err; | |
1035 | } | |
1036 | memcpy(res, r, sizeof(*res)); | |
1037 | ||
0d35583a MG |
1038 | /* Only OMAP2/3 can be non-DT */ |
1039 | dd->pdata = &omap_aes_pdata_omap2; | |
1040 | ||
bc69d124 MG |
1041 | err: |
1042 | return err; | |
1043 | } | |
1044 | ||
537c62ca TK |
1045 | static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, |
1046 | char *buf) | |
1047 | { | |
1048 | return sprintf(buf, "%d\n", aes_fallback_sz); | |
1049 | } | |
1050 | ||
1051 | static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, | |
1052 | const char *buf, size_t size) | |
1053 | { | |
1054 | ssize_t status; | |
1055 | long value; | |
1056 | ||
1057 | status = kstrtol(buf, 0, &value); | |
1058 | if (status) | |
1059 | return status; | |
1060 | ||
1061 | /* HW accelerator only works with buffers > 9 */ | |
1062 | if (value < 9) { | |
1063 | dev_err(dev, "minimum fallback size 9\n"); | |
1064 | return -EINVAL; | |
1065 | } | |
1066 | ||
1067 | aes_fallback_sz = value; | |
1068 | ||
1069 | return size; | |
1070 | } | |
1071 | ||
5007387f TK |
1072 | static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, |
1073 | char *buf) | |
1074 | { | |
1075 | struct omap_aes_dev *dd = dev_get_drvdata(dev); | |
1076 | ||
1077 | return sprintf(buf, "%d\n", dd->engine->queue.max_qlen); | |
1078 | } | |
1079 | ||
1080 | static ssize_t queue_len_store(struct device *dev, | |
1081 | struct device_attribute *attr, const char *buf, | |
1082 | size_t size) | |
1083 | { | |
1084 | struct omap_aes_dev *dd; | |
1085 | ssize_t status; | |
1086 | long value; | |
1087 | unsigned long flags; | |
1088 | ||
1089 | status = kstrtol(buf, 0, &value); | |
1090 | if (status) | |
1091 | return status; | |
1092 | ||
1093 | if (value < 1) | |
1094 | return -EINVAL; | |
1095 | ||
1096 | /* | |
1097 | * Changing the queue size in fly is safe, if size becomes smaller | |
1098 | * than current size, it will just not accept new entries until | |
1099 | * it has shrank enough. | |
1100 | */ | |
1101 | spin_lock_bh(&list_lock); | |
1102 | list_for_each_entry(dd, &dev_list, list) { | |
1103 | spin_lock_irqsave(&dd->lock, flags); | |
1104 | dd->engine->queue.max_qlen = value; | |
1105 | dd->aead_queue.base.max_qlen = value; | |
1106 | spin_unlock_irqrestore(&dd->lock, flags); | |
1107 | } | |
1108 | spin_unlock_bh(&list_lock); | |
1109 | ||
1110 | return size; | |
1111 | } | |
1112 | ||
1113 | static DEVICE_ATTR_RW(queue_len); | |
537c62ca TK |
1114 | static DEVICE_ATTR_RW(fallback); |
1115 | ||
1116 | static struct attribute *omap_aes_attrs[] = { | |
5007387f | 1117 | &dev_attr_queue_len.attr, |
537c62ca TK |
1118 | &dev_attr_fallback.attr, |
1119 | NULL, | |
1120 | }; | |
1121 | ||
1122 | static struct attribute_group omap_aes_attr_group = { | |
1123 | .attrs = omap_aes_attrs, | |
1124 | }; | |
1125 | ||
537559a5 DK |
1126 | static int omap_aes_probe(struct platform_device *pdev) |
1127 | { | |
1128 | struct device *dev = &pdev->dev; | |
1129 | struct omap_aes_dev *dd; | |
f9fb69e7 | 1130 | struct crypto_alg *algp; |
ad18cc9d | 1131 | struct aead_alg *aalg; |
bc69d124 | 1132 | struct resource res; |
1801ad94 | 1133 | int err = -ENOMEM, i, j, irq = -1; |
537559a5 DK |
1134 | u32 reg; |
1135 | ||
05007c10 | 1136 | dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); |
537559a5 DK |
1137 | if (dd == NULL) { |
1138 | dev_err(dev, "unable to alloc data struct.\n"); | |
1139 | goto err_data; | |
1140 | } | |
1141 | dd->dev = dev; | |
1142 | platform_set_drvdata(pdev, dd); | |
1143 | ||
ad18cc9d TK |
1144 | aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); |
1145 | ||
bc69d124 MG |
1146 | err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : |
1147 | omap_aes_get_res_pdev(dd, pdev, &res); | |
1148 | if (err) | |
537559a5 | 1149 | goto err_res; |
bc69d124 | 1150 | |
30862281 LN |
1151 | dd->io_base = devm_ioremap_resource(dev, &res); |
1152 | if (IS_ERR(dd->io_base)) { | |
1153 | err = PTR_ERR(dd->io_base); | |
5946c4a5 | 1154 | goto err_res; |
537559a5 | 1155 | } |
bc69d124 | 1156 | dd->phys_base = res.start; |
537559a5 | 1157 | |
f303b455 TK |
1158 | pm_runtime_use_autosuspend(dev); |
1159 | pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); | |
1160 | ||
5946c4a5 | 1161 | pm_runtime_enable(dev); |
f7b2b5dd NM |
1162 | err = pm_runtime_get_sync(dev); |
1163 | if (err < 0) { | |
1164 | dev_err(dev, "%s: failed to get_sync(%d)\n", | |
1165 | __func__, err); | |
1166 | goto err_res; | |
1167 | } | |
5946c4a5 | 1168 | |
0d35583a MG |
1169 | omap_aes_dma_stop(dd); |
1170 | ||
1171 | reg = omap_aes_read(dd, AES_REG_REV(dd)); | |
5946c4a5 MG |
1172 | |
1173 | pm_runtime_put_sync(dev); | |
537559a5 | 1174 | |
0d35583a MG |
1175 | dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", |
1176 | (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, | |
1177 | (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); | |
1178 | ||
21fe9767 | 1179 | tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); |
537559a5 DK |
1180 | |
1181 | err = omap_aes_dma_init(dd); | |
da8b29a6 PU |
1182 | if (err == -EPROBE_DEFER) { |
1183 | goto err_irq; | |
1184 | } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { | |
1801ad94 JF |
1185 | dd->pio_only = 1; |
1186 | ||
1187 | irq = platform_get_irq(pdev, 0); | |
1188 | if (irq < 0) { | |
1189 | dev_err(dev, "can't get IRQ resource\n"); | |
62c58f8d | 1190 | err = irq; |
1801ad94 JF |
1191 | goto err_irq; |
1192 | } | |
1193 | ||
bce2a228 | 1194 | err = devm_request_irq(dev, irq, omap_aes_irq, 0, |
1801ad94 JF |
1195 | dev_name(dev), dd); |
1196 | if (err) { | |
1197 | dev_err(dev, "Unable to grab omap-aes IRQ\n"); | |
1198 | goto err_irq; | |
1199 | } | |
1200 | } | |
1201 | ||
ad18cc9d | 1202 | spin_lock_init(&dd->lock); |
537559a5 DK |
1203 | |
1204 | INIT_LIST_HEAD(&dd->list); | |
1205 | spin_lock(&list_lock); | |
1206 | list_add_tail(&dd->list, &dev_list); | |
1207 | spin_unlock(&list_lock); | |
1208 | ||
0d0cda93 TK |
1209 | /* Initialize crypto engine */ |
1210 | dd->engine = crypto_engine_alloc_init(dev, 1); | |
c98ef8db WY |
1211 | if (!dd->engine) { |
1212 | err = -ENOMEM; | |
0d0cda93 | 1213 | goto err_engine; |
c98ef8db | 1214 | } |
0d0cda93 | 1215 | |
0d0cda93 TK |
1216 | err = crypto_engine_start(dd->engine); |
1217 | if (err) | |
1218 | goto err_engine; | |
1219 | ||
f9fb69e7 | 1220 | for (i = 0; i < dd->pdata->algs_info_size; i++) { |
3741bbb2 LV |
1221 | if (!dd->pdata->algs_info[i].registered) { |
1222 | for (j = 0; j < dd->pdata->algs_info[i].size; j++) { | |
1223 | algp = &dd->pdata->algs_info[i].algs_list[j]; | |
f9fb69e7 | 1224 | |
3741bbb2 LV |
1225 | pr_debug("reg alg: %s\n", algp->cra_name); |
1226 | INIT_LIST_HEAD(&algp->cra_list); | |
f9fb69e7 | 1227 | |
3741bbb2 LV |
1228 | err = crypto_register_alg(algp); |
1229 | if (err) | |
1230 | goto err_algs; | |
f9fb69e7 | 1231 | |
3741bbb2 LV |
1232 | dd->pdata->algs_info[i].registered++; |
1233 | } | |
f9fb69e7 | 1234 | } |
537559a5 DK |
1235 | } |
1236 | ||
ad18cc9d TK |
1237 | if (dd->pdata->aead_algs_info && |
1238 | !dd->pdata->aead_algs_info->registered) { | |
1239 | for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { | |
1240 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; | |
1241 | algp = &aalg->base; | |
1242 | ||
1243 | pr_debug("reg alg: %s\n", algp->cra_name); | |
1244 | INIT_LIST_HEAD(&algp->cra_list); | |
1245 | ||
1246 | err = crypto_register_aead(aalg); | |
1247 | if (err) | |
1248 | goto err_aead_algs; | |
1249 | ||
1250 | dd->pdata->aead_algs_info->registered++; | |
1251 | } | |
1252 | } | |
1253 | ||
537c62ca TK |
1254 | err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group); |
1255 | if (err) { | |
1256 | dev_err(dev, "could not create sysfs device attrs\n"); | |
1257 | goto err_aead_algs; | |
1258 | } | |
1259 | ||
537559a5 | 1260 | return 0; |
ad18cc9d TK |
1261 | err_aead_algs: |
1262 | for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { | |
1263 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; | |
1264 | crypto_unregister_aead(aalg); | |
1265 | } | |
537559a5 | 1266 | err_algs: |
f9fb69e7 MG |
1267 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1268 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
1269 | crypto_unregister_alg( | |
1270 | &dd->pdata->algs_info[i].algs_list[j]); | |
da8b29a6 | 1271 | |
0d0cda93 TK |
1272 | err_engine: |
1273 | if (dd->engine) | |
1274 | crypto_engine_exit(dd->engine); | |
1275 | ||
da8b29a6 | 1276 | omap_aes_dma_cleanup(dd); |
1801ad94 | 1277 | err_irq: |
21fe9767 | 1278 | tasklet_kill(&dd->done_task); |
5946c4a5 | 1279 | pm_runtime_disable(dev); |
537559a5 | 1280 | err_res: |
537559a5 DK |
1281 | dd = NULL; |
1282 | err_data: | |
1283 | dev_err(dev, "initialization failed.\n"); | |
1284 | return err; | |
1285 | } | |
1286 | ||
1287 | static int omap_aes_remove(struct platform_device *pdev) | |
1288 | { | |
1289 | struct omap_aes_dev *dd = platform_get_drvdata(pdev); | |
ad18cc9d | 1290 | struct aead_alg *aalg; |
f9fb69e7 | 1291 | int i, j; |
537559a5 DK |
1292 | |
1293 | if (!dd) | |
1294 | return -ENODEV; | |
1295 | ||
1296 | spin_lock(&list_lock); | |
1297 | list_del(&dd->list); | |
1298 | spin_unlock(&list_lock); | |
1299 | ||
f9fb69e7 MG |
1300 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1301 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
1302 | crypto_unregister_alg( | |
1303 | &dd->pdata->algs_info[i].algs_list[j]); | |
537559a5 | 1304 | |
ad18cc9d TK |
1305 | for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) { |
1306 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; | |
1307 | crypto_unregister_aead(aalg); | |
1308 | } | |
1309 | ||
0529900a | 1310 | crypto_engine_exit(dd->engine); |
ad18cc9d | 1311 | |
21fe9767 | 1312 | tasklet_kill(&dd->done_task); |
537559a5 | 1313 | omap_aes_dma_cleanup(dd); |
5946c4a5 | 1314 | pm_runtime_disable(dd->dev); |
537559a5 DK |
1315 | dd = NULL; |
1316 | ||
1317 | return 0; | |
1318 | } | |
1319 | ||
0635fb3a MG |
1320 | #ifdef CONFIG_PM_SLEEP |
1321 | static int omap_aes_suspend(struct device *dev) | |
1322 | { | |
1323 | pm_runtime_put_sync(dev); | |
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | static int omap_aes_resume(struct device *dev) | |
1328 | { | |
1329 | pm_runtime_get_sync(dev); | |
1330 | return 0; | |
1331 | } | |
1332 | #endif | |
1333 | ||
ea7b2843 | 1334 | static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); |
0635fb3a | 1335 | |
537559a5 DK |
1336 | static struct platform_driver omap_aes_driver = { |
1337 | .probe = omap_aes_probe, | |
1338 | .remove = omap_aes_remove, | |
1339 | .driver = { | |
1340 | .name = "omap-aes", | |
0635fb3a | 1341 | .pm = &omap_aes_pm_ops, |
bc69d124 | 1342 | .of_match_table = omap_aes_of_match, |
537559a5 DK |
1343 | }, |
1344 | }; | |
1345 | ||
94e51df9 | 1346 | module_platform_driver(omap_aes_driver); |
537559a5 DK |
1347 | |
1348 | MODULE_DESCRIPTION("OMAP AES hw acceleration support."); | |
1349 | MODULE_LICENSE("GPL v2"); | |
1350 | MODULE_AUTHOR("Dmitry Kasatkin"); | |
1351 |