Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
537559a5 DK |
2 | /* |
3 | * Cryptographic API. | |
4 | * | |
5 | * Support for OMAP AES HW acceleration. | |
6 | * | |
7 | * Copyright (c) 2010 Nokia Corporation | |
8 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
0d35583a | 9 | * Copyright (c) 2011 Texas Instruments Incorporated |
537559a5 DK |
10 | */ |
11 | ||
016af9b5 JF |
12 | #define pr_fmt(fmt) "%20s: " fmt, __func__ |
13 | #define prn(num) pr_debug(#num "=%d\n", num) | |
14 | #define prx(num) pr_debug(#num "=%x\n", num) | |
537559a5 DK |
15 | |
16 | #include <linux/err.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/kernel.h> | |
537559a5 DK |
21 | #include <linux/platform_device.h> |
22 | #include <linux/scatterlist.h> | |
23 | #include <linux/dma-mapping.h> | |
ebedbf79 | 24 | #include <linux/dmaengine.h> |
5946c4a5 | 25 | #include <linux/pm_runtime.h> |
bc69d124 MG |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
28 | #include <linux/of_address.h> | |
537559a5 DK |
29 | #include <linux/io.h> |
30 | #include <linux/crypto.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <crypto/scatterwalk.h> | |
33 | #include <crypto/aes.h> | |
cb3f3817 | 34 | #include <crypto/gcm.h> |
2589ad84 | 35 | #include <crypto/engine.h> |
9fcb191a | 36 | #include <crypto/internal/skcipher.h> |
ad18cc9d | 37 | #include <crypto/internal/aead.h> |
537559a5 | 38 | |
afc2dc13 | 39 | #include "omap-crypto.h" |
5b3d4d2e | 40 | #include "omap-aes.h" |
537559a5 DK |
41 | |
42 | /* keep registered devices data here */ | |
43 | static LIST_HEAD(dev_list); | |
44 | static DEFINE_SPINLOCK(list_lock); | |
45 | ||
537c62ca TK |
46 | static int aes_fallback_sz = 200; |
47 | ||
016af9b5 JF |
48 | #ifdef DEBUG |
49 | #define omap_aes_read(dd, offset) \ | |
50 | ({ \ | |
51 | int _read_ret; \ | |
52 | _read_ret = __raw_readl(dd->io_base + offset); \ | |
53 | pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ | |
54 | offset, _read_ret); \ | |
55 | _read_ret; \ | |
56 | }) | |
57 | #else | |
d695bfd6 | 58 | inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) |
537559a5 DK |
59 | { |
60 | return __raw_readl(dd->io_base + offset); | |
61 | } | |
016af9b5 JF |
62 | #endif |
63 | ||
64 | #ifdef DEBUG | |
65 | #define omap_aes_write(dd, offset, value) \ | |
66 | do { \ | |
67 | pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ | |
68 | offset, value); \ | |
69 | __raw_writel(value, dd->io_base + offset); \ | |
70 | } while (0) | |
71 | #else | |
d695bfd6 | 72 | inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, |
537559a5 DK |
73 | u32 value) |
74 | { | |
75 | __raw_writel(value, dd->io_base + offset); | |
76 | } | |
016af9b5 | 77 | #endif |
537559a5 DK |
78 | |
79 | static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, | |
80 | u32 value, u32 mask) | |
81 | { | |
82 | u32 val; | |
83 | ||
84 | val = omap_aes_read(dd, offset); | |
85 | val &= ~mask; | |
86 | val |= value; | |
87 | omap_aes_write(dd, offset, val); | |
88 | } | |
89 | ||
90 | static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, | |
91 | u32 *value, int count) | |
92 | { | |
93 | for (; count--; value++, offset += 4) | |
94 | omap_aes_write(dd, offset, *value); | |
95 | } | |
96 | ||
537559a5 DK |
97 | static int omap_aes_hw_init(struct omap_aes_dev *dd) |
98 | { | |
f303b455 TK |
99 | int err; |
100 | ||
537559a5 | 101 | if (!(dd->flags & FLAGS_INIT)) { |
eeb2b202 | 102 | dd->flags |= FLAGS_INIT; |
21fe9767 | 103 | dd->err = 0; |
537559a5 DK |
104 | } |
105 | ||
f303b455 TK |
106 | err = pm_runtime_get_sync(dd->dev); |
107 | if (err < 0) { | |
108 | dev_err(dd->dev, "failed to get sync: %d\n", err); | |
109 | return err; | |
110 | } | |
111 | ||
eeb2b202 | 112 | return 0; |
537559a5 DK |
113 | } |
114 | ||
ad18cc9d TK |
115 | void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) |
116 | { | |
117 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); | |
118 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); | |
119 | dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); | |
120 | } | |
121 | ||
d695bfd6 | 122 | int omap_aes_write_ctrl(struct omap_aes_dev *dd) |
537559a5 | 123 | { |
ad18cc9d | 124 | struct omap_aes_reqctx *rctx; |
537559a5 | 125 | unsigned int key32; |
67a730ce | 126 | int i, err; |
5396c6c0 | 127 | u32 val; |
537559a5 | 128 | |
21fe9767 DK |
129 | err = omap_aes_hw_init(dd); |
130 | if (err) | |
131 | return err; | |
132 | ||
537559a5 | 133 | key32 = dd->ctx->keylen / sizeof(u32); |
67a730ce | 134 | |
ad18cc9d TK |
135 | /* RESET the key as previous HASH keys should not get affected*/ |
136 | if (dd->flags & FLAGS_GCM) | |
137 | for (i = 0; i < 0x40; i = i + 4) | |
138 | omap_aes_write(dd, i, 0x0); | |
139 | ||
537559a5 | 140 | for (i = 0; i < key32; i++) { |
0d35583a | 141 | omap_aes_write(dd, AES_REG_KEY(dd, i), |
537559a5 DK |
142 | __le32_to_cpu(dd->ctx->key[i])); |
143 | } | |
537559a5 | 144 | |
f9fb69e7 | 145 | if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info) |
0d35583a | 146 | omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4); |
67a730ce | 147 | |
ad18cc9d TK |
148 | if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { |
149 | rctx = aead_request_ctx(dd->aead_req); | |
150 | omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); | |
151 | } | |
152 | ||
67a730ce DK |
153 | val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); |
154 | if (dd->flags & FLAGS_CBC) | |
155 | val |= AES_REG_CTRL_CBC; | |
ad18cc9d TK |
156 | |
157 | if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) | |
8ed49c76 | 158 | val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; |
5396c6c0 | 159 | |
ad18cc9d TK |
160 | if (dd->flags & FLAGS_GCM) |
161 | val |= AES_REG_CTRL_GCM; | |
162 | ||
67a730ce DK |
163 | if (dd->flags & FLAGS_ENCRYPT) |
164 | val |= AES_REG_CTRL_DIRECTION; | |
537559a5 | 165 | |
5396c6c0 | 166 | omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); |
537559a5 | 167 | |
21fe9767 | 168 | return 0; |
537559a5 DK |
169 | } |
170 | ||
0d35583a MG |
171 | static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) |
172 | { | |
173 | u32 mask, val; | |
174 | ||
175 | val = dd->pdata->dma_start; | |
176 | ||
177 | if (dd->dma_lch_out != NULL) | |
178 | val |= dd->pdata->dma_enable_out; | |
179 | if (dd->dma_lch_in != NULL) | |
180 | val |= dd->pdata->dma_enable_in; | |
181 | ||
182 | mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | | |
183 | dd->pdata->dma_start; | |
184 | ||
185 | omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); | |
186 | ||
187 | } | |
188 | ||
189 | static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) | |
190 | { | |
191 | omap_aes_write(dd, AES_REG_LENGTH_N(0), length); | |
192 | omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); | |
ad18cc9d TK |
193 | if (dd->flags & FLAGS_GCM) |
194 | omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); | |
0d35583a MG |
195 | |
196 | omap_aes_dma_trigger_omap2(dd, length); | |
197 | } | |
198 | ||
199 | static void omap_aes_dma_stop(struct omap_aes_dev *dd) | |
200 | { | |
201 | u32 mask; | |
202 | ||
203 | mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | | |
204 | dd->pdata->dma_start; | |
205 | ||
206 | omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); | |
207 | } | |
208 | ||
d695bfd6 | 209 | struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) |
537559a5 | 210 | { |
164f3ef3 | 211 | struct omap_aes_dev *dd; |
537559a5 DK |
212 | |
213 | spin_lock_bh(&list_lock); | |
164f3ef3 LV |
214 | dd = list_first_entry(&dev_list, struct omap_aes_dev, list); |
215 | list_move_tail(&dd->list, &dev_list); | |
619ce700 | 216 | rctx->dd = dd; |
537559a5 DK |
217 | spin_unlock_bh(&list_lock); |
218 | ||
219 | return dd; | |
220 | } | |
221 | ||
ebedbf79 MG |
222 | static void omap_aes_dma_out_callback(void *data) |
223 | { | |
224 | struct omap_aes_dev *dd = data; | |
225 | ||
226 | /* dma_lch_out - completed */ | |
227 | tasklet_schedule(&dd->done_task); | |
228 | } | |
537559a5 DK |
229 | |
230 | static int omap_aes_dma_init(struct omap_aes_dev *dd) | |
231 | { | |
da8b29a6 | 232 | int err; |
537559a5 | 233 | |
ebedbf79 MG |
234 | dd->dma_lch_out = NULL; |
235 | dd->dma_lch_in = NULL; | |
537559a5 | 236 | |
da8b29a6 PU |
237 | dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); |
238 | if (IS_ERR(dd->dma_lch_in)) { | |
ebedbf79 | 239 | dev_err(dd->dev, "Unable to request in DMA channel\n"); |
da8b29a6 | 240 | return PTR_ERR(dd->dma_lch_in); |
ebedbf79 MG |
241 | } |
242 | ||
da8b29a6 PU |
243 | dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); |
244 | if (IS_ERR(dd->dma_lch_out)) { | |
ebedbf79 | 245 | dev_err(dd->dev, "Unable to request out DMA channel\n"); |
da8b29a6 | 246 | err = PTR_ERR(dd->dma_lch_out); |
ebedbf79 MG |
247 | goto err_dma_out; |
248 | } | |
537559a5 | 249 | |
537559a5 DK |
250 | return 0; |
251 | ||
252 | err_dma_out: | |
ebedbf79 | 253 | dma_release_channel(dd->dma_lch_in); |
da8b29a6 | 254 | |
537559a5 DK |
255 | return err; |
256 | } | |
257 | ||
258 | static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) | |
259 | { | |
da8b29a6 PU |
260 | if (dd->pio_only) |
261 | return; | |
262 | ||
ebedbf79 MG |
263 | dma_release_channel(dd->dma_lch_out); |
264 | dma_release_channel(dd->dma_lch_in); | |
537559a5 DK |
265 | } |
266 | ||
619ce700 TK |
267 | static int omap_aes_crypt_dma(struct omap_aes_dev *dd, |
268 | struct scatterlist *in_sg, | |
269 | struct scatterlist *out_sg, | |
270 | int in_sg_len, int out_sg_len) | |
537559a5 | 271 | { |
ebedbf79 MG |
272 | struct dma_async_tx_descriptor *tx_in, *tx_out; |
273 | struct dma_slave_config cfg; | |
4b645c94 | 274 | int ret; |
537559a5 | 275 | |
98837abc JF |
276 | if (dd->pio_only) { |
277 | scatterwalk_start(&dd->in_walk, dd->in_sg); | |
278 | scatterwalk_start(&dd->out_walk, dd->out_sg); | |
279 | ||
280 | /* Enable DATAIN interrupt and let it take | |
281 | care of the rest */ | |
282 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); | |
283 | return 0; | |
284 | } | |
285 | ||
0a641712 JF |
286 | dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); |
287 | ||
ebedbf79 MG |
288 | memset(&cfg, 0, sizeof(cfg)); |
289 | ||
0d35583a MG |
290 | cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); |
291 | cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); | |
ebedbf79 MG |
292 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
293 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
294 | cfg.src_maxburst = DST_MAXBURST; | |
295 | cfg.dst_maxburst = DST_MAXBURST; | |
296 | ||
297 | /* IN */ | |
298 | ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); | |
299 | if (ret) { | |
300 | dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", | |
301 | ret); | |
302 | return ret; | |
303 | } | |
304 | ||
4b645c94 | 305 | tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, |
ebedbf79 MG |
306 | DMA_MEM_TO_DEV, |
307 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
308 | if (!tx_in) { | |
309 | dev_err(dd->dev, "IN prep_slave_sg() failed\n"); | |
310 | return -EINVAL; | |
311 | } | |
312 | ||
313 | /* No callback necessary */ | |
314 | tx_in->callback_param = dd; | |
315 | ||
316 | /* OUT */ | |
317 | ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); | |
318 | if (ret) { | |
319 | dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", | |
320 | ret); | |
321 | return ret; | |
322 | } | |
323 | ||
4b645c94 | 324 | tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, |
ebedbf79 MG |
325 | DMA_DEV_TO_MEM, |
326 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
327 | if (!tx_out) { | |
328 | dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); | |
329 | return -EINVAL; | |
330 | } | |
331 | ||
ad18cc9d TK |
332 | if (dd->flags & FLAGS_GCM) |
333 | tx_out->callback = omap_aes_gcm_dma_out_callback; | |
334 | else | |
335 | tx_out->callback = omap_aes_dma_out_callback; | |
ebedbf79 MG |
336 | tx_out->callback_param = dd; |
337 | ||
338 | dmaengine_submit(tx_in); | |
339 | dmaengine_submit(tx_out); | |
340 | ||
341 | dma_async_issue_pending(dd->dma_lch_in); | |
342 | dma_async_issue_pending(dd->dma_lch_out); | |
537559a5 | 343 | |
0d35583a | 344 | /* start DMA */ |
4b645c94 | 345 | dd->pdata->trigger(dd, dd->total); |
83ea7e0f | 346 | |
537559a5 DK |
347 | return 0; |
348 | } | |
349 | ||
d695bfd6 | 350 | int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) |
537559a5 | 351 | { |
4b645c94 | 352 | int err; |
537559a5 DK |
353 | |
354 | pr_debug("total: %d\n", dd->total); | |
355 | ||
98837abc JF |
356 | if (!dd->pio_only) { |
357 | err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, | |
358 | DMA_TO_DEVICE); | |
359 | if (!err) { | |
360 | dev_err(dd->dev, "dma_map_sg() error\n"); | |
361 | return -EINVAL; | |
362 | } | |
537559a5 | 363 | |
98837abc JF |
364 | err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, |
365 | DMA_FROM_DEVICE); | |
366 | if (!err) { | |
367 | dev_err(dd->dev, "dma_map_sg() error\n"); | |
368 | return -EINVAL; | |
369 | } | |
537559a5 DK |
370 | } |
371 | ||
619ce700 | 372 | err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, |
4b645c94 | 373 | dd->out_sg_len); |
98837abc | 374 | if (err && !dd->pio_only) { |
4b645c94 JF |
375 | dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
376 | dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, | |
377 | DMA_FROM_DEVICE); | |
21fe9767 | 378 | } |
537559a5 DK |
379 | |
380 | return err; | |
381 | } | |
382 | ||
383 | static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) | |
384 | { | |
21fe9767 | 385 | struct ablkcipher_request *req = dd->req; |
537559a5 DK |
386 | |
387 | pr_debug("err: %d\n", err); | |
388 | ||
c21c8b89 | 389 | crypto_finalize_ablkcipher_request(dd->engine, req, err); |
f303b455 TK |
390 | |
391 | pm_runtime_mark_last_busy(dd->dev); | |
392 | pm_runtime_put_autosuspend(dd->dev); | |
537559a5 DK |
393 | } |
394 | ||
d695bfd6 | 395 | int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) |
537559a5 | 396 | { |
537559a5 DK |
397 | pr_debug("total: %d\n", dd->total); |
398 | ||
0d35583a | 399 | omap_aes_dma_stop(dd); |
537559a5 | 400 | |
537559a5 | 401 | |
16f080aa | 402 | return 0; |
537559a5 DK |
403 | } |
404 | ||
21fe9767 | 405 | static int omap_aes_handle_queue(struct omap_aes_dev *dd, |
0529900a | 406 | struct ablkcipher_request *req) |
537559a5 | 407 | { |
eeb2b202 | 408 | if (req) |
c21c8b89 | 409 | return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req); |
537559a5 | 410 | |
0529900a BW |
411 | return 0; |
412 | } | |
537559a5 | 413 | |
0529900a | 414 | static int omap_aes_prepare_req(struct crypto_engine *engine, |
c21c8b89 | 415 | void *areq) |
0529900a | 416 | { |
c21c8b89 | 417 | struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base); |
0529900a BW |
418 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( |
419 | crypto_ablkcipher_reqtfm(req)); | |
619ce700 TK |
420 | struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); |
421 | struct omap_aes_dev *dd = rctx->dd; | |
afc2dc13 TK |
422 | int ret; |
423 | u16 flags; | |
537559a5 | 424 | |
0529900a BW |
425 | if (!dd) |
426 | return -ENODEV; | |
537559a5 | 427 | |
537559a5 DK |
428 | /* assign new request to device */ |
429 | dd->req = req; | |
430 | dd->total = req->nbytes; | |
6242332f | 431 | dd->total_save = req->nbytes; |
537559a5 | 432 | dd->in_sg = req->src; |
537559a5 | 433 | dd->out_sg = req->dst; |
afc2dc13 TK |
434 | dd->orig_out = req->dst; |
435 | ||
436 | flags = OMAP_CRYPTO_COPY_DATA; | |
437 | if (req->src == req->dst) | |
438 | flags |= OMAP_CRYPTO_FORCE_COPY; | |
439 | ||
440 | ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, | |
ad18cc9d | 441 | dd->in_sgl, flags, |
afc2dc13 TK |
442 | FLAGS_IN_DATA_ST_SHIFT, &dd->flags); |
443 | if (ret) | |
444 | return ret; | |
445 | ||
446 | ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, | |
447 | &dd->out_sgl, 0, | |
448 | FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); | |
449 | if (ret) | |
450 | return ret; | |
537559a5 | 451 | |
7c001a86 HX |
452 | dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); |
453 | if (dd->in_sg_len < 0) | |
454 | return dd->in_sg_len; | |
455 | ||
456 | dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); | |
457 | if (dd->out_sg_len < 0) | |
458 | return dd->out_sg_len; | |
459 | ||
537559a5 DK |
460 | rctx->mode &= FLAGS_MODE_MASK; |
461 | dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; | |
462 | ||
67a730ce | 463 | dd->ctx = ctx; |
619ce700 | 464 | rctx->dd = dd; |
537559a5 | 465 | |
0529900a BW |
466 | return omap_aes_write_ctrl(dd); |
467 | } | |
eeb2b202 | 468 | |
0529900a | 469 | static int omap_aes_crypt_req(struct crypto_engine *engine, |
c21c8b89 | 470 | void *areq) |
0529900a | 471 | { |
c21c8b89 | 472 | struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base); |
619ce700 TK |
473 | struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); |
474 | struct omap_aes_dev *dd = rctx->dd; | |
0529900a BW |
475 | |
476 | if (!dd) | |
477 | return -ENODEV; | |
478 | ||
479 | return omap_aes_crypt_dma_start(dd); | |
537559a5 DK |
480 | } |
481 | ||
21fe9767 | 482 | static void omap_aes_done_task(unsigned long data) |
537559a5 DK |
483 | { |
484 | struct omap_aes_dev *dd = (struct omap_aes_dev *)data; | |
537559a5 | 485 | |
4b645c94 | 486 | pr_debug("enter done_task\n"); |
21fe9767 | 487 | |
98837abc JF |
488 | if (!dd->pio_only) { |
489 | dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, | |
490 | DMA_FROM_DEVICE); | |
6242332f JF |
491 | dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
492 | dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, | |
493 | DMA_FROM_DEVICE); | |
98837abc JF |
494 | omap_aes_crypt_dma_stop(dd); |
495 | } | |
6242332f | 496 | |
ad18cc9d | 497 | omap_crypto_cleanup(dd->in_sgl, NULL, 0, dd->total_save, |
afc2dc13 | 498 | FLAGS_IN_DATA_ST_SHIFT, dd->flags); |
6242332f | 499 | |
afc2dc13 TK |
500 | omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save, |
501 | FLAGS_OUT_DATA_ST_SHIFT, dd->flags); | |
6242332f | 502 | |
4b645c94 | 503 | omap_aes_finish_req(dd, 0); |
537559a5 DK |
504 | |
505 | pr_debug("exit\n"); | |
506 | } | |
507 | ||
508 | static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) | |
509 | { | |
510 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( | |
511 | crypto_ablkcipher_reqtfm(req)); | |
512 | struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); | |
513 | struct omap_aes_dev *dd; | |
9fcb191a | 514 | int ret; |
537559a5 DK |
515 | |
516 | pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, | |
517 | !!(mode & FLAGS_ENCRYPT), | |
518 | !!(mode & FLAGS_CBC)); | |
519 | ||
537c62ca | 520 | if (req->nbytes < aes_fallback_sz) { |
e87f203c | 521 | SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); |
9fcb191a | 522 | |
e87f203c | 523 | skcipher_request_set_sync_tfm(subreq, ctx->fallback); |
9fcb191a LV |
524 | skcipher_request_set_callback(subreq, req->base.flags, NULL, |
525 | NULL); | |
526 | skcipher_request_set_crypt(subreq, req->src, req->dst, | |
527 | req->nbytes, req->info); | |
528 | ||
529 | if (mode & FLAGS_ENCRYPT) | |
530 | ret = crypto_skcipher_encrypt(subreq); | |
531 | else | |
532 | ret = crypto_skcipher_decrypt(subreq); | |
533 | ||
534 | skcipher_request_zero(subreq); | |
535 | return ret; | |
536 | } | |
619ce700 | 537 | dd = omap_aes_find_dev(rctx); |
537559a5 DK |
538 | if (!dd) |
539 | return -ENODEV; | |
540 | ||
541 | rctx->mode = mode; | |
542 | ||
21fe9767 | 543 | return omap_aes_handle_queue(dd, req); |
537559a5 DK |
544 | } |
545 | ||
546 | /* ********************** ALG API ************************************ */ | |
547 | ||
548 | static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, | |
549 | unsigned int keylen) | |
550 | { | |
551 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); | |
9fcb191a | 552 | int ret; |
537559a5 DK |
553 | |
554 | if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && | |
555 | keylen != AES_KEYSIZE_256) | |
556 | return -EINVAL; | |
557 | ||
558 | pr_debug("enter, keylen: %d\n", keylen); | |
559 | ||
560 | memcpy(ctx->key, key, keylen); | |
561 | ctx->keylen = keylen; | |
537559a5 | 562 | |
e87f203c KC |
563 | crypto_sync_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); |
564 | crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & | |
9fcb191a LV |
565 | CRYPTO_TFM_REQ_MASK); |
566 | ||
e87f203c | 567 | ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen); |
9fcb191a LV |
568 | if (!ret) |
569 | return 0; | |
570 | ||
537559a5 DK |
571 | return 0; |
572 | } | |
573 | ||
574 | static int omap_aes_ecb_encrypt(struct ablkcipher_request *req) | |
575 | { | |
576 | return omap_aes_crypt(req, FLAGS_ENCRYPT); | |
577 | } | |
578 | ||
579 | static int omap_aes_ecb_decrypt(struct ablkcipher_request *req) | |
580 | { | |
581 | return omap_aes_crypt(req, 0); | |
582 | } | |
583 | ||
584 | static int omap_aes_cbc_encrypt(struct ablkcipher_request *req) | |
585 | { | |
586 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); | |
587 | } | |
588 | ||
589 | static int omap_aes_cbc_decrypt(struct ablkcipher_request *req) | |
590 | { | |
591 | return omap_aes_crypt(req, FLAGS_CBC); | |
592 | } | |
593 | ||
f9fb69e7 MG |
594 | static int omap_aes_ctr_encrypt(struct ablkcipher_request *req) |
595 | { | |
596 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); | |
597 | } | |
598 | ||
599 | static int omap_aes_ctr_decrypt(struct ablkcipher_request *req) | |
600 | { | |
601 | return omap_aes_crypt(req, FLAGS_CTR); | |
602 | } | |
603 | ||
c21c8b89 CL |
604 | static int omap_aes_prepare_req(struct crypto_engine *engine, |
605 | void *req); | |
606 | static int omap_aes_crypt_req(struct crypto_engine *engine, | |
607 | void *req); | |
608 | ||
537559a5 DK |
609 | static int omap_aes_cra_init(struct crypto_tfm *tfm) |
610 | { | |
9fcb191a | 611 | const char *name = crypto_tfm_alg_name(tfm); |
9fcb191a | 612 | struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); |
e87f203c | 613 | struct crypto_sync_skcipher *blk; |
9fcb191a | 614 | |
e87f203c | 615 | blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); |
9fcb191a LV |
616 | if (IS_ERR(blk)) |
617 | return PTR_ERR(blk); | |
618 | ||
619 | ctx->fallback = blk; | |
620 | ||
537559a5 DK |
621 | tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); |
622 | ||
c21c8b89 CL |
623 | ctx->enginectx.op.prepare_request = omap_aes_prepare_req; |
624 | ctx->enginectx.op.unprepare_request = NULL; | |
625 | ctx->enginectx.op.do_one_request = omap_aes_crypt_req; | |
626 | ||
537559a5 DK |
627 | return 0; |
628 | } | |
629 | ||
ad18cc9d TK |
630 | static int omap_aes_gcm_cra_init(struct crypto_aead *tfm) |
631 | { | |
632 | struct omap_aes_dev *dd = NULL; | |
633 | struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); | |
634 | int err; | |
635 | ||
636 | /* Find AES device, currently picks the first device */ | |
637 | spin_lock_bh(&list_lock); | |
638 | list_for_each_entry(dd, &dev_list, list) { | |
639 | break; | |
640 | } | |
641 | spin_unlock_bh(&list_lock); | |
642 | ||
643 | err = pm_runtime_get_sync(dd->dev); | |
644 | if (err < 0) { | |
645 | dev_err(dd->dev, "%s: failed to get_sync(%d)\n", | |
646 | __func__, err); | |
647 | return err; | |
648 | } | |
649 | ||
650 | tfm->reqsize = sizeof(struct omap_aes_reqctx); | |
651 | ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0); | |
652 | if (IS_ERR(ctx->ctr)) { | |
653 | pr_warn("could not load aes driver for encrypting IV\n"); | |
654 | return PTR_ERR(ctx->ctr); | |
655 | } | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
537559a5 DK |
660 | static void omap_aes_cra_exit(struct crypto_tfm *tfm) |
661 | { | |
9fcb191a LV |
662 | struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); |
663 | ||
664 | if (ctx->fallback) | |
e87f203c | 665 | crypto_free_sync_skcipher(ctx->fallback); |
9fcb191a LV |
666 | |
667 | ctx->fallback = NULL; | |
537559a5 DK |
668 | } |
669 | ||
ad18cc9d TK |
670 | static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm) |
671 | { | |
672 | struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); | |
673 | ||
674 | omap_aes_cra_exit(crypto_aead_tfm(tfm)); | |
675 | ||
676 | if (ctx->ctr) | |
677 | crypto_free_skcipher(ctx->ctr); | |
678 | } | |
679 | ||
537559a5 DK |
680 | /* ********************** ALGS ************************************ */ |
681 | ||
f9fb69e7 | 682 | static struct crypto_alg algs_ecb_cbc[] = { |
537559a5 DK |
683 | { |
684 | .cra_name = "ecb(aes)", | |
685 | .cra_driver_name = "ecb-aes-omap", | |
6e2e3d1d | 686 | .cra_priority = 300, |
d912bb76 NM |
687 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
688 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
9fcb191a | 689 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, |
537559a5 DK |
690 | .cra_blocksize = AES_BLOCK_SIZE, |
691 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
efce41b6 | 692 | .cra_alignmask = 0, |
537559a5 DK |
693 | .cra_type = &crypto_ablkcipher_type, |
694 | .cra_module = THIS_MODULE, | |
695 | .cra_init = omap_aes_cra_init, | |
696 | .cra_exit = omap_aes_cra_exit, | |
697 | .cra_u.ablkcipher = { | |
698 | .min_keysize = AES_MIN_KEY_SIZE, | |
699 | .max_keysize = AES_MAX_KEY_SIZE, | |
700 | .setkey = omap_aes_setkey, | |
701 | .encrypt = omap_aes_ecb_encrypt, | |
702 | .decrypt = omap_aes_ecb_decrypt, | |
703 | } | |
704 | }, | |
705 | { | |
706 | .cra_name = "cbc(aes)", | |
707 | .cra_driver_name = "cbc-aes-omap", | |
6e2e3d1d | 708 | .cra_priority = 300, |
d912bb76 NM |
709 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
710 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
9fcb191a | 711 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, |
537559a5 DK |
712 | .cra_blocksize = AES_BLOCK_SIZE, |
713 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
efce41b6 | 714 | .cra_alignmask = 0, |
537559a5 DK |
715 | .cra_type = &crypto_ablkcipher_type, |
716 | .cra_module = THIS_MODULE, | |
717 | .cra_init = omap_aes_cra_init, | |
718 | .cra_exit = omap_aes_cra_exit, | |
719 | .cra_u.ablkcipher = { | |
720 | .min_keysize = AES_MIN_KEY_SIZE, | |
721 | .max_keysize = AES_MAX_KEY_SIZE, | |
722 | .ivsize = AES_BLOCK_SIZE, | |
723 | .setkey = omap_aes_setkey, | |
724 | .encrypt = omap_aes_cbc_encrypt, | |
725 | .decrypt = omap_aes_cbc_decrypt, | |
726 | } | |
727 | } | |
728 | }; | |
729 | ||
f9fb69e7 MG |
730 | static struct crypto_alg algs_ctr[] = { |
731 | { | |
732 | .cra_name = "ctr(aes)", | |
733 | .cra_driver_name = "ctr-aes-omap", | |
6e2e3d1d | 734 | .cra_priority = 300, |
f9fb69e7 MG |
735 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
736 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
9fcb191a | 737 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, |
f9fb69e7 MG |
738 | .cra_blocksize = AES_BLOCK_SIZE, |
739 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
740 | .cra_alignmask = 0, | |
741 | .cra_type = &crypto_ablkcipher_type, | |
742 | .cra_module = THIS_MODULE, | |
743 | .cra_init = omap_aes_cra_init, | |
744 | .cra_exit = omap_aes_cra_exit, | |
745 | .cra_u.ablkcipher = { | |
746 | .min_keysize = AES_MIN_KEY_SIZE, | |
747 | .max_keysize = AES_MAX_KEY_SIZE, | |
f9fb69e7 MG |
748 | .ivsize = AES_BLOCK_SIZE, |
749 | .setkey = omap_aes_setkey, | |
750 | .encrypt = omap_aes_ctr_encrypt, | |
751 | .decrypt = omap_aes_ctr_decrypt, | |
752 | } | |
753 | } , | |
754 | }; | |
755 | ||
756 | static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { | |
757 | { | |
758 | .algs_list = algs_ecb_cbc, | |
759 | .size = ARRAY_SIZE(algs_ecb_cbc), | |
760 | }, | |
761 | }; | |
762 | ||
ad18cc9d TK |
763 | static struct aead_alg algs_aead_gcm[] = { |
764 | { | |
765 | .base = { | |
766 | .cra_name = "gcm(aes)", | |
767 | .cra_driver_name = "gcm-aes-omap", | |
768 | .cra_priority = 300, | |
769 | .cra_flags = CRYPTO_ALG_ASYNC | | |
770 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
771 | .cra_blocksize = 1, | |
772 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
773 | .cra_alignmask = 0xf, | |
774 | .cra_module = THIS_MODULE, | |
775 | }, | |
776 | .init = omap_aes_gcm_cra_init, | |
777 | .exit = omap_aes_gcm_cra_exit, | |
cb3f3817 | 778 | .ivsize = GCM_AES_IV_SIZE, |
ad18cc9d TK |
779 | .maxauthsize = AES_BLOCK_SIZE, |
780 | .setkey = omap_aes_gcm_setkey, | |
781 | .encrypt = omap_aes_gcm_encrypt, | |
782 | .decrypt = omap_aes_gcm_decrypt, | |
783 | }, | |
784 | { | |
785 | .base = { | |
786 | .cra_name = "rfc4106(gcm(aes))", | |
787 | .cra_driver_name = "rfc4106-gcm-aes-omap", | |
788 | .cra_priority = 300, | |
789 | .cra_flags = CRYPTO_ALG_ASYNC | | |
790 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
791 | .cra_blocksize = 1, | |
792 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
793 | .cra_alignmask = 0xf, | |
794 | .cra_module = THIS_MODULE, | |
795 | }, | |
796 | .init = omap_aes_gcm_cra_init, | |
797 | .exit = omap_aes_gcm_cra_exit, | |
798 | .maxauthsize = AES_BLOCK_SIZE, | |
cb3f3817 | 799 | .ivsize = GCM_RFC4106_IV_SIZE, |
ad18cc9d TK |
800 | .setkey = omap_aes_4106gcm_setkey, |
801 | .encrypt = omap_aes_4106gcm_encrypt, | |
802 | .decrypt = omap_aes_4106gcm_decrypt, | |
803 | }, | |
804 | }; | |
805 | ||
806 | static struct omap_aes_aead_algs omap_aes_aead_info = { | |
807 | .algs_list = algs_aead_gcm, | |
808 | .size = ARRAY_SIZE(algs_aead_gcm), | |
809 | }; | |
810 | ||
0d35583a | 811 | static const struct omap_aes_pdata omap_aes_pdata_omap2 = { |
f9fb69e7 MG |
812 | .algs_info = omap_aes_algs_info_ecb_cbc, |
813 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), | |
0d35583a MG |
814 | .trigger = omap_aes_dma_trigger_omap2, |
815 | .key_ofs = 0x1c, | |
816 | .iv_ofs = 0x20, | |
817 | .ctrl_ofs = 0x30, | |
818 | .data_ofs = 0x34, | |
819 | .rev_ofs = 0x44, | |
820 | .mask_ofs = 0x48, | |
821 | .dma_enable_in = BIT(2), | |
822 | .dma_enable_out = BIT(3), | |
823 | .dma_start = BIT(5), | |
824 | .major_mask = 0xf0, | |
825 | .major_shift = 4, | |
826 | .minor_mask = 0x0f, | |
827 | .minor_shift = 0, | |
828 | }; | |
829 | ||
bc69d124 | 830 | #ifdef CONFIG_OF |
f9fb69e7 MG |
831 | static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { |
832 | { | |
833 | .algs_list = algs_ecb_cbc, | |
834 | .size = ARRAY_SIZE(algs_ecb_cbc), | |
835 | }, | |
836 | { | |
837 | .algs_list = algs_ctr, | |
838 | .size = ARRAY_SIZE(algs_ctr), | |
839 | }, | |
840 | }; | |
841 | ||
842 | static const struct omap_aes_pdata omap_aes_pdata_omap3 = { | |
843 | .algs_info = omap_aes_algs_info_ecb_cbc_ctr, | |
844 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), | |
845 | .trigger = omap_aes_dma_trigger_omap2, | |
846 | .key_ofs = 0x1c, | |
847 | .iv_ofs = 0x20, | |
848 | .ctrl_ofs = 0x30, | |
849 | .data_ofs = 0x34, | |
850 | .rev_ofs = 0x44, | |
851 | .mask_ofs = 0x48, | |
852 | .dma_enable_in = BIT(2), | |
853 | .dma_enable_out = BIT(3), | |
854 | .dma_start = BIT(5), | |
855 | .major_mask = 0xf0, | |
856 | .major_shift = 4, | |
857 | .minor_mask = 0x0f, | |
858 | .minor_shift = 0, | |
859 | }; | |
860 | ||
0d35583a | 861 | static const struct omap_aes_pdata omap_aes_pdata_omap4 = { |
f9fb69e7 MG |
862 | .algs_info = omap_aes_algs_info_ecb_cbc_ctr, |
863 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), | |
ad18cc9d | 864 | .aead_algs_info = &omap_aes_aead_info, |
0d35583a MG |
865 | .trigger = omap_aes_dma_trigger_omap4, |
866 | .key_ofs = 0x3c, | |
867 | .iv_ofs = 0x40, | |
868 | .ctrl_ofs = 0x50, | |
869 | .data_ofs = 0x60, | |
870 | .rev_ofs = 0x80, | |
871 | .mask_ofs = 0x84, | |
67216756 JF |
872 | .irq_status_ofs = 0x8c, |
873 | .irq_enable_ofs = 0x90, | |
0d35583a MG |
874 | .dma_enable_in = BIT(5), |
875 | .dma_enable_out = BIT(6), | |
876 | .major_mask = 0x0700, | |
877 | .major_shift = 8, | |
878 | .minor_mask = 0x003f, | |
879 | .minor_shift = 0, | |
880 | }; | |
881 | ||
1bf95cca JF |
882 | static irqreturn_t omap_aes_irq(int irq, void *dev_id) |
883 | { | |
884 | struct omap_aes_dev *dd = dev_id; | |
885 | u32 status, i; | |
886 | u32 *src, *dst; | |
887 | ||
888 | status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); | |
889 | if (status & AES_REG_IRQ_DATA_IN) { | |
890 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); | |
891 | ||
892 | BUG_ON(!dd->in_sg); | |
893 | ||
894 | BUG_ON(_calc_walked(in) > dd->in_sg->length); | |
895 | ||
896 | src = sg_virt(dd->in_sg) + _calc_walked(in); | |
897 | ||
898 | for (i = 0; i < AES_BLOCK_WORDS; i++) { | |
899 | omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); | |
900 | ||
901 | scatterwalk_advance(&dd->in_walk, 4); | |
902 | if (dd->in_sg->length == _calc_walked(in)) { | |
5be4d4c9 | 903 | dd->in_sg = sg_next(dd->in_sg); |
1bf95cca JF |
904 | if (dd->in_sg) { |
905 | scatterwalk_start(&dd->in_walk, | |
906 | dd->in_sg); | |
907 | src = sg_virt(dd->in_sg) + | |
908 | _calc_walked(in); | |
909 | } | |
910 | } else { | |
911 | src++; | |
912 | } | |
913 | } | |
914 | ||
915 | /* Clear IRQ status */ | |
916 | status &= ~AES_REG_IRQ_DATA_IN; | |
917 | omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); | |
918 | ||
919 | /* Enable DATA_OUT interrupt */ | |
920 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); | |
921 | ||
922 | } else if (status & AES_REG_IRQ_DATA_OUT) { | |
923 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); | |
924 | ||
925 | BUG_ON(!dd->out_sg); | |
926 | ||
927 | BUG_ON(_calc_walked(out) > dd->out_sg->length); | |
928 | ||
929 | dst = sg_virt(dd->out_sg) + _calc_walked(out); | |
930 | ||
931 | for (i = 0; i < AES_BLOCK_WORDS; i++) { | |
932 | *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); | |
933 | scatterwalk_advance(&dd->out_walk, 4); | |
934 | if (dd->out_sg->length == _calc_walked(out)) { | |
5be4d4c9 | 935 | dd->out_sg = sg_next(dd->out_sg); |
1bf95cca JF |
936 | if (dd->out_sg) { |
937 | scatterwalk_start(&dd->out_walk, | |
938 | dd->out_sg); | |
939 | dst = sg_virt(dd->out_sg) + | |
940 | _calc_walked(out); | |
941 | } | |
942 | } else { | |
943 | dst++; | |
944 | } | |
945 | } | |
946 | ||
310b0d55 | 947 | dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); |
1bf95cca JF |
948 | |
949 | /* Clear IRQ status */ | |
950 | status &= ~AES_REG_IRQ_DATA_OUT; | |
951 | omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); | |
952 | ||
953 | if (!dd->total) | |
954 | /* All bytes read! */ | |
955 | tasklet_schedule(&dd->done_task); | |
956 | else | |
957 | /* Enable DATA_IN interrupt for next block */ | |
958 | omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); | |
959 | } | |
960 | ||
961 | return IRQ_HANDLED; | |
962 | } | |
963 | ||
bc69d124 MG |
964 | static const struct of_device_id omap_aes_of_match[] = { |
965 | { | |
966 | .compatible = "ti,omap2-aes", | |
0d35583a MG |
967 | .data = &omap_aes_pdata_omap2, |
968 | }, | |
f9fb69e7 MG |
969 | { |
970 | .compatible = "ti,omap3-aes", | |
971 | .data = &omap_aes_pdata_omap3, | |
972 | }, | |
0d35583a MG |
973 | { |
974 | .compatible = "ti,omap4-aes", | |
975 | .data = &omap_aes_pdata_omap4, | |
bc69d124 MG |
976 | }, |
977 | {}, | |
978 | }; | |
979 | MODULE_DEVICE_TABLE(of, omap_aes_of_match); | |
980 | ||
981 | static int omap_aes_get_res_of(struct omap_aes_dev *dd, | |
982 | struct device *dev, struct resource *res) | |
983 | { | |
984 | struct device_node *node = dev->of_node; | |
bc69d124 MG |
985 | int err = 0; |
986 | ||
7d556931 CL |
987 | dd->pdata = of_device_get_match_data(dev); |
988 | if (!dd->pdata) { | |
bc69d124 MG |
989 | dev_err(dev, "no compatible OF match\n"); |
990 | err = -EINVAL; | |
991 | goto err; | |
992 | } | |
993 | ||
994 | err = of_address_to_resource(node, 0, res); | |
995 | if (err < 0) { | |
996 | dev_err(dev, "can't translate OF node address\n"); | |
997 | err = -EINVAL; | |
998 | goto err; | |
999 | } | |
1000 | ||
bc69d124 MG |
1001 | err: |
1002 | return err; | |
1003 | } | |
1004 | #else | |
1005 | static const struct of_device_id omap_aes_of_match[] = { | |
1006 | {}, | |
1007 | }; | |
1008 | ||
1009 | static int omap_aes_get_res_of(struct omap_aes_dev *dd, | |
1010 | struct device *dev, struct resource *res) | |
1011 | { | |
1012 | return -EINVAL; | |
1013 | } | |
1014 | #endif | |
1015 | ||
1016 | static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, | |
1017 | struct platform_device *pdev, struct resource *res) | |
1018 | { | |
1019 | struct device *dev = &pdev->dev; | |
1020 | struct resource *r; | |
1021 | int err = 0; | |
1022 | ||
1023 | /* Get the base address */ | |
1024 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1025 | if (!r) { | |
1026 | dev_err(dev, "no MEM resource info\n"); | |
1027 | err = -ENODEV; | |
1028 | goto err; | |
1029 | } | |
1030 | memcpy(res, r, sizeof(*res)); | |
1031 | ||
0d35583a MG |
1032 | /* Only OMAP2/3 can be non-DT */ |
1033 | dd->pdata = &omap_aes_pdata_omap2; | |
1034 | ||
bc69d124 MG |
1035 | err: |
1036 | return err; | |
1037 | } | |
1038 | ||
537c62ca TK |
1039 | static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, |
1040 | char *buf) | |
1041 | { | |
1042 | return sprintf(buf, "%d\n", aes_fallback_sz); | |
1043 | } | |
1044 | ||
1045 | static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, | |
1046 | const char *buf, size_t size) | |
1047 | { | |
1048 | ssize_t status; | |
1049 | long value; | |
1050 | ||
1051 | status = kstrtol(buf, 0, &value); | |
1052 | if (status) | |
1053 | return status; | |
1054 | ||
1055 | /* HW accelerator only works with buffers > 9 */ | |
1056 | if (value < 9) { | |
1057 | dev_err(dev, "minimum fallback size 9\n"); | |
1058 | return -EINVAL; | |
1059 | } | |
1060 | ||
1061 | aes_fallback_sz = value; | |
1062 | ||
1063 | return size; | |
1064 | } | |
1065 | ||
5007387f TK |
1066 | static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, |
1067 | char *buf) | |
1068 | { | |
1069 | struct omap_aes_dev *dd = dev_get_drvdata(dev); | |
1070 | ||
1071 | return sprintf(buf, "%d\n", dd->engine->queue.max_qlen); | |
1072 | } | |
1073 | ||
1074 | static ssize_t queue_len_store(struct device *dev, | |
1075 | struct device_attribute *attr, const char *buf, | |
1076 | size_t size) | |
1077 | { | |
1078 | struct omap_aes_dev *dd; | |
1079 | ssize_t status; | |
1080 | long value; | |
1081 | unsigned long flags; | |
1082 | ||
1083 | status = kstrtol(buf, 0, &value); | |
1084 | if (status) | |
1085 | return status; | |
1086 | ||
1087 | if (value < 1) | |
1088 | return -EINVAL; | |
1089 | ||
1090 | /* | |
1091 | * Changing the queue size in fly is safe, if size becomes smaller | |
1092 | * than current size, it will just not accept new entries until | |
1093 | * it has shrank enough. | |
1094 | */ | |
1095 | spin_lock_bh(&list_lock); | |
1096 | list_for_each_entry(dd, &dev_list, list) { | |
1097 | spin_lock_irqsave(&dd->lock, flags); | |
1098 | dd->engine->queue.max_qlen = value; | |
1099 | dd->aead_queue.base.max_qlen = value; | |
1100 | spin_unlock_irqrestore(&dd->lock, flags); | |
1101 | } | |
1102 | spin_unlock_bh(&list_lock); | |
1103 | ||
1104 | return size; | |
1105 | } | |
1106 | ||
1107 | static DEVICE_ATTR_RW(queue_len); | |
537c62ca TK |
1108 | static DEVICE_ATTR_RW(fallback); |
1109 | ||
1110 | static struct attribute *omap_aes_attrs[] = { | |
5007387f | 1111 | &dev_attr_queue_len.attr, |
537c62ca TK |
1112 | &dev_attr_fallback.attr, |
1113 | NULL, | |
1114 | }; | |
1115 | ||
1116 | static struct attribute_group omap_aes_attr_group = { | |
1117 | .attrs = omap_aes_attrs, | |
1118 | }; | |
1119 | ||
537559a5 DK |
1120 | static int omap_aes_probe(struct platform_device *pdev) |
1121 | { | |
1122 | struct device *dev = &pdev->dev; | |
1123 | struct omap_aes_dev *dd; | |
f9fb69e7 | 1124 | struct crypto_alg *algp; |
ad18cc9d | 1125 | struct aead_alg *aalg; |
bc69d124 | 1126 | struct resource res; |
1801ad94 | 1127 | int err = -ENOMEM, i, j, irq = -1; |
537559a5 DK |
1128 | u32 reg; |
1129 | ||
05007c10 | 1130 | dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); |
537559a5 DK |
1131 | if (dd == NULL) { |
1132 | dev_err(dev, "unable to alloc data struct.\n"); | |
1133 | goto err_data; | |
1134 | } | |
1135 | dd->dev = dev; | |
1136 | platform_set_drvdata(pdev, dd); | |
1137 | ||
ad18cc9d TK |
1138 | aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); |
1139 | ||
bc69d124 MG |
1140 | err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : |
1141 | omap_aes_get_res_pdev(dd, pdev, &res); | |
1142 | if (err) | |
537559a5 | 1143 | goto err_res; |
bc69d124 | 1144 | |
30862281 LN |
1145 | dd->io_base = devm_ioremap_resource(dev, &res); |
1146 | if (IS_ERR(dd->io_base)) { | |
1147 | err = PTR_ERR(dd->io_base); | |
5946c4a5 | 1148 | goto err_res; |
537559a5 | 1149 | } |
bc69d124 | 1150 | dd->phys_base = res.start; |
537559a5 | 1151 | |
f303b455 TK |
1152 | pm_runtime_use_autosuspend(dev); |
1153 | pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); | |
1154 | ||
5946c4a5 | 1155 | pm_runtime_enable(dev); |
f7b2b5dd NM |
1156 | err = pm_runtime_get_sync(dev); |
1157 | if (err < 0) { | |
1158 | dev_err(dev, "%s: failed to get_sync(%d)\n", | |
1159 | __func__, err); | |
1160 | goto err_res; | |
1161 | } | |
5946c4a5 | 1162 | |
0d35583a MG |
1163 | omap_aes_dma_stop(dd); |
1164 | ||
1165 | reg = omap_aes_read(dd, AES_REG_REV(dd)); | |
5946c4a5 MG |
1166 | |
1167 | pm_runtime_put_sync(dev); | |
537559a5 | 1168 | |
0d35583a MG |
1169 | dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", |
1170 | (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, | |
1171 | (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); | |
1172 | ||
21fe9767 | 1173 | tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); |
537559a5 DK |
1174 | |
1175 | err = omap_aes_dma_init(dd); | |
da8b29a6 PU |
1176 | if (err == -EPROBE_DEFER) { |
1177 | goto err_irq; | |
1178 | } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { | |
1801ad94 JF |
1179 | dd->pio_only = 1; |
1180 | ||
1181 | irq = platform_get_irq(pdev, 0); | |
1182 | if (irq < 0) { | |
1183 | dev_err(dev, "can't get IRQ resource\n"); | |
62c58f8d | 1184 | err = irq; |
1801ad94 JF |
1185 | goto err_irq; |
1186 | } | |
1187 | ||
bce2a228 | 1188 | err = devm_request_irq(dev, irq, omap_aes_irq, 0, |
1801ad94 JF |
1189 | dev_name(dev), dd); |
1190 | if (err) { | |
1191 | dev_err(dev, "Unable to grab omap-aes IRQ\n"); | |
1192 | goto err_irq; | |
1193 | } | |
1194 | } | |
1195 | ||
ad18cc9d | 1196 | spin_lock_init(&dd->lock); |
537559a5 DK |
1197 | |
1198 | INIT_LIST_HEAD(&dd->list); | |
1199 | spin_lock(&list_lock); | |
1200 | list_add_tail(&dd->list, &dev_list); | |
1201 | spin_unlock(&list_lock); | |
1202 | ||
0d0cda93 TK |
1203 | /* Initialize crypto engine */ |
1204 | dd->engine = crypto_engine_alloc_init(dev, 1); | |
c98ef8db WY |
1205 | if (!dd->engine) { |
1206 | err = -ENOMEM; | |
0d0cda93 | 1207 | goto err_engine; |
c98ef8db | 1208 | } |
0d0cda93 | 1209 | |
0d0cda93 TK |
1210 | err = crypto_engine_start(dd->engine); |
1211 | if (err) | |
1212 | goto err_engine; | |
1213 | ||
f9fb69e7 | 1214 | for (i = 0; i < dd->pdata->algs_info_size; i++) { |
3741bbb2 LV |
1215 | if (!dd->pdata->algs_info[i].registered) { |
1216 | for (j = 0; j < dd->pdata->algs_info[i].size; j++) { | |
1217 | algp = &dd->pdata->algs_info[i].algs_list[j]; | |
f9fb69e7 | 1218 | |
3741bbb2 | 1219 | pr_debug("reg alg: %s\n", algp->cra_name); |
f9fb69e7 | 1220 | |
3741bbb2 LV |
1221 | err = crypto_register_alg(algp); |
1222 | if (err) | |
1223 | goto err_algs; | |
f9fb69e7 | 1224 | |
3741bbb2 LV |
1225 | dd->pdata->algs_info[i].registered++; |
1226 | } | |
f9fb69e7 | 1227 | } |
537559a5 DK |
1228 | } |
1229 | ||
ad18cc9d TK |
1230 | if (dd->pdata->aead_algs_info && |
1231 | !dd->pdata->aead_algs_info->registered) { | |
1232 | for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { | |
1233 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; | |
1234 | algp = &aalg->base; | |
1235 | ||
1236 | pr_debug("reg alg: %s\n", algp->cra_name); | |
ad18cc9d TK |
1237 | |
1238 | err = crypto_register_aead(aalg); | |
1239 | if (err) | |
1240 | goto err_aead_algs; | |
1241 | ||
1242 | dd->pdata->aead_algs_info->registered++; | |
1243 | } | |
1244 | } | |
1245 | ||
537c62ca TK |
1246 | err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group); |
1247 | if (err) { | |
1248 | dev_err(dev, "could not create sysfs device attrs\n"); | |
1249 | goto err_aead_algs; | |
1250 | } | |
1251 | ||
537559a5 | 1252 | return 0; |
ad18cc9d TK |
1253 | err_aead_algs: |
1254 | for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { | |
1255 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; | |
1256 | crypto_unregister_aead(aalg); | |
1257 | } | |
537559a5 | 1258 | err_algs: |
f9fb69e7 MG |
1259 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1260 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
1261 | crypto_unregister_alg( | |
1262 | &dd->pdata->algs_info[i].algs_list[j]); | |
da8b29a6 | 1263 | |
0d0cda93 TK |
1264 | err_engine: |
1265 | if (dd->engine) | |
1266 | crypto_engine_exit(dd->engine); | |
1267 | ||
da8b29a6 | 1268 | omap_aes_dma_cleanup(dd); |
1801ad94 | 1269 | err_irq: |
21fe9767 | 1270 | tasklet_kill(&dd->done_task); |
5946c4a5 | 1271 | pm_runtime_disable(dev); |
537559a5 | 1272 | err_res: |
537559a5 DK |
1273 | dd = NULL; |
1274 | err_data: | |
1275 | dev_err(dev, "initialization failed.\n"); | |
1276 | return err; | |
1277 | } | |
1278 | ||
1279 | static int omap_aes_remove(struct platform_device *pdev) | |
1280 | { | |
1281 | struct omap_aes_dev *dd = platform_get_drvdata(pdev); | |
ad18cc9d | 1282 | struct aead_alg *aalg; |
f9fb69e7 | 1283 | int i, j; |
537559a5 DK |
1284 | |
1285 | if (!dd) | |
1286 | return -ENODEV; | |
1287 | ||
1288 | spin_lock(&list_lock); | |
1289 | list_del(&dd->list); | |
1290 | spin_unlock(&list_lock); | |
1291 | ||
f9fb69e7 MG |
1292 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1293 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
1294 | crypto_unregister_alg( | |
1295 | &dd->pdata->algs_info[i].algs_list[j]); | |
537559a5 | 1296 | |
ad18cc9d TK |
1297 | for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) { |
1298 | aalg = &dd->pdata->aead_algs_info->algs_list[i]; | |
1299 | crypto_unregister_aead(aalg); | |
1300 | } | |
1301 | ||
0529900a | 1302 | crypto_engine_exit(dd->engine); |
ad18cc9d | 1303 | |
21fe9767 | 1304 | tasklet_kill(&dd->done_task); |
537559a5 | 1305 | omap_aes_dma_cleanup(dd); |
5946c4a5 | 1306 | pm_runtime_disable(dd->dev); |
537559a5 DK |
1307 | dd = NULL; |
1308 | ||
1309 | return 0; | |
1310 | } | |
1311 | ||
0635fb3a MG |
1312 | #ifdef CONFIG_PM_SLEEP |
1313 | static int omap_aes_suspend(struct device *dev) | |
1314 | { | |
1315 | pm_runtime_put_sync(dev); | |
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | static int omap_aes_resume(struct device *dev) | |
1320 | { | |
1321 | pm_runtime_get_sync(dev); | |
1322 | return 0; | |
1323 | } | |
1324 | #endif | |
1325 | ||
ea7b2843 | 1326 | static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); |
0635fb3a | 1327 | |
537559a5 DK |
1328 | static struct platform_driver omap_aes_driver = { |
1329 | .probe = omap_aes_probe, | |
1330 | .remove = omap_aes_remove, | |
1331 | .driver = { | |
1332 | .name = "omap-aes", | |
0635fb3a | 1333 | .pm = &omap_aes_pm_ops, |
bc69d124 | 1334 | .of_match_table = omap_aes_of_match, |
537559a5 DK |
1335 | }, |
1336 | }; | |
1337 | ||
94e51df9 | 1338 | module_platform_driver(omap_aes_driver); |
537559a5 DK |
1339 | |
1340 | MODULE_DESCRIPTION("OMAP AES hw acceleration support."); | |
1341 | MODULE_LICENSE("GPL v2"); | |
1342 | MODULE_AUTHOR("Dmitry Kasatkin"); | |
1343 |