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crypto: caam - fix hash context DMA unmap size
[linux-2.6-block.git] / drivers / crypto / omap-aes.c
CommitLineData
537559a5
DK		 1/*
2 * Cryptographic API.
3 *
4 * Support for OMAP AES HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
0d35583a 8 * Copyright (c) 2011 Texas Instruments Incorporated
537559a5
DK		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15
016af9b5
JF		 16#define pr_fmt(fmt) "%20s: " fmt, __func__
17#define prn(num) pr_debug(#num "=%d\n", num)
18#define prx(num) pr_debug(#num "=%x\n", num)
537559a5
DK		 19
20#include <linux/err.h>
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/errno.h>
24#include <linux/kernel.h>
537559a5
DK		 25#include <linux/platform_device.h>
26#include <linux/scatterlist.h>
27#include <linux/dma-mapping.h>
ebedbf79 28#include <linux/dmaengine.h>
5946c4a5 29#include <linux/pm_runtime.h>
bc69d124
MG		 30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/of_address.h>
537559a5
DK		 33#include <linux/io.h>
34#include <linux/crypto.h>
35#include <linux/interrupt.h>
36#include <crypto/scatterwalk.h>
37#include <crypto/aes.h>
cb3f3817 38#include <crypto/gcm.h>
2589ad84 39#include <crypto/engine.h>
9fcb191a 40#include <crypto/internal/skcipher.h>
ad18cc9d 41#include <crypto/internal/aead.h>
537559a5 42
afc2dc13 43#include "omap-crypto.h"
5b3d4d2e 44#include "omap-aes.h"
537559a5
DK		 45
46/* keep registered devices data here */
47static LIST_HEAD(dev_list);
48static DEFINE_SPINLOCK(list_lock);
49
537c62ca
TK		 50static int aes_fallback_sz = 200;
51
016af9b5
JF		 52#ifdef DEBUG
53#define omap_aes_read(dd, offset) \
54({ \
55 int _read_ret; \
56 _read_ret = __raw_readl(dd->io_base + offset); \
57 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
58 offset, _read_ret); \
59 _read_ret; \
60})
61#else
d695bfd6 62inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
537559a5
DK		 63{
64 return __raw_readl(dd->io_base + offset);
65}
016af9b5
JF		 66#endif
67
68#ifdef DEBUG
69#define omap_aes_write(dd, offset, value) \
70 do { \
71 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
72 offset, value); \
73 __raw_writel(value, dd->io_base + offset); \
74 } while (0)
75#else
d695bfd6 76inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
537559a5
DK		 77 u32 value)
78{
79 __raw_writel(value, dd->io_base + offset);
80}
016af9b5 81#endif
537559a5
DK		 82
83static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
84 u32 value, u32 mask)
85{
86 u32 val;
87
88 val = omap_aes_read(dd, offset);
89 val &= ~mask;
90 val |= value;
91 omap_aes_write(dd, offset, val);
92}
93
94static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
95 u32 *value, int count)
96{
97 for (; count--; value++, offset += 4)
98 omap_aes_write(dd, offset, *value);
99}
100
537559a5
DK		 101static int omap_aes_hw_init(struct omap_aes_dev *dd)
102{
f303b455
TK		 103 int err;
104
537559a5 105 if (!(dd->flags & FLAGS_INIT)) {
eeb2b202 106 dd->flags |= FLAGS_INIT;
21fe9767 107 dd->err = 0;
537559a5
DK		 108 }
109
f303b455
TK		 110 err = pm_runtime_get_sync(dd->dev);
111 if (err < 0) {
112 dev_err(dd->dev, "failed to get sync: %d\n", err);
113 return err;
114 }
115
eeb2b202 116 return 0;
537559a5
DK		 117}
118
ad18cc9d
TK		 119void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
120{
121 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
122 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
123 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
124}
125
d695bfd6 126int omap_aes_write_ctrl(struct omap_aes_dev *dd)
537559a5 127{
ad18cc9d 128 struct omap_aes_reqctx *rctx;
537559a5 129 unsigned int key32;
67a730ce 130 int i, err;
5396c6c0 131 u32 val;
537559a5 132
21fe9767
DK		 133 err = omap_aes_hw_init(dd);
134 if (err)
135 return err;
136
537559a5 137 key32 = dd->ctx->keylen / sizeof(u32);
67a730ce 138
ad18cc9d
TK		 139 /* RESET the key as previous HASH keys should not get affected*/
140 if (dd->flags & FLAGS_GCM)
141 for (i = 0; i < 0x40; i = i + 4)
142 omap_aes_write(dd, i, 0x0);
143
537559a5 144 for (i = 0; i < key32; i++) {
0d35583a 145 omap_aes_write(dd, AES_REG_KEY(dd, i),
537559a5
DK		 146 __le32_to_cpu(dd->ctx->key[i]));
147 }
537559a5 148
f9fb69e7 149 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
0d35583a 150 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
67a730ce 151
ad18cc9d
TK		 152 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
153 rctx = aead_request_ctx(dd->aead_req);
154 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
155 }
156
67a730ce
DK		 157 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
158 if (dd->flags & FLAGS_CBC)
159 val |= AES_REG_CTRL_CBC;
ad18cc9d
TK		 160
161 if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
8ed49c76 162 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
5396c6c0 163
ad18cc9d
TK		 164 if (dd->flags & FLAGS_GCM)
165 val |= AES_REG_CTRL_GCM;
166
67a730ce
DK		 167 if (dd->flags & FLAGS_ENCRYPT)
168 val |= AES_REG_CTRL_DIRECTION;
537559a5 169
5396c6c0 170 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
537559a5 171
21fe9767 172 return 0;
537559a5
DK		 173}
174
0d35583a
MG		 175static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
176{
177 u32 mask, val;
178
179 val = dd->pdata->dma_start;
180
181 if (dd->dma_lch_out != NULL)
182 val |= dd->pdata->dma_enable_out;
183 if (dd->dma_lch_in != NULL)
184 val |= dd->pdata->dma_enable_in;
185
186 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
187 dd->pdata->dma_start;
188
189 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
190
191}
192
193static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
194{
195 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
196 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
ad18cc9d
TK		 197 if (dd->flags & FLAGS_GCM)
198 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
0d35583a
MG		 199
200 omap_aes_dma_trigger_omap2(dd, length);
201}
202
203static void omap_aes_dma_stop(struct omap_aes_dev *dd)
204{
205 u32 mask;
206
207 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
208 dd->pdata->dma_start;
209
210 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
211}
212
d695bfd6 213struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
537559a5 214{
164f3ef3 215 struct omap_aes_dev *dd;
537559a5
DK		 216
217 spin_lock_bh(&list_lock);
164f3ef3
LV		 218 dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
219 list_move_tail(&dd->list, &dev_list);
619ce700 220 rctx->dd = dd;
537559a5
DK		 221 spin_unlock_bh(&list_lock);
222
223 return dd;
224}
225
ebedbf79
MG		 226static void omap_aes_dma_out_callback(void *data)
227{
228 struct omap_aes_dev *dd = data;
229
230 /* dma_lch_out - completed */
231 tasklet_schedule(&dd->done_task);
232}
537559a5
DK		 233
234static int omap_aes_dma_init(struct omap_aes_dev *dd)
235{
da8b29a6 236 int err;
537559a5 237
ebedbf79
MG		 238 dd->dma_lch_out = NULL;
239 dd->dma_lch_in = NULL;
537559a5 240
da8b29a6
PU		 241 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
242 if (IS_ERR(dd->dma_lch_in)) {
ebedbf79 243 dev_err(dd->dev, "Unable to request in DMA channel\n");
da8b29a6 244 return PTR_ERR(dd->dma_lch_in);
ebedbf79
MG		 245 }
246
da8b29a6
PU		 247 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
248 if (IS_ERR(dd->dma_lch_out)) {
ebedbf79 249 dev_err(dd->dev, "Unable to request out DMA channel\n");
da8b29a6 250 err = PTR_ERR(dd->dma_lch_out);
ebedbf79
MG		 251 goto err_dma_out;
252 }
537559a5 253
537559a5
DK		 254 return 0;
255
256err_dma_out:
ebedbf79 257 dma_release_channel(dd->dma_lch_in);
da8b29a6 258
537559a5
DK		 259 return err;
260}
261
262static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
263{
da8b29a6
PU		 264 if (dd->pio_only)
265 return;
266
ebedbf79
MG		 267 dma_release_channel(dd->dma_lch_out);
268 dma_release_channel(dd->dma_lch_in);
537559a5
DK		 269}
270
619ce700
TK		 271static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
272 struct scatterlist *in_sg,
273 struct scatterlist *out_sg,
274 int in_sg_len, int out_sg_len)
537559a5 275{
ebedbf79
MG		 276 struct dma_async_tx_descriptor *tx_in, *tx_out;
277 struct dma_slave_config cfg;
4b645c94 278 int ret;
537559a5 279
98837abc
JF		 280 if (dd->pio_only) {
281 scatterwalk_start(&dd->in_walk, dd->in_sg);
282 scatterwalk_start(&dd->out_walk, dd->out_sg);
283
284 /* Enable DATAIN interrupt and let it take
285 care of the rest */
286 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
287 return 0;
288 }
289
0a641712
JF		 290 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
291
ebedbf79
MG		 292 memset(&cfg, 0, sizeof(cfg));
293
0d35583a
MG		 294 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
295 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
ebedbf79
MG		 296 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
297 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
298 cfg.src_maxburst = DST_MAXBURST;
299 cfg.dst_maxburst = DST_MAXBURST;
300
301 /* IN */
302 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
303 if (ret) {
304 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
305 ret);
306 return ret;
307 }
308
4b645c94 309 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
ebedbf79
MG		 310 DMA_MEM_TO_DEV,
311 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
312 if (!tx_in) {
313 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
314 return -EINVAL;
315 }
316
317 /* No callback necessary */
318 tx_in->callback_param = dd;
319
320 /* OUT */
321 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
322 if (ret) {
323 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
324 ret);
325 return ret;
326 }
327
4b645c94 328 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
ebedbf79
MG		 329 DMA_DEV_TO_MEM,
330 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
331 if (!tx_out) {
332 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
333 return -EINVAL;
334 }
335
ad18cc9d
TK		 336 if (dd->flags & FLAGS_GCM)
337 tx_out->callback = omap_aes_gcm_dma_out_callback;
338 else
339 tx_out->callback = omap_aes_dma_out_callback;
ebedbf79
MG		 340 tx_out->callback_param = dd;
341
342 dmaengine_submit(tx_in);
343 dmaengine_submit(tx_out);
344
345 dma_async_issue_pending(dd->dma_lch_in);
346 dma_async_issue_pending(dd->dma_lch_out);
537559a5 347
0d35583a 348 /* start DMA */
4b645c94 349 dd->pdata->trigger(dd, dd->total);
83ea7e0f 350
537559a5
DK		 351 return 0;
352}
353
d695bfd6 354int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
537559a5 355{
4b645c94 356 int err;
537559a5
DK		 357
358 pr_debug("total: %d\n", dd->total);
359
98837abc
JF		 360 if (!dd->pio_only) {
361 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
362 DMA_TO_DEVICE);
363 if (!err) {
364 dev_err(dd->dev, "dma_map_sg() error\n");
365 return -EINVAL;
366 }
537559a5 367
98837abc
JF		 368 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
369 DMA_FROM_DEVICE);
370 if (!err) {
371 dev_err(dd->dev, "dma_map_sg() error\n");
372 return -EINVAL;
373 }
537559a5
DK		 374 }
375
619ce700 376 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
4b645c94 377 dd->out_sg_len);
98837abc 378 if (err && !dd->pio_only) {
4b645c94
JF		 379 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
380 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
381 DMA_FROM_DEVICE);
21fe9767 382 }
537559a5
DK		 383
384 return err;
385}
386
387static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
388{
21fe9767 389 struct ablkcipher_request *req = dd->req;
537559a5
DK		 390
391 pr_debug("err: %d\n", err);
392
c21c8b89 393 crypto_finalize_ablkcipher_request(dd->engine, req, err);
f303b455
TK		 394
395 pm_runtime_mark_last_busy(dd->dev);
396 pm_runtime_put_autosuspend(dd->dev);
537559a5
DK		 397}
398
d695bfd6 399int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
537559a5 400{
537559a5
DK		 401 pr_debug("total: %d\n", dd->total);
402
0d35583a 403 omap_aes_dma_stop(dd);
537559a5 404
537559a5 405
16f080aa 406 return 0;
537559a5
DK		 407}
408
21fe9767 409static int omap_aes_handle_queue(struct omap_aes_dev *dd,
0529900a 410 struct ablkcipher_request *req)
537559a5 411{
eeb2b202 412 if (req)
c21c8b89 413 return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
537559a5 414
0529900a
BW		 415 return 0;
416}
537559a5 417
0529900a 418static int omap_aes_prepare_req(struct crypto_engine *engine,
c21c8b89 419 void *areq)
0529900a 420{
c21c8b89 421 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
0529900a
BW		 422 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
423 crypto_ablkcipher_reqtfm(req));
619ce700
TK		 424 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
425 struct omap_aes_dev *dd = rctx->dd;
afc2dc13
TK		 426 int ret;
427 u16 flags;
537559a5 428
0529900a
BW		 429 if (!dd)
430 return -ENODEV;
537559a5 431
537559a5
DK		 432 /* assign new request to device */
433 dd->req = req;
434 dd->total = req->nbytes;
6242332f 435 dd->total_save = req->nbytes;
537559a5 436 dd->in_sg = req->src;
537559a5 437 dd->out_sg = req->dst;
afc2dc13
TK		 438 dd->orig_out = req->dst;
439
440 flags = OMAP_CRYPTO_COPY_DATA;
441 if (req->src == req->dst)
442 flags |= OMAP_CRYPTO_FORCE_COPY;
443
444 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
ad18cc9d 445 dd->in_sgl, flags,
afc2dc13
TK		 446 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
447 if (ret)
448 return ret;
449
450 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
451 &dd->out_sgl, 0,
452 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
453 if (ret)
454 return ret;
537559a5 455
7c001a86
HX		 456 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
457 if (dd->in_sg_len < 0)
458 return dd->in_sg_len;
459
460 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
461 if (dd->out_sg_len < 0)
462 return dd->out_sg_len;
463
537559a5
DK		 464 rctx->mode &= FLAGS_MODE_MASK;
465 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
466
67a730ce 467 dd->ctx = ctx;
619ce700 468 rctx->dd = dd;
537559a5 469
0529900a
BW		 470 return omap_aes_write_ctrl(dd);
471}
eeb2b202 472
0529900a 473static int omap_aes_crypt_req(struct crypto_engine *engine,
c21c8b89 474 void *areq)
0529900a 475{
c21c8b89 476 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
619ce700
TK		 477 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
478 struct omap_aes_dev *dd = rctx->dd;
0529900a
BW		 479
480 if (!dd)
481 return -ENODEV;
482
483 return omap_aes_crypt_dma_start(dd);
537559a5
DK		 484}
485
21fe9767 486static void omap_aes_done_task(unsigned long data)
537559a5
DK		 487{
488 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
537559a5 489
4b645c94 490 pr_debug("enter done_task\n");
21fe9767 491
98837abc
JF		 492 if (!dd->pio_only) {
493 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
494 DMA_FROM_DEVICE);
6242332f
JF		 495 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
496 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
497 DMA_FROM_DEVICE);
98837abc
JF		 498 omap_aes_crypt_dma_stop(dd);
499 }
6242332f 500
ad18cc9d 501 omap_crypto_cleanup(dd->in_sgl, NULL, 0, dd->total_save,
afc2dc13 502 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
6242332f 503
afc2dc13
TK		 504 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
505 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
6242332f 506
4b645c94 507 omap_aes_finish_req(dd, 0);
537559a5
DK		 508
509 pr_debug("exit\n");
510}
511
512static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
513{
514 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
515 crypto_ablkcipher_reqtfm(req));
516 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
517 struct omap_aes_dev *dd;
9fcb191a 518 int ret;
537559a5
DK		 519
520 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
521 !!(mode & FLAGS_ENCRYPT),
522 !!(mode & FLAGS_CBC));
523
537c62ca 524 if (req->nbytes < aes_fallback_sz) {
e87f203c 525 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
9fcb191a 526
e87f203c 527 skcipher_request_set_sync_tfm(subreq, ctx->fallback);
9fcb191a
LV		 528 skcipher_request_set_callback(subreq, req->base.flags, NULL,
529 NULL);
530 skcipher_request_set_crypt(subreq, req->src, req->dst,
531 req->nbytes, req->info);
532
533 if (mode & FLAGS_ENCRYPT)
534 ret = crypto_skcipher_encrypt(subreq);
535 else
536 ret = crypto_skcipher_decrypt(subreq);
537
538 skcipher_request_zero(subreq);
539 return ret;
540 }
619ce700 541 dd = omap_aes_find_dev(rctx);
537559a5
DK		 542 if (!dd)
543 return -ENODEV;
544
545 rctx->mode = mode;
546
21fe9767 547 return omap_aes_handle_queue(dd, req);
537559a5
DK		 548}
549
550/* ********************** ALG API ************************************ */
551
552static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
553 unsigned int keylen)
554{
555 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
9fcb191a 556 int ret;
537559a5
DK		 557
558 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
559 keylen != AES_KEYSIZE_256)
560 return -EINVAL;
561
562 pr_debug("enter, keylen: %d\n", keylen);
563
564 memcpy(ctx->key, key, keylen);
565 ctx->keylen = keylen;
537559a5 566
e87f203c
KC		 567 crypto_sync_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
568 crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
9fcb191a
LV		 569 CRYPTO_TFM_REQ_MASK);
570
e87f203c 571 ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
9fcb191a
LV		 572 if (!ret)
573 return 0;
574
537559a5
DK		 575 return 0;
576}
577
578static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
579{
580 return omap_aes_crypt(req, FLAGS_ENCRYPT);
581}
582
583static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
584{
585 return omap_aes_crypt(req, 0);
586}
587
588static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
589{
590 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
591}
592
593static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
594{
595 return omap_aes_crypt(req, FLAGS_CBC);
596}
597
f9fb69e7
MG		 598static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
599{
600 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
601}
602
603static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
604{
605 return omap_aes_crypt(req, FLAGS_CTR);
606}
607
c21c8b89
CL		 608static int omap_aes_prepare_req(struct crypto_engine *engine,
609 void *req);
610static int omap_aes_crypt_req(struct crypto_engine *engine,
611 void *req);
612
537559a5
DK		 613static int omap_aes_cra_init(struct crypto_tfm *tfm)
614{
9fcb191a 615 const char *name = crypto_tfm_alg_name(tfm);
9fcb191a 616 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
e87f203c 617 struct crypto_sync_skcipher *blk;
9fcb191a 618
e87f203c 619 blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
9fcb191a
LV		 620 if (IS_ERR(blk))
621 return PTR_ERR(blk);
622
623 ctx->fallback = blk;
624
537559a5
DK		 625 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
626
c21c8b89
CL		 627 ctx->enginectx.op.prepare_request = omap_aes_prepare_req;
628 ctx->enginectx.op.unprepare_request = NULL;
629 ctx->enginectx.op.do_one_request = omap_aes_crypt_req;
630
537559a5
DK		 631 return 0;
632}
633
ad18cc9d
TK		 634static int omap_aes_gcm_cra_init(struct crypto_aead *tfm)
635{
636 struct omap_aes_dev *dd = NULL;
637 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm);
638 int err;
639
640 /* Find AES device, currently picks the first device */
641 spin_lock_bh(&list_lock);
642 list_for_each_entry(dd, &dev_list, list) {
643 break;
644 }
645 spin_unlock_bh(&list_lock);
646
647 err = pm_runtime_get_sync(dd->dev);
648 if (err < 0) {
649 dev_err(dd->dev, "%s: failed to get_sync(%d)\n",
650 __func__, err);
651 return err;
652 }
653
654 tfm->reqsize = sizeof(struct omap_aes_reqctx);
655 ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0);
656 if (IS_ERR(ctx->ctr)) {
657 pr_warn("could not load aes driver for encrypting IV\n");
658 return PTR_ERR(ctx->ctr);
659 }
660
661 return 0;
662}
663
537559a5
DK		 664static void omap_aes_cra_exit(struct crypto_tfm *tfm)
665{
9fcb191a
LV		 666 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
667
668 if (ctx->fallback)
e87f203c 669 crypto_free_sync_skcipher(ctx->fallback);
9fcb191a
LV		 670
671 ctx->fallback = NULL;
537559a5
DK		 672}
673
ad18cc9d
TK		 674static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm)
675{
676 struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm);
677
678 omap_aes_cra_exit(crypto_aead_tfm(tfm));
679
680 if (ctx->ctr)
681 crypto_free_skcipher(ctx->ctr);
682}
683
537559a5
DK		 684/* ********************** ALGS ************************************ */
685
f9fb69e7 686static struct crypto_alg algs_ecb_cbc[] = {
537559a5
DK		 687{
688 .cra_name = "ecb(aes)",
689 .cra_driver_name = "ecb-aes-omap",
6e2e3d1d 690 .cra_priority = 300,
d912bb76
NM		 691 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
692 CRYPTO_ALG_KERN_DRIVER_ONLY |
9fcb191a 693 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
537559a5
DK		 694 .cra_blocksize = AES_BLOCK_SIZE,
695 .cra_ctxsize = sizeof(struct omap_aes_ctx),
efce41b6 696 .cra_alignmask = 0,
537559a5
DK		 697 .cra_type = &crypto_ablkcipher_type,
698 .cra_module = THIS_MODULE,
699 .cra_init = omap_aes_cra_init,
700 .cra_exit = omap_aes_cra_exit,
701 .cra_u.ablkcipher = {
702 .min_keysize = AES_MIN_KEY_SIZE,
703 .max_keysize = AES_MAX_KEY_SIZE,
704 .setkey = omap_aes_setkey,
705 .encrypt = omap_aes_ecb_encrypt,
706 .decrypt = omap_aes_ecb_decrypt,
707 }
708},
709{
710 .cra_name = "cbc(aes)",
711 .cra_driver_name = "cbc-aes-omap",
6e2e3d1d 712 .cra_priority = 300,
d912bb76
NM		 713 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
714 CRYPTO_ALG_KERN_DRIVER_ONLY |
9fcb191a 715 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
537559a5
DK		 716 .cra_blocksize = AES_BLOCK_SIZE,
717 .cra_ctxsize = sizeof(struct omap_aes_ctx),
efce41b6 718 .cra_alignmask = 0,
537559a5
DK		 719 .cra_type = &crypto_ablkcipher_type,
720 .cra_module = THIS_MODULE,
721 .cra_init = omap_aes_cra_init,
722 .cra_exit = omap_aes_cra_exit,
723 .cra_u.ablkcipher = {
724 .min_keysize = AES_MIN_KEY_SIZE,
725 .max_keysize = AES_MAX_KEY_SIZE,
726 .ivsize = AES_BLOCK_SIZE,
727 .setkey = omap_aes_setkey,
728 .encrypt = omap_aes_cbc_encrypt,
729 .decrypt = omap_aes_cbc_decrypt,
730 }
731}
732};
733
f9fb69e7
MG		 734static struct crypto_alg algs_ctr[] = {
735{
736 .cra_name = "ctr(aes)",
737 .cra_driver_name = "ctr-aes-omap",
6e2e3d1d 738 .cra_priority = 300,
f9fb69e7
MG		 739 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
740 CRYPTO_ALG_KERN_DRIVER_ONLY |
9fcb191a 741 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
f9fb69e7
MG		 742 .cra_blocksize = AES_BLOCK_SIZE,
743 .cra_ctxsize = sizeof(struct omap_aes_ctx),
744 .cra_alignmask = 0,
745 .cra_type = &crypto_ablkcipher_type,
746 .cra_module = THIS_MODULE,
747 .cra_init = omap_aes_cra_init,
748 .cra_exit = omap_aes_cra_exit,
749 .cra_u.ablkcipher = {
750 .min_keysize = AES_MIN_KEY_SIZE,
751 .max_keysize = AES_MAX_KEY_SIZE,
f9fb69e7
MG		 752 .ivsize = AES_BLOCK_SIZE,
753 .setkey = omap_aes_setkey,
754 .encrypt = omap_aes_ctr_encrypt,
755 .decrypt = omap_aes_ctr_decrypt,
756 }
757} ,
758};
759
760static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
761 {
762 .algs_list = algs_ecb_cbc,
763 .size = ARRAY_SIZE(algs_ecb_cbc),
764 },
765};
766
ad18cc9d
TK		 767static struct aead_alg algs_aead_gcm[] = {
768{
769 .base = {
770 .cra_name = "gcm(aes)",
771 .cra_driver_name = "gcm-aes-omap",
772 .cra_priority = 300,
773 .cra_flags = CRYPTO_ALG_ASYNC |
774 CRYPTO_ALG_KERN_DRIVER_ONLY,
775 .cra_blocksize = 1,
776 .cra_ctxsize = sizeof(struct omap_aes_ctx),
777 .cra_alignmask = 0xf,
778 .cra_module = THIS_MODULE,
779 },
780 .init = omap_aes_gcm_cra_init,
781 .exit = omap_aes_gcm_cra_exit,
cb3f3817 782 .ivsize = GCM_AES_IV_SIZE,
ad18cc9d
TK		 783 .maxauthsize = AES_BLOCK_SIZE,
784 .setkey = omap_aes_gcm_setkey,
785 .encrypt = omap_aes_gcm_encrypt,
786 .decrypt = omap_aes_gcm_decrypt,
787},
788{
789 .base = {
790 .cra_name = "rfc4106(gcm(aes))",
791 .cra_driver_name = "rfc4106-gcm-aes-omap",
792 .cra_priority = 300,
793 .cra_flags = CRYPTO_ALG_ASYNC |
794 CRYPTO_ALG_KERN_DRIVER_ONLY,
795 .cra_blocksize = 1,
796 .cra_ctxsize = sizeof(struct omap_aes_ctx),
797 .cra_alignmask = 0xf,
798 .cra_module = THIS_MODULE,
799 },
800 .init = omap_aes_gcm_cra_init,
801 .exit = omap_aes_gcm_cra_exit,
802 .maxauthsize = AES_BLOCK_SIZE,
cb3f3817 803 .ivsize = GCM_RFC4106_IV_SIZE,
ad18cc9d
TK		 804 .setkey = omap_aes_4106gcm_setkey,
805 .encrypt = omap_aes_4106gcm_encrypt,
806 .decrypt = omap_aes_4106gcm_decrypt,
807},
808};
809
810static struct omap_aes_aead_algs omap_aes_aead_info = {
811 .algs_list = algs_aead_gcm,
812 .size = ARRAY_SIZE(algs_aead_gcm),
813};
814
0d35583a 815static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
f9fb69e7
MG		 816 .algs_info = omap_aes_algs_info_ecb_cbc,
817 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
0d35583a
MG		 818 .trigger = omap_aes_dma_trigger_omap2,
819 .key_ofs = 0x1c,
820 .iv_ofs = 0x20,
821 .ctrl_ofs = 0x30,
822 .data_ofs = 0x34,
823 .rev_ofs = 0x44,
824 .mask_ofs = 0x48,
825 .dma_enable_in = BIT(2),
826 .dma_enable_out = BIT(3),
827 .dma_start = BIT(5),
828 .major_mask = 0xf0,
829 .major_shift = 4,
830 .minor_mask = 0x0f,
831 .minor_shift = 0,
832};
833
bc69d124 834#ifdef CONFIG_OF
f9fb69e7
MG		 835static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
836 {
837 .algs_list = algs_ecb_cbc,
838 .size = ARRAY_SIZE(algs_ecb_cbc),
839 },
840 {
841 .algs_list = algs_ctr,
842 .size = ARRAY_SIZE(algs_ctr),
843 },
844};
845
846static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
847 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
848 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
849 .trigger = omap_aes_dma_trigger_omap2,
850 .key_ofs = 0x1c,
851 .iv_ofs = 0x20,
852 .ctrl_ofs = 0x30,
853 .data_ofs = 0x34,
854 .rev_ofs = 0x44,
855 .mask_ofs = 0x48,
856 .dma_enable_in = BIT(2),
857 .dma_enable_out = BIT(3),
858 .dma_start = BIT(5),
859 .major_mask = 0xf0,
860 .major_shift = 4,
861 .minor_mask = 0x0f,
862 .minor_shift = 0,
863};
864
0d35583a 865static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
f9fb69e7
MG		 866 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
867 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
ad18cc9d 868 .aead_algs_info = &omap_aes_aead_info,
0d35583a
MG		 869 .trigger = omap_aes_dma_trigger_omap4,
870 .key_ofs = 0x3c,
871 .iv_ofs = 0x40,
872 .ctrl_ofs = 0x50,
873 .data_ofs = 0x60,
874 .rev_ofs = 0x80,
875 .mask_ofs = 0x84,
67216756
JF		 876 .irq_status_ofs = 0x8c,
877 .irq_enable_ofs = 0x90,
0d35583a
MG		 878 .dma_enable_in = BIT(5),
879 .dma_enable_out = BIT(6),
880 .major_mask = 0x0700,
881 .major_shift = 8,
882 .minor_mask = 0x003f,
883 .minor_shift = 0,
884};
885
1bf95cca
JF		 886static irqreturn_t omap_aes_irq(int irq, void *dev_id)
887{
888 struct omap_aes_dev *dd = dev_id;
889 u32 status, i;
890 u32 *src, *dst;
891
892 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
893 if (status & AES_REG_IRQ_DATA_IN) {
894 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
895
896 BUG_ON(!dd->in_sg);
897
898 BUG_ON(_calc_walked(in) > dd->in_sg->length);
899
900 src = sg_virt(dd->in_sg) + _calc_walked(in);
901
902 for (i = 0; i < AES_BLOCK_WORDS; i++) {
903 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
904
905 scatterwalk_advance(&dd->in_walk, 4);
906 if (dd->in_sg->length == _calc_walked(in)) {
5be4d4c9 907 dd->in_sg = sg_next(dd->in_sg);
1bf95cca
JF		 908 if (dd->in_sg) {
909 scatterwalk_start(&dd->in_walk,
910 dd->in_sg);
911 src = sg_virt(dd->in_sg) +
912 _calc_walked(in);
913 }
914 } else {
915 src++;
916 }
917 }
918
919 /* Clear IRQ status */
920 status &= ~AES_REG_IRQ_DATA_IN;
921 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
922
923 /* Enable DATA_OUT interrupt */
924 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
925
926 } else if (status & AES_REG_IRQ_DATA_OUT) {
927 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
928
929 BUG_ON(!dd->out_sg);
930
931 BUG_ON(_calc_walked(out) > dd->out_sg->length);
932
933 dst = sg_virt(dd->out_sg) + _calc_walked(out);
934
935 for (i = 0; i < AES_BLOCK_WORDS; i++) {
936 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
937 scatterwalk_advance(&dd->out_walk, 4);
938 if (dd->out_sg->length == _calc_walked(out)) {
5be4d4c9 939 dd->out_sg = sg_next(dd->out_sg);
1bf95cca
JF		 940 if (dd->out_sg) {
941 scatterwalk_start(&dd->out_walk,
942 dd->out_sg);
943 dst = sg_virt(dd->out_sg) +
944 _calc_walked(out);
945 }
946 } else {
947 dst++;
948 }
949 }
950
310b0d55 951 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
1bf95cca
JF		 952
953 /* Clear IRQ status */
954 status &= ~AES_REG_IRQ_DATA_OUT;
955 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
956
957 if (!dd->total)
958 /* All bytes read! */
959 tasklet_schedule(&dd->done_task);
960 else
961 /* Enable DATA_IN interrupt for next block */
962 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
963 }
964
965 return IRQ_HANDLED;
966}
967
bc69d124
MG		 968static const struct of_device_id omap_aes_of_match[] = {
969 {
970 .compatible = "ti,omap2-aes",
0d35583a
MG		 971 .data = &omap_aes_pdata_omap2,
972 },
f9fb69e7
MG		 973 {
974 .compatible = "ti,omap3-aes",
975 .data = &omap_aes_pdata_omap3,
976 },
0d35583a
MG		 977 {
978 .compatible = "ti,omap4-aes",
979 .data = &omap_aes_pdata_omap4,
bc69d124
MG		 980 },
981 {},
982};
983MODULE_DEVICE_TABLE(of, omap_aes_of_match);
984
985static int omap_aes_get_res_of(struct omap_aes_dev *dd,
986 struct device *dev, struct resource *res)
987{
988 struct device_node *node = dev->of_node;
bc69d124
MG		 989 int err = 0;
990
7d556931
CL		 991 dd->pdata = of_device_get_match_data(dev);
992 if (!dd->pdata) {
bc69d124
MG		 993 dev_err(dev, "no compatible OF match\n");
994 err = -EINVAL;
995 goto err;
996 }
997
998 err = of_address_to_resource(node, 0, res);
999 if (err < 0) {
1000 dev_err(dev, "can't translate OF node address\n");
1001 err = -EINVAL;
1002 goto err;
1003 }
1004
bc69d124
MG		 1005err:
1006 return err;
1007}
1008#else
1009static const struct of_device_id omap_aes_of_match[] = {
1010 {},
1011};
1012
1013static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1014 struct device *dev, struct resource *res)
1015{
1016 return -EINVAL;
1017}
1018#endif
1019
1020static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1021 struct platform_device *pdev, struct resource *res)
1022{
1023 struct device *dev = &pdev->dev;
1024 struct resource *r;
1025 int err = 0;
1026
1027 /* Get the base address */
1028 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 if (!r) {
1030 dev_err(dev, "no MEM resource info\n");
1031 err = -ENODEV;
1032 goto err;
1033 }
1034 memcpy(res, r, sizeof(*res));
1035
0d35583a
MG		 1036 /* Only OMAP2/3 can be non-DT */
1037 dd->pdata = &omap_aes_pdata_omap2;
1038
bc69d124
MG		 1039err:
1040 return err;
1041}
1042
537c62ca
TK		 1043static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1044 char *buf)
1045{
1046 return sprintf(buf, "%d\n", aes_fallback_sz);
1047}
1048
1049static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1050 const char *buf, size_t size)
1051{
1052 ssize_t status;
1053 long value;
1054
1055 status = kstrtol(buf, 0, &value);
1056 if (status)
1057 return status;
1058
1059 /* HW accelerator only works with buffers > 9 */
1060 if (value < 9) {
1061 dev_err(dev, "minimum fallback size 9\n");
1062 return -EINVAL;
1063 }
1064
1065 aes_fallback_sz = value;
1066
1067 return size;
1068}
1069
5007387f
TK		 1070static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
1071 char *buf)
1072{
1073 struct omap_aes_dev *dd = dev_get_drvdata(dev);
1074
1075 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
1076}
1077
1078static ssize_t queue_len_store(struct device *dev,
1079 struct device_attribute *attr, const char *buf,
1080 size_t size)
1081{
1082 struct omap_aes_dev *dd;
1083 ssize_t status;
1084 long value;
1085 unsigned long flags;
1086
1087 status = kstrtol(buf, 0, &value);
1088 if (status)
1089 return status;
1090
1091 if (value < 1)
1092 return -EINVAL;
1093
1094 /*
1095 * Changing the queue size in fly is safe, if size becomes smaller
1096 * than current size, it will just not accept new entries until
1097 * it has shrank enough.
1098 */
1099 spin_lock_bh(&list_lock);
1100 list_for_each_entry(dd, &dev_list, list) {
1101 spin_lock_irqsave(&dd->lock, flags);
1102 dd->engine->queue.max_qlen = value;
1103 dd->aead_queue.base.max_qlen = value;
1104 spin_unlock_irqrestore(&dd->lock, flags);
1105 }
1106 spin_unlock_bh(&list_lock);
1107
1108 return size;
1109}
1110
1111static DEVICE_ATTR_RW(queue_len);
537c62ca
TK		 1112static DEVICE_ATTR_RW(fallback);
1113
1114static struct attribute *omap_aes_attrs[] = {
5007387f 1115 &dev_attr_queue_len.attr,
537c62ca
TK		 1116 &dev_attr_fallback.attr,
1117 NULL,
1118};
1119
1120static struct attribute_group omap_aes_attr_group = {
1121 .attrs = omap_aes_attrs,
1122};
1123
537559a5
DK		 1124static int omap_aes_probe(struct platform_device *pdev)
1125{
1126 struct device *dev = &pdev->dev;
1127 struct omap_aes_dev *dd;
f9fb69e7 1128 struct crypto_alg *algp;
ad18cc9d 1129 struct aead_alg *aalg;
bc69d124 1130 struct resource res;
1801ad94 1131 int err = -ENOMEM, i, j, irq = -1;
537559a5
DK		 1132 u32 reg;
1133
05007c10 1134 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
537559a5
DK		 1135 if (dd == NULL) {
1136 dev_err(dev, "unable to alloc data struct.\n");
1137 goto err_data;
1138 }
1139 dd->dev = dev;
1140 platform_set_drvdata(pdev, dd);
1141
ad18cc9d
TK		 1142 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
1143
bc69d124
MG		 1144 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1145 omap_aes_get_res_pdev(dd, pdev, &res);
1146 if (err)
537559a5 1147 goto err_res;
bc69d124 1148
30862281
LN		 1149 dd->io_base = devm_ioremap_resource(dev, &res);
1150 if (IS_ERR(dd->io_base)) {
1151 err = PTR_ERR(dd->io_base);
5946c4a5 1152 goto err_res;
537559a5 1153 }
bc69d124 1154 dd->phys_base = res.start;
537559a5 1155
f303b455
TK		 1156 pm_runtime_use_autosuspend(dev);
1157 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1158
5946c4a5 1159 pm_runtime_enable(dev);
f7b2b5dd
NM		 1160 err = pm_runtime_get_sync(dev);
1161 if (err < 0) {
1162 dev_err(dev, "%s: failed to get_sync(%d)\n",
1163 __func__, err);
1164 goto err_res;
1165 }
5946c4a5 1166
0d35583a
MG		 1167 omap_aes_dma_stop(dd);
1168
1169 reg = omap_aes_read(dd, AES_REG_REV(dd));
5946c4a5
MG		 1170
1171 pm_runtime_put_sync(dev);
537559a5 1172
0d35583a
MG		 1173 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1174 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1175 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1176
21fe9767 1177 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
537559a5
DK		 1178
1179 err = omap_aes_dma_init(dd);
da8b29a6
PU		 1180 if (err == -EPROBE_DEFER) {
1181 goto err_irq;
1182 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1801ad94
JF		 1183 dd->pio_only = 1;
1184
1185 irq = platform_get_irq(pdev, 0);
1186 if (irq < 0) {
1187 dev_err(dev, "can't get IRQ resource\n");
62c58f8d 1188 err = irq;
1801ad94
JF		 1189 goto err_irq;
1190 }
1191
bce2a228 1192 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1801ad94
JF		 1193 dev_name(dev), dd);
1194 if (err) {
1195 dev_err(dev, "Unable to grab omap-aes IRQ\n");
1196 goto err_irq;
1197 }
1198 }
1199
ad18cc9d 1200 spin_lock_init(&dd->lock);
537559a5
DK		 1201
1202 INIT_LIST_HEAD(&dd->list);
1203 spin_lock(&list_lock);
1204 list_add_tail(&dd->list, &dev_list);
1205 spin_unlock(&list_lock);
1206
0d0cda93
TK		 1207 /* Initialize crypto engine */
1208 dd->engine = crypto_engine_alloc_init(dev, 1);
c98ef8db
WY		 1209 if (!dd->engine) {
1210 err = -ENOMEM;
0d0cda93 1211 goto err_engine;
c98ef8db 1212 }
0d0cda93 1213
0d0cda93
TK		 1214 err = crypto_engine_start(dd->engine);
1215 if (err)
1216 goto err_engine;
1217
f9fb69e7 1218 for (i = 0; i < dd->pdata->algs_info_size; i++) {
3741bbb2
LV		 1219 if (!dd->pdata->algs_info[i].registered) {
1220 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1221 algp = &dd->pdata->algs_info[i].algs_list[j];
f9fb69e7 1222
3741bbb2 1223 pr_debug("reg alg: %s\n", algp->cra_name);
f9fb69e7 1224
3741bbb2
LV		 1225 err = crypto_register_alg(algp);
1226 if (err)
1227 goto err_algs;
f9fb69e7 1228
3741bbb2
LV		 1229 dd->pdata->algs_info[i].registered++;
1230 }
f9fb69e7 1231 }
537559a5
DK		 1232 }
1233
ad18cc9d
TK		 1234 if (dd->pdata->aead_algs_info &&
1235 !dd->pdata->aead_algs_info->registered) {
1236 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
1237 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1238 algp = &aalg->base;
1239
1240 pr_debug("reg alg: %s\n", algp->cra_name);
ad18cc9d
TK		 1241
1242 err = crypto_register_aead(aalg);
1243 if (err)
1244 goto err_aead_algs;
1245
1246 dd->pdata->aead_algs_info->registered++;
1247 }
1248 }
1249
537c62ca
TK		 1250 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
1251 if (err) {
1252 dev_err(dev, "could not create sysfs device attrs\n");
1253 goto err_aead_algs;
1254 }
1255
537559a5 1256 return 0;
ad18cc9d
TK		 1257err_aead_algs:
1258 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1259 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1260 crypto_unregister_aead(aalg);
1261 }
537559a5 1262err_algs:
f9fb69e7
MG		 1263 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1264 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1265 crypto_unregister_alg(
1266 &dd->pdata->algs_info[i].algs_list[j]);
da8b29a6 1267
0d0cda93
TK		 1268err_engine:
1269 if (dd->engine)
1270 crypto_engine_exit(dd->engine);
1271
da8b29a6 1272 omap_aes_dma_cleanup(dd);
1801ad94 1273err_irq:
21fe9767 1274 tasklet_kill(&dd->done_task);
5946c4a5 1275 pm_runtime_disable(dev);
537559a5 1276err_res:
537559a5
DK		 1277 dd = NULL;
1278err_data:
1279 dev_err(dev, "initialization failed.\n");
1280 return err;
1281}
1282
1283static int omap_aes_remove(struct platform_device *pdev)
1284{
1285 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
ad18cc9d 1286 struct aead_alg *aalg;
f9fb69e7 1287 int i, j;
537559a5
DK		 1288
1289 if (!dd)
1290 return -ENODEV;
1291
1292 spin_lock(&list_lock);
1293 list_del(&dd->list);
1294 spin_unlock(&list_lock);
1295
f9fb69e7
MG		 1296 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1297 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1298 crypto_unregister_alg(
1299 &dd->pdata->algs_info[i].algs_list[j]);
537559a5 1300
ad18cc9d
TK		 1301 for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) {
1302 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1303 crypto_unregister_aead(aalg);
1304 }
1305
0529900a 1306 crypto_engine_exit(dd->engine);
ad18cc9d 1307
21fe9767 1308 tasklet_kill(&dd->done_task);
537559a5 1309 omap_aes_dma_cleanup(dd);
5946c4a5 1310 pm_runtime_disable(dd->dev);
537559a5
DK		 1311 dd = NULL;
1312
1313 return 0;
1314}
1315
0635fb3a
MG		 1316#ifdef CONFIG_PM_SLEEP
1317static int omap_aes_suspend(struct device *dev)
1318{
1319 pm_runtime_put_sync(dev);
1320 return 0;
1321}
1322
1323static int omap_aes_resume(struct device *dev)
1324{
1325 pm_runtime_get_sync(dev);
1326 return 0;
1327}
1328#endif
1329
ea7b2843 1330static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
0635fb3a 1331
537559a5
DK		 1332static struct platform_driver omap_aes_driver = {
1333 .probe = omap_aes_probe,
1334 .remove = omap_aes_remove,
1335 .driver = {
1336 .name = "omap-aes",
0635fb3a 1337 .pm = &omap_aes_pm_ops,
bc69d124 1338 .of_match_table = omap_aes_of_match,
537559a5
DK		 1339 },
1340};
1341
94e51df9 1342module_platform_driver(omap_aes_driver);
537559a5
DK		 1343
1344MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1345MODULE_LICENSE("GPL v2");
1346MODULE_AUTHOR("Dmitry Kasatkin");
1347
Linux 6.x block layer and io_uring tree(s)