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crypto: arm64/aes-blk - ensure XTS mask is always loaded
[linux-block.git] / drivers / crypto / mxs-dcp.c
CommitLineData
15b59e7c
MV		 1/*
2 * Freescale i.MX23/i.MX28 Data Co-Processor driver
3 *
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
15b59e7c
MV		 14#include <linux/dma-mapping.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/kthread.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/stmp_device.h>
23
24#include <crypto/aes.h>
25#include <crypto/sha.h>
26#include <crypto/internal/hash.h>
29406bb9 27#include <crypto/internal/skcipher.h>
15b59e7c
MV		 28
29#define DCP_MAX_CHANS 4
30#define DCP_BUF_SZ PAGE_SIZE
c709eeba 31#define DCP_SHA_PAY_SZ 64
15b59e7c 32
1a7c6856
MV		 33#define DCP_ALIGNMENT 64
34
c709eeba
RS		 35/*
36 * Null hashes to align with hw behavior on imx6sl and ull
37 * these are flipped for consistency with hw output
38 */
39const uint8_t sha1_null_hash[] =
40 "\x09\x07\xd8\xaf\x90\x18\x60\x95\xef\xbf"
41 "\x55\x32\x0d\x4b\x6b\x5e\xee\xa3\x39\xda";
42
43const uint8_t sha256_null_hash[] =
44 "\x55\xb8\x52\x78\x1b\x99\x95\xa4"
45 "\x4c\x93\x9b\x64\xe4\x41\xae\x27"
46 "\x24\xb9\x6f\x99\xc8\xf4\xfb\x9a"
47 "\x14\x1c\xfc\x98\x42\xc4\xb0\xe3";
48
15b59e7c
MV		 49/* DCP DMA descriptor. */
50struct dcp_dma_desc {
51 uint32_t next_cmd_addr;
52 uint32_t control0;
53 uint32_t control1;
54 uint32_t source;
55 uint32_t destination;
56 uint32_t size;
57 uint32_t payload;
58 uint32_t status;
59};
60
61/* Coherent aligned block for bounce buffering. */
62struct dcp_coherent_block {
63 uint8_t aes_in_buf[DCP_BUF_SZ];
64 uint8_t aes_out_buf[DCP_BUF_SZ];
65 uint8_t sha_in_buf[DCP_BUF_SZ];
c709eeba 66 uint8_t sha_out_buf[DCP_SHA_PAY_SZ];
15b59e7c
MV		 67
68 uint8_t aes_key[2 * AES_KEYSIZE_128];
15b59e7c
MV		 69
70 struct dcp_dma_desc desc[DCP_MAX_CHANS];
71};
72
73struct dcp {
74 struct device *dev;
75 void __iomem *base;
76
77 uint32_t caps;
78
79 struct dcp_coherent_block *coh;
80
81 struct completion completion[DCP_MAX_CHANS];
82 struct mutex mutex[DCP_MAX_CHANS];
83 struct task_struct *thread[DCP_MAX_CHANS];
84 struct crypto_queue queue[DCP_MAX_CHANS];
85};
86
87enum dcp_chan {
88 DCP_CHAN_HASH_SHA = 0,
89 DCP_CHAN_CRYPTO = 2,
90};
91
92struct dcp_async_ctx {
93 /* Common context */
94 enum dcp_chan chan;
95 uint32_t fill;
96
97 /* SHA Hash-specific context */
98 struct mutex mutex;
99 uint32_t alg;
100 unsigned int hot:1;
101
102 /* Crypto-specific context */
f805f59d 103 struct crypto_sync_skcipher *fallback;
15b59e7c
MV		 104 unsigned int key_len;
105 uint8_t key[AES_KEYSIZE_128];
106};
107
2021abaa
MV		 108struct dcp_aes_req_ctx {
109 unsigned int enc:1;
110 unsigned int ecb:1;
111};
112
15b59e7c
MV		 113struct dcp_sha_req_ctx {
114 unsigned int init:1;
115 unsigned int fini:1;
116};
117
ea9e7568
DD		 118struct dcp_export_state {
119 struct dcp_sha_req_ctx req_ctx;
120 struct dcp_async_ctx async_ctx;
121};
122
15b59e7c
MV		 123/*
124 * There can even be only one instance of the MXS DCP due to the
125 * design of Linux Crypto API.
126 */
127static struct dcp *global_sdcp;
15b59e7c
MV		 128
129/* DCP register layout. */
130#define MXS_DCP_CTRL 0x00
131#define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23)
132#define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22)
133
134#define MXS_DCP_STAT 0x10
135#define MXS_DCP_STAT_CLR 0x18
136#define MXS_DCP_STAT_IRQ_MASK 0xf
137
138#define MXS_DCP_CHANNELCTRL 0x20
139#define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
140
141#define MXS_DCP_CAPABILITY1 0x40
142#define MXS_DCP_CAPABILITY1_SHA256 (4 << 16)
143#define MXS_DCP_CAPABILITY1_SHA1 (1 << 16)
144#define MXS_DCP_CAPABILITY1_AES128 (1 << 0)
145
146#define MXS_DCP_CONTEXT 0x50
147
148#define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40))
149
150#define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40))
151
152#define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40))
153#define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40))
154
155/* DMA descriptor bits. */
156#define MXS_DCP_CONTROL0_HASH_TERM (1 << 13)
157#define MXS_DCP_CONTROL0_HASH_INIT (1 << 12)
158#define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11)
159#define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8)
160#define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9)
161#define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6)
162#define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5)
163#define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1)
164#define MXS_DCP_CONTROL0_INTERRUPT (1 << 0)
165
166#define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16)
167#define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16)
168#define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4)
169#define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4)
170#define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0)
171
172static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
173{
174 struct dcp *sdcp = global_sdcp;
175 const int chan = actx->chan;
176 uint32_t stat;
dd0fff8d 177 unsigned long ret;
15b59e7c
MV		 178 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
179
180 dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
181 DMA_TO_DEVICE);
182
183 reinit_completion(&sdcp->completion[chan]);
184
185 /* Clear status register. */
186 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
187
188 /* Load the DMA descriptor. */
189 writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
190
191 /* Increment the semaphore to start the DMA transfer. */
192 writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
193
194 ret = wait_for_completion_timeout(&sdcp->completion[chan],
195 msecs_to_jiffies(1000));
196 if (!ret) {
197 dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
198 chan, readl(sdcp->base + MXS_DCP_STAT));
199 return -ETIMEDOUT;
200 }
201
202 stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
203 if (stat & 0xff) {
204 dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
205 chan, stat);
206 return -EINVAL;
207 }
208
209 dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
210
211 return 0;
212}
213
214/*
215 * Encryption (AES128)
216 */
2021abaa
MV		 217static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
218 struct ablkcipher_request *req, int init)
15b59e7c
MV		 219{
220 struct dcp *sdcp = global_sdcp;
221 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
2021abaa 222 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
15b59e7c
MV		 223 int ret;
224
225 dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
226 2 * AES_KEYSIZE_128,
227 DMA_TO_DEVICE);
228 dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
229 DCP_BUF_SZ, DMA_TO_DEVICE);
230 dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
231 DCP_BUF_SZ, DMA_FROM_DEVICE);
232
fadd7a6e
RS		 233 if (actx->fill % AES_BLOCK_SIZE) {
234 dev_err(sdcp->dev, "Invalid block size!\n");
235 ret = -EINVAL;
236 goto aes_done_run;
237 }
238
15b59e7c
MV		 239 /* Fill in the DMA descriptor. */
240 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
241 MXS_DCP_CONTROL0_INTERRUPT |
242 MXS_DCP_CONTROL0_ENABLE_CIPHER;
243
244 /* Payload contains the key. */
245 desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
246
2021abaa 247 if (rctx->enc)
15b59e7c
MV		 248 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
249 if (init)
250 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
251
252 desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
253
2021abaa 254 if (rctx->ecb)
15b59e7c
MV		 255 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
256 else
257 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
258
259 desc->next_cmd_addr = 0;
260 desc->source = src_phys;
261 desc->destination = dst_phys;
262 desc->size = actx->fill;
263 desc->payload = key_phys;
264 desc->status = 0;
265
266 ret = mxs_dcp_start_dma(actx);
267
fadd7a6e 268aes_done_run:
15b59e7c
MV		 269 dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
270 DMA_TO_DEVICE);
271 dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
272 dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
273
274 return ret;
275}
276
277static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
278{
279 struct dcp *sdcp = global_sdcp;
280
281 struct ablkcipher_request *req = ablkcipher_request_cast(arq);
282 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
2021abaa 283 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
15b59e7c
MV		 284
285 struct scatterlist *dst = req->dst;
286 struct scatterlist *src = req->src;
287 const int nents = sg_nents(req->src);
288
289 const int out_off = DCP_BUF_SZ;
290 uint8_t *in_buf = sdcp->coh->aes_in_buf;
291 uint8_t *out_buf = sdcp->coh->aes_out_buf;
292
293 uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
294 uint32_t dst_off = 0;
fadd7a6e 295 uint32_t last_out_len = 0;
15b59e7c
MV		 296
297 uint8_t *key = sdcp->coh->aes_key;
298
299 int ret = 0;
300 int split = 0;
fadd7a6e 301 unsigned int i, len, clen, rem = 0, tlen = 0;
15b59e7c 302 int init = 0;
fadd7a6e 303 bool limit_hit = false;
15b59e7c
MV		 304
305 actx->fill = 0;
306
307 /* Copy the key from the temporary location. */
308 memcpy(key, actx->key, actx->key_len);
309
2021abaa 310 if (!rctx->ecb) {
15b59e7c
MV		 311 /* Copy the CBC IV just past the key. */
312 memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128);
313 /* CBC needs the INIT set. */
314 init = 1;
315 } else {
316 memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
317 }
318
319 for_each_sg(req->src, src, nents, i) {
320 src_buf = sg_virt(src);
321 len = sg_dma_len(src);
fadd7a6e
RS		 322 tlen += len;
323 limit_hit = tlen > req->nbytes;
324
325 if (limit_hit)
326 len = req->nbytes - (tlen - len);
15b59e7c
MV		 327
328 do {
329 if (actx->fill + len > out_off)
330 clen = out_off - actx->fill;
331 else
332 clen = len;
333
334 memcpy(in_buf + actx->fill, src_buf, clen);
335 len -= clen;
336 src_buf += clen;
337 actx->fill += clen;
338
339 /*
340 * If we filled the buffer or this is the last SG,
341 * submit the buffer.
342 */
fadd7a6e
RS		 343 if (actx->fill == out_off || sg_is_last(src) ||
344 limit_hit) {
2021abaa 345 ret = mxs_dcp_run_aes(actx, req, init);
15b59e7c
MV		 346 if (ret)
347 return ret;
348 init = 0;
349
350 out_tmp = out_buf;
fadd7a6e 351 last_out_len = actx->fill;
15b59e7c
MV		 352 while (dst && actx->fill) {
353 if (!split) {
354 dst_buf = sg_virt(dst);
355 dst_off = 0;
356 }
357 rem = min(sg_dma_len(dst) - dst_off,
358 actx->fill);
359
360 memcpy(dst_buf + dst_off, out_tmp, rem);
361 out_tmp += rem;
362 dst_off += rem;
363 actx->fill -= rem;
364
365 if (dst_off == sg_dma_len(dst)) {
366 dst = sg_next(dst);
367 split = 0;
368 } else {
369 split = 1;
370 }
371 }
372 }
373 } while (len);
fadd7a6e
RS		 374
375 if (limit_hit)
376 break;
377 }
378
379 /* Copy the IV for CBC for chaining */
380 if (!rctx->ecb) {
381 if (rctx->enc)
382 memcpy(req->info, out_buf+(last_out_len-AES_BLOCK_SIZE),
383 AES_BLOCK_SIZE);
384 else
385 memcpy(req->info, in_buf+(last_out_len-AES_BLOCK_SIZE),
386 AES_BLOCK_SIZE);
15b59e7c
MV		 387 }
388
389 return ret;
390}
391
392static int dcp_chan_thread_aes(void *data)
393{
394 struct dcp *sdcp = global_sdcp;
395 const int chan = DCP_CHAN_CRYPTO;
396
397 struct crypto_async_request *backlog;
398 struct crypto_async_request *arq;
399
400 int ret;
401
402 do {
403 __set_current_state(TASK_INTERRUPTIBLE);
404
405 mutex_lock(&sdcp->mutex[chan]);
406 backlog = crypto_get_backlog(&sdcp->queue[chan]);
407 arq = crypto_dequeue_request(&sdcp->queue[chan]);
408 mutex_unlock(&sdcp->mutex[chan]);
409
410 if (backlog)
411 backlog->complete(backlog, -EINPROGRESS);
412
413 if (arq) {
414 ret = mxs_dcp_aes_block_crypt(arq);
415 arq->complete(arq, ret);
416 continue;
417 }
418
419 schedule();
420 } while (!kthread_should_stop());
421
422 return 0;
423}
424
425static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc)
426{
29406bb9
HX		 427 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
428 struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx(tfm);
f805f59d 429 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
15b59e7c
MV		 430 int ret;
431
f805f59d 432 skcipher_request_set_sync_tfm(subreq, ctx->fallback);
29406bb9
HX		 433 skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL);
434 skcipher_request_set_crypt(subreq, req->src, req->dst,
435 req->nbytes, req->info);
15b59e7c
MV		 436
437 if (enc)
29406bb9 438 ret = crypto_skcipher_encrypt(subreq);
15b59e7c 439 else
29406bb9 440 ret = crypto_skcipher_decrypt(subreq);
15b59e7c 441
29406bb9 442 skcipher_request_zero(subreq);
15b59e7c
MV		 443
444 return ret;
445}
446
447static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb)
448{
449 struct dcp *sdcp = global_sdcp;
450 struct crypto_async_request *arq = &req->base;
451 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
2021abaa 452 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
15b59e7c
MV		 453 int ret;
454
455 if (unlikely(actx->key_len != AES_KEYSIZE_128))
456 return mxs_dcp_block_fallback(req, enc);
457
2021abaa
MV		 458 rctx->enc = enc;
459 rctx->ecb = ecb;
15b59e7c
MV		 460 actx->chan = DCP_CHAN_CRYPTO;
461
462 mutex_lock(&sdcp->mutex[actx->chan]);
463 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
464 mutex_unlock(&sdcp->mutex[actx->chan]);
465
466 wake_up_process(sdcp->thread[actx->chan]);
467
468 return -EINPROGRESS;
469}
470
471static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req)
472{
473 return mxs_dcp_aes_enqueue(req, 0, 1);
474}
475
476static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req)
477{
478 return mxs_dcp_aes_enqueue(req, 1, 1);
479}
480
481static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req)
482{
483 return mxs_dcp_aes_enqueue(req, 0, 0);
484}
485
486static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req)
487{
488 return mxs_dcp_aes_enqueue(req, 1, 0);
489}
490
491static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
492 unsigned int len)
493{
494 struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm);
495 unsigned int ret;
496
497 /*
498 * AES 128 is supposed by the hardware, store key into temporary
499 * buffer and exit. We must use the temporary buffer here, since
500 * there can still be an operation in progress.
501 */
502 actx->key_len = len;
503 if (len == AES_KEYSIZE_128) {
504 memcpy(actx->key, key, len);
505 return 0;
506 }
507
15b59e7c
MV		 508 /*
509 * If the requested AES key size is not supported by the hardware,
510 * but is supported by in-kernel software implementation, we use
511 * software fallback.
512 */
f805f59d
KC		 513 crypto_sync_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK);
514 crypto_sync_skcipher_set_flags(actx->fallback,
29406bb9 515 tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
15b59e7c 516
f805f59d 517 ret = crypto_sync_skcipher_setkey(actx->fallback, key, len);
15b59e7c
MV		 518 if (!ret)
519 return 0;
520
521 tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
f805f59d 522 tfm->base.crt_flags |= crypto_sync_skcipher_get_flags(actx->fallback) &
29406bb9 523 CRYPTO_TFM_RES_MASK;
15b59e7c
MV		 524
525 return ret;
526}
527
528static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm)
529{
2231204b 530 const char *name = crypto_tfm_alg_name(tfm);
15b59e7c 531 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
f805f59d 532 struct crypto_sync_skcipher *blk;
15b59e7c 533
f805f59d 534 blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
15b59e7c
MV		 535 if (IS_ERR(blk))
536 return PTR_ERR(blk);
537
538 actx->fallback = blk;
2021abaa 539 tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx);
15b59e7c
MV		 540 return 0;
541}
542
543static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm)
544{
545 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
546
f805f59d 547 crypto_free_sync_skcipher(actx->fallback);
15b59e7c
MV		 548}
549
550/*
551 * Hashing (SHA1/SHA256)
552 */
553static int mxs_dcp_run_sha(struct ahash_request *req)
554{
555 struct dcp *sdcp = global_sdcp;
556 int ret;
557
558 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
559 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
560 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
15b59e7c 561 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
15b59e7c 562
04d088cc 563 dma_addr_t digest_phys = 0;
15b59e7c
MV		 564 dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
565 DCP_BUF_SZ, DMA_TO_DEVICE);
566
567 /* Fill in the DMA descriptor. */
568 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
569 MXS_DCP_CONTROL0_INTERRUPT |
570 MXS_DCP_CONTROL0_ENABLE_HASH;
571 if (rctx->init)
572 desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
573
574 desc->control1 = actx->alg;
575 desc->next_cmd_addr = 0;
576 desc->source = buf_phys;
577 desc->destination = 0;
578 desc->size = actx->fill;
579 desc->payload = 0;
580 desc->status = 0;
581
c709eeba
RS		 582 /*
583 * Align driver with hw behavior when generating null hashes
584 */
585 if (rctx->init && rctx->fini && desc->size == 0) {
586 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
587 const uint8_t *sha_buf =
588 (actx->alg == MXS_DCP_CONTROL1_HASH_SELECT_SHA1) ?
589 sha1_null_hash : sha256_null_hash;
590 memcpy(sdcp->coh->sha_out_buf, sha_buf, halg->digestsize);
591 ret = 0;
592 goto done_run;
593 }
594
15b59e7c
MV		 595 /* Set HASH_TERM bit for last transfer block. */
596 if (rctx->fini) {
c709eeba
RS		 597 digest_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_out_buf,
598 DCP_SHA_PAY_SZ, DMA_FROM_DEVICE);
15b59e7c
MV		 599 desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
600 desc->payload = digest_phys;
601 }
602
603 ret = mxs_dcp_start_dma(actx);
604
04d088cc 605 if (rctx->fini)
c709eeba 606 dma_unmap_single(sdcp->dev, digest_phys, DCP_SHA_PAY_SZ,
04d088cc
MV		 607 DMA_FROM_DEVICE);
608
c709eeba 609done_run:
15b59e7c
MV		 610 dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
611
612 return ret;
613}
614
615static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
616{
617 struct dcp *sdcp = global_sdcp;
618
619 struct ahash_request *req = ahash_request_cast(arq);
620 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
621 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
622 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
623 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
624 const int nents = sg_nents(req->src);
625
15b59e7c 626 uint8_t *in_buf = sdcp->coh->sha_in_buf;
c709eeba 627 uint8_t *out_buf = sdcp->coh->sha_out_buf;
15b59e7c
MV		 628
629 uint8_t *src_buf;
630
631 struct scatterlist *src;
632
633 unsigned int i, len, clen;
634 int ret;
635
636 int fin = rctx->fini;
637 if (fin)
638 rctx->fini = 0;
639
640 for_each_sg(req->src, src, nents, i) {
641 src_buf = sg_virt(src);
642 len = sg_dma_len(src);
643
644 do {
645 if (actx->fill + len > DCP_BUF_SZ)
646 clen = DCP_BUF_SZ - actx->fill;
647 else
648 clen = len;
649
650 memcpy(in_buf + actx->fill, src_buf, clen);
651 len -= clen;
652 src_buf += clen;
653 actx->fill += clen;
654
655 /*
656 * If we filled the buffer and still have some
657 * more data, submit the buffer.
658 */
659 if (len && actx->fill == DCP_BUF_SZ) {
660 ret = mxs_dcp_run_sha(req);
661 if (ret)
662 return ret;
663 actx->fill = 0;
664 rctx->init = 0;
665 }
666 } while (len);
667 }
668
669 if (fin) {
670 rctx->fini = 1;
671
672 /* Submit whatever is left. */
04d088cc
MV		 673 if (!req->result)
674 return -EINVAL;
675
15b59e7c 676 ret = mxs_dcp_run_sha(req);
04d088cc 677 if (ret)
15b59e7c 678 return ret;
04d088cc 679
15b59e7c
MV		 680 actx->fill = 0;
681
c709eeba
RS		 682 /* For some reason the result is flipped */
683 for (i = 0; i < halg->digestsize; i++)
684 req->result[i] = out_buf[halg->digestsize - i - 1];
15b59e7c
MV		 685 }
686
687 return 0;
688}
689
690static int dcp_chan_thread_sha(void *data)
691{
692 struct dcp *sdcp = global_sdcp;
693 const int chan = DCP_CHAN_HASH_SHA;
694
695 struct crypto_async_request *backlog;
696 struct crypto_async_request *arq;
697
698 struct dcp_sha_req_ctx *rctx;
699
700 struct ahash_request *req;
701 int ret, fini;
702
703 do {
704 __set_current_state(TASK_INTERRUPTIBLE);
705
706 mutex_lock(&sdcp->mutex[chan]);
707 backlog = crypto_get_backlog(&sdcp->queue[chan]);
708 arq = crypto_dequeue_request(&sdcp->queue[chan]);
709 mutex_unlock(&sdcp->mutex[chan]);
710
711 if (backlog)
712 backlog->complete(backlog, -EINPROGRESS);
713
714 if (arq) {
715 req = ahash_request_cast(arq);
716 rctx = ahash_request_ctx(req);
717
718 ret = dcp_sha_req_to_buf(arq);
719 fini = rctx->fini;
720 arq->complete(arq, ret);
721 if (!fini)
722 continue;
723 }
724
725 schedule();
726 } while (!kthread_should_stop());
727
728 return 0;
729}
730
731static int dcp_sha_init(struct ahash_request *req)
732{
733 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
734 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
735
736 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
737
738 /*
739 * Start hashing session. The code below only inits the
740 * hashing session context, nothing more.
741 */
742 memset(actx, 0, sizeof(*actx));
743
744 if (strcmp(halg->base.cra_name, "sha1") == 0)
745 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
746 else
747 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
748
749 actx->fill = 0;
750 actx->hot = 0;
751 actx->chan = DCP_CHAN_HASH_SHA;
752
753 mutex_init(&actx->mutex);
754
755 return 0;
756}
757
758static int dcp_sha_update_fx(struct ahash_request *req, int fini)
759{
760 struct dcp *sdcp = global_sdcp;
761
762 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
763 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
764 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
765
766 int ret;
767
768 /*
769 * Ignore requests that have no data in them and are not
770 * the trailing requests in the stream of requests.
771 */
772 if (!req->nbytes && !fini)
773 return 0;
774
775 mutex_lock(&actx->mutex);
776
777 rctx->fini = fini;
778
779 if (!actx->hot) {
780 actx->hot = 1;
781 rctx->init = 1;
782 }
783
784 mutex_lock(&sdcp->mutex[actx->chan]);
785 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
786 mutex_unlock(&sdcp->mutex[actx->chan]);
787
788 wake_up_process(sdcp->thread[actx->chan]);
789 mutex_unlock(&actx->mutex);
790
791 return -EINPROGRESS;
792}
793
794static int dcp_sha_update(struct ahash_request *req)
795{
796 return dcp_sha_update_fx(req, 0);
797}
798
799static int dcp_sha_final(struct ahash_request *req)
800{
801 ahash_request_set_crypt(req, NULL, req->result, 0);
802 req->nbytes = 0;
803 return dcp_sha_update_fx(req, 1);
804}
805
806static int dcp_sha_finup(struct ahash_request *req)
807{
808 return dcp_sha_update_fx(req, 1);
809}
810
811static int dcp_sha_digest(struct ahash_request *req)
812{
813 int ret;
814
815 ret = dcp_sha_init(req);
816 if (ret)
817 return ret;
818
819 return dcp_sha_finup(req);
820}
821
ea9e7568 822static int dcp_sha_import(struct ahash_request *req, const void *in)
9190b6fd 823{
ea9e7568
DD		 824 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
825 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
826 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
827 const struct dcp_export_state *export = in;
828
829 memset(rctx, 0, sizeof(struct dcp_sha_req_ctx));
830 memset(actx, 0, sizeof(struct dcp_async_ctx));
831 memcpy(rctx, &export->req_ctx, sizeof(struct dcp_sha_req_ctx));
832 memcpy(actx, &export->async_ctx, sizeof(struct dcp_async_ctx));
833
834 return 0;
9190b6fd
KK		 835}
836
ea9e7568 837static int dcp_sha_export(struct ahash_request *req, void *out)
9190b6fd 838{
ea9e7568
DD		 839 struct dcp_sha_req_ctx *rctx_state = ahash_request_ctx(req);
840 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
841 struct dcp_async_ctx *actx_state = crypto_ahash_ctx(tfm);
842 struct dcp_export_state *export = out;
843
844 memcpy(&export->req_ctx, rctx_state, sizeof(struct dcp_sha_req_ctx));
845 memcpy(&export->async_ctx, actx_state, sizeof(struct dcp_async_ctx));
846
847 return 0;
9190b6fd
KK		 848}
849
15b59e7c
MV		 850static int dcp_sha_cra_init(struct crypto_tfm *tfm)
851{
852 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
853 sizeof(struct dcp_sha_req_ctx));
854 return 0;
855}
856
857static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
858{
859}
860
861/* AES 128 ECB and AES 128 CBC */
862static struct crypto_alg dcp_aes_algs[] = {
863 {
864 .cra_name = "ecb(aes)",
865 .cra_driver_name = "ecb-aes-dcp",
866 .cra_priority = 400,
867 .cra_alignmask = 15,
868 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
869 CRYPTO_ALG_ASYNC |
870 CRYPTO_ALG_NEED_FALLBACK,
871 .cra_init = mxs_dcp_aes_fallback_init,
872 .cra_exit = mxs_dcp_aes_fallback_exit,
873 .cra_blocksize = AES_BLOCK_SIZE,
874 .cra_ctxsize = sizeof(struct dcp_async_ctx),
875 .cra_type = &crypto_ablkcipher_type,
876 .cra_module = THIS_MODULE,
877 .cra_u = {
878 .ablkcipher = {
879 .min_keysize = AES_MIN_KEY_SIZE,
880 .max_keysize = AES_MAX_KEY_SIZE,
881 .setkey = mxs_dcp_aes_setkey,
882 .encrypt = mxs_dcp_aes_ecb_encrypt,
883 .decrypt = mxs_dcp_aes_ecb_decrypt
884 },
885 },
886 }, {
887 .cra_name = "cbc(aes)",
888 .cra_driver_name = "cbc-aes-dcp",
889 .cra_priority = 400,
890 .cra_alignmask = 15,
891 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
892 CRYPTO_ALG_ASYNC |
893 CRYPTO_ALG_NEED_FALLBACK,
894 .cra_init = mxs_dcp_aes_fallback_init,
895 .cra_exit = mxs_dcp_aes_fallback_exit,
896 .cra_blocksize = AES_BLOCK_SIZE,
897 .cra_ctxsize = sizeof(struct dcp_async_ctx),
898 .cra_type = &crypto_ablkcipher_type,
899 .cra_module = THIS_MODULE,
900 .cra_u = {
901 .ablkcipher = {
902 .min_keysize = AES_MIN_KEY_SIZE,
903 .max_keysize = AES_MAX_KEY_SIZE,
904 .setkey = mxs_dcp_aes_setkey,
905 .encrypt = mxs_dcp_aes_cbc_encrypt,
906 .decrypt = mxs_dcp_aes_cbc_decrypt,
907 .ivsize = AES_BLOCK_SIZE,
908 },
909 },
910 },
911};
912
913/* SHA1 */
914static struct ahash_alg dcp_sha1_alg = {
915 .init = dcp_sha_init,
916 .update = dcp_sha_update,
917 .final = dcp_sha_final,
918 .finup = dcp_sha_finup,
919 .digest = dcp_sha_digest,
ea9e7568
DD		 920 .import = dcp_sha_import,
921 .export = dcp_sha_export,
15b59e7c
MV		 922 .halg = {
923 .digestsize = SHA1_DIGEST_SIZE,
ea9e7568 924 .statesize = sizeof(struct dcp_export_state),
15b59e7c
MV		 925 .base = {
926 .cra_name = "sha1",
927 .cra_driver_name = "sha1-dcp",
928 .cra_priority = 400,
929 .cra_alignmask = 63,
930 .cra_flags = CRYPTO_ALG_ASYNC,
931 .cra_blocksize = SHA1_BLOCK_SIZE,
932 .cra_ctxsize = sizeof(struct dcp_async_ctx),
933 .cra_module = THIS_MODULE,
934 .cra_init = dcp_sha_cra_init,
935 .cra_exit = dcp_sha_cra_exit,
936 },
937 },
938};
939
940/* SHA256 */
941static struct ahash_alg dcp_sha256_alg = {
942 .init = dcp_sha_init,
943 .update = dcp_sha_update,
944 .final = dcp_sha_final,
945 .finup = dcp_sha_finup,
946 .digest = dcp_sha_digest,
ea9e7568
DD		 947 .import = dcp_sha_import,
948 .export = dcp_sha_export,
15b59e7c
MV		 949 .halg = {
950 .digestsize = SHA256_DIGEST_SIZE,
ea9e7568 951 .statesize = sizeof(struct dcp_export_state),
15b59e7c
MV		 952 .base = {
953 .cra_name = "sha256",
954 .cra_driver_name = "sha256-dcp",
955 .cra_priority = 400,
956 .cra_alignmask = 63,
957 .cra_flags = CRYPTO_ALG_ASYNC,
958 .cra_blocksize = SHA256_BLOCK_SIZE,
959 .cra_ctxsize = sizeof(struct dcp_async_ctx),
960 .cra_module = THIS_MODULE,
961 .cra_init = dcp_sha_cra_init,
962 .cra_exit = dcp_sha_cra_exit,
963 },
964 },
965};
966
967static irqreturn_t mxs_dcp_irq(int irq, void *context)
968{
969 struct dcp *sdcp = context;
970 uint32_t stat;
971 int i;
972
973 stat = readl(sdcp->base + MXS_DCP_STAT);
974 stat &= MXS_DCP_STAT_IRQ_MASK;
975 if (!stat)
976 return IRQ_NONE;
977
978 /* Clear the interrupts. */
979 writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
980
981 /* Complete the DMA requests that finished. */
982 for (i = 0; i < DCP_MAX_CHANS; i++)
983 if (stat & (1 << i))
984 complete(&sdcp->completion[i]);
985
986 return IRQ_HANDLED;
987}
988
989static int mxs_dcp_probe(struct platform_device *pdev)
990{
991 struct device *dev = &pdev->dev;
992 struct dcp *sdcp = NULL;
993 int i, ret;
994
995 struct resource *iores;
996 int dcp_vmi_irq, dcp_irq;
997
15b59e7c
MV		 998 if (global_sdcp) {
999 dev_err(dev, "Only one DCP instance allowed!\n");
5fc8005b 1000 return -ENODEV;
15b59e7c
MV		 1001 }
1002
1003 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004 dcp_vmi_irq = platform_get_irq(pdev, 0);
353ef083
GS		 1005 if (dcp_vmi_irq < 0) {
1006 dev_err(dev, "Failed to get IRQ: (%d)!\n", dcp_vmi_irq);
5fc8005b 1007 return dcp_vmi_irq;
353ef083 1008 }
d9588f87 1009
15b59e7c 1010 dcp_irq = platform_get_irq(pdev, 1);
353ef083
GS		 1011 if (dcp_irq < 0) {
1012 dev_err(dev, "Failed to get IRQ: (%d)!\n", dcp_irq);
5fc8005b 1013 return dcp_irq;
353ef083 1014 }
15b59e7c
MV		 1015
1016 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
5fc8005b
FE		 1017 if (!sdcp)
1018 return -ENOMEM;
15b59e7c
MV		 1019
1020 sdcp->dev = dev;
1021 sdcp->base = devm_ioremap_resource(dev, iores);
5fc8005b
FE		 1022 if (IS_ERR(sdcp->base))
1023 return PTR_ERR(sdcp->base);
1024
15b59e7c
MV		 1025
1026 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
1027 "dcp-vmi-irq", sdcp);
1028 if (ret) {
1029 dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
5fc8005b 1030 return ret;
15b59e7c
MV		 1031 }
1032
1033 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
1034 "dcp-irq", sdcp);
1035 if (ret) {
1036 dev_err(dev, "Failed to claim DCP IRQ!\n");
5fc8005b 1037 return ret;
15b59e7c
MV		 1038 }
1039
1040 /* Allocate coherent helper block. */
1a7c6856
MV		 1041 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
1042 GFP_KERNEL);
5fc8005b
FE		 1043 if (!sdcp->coh)
1044 return -ENOMEM;
15b59e7c 1045
1a7c6856
MV		 1046 /* Re-align the structure so it fits the DCP constraints. */
1047 sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
1048
15b59e7c 1049 /* Restart the DCP block. */
fecfd7f7
FE		 1050 ret = stmp_reset_block(sdcp->base);
1051 if (ret)
5fc8005b 1052 return ret;
15b59e7c
MV		 1053
1054 /* Initialize control register. */
1055 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
1056 MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
1057 sdcp->base + MXS_DCP_CTRL);
1058
1059 /* Enable all DCP DMA channels. */
1060 writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
1061 sdcp->base + MXS_DCP_CHANNELCTRL);
1062
1063 /*
1064 * We do not enable context switching. Give the context buffer a
1065 * pointer to an illegal address so if context switching is
1066 * inadvertantly enabled, the DCP will return an error instead of
1067 * trashing good memory. The DCP DMA cannot access ROM, so any ROM
1068 * address will do.
1069 */
1070 writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
1071 for (i = 0; i < DCP_MAX_CHANS; i++)
1072 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
1073 writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
1074
1075 global_sdcp = sdcp;
1076
1077 platform_set_drvdata(pdev, sdcp);
1078
1079 for (i = 0; i < DCP_MAX_CHANS; i++) {
1080 mutex_init(&sdcp->mutex[i]);
1081 init_completion(&sdcp->completion[i]);
1082 crypto_init_queue(&sdcp->queue[i], 50);
1083 }
1084
1085 /* Create the SHA and AES handler threads. */
1086 sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
1087 NULL, "mxs_dcp_chan/sha");
1088 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
1089 dev_err(dev, "Error starting SHA thread!\n");
5fc8005b 1090 return PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
15b59e7c
MV		 1091 }
1092
1093 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
1094 NULL, "mxs_dcp_chan/aes");
1095 if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
1096 dev_err(dev, "Error starting SHA thread!\n");
1097 ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1098 goto err_destroy_sha_thread;
1099 }
1100
1101 /* Register the various crypto algorithms. */
1102 sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1103
1104 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1105 ret = crypto_register_algs(dcp_aes_algs,
1106 ARRAY_SIZE(dcp_aes_algs));
1107 if (ret) {
1108 /* Failed to register algorithm. */
1109 dev_err(dev, "Failed to register AES crypto!\n");
1110 goto err_destroy_aes_thread;
1111 }
1112 }
1113
1114 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1115 ret = crypto_register_ahash(&dcp_sha1_alg);
1116 if (ret) {
1117 dev_err(dev, "Failed to register %s hash!\n",
1118 dcp_sha1_alg.halg.base.cra_name);
1119 goto err_unregister_aes;
1120 }
1121 }
1122
1123 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1124 ret = crypto_register_ahash(&dcp_sha256_alg);
1125 if (ret) {
1126 dev_err(dev, "Failed to register %s hash!\n",
1127 dcp_sha256_alg.halg.base.cra_name);
1128 goto err_unregister_sha1;
1129 }
1130 }
1131
1132 return 0;
1133
1134err_unregister_sha1:
1135 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1136 crypto_unregister_ahash(&dcp_sha1_alg);
1137
1138err_unregister_aes:
1139 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1140 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1141
1142err_destroy_aes_thread:
1143 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1144
1145err_destroy_sha_thread:
1146 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
15b59e7c
MV		 1147 return ret;
1148}
1149
1150static int mxs_dcp_remove(struct platform_device *pdev)
1151{
1152 struct dcp *sdcp = platform_get_drvdata(pdev);
1153
15b59e7c
MV		 1154 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1155 crypto_unregister_ahash(&dcp_sha256_alg);
1156
1157 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1158 crypto_unregister_ahash(&dcp_sha1_alg);
1159
1160 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1161 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1162
1163 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1164 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1165
1166 platform_set_drvdata(pdev, NULL);
1167
15b59e7c 1168 global_sdcp = NULL;
15b59e7c
MV		 1169
1170 return 0;
1171}
1172
1173static const struct of_device_id mxs_dcp_dt_ids[] = {
1174 { .compatible = "fsl,imx23-dcp", .data = NULL, },
1175 { .compatible = "fsl,imx28-dcp", .data = NULL, },
1176 { /* sentinel */ }
1177};
1178
1179MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1180
1181static struct platform_driver mxs_dcp_driver = {
1182 .probe = mxs_dcp_probe,
1183 .remove = mxs_dcp_remove,
1184 .driver = {
1185 .name = "mxs-dcp",
15b59e7c
MV		 1186 .of_match_table = mxs_dcp_dt_ids,
1187 },
1188};
1189
1190module_platform_driver(mxs_dcp_driver);
1191
1192MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1193MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1194MODULE_LICENSE("GPL");
1195MODULE_ALIAS("platform:mxs-dcp");
Linux 6.x block layer and io_uring tree(s)