Commit | Line | Data |
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85a7f0ac SAS |
1 | /* |
2 | * Support for Marvell's crypto engine which can be found on some Orion5X | |
3 | * boards. | |
4 | * | |
5 | * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc > | |
6 | * License: GPLv2 | |
7 | * | |
8 | */ | |
9 | #include <crypto/aes.h> | |
10 | #include <crypto/algapi.h> | |
11 | #include <linux/crypto.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/kthread.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/scatterlist.h> | |
5a0e3ad6 | 17 | #include <linux/slab.h> |
4bb33cc8 | 18 | #include <linux/module.h> |
1f80b126 | 19 | #include <linux/clk.h> |
750052dd US |
20 | #include <crypto/internal/hash.h> |
21 | #include <crypto/sha.h> | |
85a7f0ac SAS |
22 | |
23 | #include "mv_cesa.h" | |
750052dd US |
24 | |
25 | #define MV_CESA "MV-CESA:" | |
26 | #define MAX_HW_HASH_SIZE 0xFFFF | |
170dd56d | 27 | #define MV_CESA_EXPIRE 500 /* msec */ |
750052dd | 28 | |
85a7f0ac SAS |
29 | /* |
30 | * STM: | |
31 | * /---------------------------------------\ | |
32 | * | | request complete | |
33 | * \./ | | |
34 | * IDLE -> new request -> BUSY -> done -> DEQUEUE | |
35 | * /°\ | | |
36 | * | | more scatter entries | |
37 | * \________________/ | |
38 | */ | |
39 | enum engine_status { | |
40 | ENGINE_IDLE, | |
41 | ENGINE_BUSY, | |
42 | ENGINE_W_DEQUEUE, | |
43 | }; | |
44 | ||
45 | /** | |
46 | * struct req_progress - used for every crypt request | |
47 | * @src_sg_it: sg iterator for src | |
48 | * @dst_sg_it: sg iterator for dst | |
49 | * @sg_src_left: bytes left in src to process (scatter list) | |
50 | * @src_start: offset to add to src start position (scatter list) | |
750052dd | 51 | * @crypt_len: length of current hw crypt/hash process |
3b61a905 | 52 | * @hw_nbytes: total bytes to process in hw for this request |
f0d03dea | 53 | * @copy_back: whether to copy data back (crypt) or not (hash) |
85a7f0ac SAS |
54 | * @sg_dst_left: bytes left dst to process in this scatter list |
55 | * @dst_start: offset to add to dst start position (scatter list) | |
7a5f691e | 56 | * @hw_processed_bytes: number of bytes processed by hw (request). |
85a7f0ac SAS |
57 | * |
58 | * sg helper are used to iterate over the scatterlist. Since the size of the | |
59 | * SRAM may be less than the scatter size, this struct struct is used to keep | |
60 | * track of progress within current scatterlist. | |
61 | */ | |
62 | struct req_progress { | |
63 | struct sg_mapping_iter src_sg_it; | |
64 | struct sg_mapping_iter dst_sg_it; | |
a58094ac US |
65 | void (*complete) (void); |
66 | void (*process) (int is_first); | |
85a7f0ac SAS |
67 | |
68 | /* src mostly */ | |
69 | int sg_src_left; | |
70 | int src_start; | |
71 | int crypt_len; | |
3b61a905 | 72 | int hw_nbytes; |
85a7f0ac | 73 | /* dst mostly */ |
f0d03dea | 74 | int copy_back; |
85a7f0ac SAS |
75 | int sg_dst_left; |
76 | int dst_start; | |
7a5f691e | 77 | int hw_processed_bytes; |
85a7f0ac SAS |
78 | }; |
79 | ||
80 | struct crypto_priv { | |
81 | void __iomem *reg; | |
82 | void __iomem *sram; | |
83 | int irq; | |
1f80b126 | 84 | struct clk *clk; |
85a7f0ac SAS |
85 | struct task_struct *queue_th; |
86 | ||
87 | /* the lock protects queue and eng_st */ | |
88 | spinlock_t lock; | |
89 | struct crypto_queue queue; | |
90 | enum engine_status eng_st; | |
170dd56d | 91 | struct timer_list completion_timer; |
3b61a905 | 92 | struct crypto_async_request *cur_req; |
85a7f0ac SAS |
93 | struct req_progress p; |
94 | int max_req_size; | |
95 | int sram_size; | |
750052dd US |
96 | int has_sha1; |
97 | int has_hmac_sha1; | |
85a7f0ac SAS |
98 | }; |
99 | ||
100 | static struct crypto_priv *cpg; | |
101 | ||
102 | struct mv_ctx { | |
103 | u8 aes_enc_key[AES_KEY_LEN]; | |
104 | u32 aes_dec_key[8]; | |
105 | int key_len; | |
106 | u32 need_calc_aes_dkey; | |
107 | }; | |
108 | ||
109 | enum crypto_op { | |
110 | COP_AES_ECB, | |
111 | COP_AES_CBC, | |
112 | }; | |
113 | ||
114 | struct mv_req_ctx { | |
115 | enum crypto_op op; | |
116 | int decrypt; | |
117 | }; | |
118 | ||
750052dd US |
119 | enum hash_op { |
120 | COP_SHA1, | |
121 | COP_HMAC_SHA1 | |
122 | }; | |
123 | ||
124 | struct mv_tfm_hash_ctx { | |
125 | struct crypto_shash *fallback; | |
126 | struct crypto_shash *base_hash; | |
127 | u32 ivs[2 * SHA1_DIGEST_SIZE / 4]; | |
128 | int count_add; | |
129 | enum hash_op op; | |
130 | }; | |
131 | ||
132 | struct mv_req_hash_ctx { | |
133 | u64 count; | |
134 | u32 state[SHA1_DIGEST_SIZE / 4]; | |
135 | u8 buffer[SHA1_BLOCK_SIZE]; | |
136 | int first_hash; /* marks that we don't have previous state */ | |
137 | int last_chunk; /* marks that this is the 'final' request */ | |
138 | int extra_bytes; /* unprocessed bytes in buffer */ | |
139 | enum hash_op op; | |
140 | int count_add; | |
750052dd US |
141 | }; |
142 | ||
170dd56d PS |
143 | static void mv_completion_timer_callback(unsigned long unused) |
144 | { | |
145 | int active = readl(cpg->reg + SEC_ACCEL_CMD) & SEC_CMD_EN_SEC_ACCL0; | |
146 | ||
147 | printk(KERN_ERR MV_CESA | |
148 | "completion timer expired (CESA %sactive), cleaning up.\n", | |
149 | active ? "" : "in"); | |
150 | ||
151 | del_timer(&cpg->completion_timer); | |
152 | writel(SEC_CMD_DISABLE_SEC, cpg->reg + SEC_ACCEL_CMD); | |
153 | while(readl(cpg->reg + SEC_ACCEL_CMD) & SEC_CMD_DISABLE_SEC) | |
154 | printk(KERN_INFO MV_CESA "%s: waiting for engine finishing\n", __func__); | |
155 | cpg->eng_st = ENGINE_W_DEQUEUE; | |
156 | wake_up_process(cpg->queue_th); | |
157 | } | |
158 | ||
159 | static void mv_setup_timer(void) | |
160 | { | |
161 | setup_timer(&cpg->completion_timer, &mv_completion_timer_callback, 0); | |
162 | mod_timer(&cpg->completion_timer, | |
163 | jiffies + msecs_to_jiffies(MV_CESA_EXPIRE)); | |
164 | } | |
165 | ||
85a7f0ac SAS |
166 | static void compute_aes_dec_key(struct mv_ctx *ctx) |
167 | { | |
168 | struct crypto_aes_ctx gen_aes_key; | |
169 | int key_pos; | |
170 | ||
171 | if (!ctx->need_calc_aes_dkey) | |
172 | return; | |
173 | ||
174 | crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len); | |
175 | ||
176 | key_pos = ctx->key_len + 24; | |
177 | memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4); | |
178 | switch (ctx->key_len) { | |
179 | case AES_KEYSIZE_256: | |
180 | key_pos -= 2; | |
181 | /* fall */ | |
182 | case AES_KEYSIZE_192: | |
183 | key_pos -= 2; | |
184 | memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos], | |
185 | 4 * 4); | |
186 | break; | |
187 | } | |
188 | ctx->need_calc_aes_dkey = 0; | |
189 | } | |
190 | ||
191 | static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key, | |
192 | unsigned int len) | |
193 | { | |
194 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
195 | struct mv_ctx *ctx = crypto_tfm_ctx(tfm); | |
196 | ||
197 | switch (len) { | |
198 | case AES_KEYSIZE_128: | |
199 | case AES_KEYSIZE_192: | |
200 | case AES_KEYSIZE_256: | |
201 | break; | |
202 | default: | |
203 | crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
204 | return -EINVAL; | |
205 | } | |
206 | ctx->key_len = len; | |
207 | ctx->need_calc_aes_dkey = 1; | |
208 | ||
209 | memcpy(ctx->aes_enc_key, key, AES_KEY_LEN); | |
210 | return 0; | |
211 | } | |
212 | ||
15d4dd35 | 213 | static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len) |
85a7f0ac SAS |
214 | { |
215 | int ret; | |
15d4dd35 | 216 | void *sbuf; |
6677a776 | 217 | int copy_len; |
85a7f0ac | 218 | |
6677a776 | 219 | while (len) { |
15d4dd35 US |
220 | if (!p->sg_src_left) { |
221 | ret = sg_miter_next(&p->src_sg_it); | |
222 | BUG_ON(!ret); | |
223 | p->sg_src_left = p->src_sg_it.length; | |
224 | p->src_start = 0; | |
225 | } | |
85a7f0ac | 226 | |
15d4dd35 US |
227 | sbuf = p->src_sg_it.addr + p->src_start; |
228 | ||
6677a776 PS |
229 | copy_len = min(p->sg_src_left, len); |
230 | memcpy(dbuf, sbuf, copy_len); | |
231 | ||
232 | p->src_start += copy_len; | |
233 | p->sg_src_left -= copy_len; | |
234 | ||
235 | len -= copy_len; | |
236 | dbuf += copy_len; | |
15d4dd35 US |
237 | } |
238 | } | |
85a7f0ac | 239 | |
3b61a905 | 240 | static void setup_data_in(void) |
15d4dd35 US |
241 | { |
242 | struct req_progress *p = &cpg->p; | |
0c5c6c4b | 243 | int data_in_sram = |
7a5f691e | 244 | min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size); |
0c5c6c4b US |
245 | copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len, |
246 | data_in_sram - p->crypt_len); | |
247 | p->crypt_len = data_in_sram; | |
85a7f0ac SAS |
248 | } |
249 | ||
250 | static void mv_process_current_q(int first_block) | |
251 | { | |
3b61a905 | 252 | struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req); |
85a7f0ac SAS |
253 | struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm); |
254 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
255 | struct sec_accel_config op; | |
256 | ||
257 | switch (req_ctx->op) { | |
258 | case COP_AES_ECB: | |
259 | op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB; | |
260 | break; | |
261 | case COP_AES_CBC: | |
6bc6fcd6 | 262 | default: |
85a7f0ac SAS |
263 | op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC; |
264 | op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) | | |
265 | ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF); | |
266 | if (first_block) | |
267 | memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16); | |
268 | break; | |
269 | } | |
270 | if (req_ctx->decrypt) { | |
271 | op.config |= CFG_DIR_DEC; | |
272 | memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key, | |
273 | AES_KEY_LEN); | |
274 | } else { | |
275 | op.config |= CFG_DIR_ENC; | |
276 | memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key, | |
277 | AES_KEY_LEN); | |
278 | } | |
279 | ||
280 | switch (ctx->key_len) { | |
281 | case AES_KEYSIZE_128: | |
282 | op.config |= CFG_AES_LEN_128; | |
283 | break; | |
284 | case AES_KEYSIZE_192: | |
285 | op.config |= CFG_AES_LEN_192; | |
286 | break; | |
287 | case AES_KEYSIZE_256: | |
288 | op.config |= CFG_AES_LEN_256; | |
289 | break; | |
290 | } | |
291 | op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) | | |
292 | ENC_P_DST(SRAM_DATA_OUT_START); | |
293 | op.enc_key_p = SRAM_DATA_KEY_P; | |
294 | ||
3b61a905 | 295 | setup_data_in(); |
85a7f0ac SAS |
296 | op.enc_len = cpg->p.crypt_len; |
297 | memcpy(cpg->sram + SRAM_CONFIG, &op, | |
298 | sizeof(struct sec_accel_config)); | |
299 | ||
85a7f0ac | 300 | /* GO */ |
170dd56d | 301 | mv_setup_timer(); |
85a7f0ac | 302 | writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD); |
85a7f0ac SAS |
303 | } |
304 | ||
305 | static void mv_crypto_algo_completion(void) | |
306 | { | |
3b61a905 | 307 | struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req); |
85a7f0ac SAS |
308 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); |
309 | ||
a58094ac US |
310 | sg_miter_stop(&cpg->p.src_sg_it); |
311 | sg_miter_stop(&cpg->p.dst_sg_it); | |
312 | ||
85a7f0ac SAS |
313 | if (req_ctx->op != COP_AES_CBC) |
314 | return ; | |
315 | ||
316 | memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16); | |
317 | } | |
318 | ||
750052dd US |
319 | static void mv_process_hash_current(int first_block) |
320 | { | |
321 | struct ahash_request *req = ahash_request_cast(cpg->cur_req); | |
cc8d3505 | 322 | const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm); |
750052dd US |
323 | struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req); |
324 | struct req_progress *p = &cpg->p; | |
325 | struct sec_accel_config op = { 0 }; | |
326 | int is_last; | |
327 | ||
328 | switch (req_ctx->op) { | |
329 | case COP_SHA1: | |
330 | default: | |
331 | op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1; | |
332 | break; | |
333 | case COP_HMAC_SHA1: | |
334 | op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1; | |
cc8d3505 PS |
335 | memcpy(cpg->sram + SRAM_HMAC_IV_IN, |
336 | tfm_ctx->ivs, sizeof(tfm_ctx->ivs)); | |
750052dd US |
337 | break; |
338 | } | |
339 | ||
340 | op.mac_src_p = | |
341 | MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32) | |
342 | req_ctx-> | |
343 | count); | |
344 | ||
345 | setup_data_in(); | |
346 | ||
347 | op.mac_digest = | |
348 | MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len); | |
349 | op.mac_iv = | |
350 | MAC_INNER_IV_P(SRAM_HMAC_IV_IN) | | |
351 | MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT); | |
352 | ||
353 | is_last = req_ctx->last_chunk | |
354 | && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes) | |
355 | && (req_ctx->count <= MAX_HW_HASH_SIZE); | |
356 | if (req_ctx->first_hash) { | |
357 | if (is_last) | |
358 | op.config |= CFG_NOT_FRAG; | |
359 | else | |
360 | op.config |= CFG_FIRST_FRAG; | |
361 | ||
362 | req_ctx->first_hash = 0; | |
363 | } else { | |
364 | if (is_last) | |
365 | op.config |= CFG_LAST_FRAG; | |
366 | else | |
367 | op.config |= CFG_MID_FRAG; | |
86523487 | 368 | |
27425286 PS |
369 | if (first_block) { |
370 | writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A); | |
371 | writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B); | |
372 | writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C); | |
373 | writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D); | |
374 | writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E); | |
375 | } | |
750052dd US |
376 | } |
377 | ||
378 | memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config)); | |
379 | ||
750052dd | 380 | /* GO */ |
170dd56d | 381 | mv_setup_timer(); |
750052dd | 382 | writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD); |
750052dd US |
383 | } |
384 | ||
385 | static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx, | |
386 | struct shash_desc *desc) | |
387 | { | |
388 | int i; | |
389 | struct sha1_state shash_state; | |
390 | ||
391 | shash_state.count = ctx->count + ctx->count_add; | |
392 | for (i = 0; i < 5; i++) | |
393 | shash_state.state[i] = ctx->state[i]; | |
394 | memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer)); | |
395 | return crypto_shash_import(desc, &shash_state); | |
396 | } | |
397 | ||
398 | static int mv_hash_final_fallback(struct ahash_request *req) | |
399 | { | |
400 | const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm); | |
401 | struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req); | |
402 | struct { | |
403 | struct shash_desc shash; | |
404 | char ctx[crypto_shash_descsize(tfm_ctx->fallback)]; | |
405 | } desc; | |
406 | int rc; | |
407 | ||
408 | desc.shash.tfm = tfm_ctx->fallback; | |
409 | desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP; | |
410 | if (unlikely(req_ctx->first_hash)) { | |
411 | crypto_shash_init(&desc.shash); | |
412 | crypto_shash_update(&desc.shash, req_ctx->buffer, | |
413 | req_ctx->extra_bytes); | |
414 | } else { | |
415 | /* only SHA1 for now.... | |
416 | */ | |
417 | rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash); | |
418 | if (rc) | |
419 | goto out; | |
420 | } | |
421 | rc = crypto_shash_final(&desc.shash, req->result); | |
422 | out: | |
423 | return rc; | |
424 | } | |
425 | ||
426 | static void mv_hash_algo_completion(void) | |
427 | { | |
428 | struct ahash_request *req = ahash_request_cast(cpg->cur_req); | |
429 | struct mv_req_hash_ctx *ctx = ahash_request_ctx(req); | |
430 | ||
431 | if (ctx->extra_bytes) | |
432 | copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes); | |
433 | sg_miter_stop(&cpg->p.src_sg_it); | |
434 | ||
750052dd US |
435 | if (likely(ctx->last_chunk)) { |
436 | if (likely(ctx->count <= MAX_HW_HASH_SIZE)) { | |
437 | memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF, | |
438 | crypto_ahash_digestsize(crypto_ahash_reqtfm | |
439 | (req))); | |
440 | } else | |
441 | mv_hash_final_fallback(req); | |
7a1c6bcf PS |
442 | } else { |
443 | ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A); | |
444 | ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B); | |
445 | ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C); | |
446 | ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D); | |
447 | ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E); | |
750052dd US |
448 | } |
449 | } | |
450 | ||
85a7f0ac SAS |
451 | static void dequeue_complete_req(void) |
452 | { | |
3b61a905 | 453 | struct crypto_async_request *req = cpg->cur_req; |
85a7f0ac SAS |
454 | void *buf; |
455 | int ret; | |
7a5f691e | 456 | cpg->p.hw_processed_bytes += cpg->p.crypt_len; |
f0d03dea US |
457 | if (cpg->p.copy_back) { |
458 | int need_copy_len = cpg->p.crypt_len; | |
459 | int sram_offset = 0; | |
460 | do { | |
461 | int dst_copy; | |
462 | ||
463 | if (!cpg->p.sg_dst_left) { | |
464 | ret = sg_miter_next(&cpg->p.dst_sg_it); | |
465 | BUG_ON(!ret); | |
466 | cpg->p.sg_dst_left = cpg->p.dst_sg_it.length; | |
467 | cpg->p.dst_start = 0; | |
468 | } | |
469 | ||
470 | buf = cpg->p.dst_sg_it.addr; | |
471 | buf += cpg->p.dst_start; | |
472 | ||
473 | dst_copy = min(need_copy_len, cpg->p.sg_dst_left); | |
474 | ||
475 | memcpy(buf, | |
476 | cpg->sram + SRAM_DATA_OUT_START + sram_offset, | |
477 | dst_copy); | |
478 | sram_offset += dst_copy; | |
479 | cpg->p.sg_dst_left -= dst_copy; | |
480 | need_copy_len -= dst_copy; | |
481 | cpg->p.dst_start += dst_copy; | |
482 | } while (need_copy_len > 0); | |
483 | } | |
85a7f0ac | 484 | |
0c5c6c4b | 485 | cpg->p.crypt_len = 0; |
85a7f0ac SAS |
486 | |
487 | BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE); | |
7a5f691e | 488 | if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) { |
85a7f0ac SAS |
489 | /* process next scatter list entry */ |
490 | cpg->eng_st = ENGINE_BUSY; | |
a58094ac | 491 | cpg->p.process(0); |
85a7f0ac | 492 | } else { |
a58094ac | 493 | cpg->p.complete(); |
85a7f0ac | 494 | cpg->eng_st = ENGINE_IDLE; |
0328ac26 | 495 | local_bh_disable(); |
3b61a905 | 496 | req->complete(req, 0); |
0328ac26 | 497 | local_bh_enable(); |
85a7f0ac SAS |
498 | } |
499 | } | |
500 | ||
501 | static int count_sgs(struct scatterlist *sl, unsigned int total_bytes) | |
502 | { | |
503 | int i = 0; | |
15d4dd35 US |
504 | size_t cur_len; |
505 | ||
6ef84509 | 506 | while (sl) { |
15d4dd35 US |
507 | cur_len = sl[i].length; |
508 | ++i; | |
509 | if (total_bytes > cur_len) | |
510 | total_bytes -= cur_len; | |
511 | else | |
512 | break; | |
513 | } | |
85a7f0ac SAS |
514 | |
515 | return i; | |
516 | } | |
517 | ||
750052dd | 518 | static void mv_start_new_crypt_req(struct ablkcipher_request *req) |
85a7f0ac | 519 | { |
3b61a905 | 520 | struct req_progress *p = &cpg->p; |
85a7f0ac SAS |
521 | int num_sgs; |
522 | ||
3b61a905 US |
523 | cpg->cur_req = &req->base; |
524 | memset(p, 0, sizeof(struct req_progress)); | |
525 | p->hw_nbytes = req->nbytes; | |
a58094ac US |
526 | p->complete = mv_crypto_algo_completion; |
527 | p->process = mv_process_current_q; | |
f0d03dea | 528 | p->copy_back = 1; |
85a7f0ac SAS |
529 | |
530 | num_sgs = count_sgs(req->src, req->nbytes); | |
3b61a905 | 531 | sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG); |
85a7f0ac SAS |
532 | |
533 | num_sgs = count_sgs(req->dst, req->nbytes); | |
3b61a905 US |
534 | sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG); |
535 | ||
85a7f0ac SAS |
536 | mv_process_current_q(1); |
537 | } | |
538 | ||
750052dd US |
539 | static void mv_start_new_hash_req(struct ahash_request *req) |
540 | { | |
541 | struct req_progress *p = &cpg->p; | |
542 | struct mv_req_hash_ctx *ctx = ahash_request_ctx(req); | |
750052dd US |
543 | int num_sgs, hw_bytes, old_extra_bytes, rc; |
544 | cpg->cur_req = &req->base; | |
545 | memset(p, 0, sizeof(struct req_progress)); | |
546 | hw_bytes = req->nbytes + ctx->extra_bytes; | |
547 | old_extra_bytes = ctx->extra_bytes; | |
548 | ||
750052dd US |
549 | ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE; |
550 | if (ctx->extra_bytes != 0 | |
551 | && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE)) | |
552 | hw_bytes -= ctx->extra_bytes; | |
553 | else | |
554 | ctx->extra_bytes = 0; | |
555 | ||
556 | num_sgs = count_sgs(req->src, req->nbytes); | |
557 | sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG); | |
558 | ||
559 | if (hw_bytes) { | |
560 | p->hw_nbytes = hw_bytes; | |
561 | p->complete = mv_hash_algo_completion; | |
562 | p->process = mv_process_hash_current; | |
563 | ||
7759995c PS |
564 | if (unlikely(old_extra_bytes)) { |
565 | memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer, | |
566 | old_extra_bytes); | |
567 | p->crypt_len = old_extra_bytes; | |
568 | } | |
569 | ||
750052dd US |
570 | mv_process_hash_current(1); |
571 | } else { | |
572 | copy_src_to_buf(p, ctx->buffer + old_extra_bytes, | |
573 | ctx->extra_bytes - old_extra_bytes); | |
574 | sg_miter_stop(&p->src_sg_it); | |
575 | if (ctx->last_chunk) | |
576 | rc = mv_hash_final_fallback(req); | |
577 | else | |
578 | rc = 0; | |
579 | cpg->eng_st = ENGINE_IDLE; | |
580 | local_bh_disable(); | |
581 | req->base.complete(&req->base, rc); | |
582 | local_bh_enable(); | |
583 | } | |
584 | } | |
585 | ||
85a7f0ac SAS |
586 | static int queue_manag(void *data) |
587 | { | |
588 | cpg->eng_st = ENGINE_IDLE; | |
589 | do { | |
85a7f0ac SAS |
590 | struct crypto_async_request *async_req = NULL; |
591 | struct crypto_async_request *backlog; | |
592 | ||
593 | __set_current_state(TASK_INTERRUPTIBLE); | |
594 | ||
595 | if (cpg->eng_st == ENGINE_W_DEQUEUE) | |
596 | dequeue_complete_req(); | |
597 | ||
598 | spin_lock_irq(&cpg->lock); | |
599 | if (cpg->eng_st == ENGINE_IDLE) { | |
600 | backlog = crypto_get_backlog(&cpg->queue); | |
601 | async_req = crypto_dequeue_request(&cpg->queue); | |
602 | if (async_req) { | |
603 | BUG_ON(cpg->eng_st != ENGINE_IDLE); | |
604 | cpg->eng_st = ENGINE_BUSY; | |
605 | } | |
606 | } | |
607 | spin_unlock_irq(&cpg->lock); | |
608 | ||
609 | if (backlog) { | |
610 | backlog->complete(backlog, -EINPROGRESS); | |
611 | backlog = NULL; | |
612 | } | |
613 | ||
614 | if (async_req) { | |
750052dd US |
615 | if (async_req->tfm->__crt_alg->cra_type != |
616 | &crypto_ahash_type) { | |
617 | struct ablkcipher_request *req = | |
042e9e73 | 618 | ablkcipher_request_cast(async_req); |
750052dd US |
619 | mv_start_new_crypt_req(req); |
620 | } else { | |
621 | struct ahash_request *req = | |
622 | ahash_request_cast(async_req); | |
623 | mv_start_new_hash_req(req); | |
624 | } | |
85a7f0ac SAS |
625 | async_req = NULL; |
626 | } | |
627 | ||
628 | schedule(); | |
629 | ||
630 | } while (!kthread_should_stop()); | |
631 | return 0; | |
632 | } | |
633 | ||
3b61a905 | 634 | static int mv_handle_req(struct crypto_async_request *req) |
85a7f0ac SAS |
635 | { |
636 | unsigned long flags; | |
637 | int ret; | |
638 | ||
639 | spin_lock_irqsave(&cpg->lock, flags); | |
3b61a905 | 640 | ret = crypto_enqueue_request(&cpg->queue, req); |
85a7f0ac SAS |
641 | spin_unlock_irqrestore(&cpg->lock, flags); |
642 | wake_up_process(cpg->queue_th); | |
643 | return ret; | |
644 | } | |
645 | ||
646 | static int mv_enc_aes_ecb(struct ablkcipher_request *req) | |
647 | { | |
648 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
649 | ||
650 | req_ctx->op = COP_AES_ECB; | |
651 | req_ctx->decrypt = 0; | |
652 | ||
3b61a905 | 653 | return mv_handle_req(&req->base); |
85a7f0ac SAS |
654 | } |
655 | ||
656 | static int mv_dec_aes_ecb(struct ablkcipher_request *req) | |
657 | { | |
658 | struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm); | |
659 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
660 | ||
661 | req_ctx->op = COP_AES_ECB; | |
662 | req_ctx->decrypt = 1; | |
663 | ||
664 | compute_aes_dec_key(ctx); | |
3b61a905 | 665 | return mv_handle_req(&req->base); |
85a7f0ac SAS |
666 | } |
667 | ||
668 | static int mv_enc_aes_cbc(struct ablkcipher_request *req) | |
669 | { | |
670 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
671 | ||
672 | req_ctx->op = COP_AES_CBC; | |
673 | req_ctx->decrypt = 0; | |
674 | ||
3b61a905 | 675 | return mv_handle_req(&req->base); |
85a7f0ac SAS |
676 | } |
677 | ||
678 | static int mv_dec_aes_cbc(struct ablkcipher_request *req) | |
679 | { | |
680 | struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm); | |
681 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
682 | ||
683 | req_ctx->op = COP_AES_CBC; | |
684 | req_ctx->decrypt = 1; | |
685 | ||
686 | compute_aes_dec_key(ctx); | |
3b61a905 | 687 | return mv_handle_req(&req->base); |
85a7f0ac SAS |
688 | } |
689 | ||
690 | static int mv_cra_init(struct crypto_tfm *tfm) | |
691 | { | |
692 | tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx); | |
693 | return 0; | |
694 | } | |
695 | ||
750052dd US |
696 | static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op, |
697 | int is_last, unsigned int req_len, | |
698 | int count_add) | |
699 | { | |
700 | memset(ctx, 0, sizeof(*ctx)); | |
701 | ctx->op = op; | |
702 | ctx->count = req_len; | |
703 | ctx->first_hash = 1; | |
704 | ctx->last_chunk = is_last; | |
705 | ctx->count_add = count_add; | |
706 | } | |
707 | ||
708 | static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last, | |
709 | unsigned req_len) | |
710 | { | |
711 | ctx->last_chunk = is_last; | |
712 | ctx->count += req_len; | |
713 | } | |
714 | ||
715 | static int mv_hash_init(struct ahash_request *req) | |
716 | { | |
717 | const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm); | |
718 | mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0, | |
719 | tfm_ctx->count_add); | |
720 | return 0; | |
721 | } | |
722 | ||
723 | static int mv_hash_update(struct ahash_request *req) | |
724 | { | |
725 | if (!req->nbytes) | |
726 | return 0; | |
727 | ||
728 | mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes); | |
729 | return mv_handle_req(&req->base); | |
730 | } | |
731 | ||
732 | static int mv_hash_final(struct ahash_request *req) | |
733 | { | |
734 | struct mv_req_hash_ctx *ctx = ahash_request_ctx(req); | |
6ef84509 | 735 | |
f8f54e19 | 736 | ahash_request_set_crypt(req, NULL, req->result, 0); |
750052dd US |
737 | mv_update_hash_req_ctx(ctx, 1, 0); |
738 | return mv_handle_req(&req->base); | |
739 | } | |
740 | ||
741 | static int mv_hash_finup(struct ahash_request *req) | |
742 | { | |
750052dd US |
743 | mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes); |
744 | return mv_handle_req(&req->base); | |
745 | } | |
746 | ||
747 | static int mv_hash_digest(struct ahash_request *req) | |
748 | { | |
749 | const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm); | |
750 | mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1, | |
751 | req->nbytes, tfm_ctx->count_add); | |
752 | return mv_handle_req(&req->base); | |
753 | } | |
754 | ||
755 | static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate, | |
756 | const void *ostate) | |
757 | { | |
758 | const struct sha1_state *isha1_state = istate, *osha1_state = ostate; | |
759 | int i; | |
760 | for (i = 0; i < 5; i++) { | |
761 | ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]); | |
762 | ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]); | |
763 | } | |
764 | } | |
765 | ||
766 | static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key, | |
767 | unsigned int keylen) | |
768 | { | |
769 | int rc; | |
770 | struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base); | |
771 | int bs, ds, ss; | |
772 | ||
773 | if (!ctx->base_hash) | |
774 | return 0; | |
775 | ||
776 | rc = crypto_shash_setkey(ctx->fallback, key, keylen); | |
777 | if (rc) | |
778 | return rc; | |
779 | ||
780 | /* Can't see a way to extract the ipad/opad from the fallback tfm | |
781 | so I'm basically copying code from the hmac module */ | |
782 | bs = crypto_shash_blocksize(ctx->base_hash); | |
783 | ds = crypto_shash_digestsize(ctx->base_hash); | |
784 | ss = crypto_shash_statesize(ctx->base_hash); | |
785 | ||
786 | { | |
787 | struct { | |
788 | struct shash_desc shash; | |
789 | char ctx[crypto_shash_descsize(ctx->base_hash)]; | |
790 | } desc; | |
791 | unsigned int i; | |
792 | char ipad[ss]; | |
793 | char opad[ss]; | |
794 | ||
795 | desc.shash.tfm = ctx->base_hash; | |
796 | desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) & | |
797 | CRYPTO_TFM_REQ_MAY_SLEEP; | |
798 | ||
799 | if (keylen > bs) { | |
800 | int err; | |
801 | ||
802 | err = | |
803 | crypto_shash_digest(&desc.shash, key, keylen, ipad); | |
804 | if (err) | |
805 | return err; | |
806 | ||
807 | keylen = ds; | |
808 | } else | |
809 | memcpy(ipad, key, keylen); | |
810 | ||
811 | memset(ipad + keylen, 0, bs - keylen); | |
812 | memcpy(opad, ipad, bs); | |
813 | ||
814 | for (i = 0; i < bs; i++) { | |
815 | ipad[i] ^= 0x36; | |
816 | opad[i] ^= 0x5c; | |
817 | } | |
818 | ||
819 | rc = crypto_shash_init(&desc.shash) ? : | |
820 | crypto_shash_update(&desc.shash, ipad, bs) ? : | |
821 | crypto_shash_export(&desc.shash, ipad) ? : | |
822 | crypto_shash_init(&desc.shash) ? : | |
823 | crypto_shash_update(&desc.shash, opad, bs) ? : | |
824 | crypto_shash_export(&desc.shash, opad); | |
825 | ||
826 | if (rc == 0) | |
827 | mv_hash_init_ivs(ctx, ipad, opad); | |
828 | ||
829 | return rc; | |
830 | } | |
831 | } | |
832 | ||
833 | static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name, | |
834 | enum hash_op op, int count_add) | |
835 | { | |
836 | const char *fallback_driver_name = tfm->__crt_alg->cra_name; | |
837 | struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm); | |
838 | struct crypto_shash *fallback_tfm = NULL; | |
839 | struct crypto_shash *base_hash = NULL; | |
840 | int err = -ENOMEM; | |
841 | ||
842 | ctx->op = op; | |
843 | ctx->count_add = count_add; | |
844 | ||
845 | /* Allocate a fallback and abort if it failed. */ | |
846 | fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0, | |
847 | CRYPTO_ALG_NEED_FALLBACK); | |
848 | if (IS_ERR(fallback_tfm)) { | |
849 | printk(KERN_WARNING MV_CESA | |
850 | "Fallback driver '%s' could not be loaded!\n", | |
851 | fallback_driver_name); | |
852 | err = PTR_ERR(fallback_tfm); | |
853 | goto out; | |
854 | } | |
855 | ctx->fallback = fallback_tfm; | |
856 | ||
857 | if (base_hash_name) { | |
858 | /* Allocate a hash to compute the ipad/opad of hmac. */ | |
859 | base_hash = crypto_alloc_shash(base_hash_name, 0, | |
860 | CRYPTO_ALG_NEED_FALLBACK); | |
861 | if (IS_ERR(base_hash)) { | |
862 | printk(KERN_WARNING MV_CESA | |
863 | "Base driver '%s' could not be loaded!\n", | |
864 | base_hash_name); | |
41f2977d | 865 | err = PTR_ERR(base_hash); |
750052dd US |
866 | goto err_bad_base; |
867 | } | |
868 | } | |
869 | ctx->base_hash = base_hash; | |
870 | ||
871 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
872 | sizeof(struct mv_req_hash_ctx) + | |
873 | crypto_shash_descsize(ctx->fallback)); | |
874 | return 0; | |
875 | err_bad_base: | |
876 | crypto_free_shash(fallback_tfm); | |
877 | out: | |
878 | return err; | |
879 | } | |
880 | ||
881 | static void mv_cra_hash_exit(struct crypto_tfm *tfm) | |
882 | { | |
883 | struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm); | |
884 | ||
885 | crypto_free_shash(ctx->fallback); | |
886 | if (ctx->base_hash) | |
887 | crypto_free_shash(ctx->base_hash); | |
888 | } | |
889 | ||
890 | static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm) | |
891 | { | |
892 | return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0); | |
893 | } | |
894 | ||
895 | static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm) | |
896 | { | |
897 | return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE); | |
898 | } | |
899 | ||
85a7f0ac SAS |
900 | irqreturn_t crypto_int(int irq, void *priv) |
901 | { | |
902 | u32 val; | |
903 | ||
904 | val = readl(cpg->reg + SEC_ACCEL_INT_STATUS); | |
905 | if (!(val & SEC_INT_ACCEL0_DONE)) | |
906 | return IRQ_NONE; | |
907 | ||
170dd56d PS |
908 | if (!del_timer(&cpg->completion_timer)) { |
909 | printk(KERN_WARNING MV_CESA | |
910 | "got an interrupt but no pending timer?\n"); | |
911 | } | |
85a7f0ac SAS |
912 | val &= ~SEC_INT_ACCEL0_DONE; |
913 | writel(val, cpg->reg + FPGA_INT_STATUS); | |
914 | writel(val, cpg->reg + SEC_ACCEL_INT_STATUS); | |
915 | BUG_ON(cpg->eng_st != ENGINE_BUSY); | |
916 | cpg->eng_st = ENGINE_W_DEQUEUE; | |
917 | wake_up_process(cpg->queue_th); | |
918 | return IRQ_HANDLED; | |
919 | } | |
920 | ||
921 | struct crypto_alg mv_aes_alg_ecb = { | |
922 | .cra_name = "ecb(aes)", | |
923 | .cra_driver_name = "mv-ecb-aes", | |
924 | .cra_priority = 300, | |
d912bb76 NM |
925 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
926 | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, | |
85a7f0ac SAS |
927 | .cra_blocksize = 16, |
928 | .cra_ctxsize = sizeof(struct mv_ctx), | |
929 | .cra_alignmask = 0, | |
930 | .cra_type = &crypto_ablkcipher_type, | |
931 | .cra_module = THIS_MODULE, | |
932 | .cra_init = mv_cra_init, | |
933 | .cra_u = { | |
934 | .ablkcipher = { | |
935 | .min_keysize = AES_MIN_KEY_SIZE, | |
936 | .max_keysize = AES_MAX_KEY_SIZE, | |
937 | .setkey = mv_setkey_aes, | |
938 | .encrypt = mv_enc_aes_ecb, | |
939 | .decrypt = mv_dec_aes_ecb, | |
940 | }, | |
941 | }, | |
942 | }; | |
943 | ||
944 | struct crypto_alg mv_aes_alg_cbc = { | |
945 | .cra_name = "cbc(aes)", | |
946 | .cra_driver_name = "mv-cbc-aes", | |
947 | .cra_priority = 300, | |
d912bb76 NM |
948 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
949 | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, | |
85a7f0ac SAS |
950 | .cra_blocksize = AES_BLOCK_SIZE, |
951 | .cra_ctxsize = sizeof(struct mv_ctx), | |
952 | .cra_alignmask = 0, | |
953 | .cra_type = &crypto_ablkcipher_type, | |
954 | .cra_module = THIS_MODULE, | |
955 | .cra_init = mv_cra_init, | |
956 | .cra_u = { | |
957 | .ablkcipher = { | |
958 | .ivsize = AES_BLOCK_SIZE, | |
959 | .min_keysize = AES_MIN_KEY_SIZE, | |
960 | .max_keysize = AES_MAX_KEY_SIZE, | |
961 | .setkey = mv_setkey_aes, | |
962 | .encrypt = mv_enc_aes_cbc, | |
963 | .decrypt = mv_dec_aes_cbc, | |
964 | }, | |
965 | }, | |
966 | }; | |
967 | ||
750052dd US |
968 | struct ahash_alg mv_sha1_alg = { |
969 | .init = mv_hash_init, | |
970 | .update = mv_hash_update, | |
971 | .final = mv_hash_final, | |
972 | .finup = mv_hash_finup, | |
973 | .digest = mv_hash_digest, | |
974 | .halg = { | |
975 | .digestsize = SHA1_DIGEST_SIZE, | |
976 | .base = { | |
977 | .cra_name = "sha1", | |
978 | .cra_driver_name = "mv-sha1", | |
979 | .cra_priority = 300, | |
980 | .cra_flags = | |
d912bb76 NM |
981 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | |
982 | CRYPTO_ALG_NEED_FALLBACK, | |
750052dd US |
983 | .cra_blocksize = SHA1_BLOCK_SIZE, |
984 | .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx), | |
985 | .cra_init = mv_cra_hash_sha1_init, | |
986 | .cra_exit = mv_cra_hash_exit, | |
987 | .cra_module = THIS_MODULE, | |
988 | } | |
989 | } | |
990 | }; | |
991 | ||
992 | struct ahash_alg mv_hmac_sha1_alg = { | |
993 | .init = mv_hash_init, | |
994 | .update = mv_hash_update, | |
995 | .final = mv_hash_final, | |
996 | .finup = mv_hash_finup, | |
997 | .digest = mv_hash_digest, | |
998 | .setkey = mv_hash_setkey, | |
999 | .halg = { | |
1000 | .digestsize = SHA1_DIGEST_SIZE, | |
1001 | .base = { | |
1002 | .cra_name = "hmac(sha1)", | |
1003 | .cra_driver_name = "mv-hmac-sha1", | |
1004 | .cra_priority = 300, | |
1005 | .cra_flags = | |
d912bb76 NM |
1006 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | |
1007 | CRYPTO_ALG_NEED_FALLBACK, | |
750052dd US |
1008 | .cra_blocksize = SHA1_BLOCK_SIZE, |
1009 | .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx), | |
1010 | .cra_init = mv_cra_hash_hmac_sha1_init, | |
1011 | .cra_exit = mv_cra_hash_exit, | |
1012 | .cra_module = THIS_MODULE, | |
1013 | } | |
1014 | } | |
1015 | }; | |
1016 | ||
85a7f0ac SAS |
1017 | static int mv_probe(struct platform_device *pdev) |
1018 | { | |
1019 | struct crypto_priv *cp; | |
1020 | struct resource *res; | |
1021 | int irq; | |
1022 | int ret; | |
1023 | ||
1024 | if (cpg) { | |
750052dd | 1025 | printk(KERN_ERR MV_CESA "Second crypto dev?\n"); |
85a7f0ac SAS |
1026 | return -EEXIST; |
1027 | } | |
1028 | ||
1029 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); | |
1030 | if (!res) | |
1031 | return -ENXIO; | |
1032 | ||
1033 | cp = kzalloc(sizeof(*cp), GFP_KERNEL); | |
1034 | if (!cp) | |
1035 | return -ENOMEM; | |
1036 | ||
1037 | spin_lock_init(&cp->lock); | |
1038 | crypto_init_queue(&cp->queue, 50); | |
5bdd5ded | 1039 | cp->reg = ioremap(res->start, resource_size(res)); |
85a7f0ac SAS |
1040 | if (!cp->reg) { |
1041 | ret = -ENOMEM; | |
1042 | goto err; | |
1043 | } | |
1044 | ||
1045 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); | |
1046 | if (!res) { | |
1047 | ret = -ENXIO; | |
1048 | goto err_unmap_reg; | |
1049 | } | |
5bdd5ded | 1050 | cp->sram_size = resource_size(res); |
85a7f0ac SAS |
1051 | cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE; |
1052 | cp->sram = ioremap(res->start, cp->sram_size); | |
1053 | if (!cp->sram) { | |
1054 | ret = -ENOMEM; | |
1055 | goto err_unmap_reg; | |
1056 | } | |
1057 | ||
1058 | irq = platform_get_irq(pdev, 0); | |
1059 | if (irq < 0 || irq == NO_IRQ) { | |
1060 | ret = irq; | |
1061 | goto err_unmap_sram; | |
1062 | } | |
1063 | cp->irq = irq; | |
1064 | ||
1065 | platform_set_drvdata(pdev, cp); | |
1066 | cpg = cp; | |
1067 | ||
1068 | cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto"); | |
1069 | if (IS_ERR(cp->queue_th)) { | |
1070 | ret = PTR_ERR(cp->queue_th); | |
7cc28350 | 1071 | goto err_unmap_sram; |
85a7f0ac SAS |
1072 | } |
1073 | ||
1074 | ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev), | |
1075 | cp); | |
1076 | if (ret) | |
7cc28350 | 1077 | goto err_thread; |
85a7f0ac | 1078 | |
1f80b126 AL |
1079 | /* Not all platforms can gate the clock, so it is not |
1080 | an error if the clock does not exists. */ | |
1081 | cp->clk = clk_get(&pdev->dev, NULL); | |
1082 | if (!IS_ERR(cp->clk)) | |
1083 | clk_prepare_enable(cp->clk); | |
1084 | ||
5741d2ee | 1085 | writel(0, cpg->reg + SEC_ACCEL_INT_STATUS); |
85a7f0ac SAS |
1086 | writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK); |
1087 | writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG); | |
99db3eac | 1088 | writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0); |
85a7f0ac SAS |
1089 | |
1090 | ret = crypto_register_alg(&mv_aes_alg_ecb); | |
2a025f5d PS |
1091 | if (ret) { |
1092 | printk(KERN_WARNING MV_CESA | |
1093 | "Could not register aes-ecb driver\n"); | |
7cc28350 | 1094 | goto err_irq; |
2a025f5d | 1095 | } |
85a7f0ac SAS |
1096 | |
1097 | ret = crypto_register_alg(&mv_aes_alg_cbc); | |
2a025f5d PS |
1098 | if (ret) { |
1099 | printk(KERN_WARNING MV_CESA | |
1100 | "Could not register aes-cbc driver\n"); | |
85a7f0ac | 1101 | goto err_unreg_ecb; |
2a025f5d | 1102 | } |
750052dd US |
1103 | |
1104 | ret = crypto_register_ahash(&mv_sha1_alg); | |
1105 | if (ret == 0) | |
1106 | cpg->has_sha1 = 1; | |
1107 | else | |
1108 | printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n"); | |
1109 | ||
1110 | ret = crypto_register_ahash(&mv_hmac_sha1_alg); | |
1111 | if (ret == 0) { | |
1112 | cpg->has_hmac_sha1 = 1; | |
1113 | } else { | |
1114 | printk(KERN_WARNING MV_CESA | |
1115 | "Could not register hmac-sha1 driver\n"); | |
1116 | } | |
1117 | ||
85a7f0ac SAS |
1118 | return 0; |
1119 | err_unreg_ecb: | |
1120 | crypto_unregister_alg(&mv_aes_alg_ecb); | |
7cc28350 | 1121 | err_irq: |
85a7f0ac | 1122 | free_irq(irq, cp); |
7cc28350 | 1123 | err_thread: |
85a7f0ac SAS |
1124 | kthread_stop(cp->queue_th); |
1125 | err_unmap_sram: | |
1126 | iounmap(cp->sram); | |
1127 | err_unmap_reg: | |
1128 | iounmap(cp->reg); | |
1129 | err: | |
1130 | kfree(cp); | |
1131 | cpg = NULL; | |
1132 | platform_set_drvdata(pdev, NULL); | |
1133 | return ret; | |
1134 | } | |
1135 | ||
1136 | static int mv_remove(struct platform_device *pdev) | |
1137 | { | |
1138 | struct crypto_priv *cp = platform_get_drvdata(pdev); | |
1139 | ||
1140 | crypto_unregister_alg(&mv_aes_alg_ecb); | |
1141 | crypto_unregister_alg(&mv_aes_alg_cbc); | |
750052dd US |
1142 | if (cp->has_sha1) |
1143 | crypto_unregister_ahash(&mv_sha1_alg); | |
1144 | if (cp->has_hmac_sha1) | |
1145 | crypto_unregister_ahash(&mv_hmac_sha1_alg); | |
85a7f0ac SAS |
1146 | kthread_stop(cp->queue_th); |
1147 | free_irq(cp->irq, cp); | |
1148 | memset(cp->sram, 0, cp->sram_size); | |
1149 | iounmap(cp->sram); | |
1150 | iounmap(cp->reg); | |
1f80b126 AL |
1151 | |
1152 | if (!IS_ERR(cp->clk)) { | |
1153 | clk_disable_unprepare(cp->clk); | |
1154 | clk_put(cp->clk); | |
1155 | } | |
1156 | ||
85a7f0ac SAS |
1157 | kfree(cp); |
1158 | cpg = NULL; | |
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | static struct platform_driver marvell_crypto = { | |
1163 | .probe = mv_probe, | |
1164 | .remove = mv_remove, | |
1165 | .driver = { | |
1166 | .owner = THIS_MODULE, | |
1167 | .name = "mv_crypto", | |
1168 | }, | |
1169 | }; | |
1170 | MODULE_ALIAS("platform:mv_crypto"); | |
1171 | ||
741e8c2d | 1172 | module_platform_driver(marvell_crypto); |
85a7f0ac SAS |
1173 | |
1174 | MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>"); | |
1175 | MODULE_DESCRIPTION("Support for Marvell's cryptographic engine"); | |
1176 | MODULE_LICENSE("GPL"); |