Commit | Line | Data |
---|---|---|
f63601fd BB |
1 | /* |
2 | * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256. | |
3 | * | |
4 | * Author: Boris Brezillon <boris.brezillon@free-electrons.com> | |
5 | * Author: Arnaud Ebalard <arno@natisbad.org> | |
6 | * | |
7 | * This work is based on an initial version written by | |
8 | * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc > | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published | |
12 | * by the Free Software Foundation. | |
13 | */ | |
14 | ||
d477d813 | 15 | #include <crypto/hmac.h> |
7aeef693 | 16 | #include <crypto/md5.h> |
f63601fd BB |
17 | #include <crypto/sha.h> |
18 | ||
19 | #include "cesa.h" | |
20 | ||
db509a45 BB |
21 | struct mv_cesa_ahash_dma_iter { |
22 | struct mv_cesa_dma_iter base; | |
23 | struct mv_cesa_sg_dma_iter src; | |
24 | }; | |
25 | ||
26 | static inline void | |
27 | mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter, | |
28 | struct ahash_request *req) | |
29 | { | |
30 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
bd274b10 | 31 | unsigned int len = req->nbytes + creq->cache_ptr; |
db509a45 BB |
32 | |
33 | if (!creq->last_req) | |
bd274b10 | 34 | len &= ~CESA_HASH_BLOCK_SIZE_MSK; |
db509a45 BB |
35 | |
36 | mv_cesa_req_dma_iter_init(&iter->base, len); | |
37 | mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE); | |
38 | iter->src.op_offset = creq->cache_ptr; | |
39 | } | |
40 | ||
41 | static inline bool | |
42 | mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter) | |
43 | { | |
44 | iter->src.op_offset = 0; | |
45 | ||
46 | return mv_cesa_req_dma_iter_next_op(&iter->base); | |
47 | } | |
48 | ||
7850c91b BB |
49 | static inline int |
50 | mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_dma_req *req, gfp_t flags) | |
db509a45 | 51 | { |
7850c91b BB |
52 | req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags, |
53 | &req->cache_dma); | |
54 | if (!req->cache) | |
f63601fd BB |
55 | return -ENOMEM; |
56 | ||
57 | return 0; | |
58 | } | |
59 | ||
7850c91b BB |
60 | static inline void |
61 | mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_dma_req *req) | |
f63601fd | 62 | { |
7850c91b | 63 | if (!req->cache) |
f63601fd BB |
64 | return; |
65 | ||
7850c91b BB |
66 | dma_pool_free(cesa_dev->dma->cache_pool, req->cache, |
67 | req->cache_dma); | |
f63601fd BB |
68 | } |
69 | ||
db509a45 BB |
70 | static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req, |
71 | gfp_t flags) | |
72 | { | |
73 | if (req->padding) | |
74 | return 0; | |
75 | ||
76 | req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags, | |
77 | &req->padding_dma); | |
78 | if (!req->padding) | |
79 | return -ENOMEM; | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
84 | static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req) | |
85 | { | |
86 | if (!req->padding) | |
87 | return; | |
88 | ||
89 | dma_pool_free(cesa_dev->dma->padding_pool, req->padding, | |
90 | req->padding_dma); | |
91 | req->padding = NULL; | |
92 | } | |
93 | ||
94 | static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req) | |
95 | { | |
96 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
97 | ||
98 | mv_cesa_ahash_dma_free_padding(&creq->req.dma); | |
99 | } | |
100 | ||
101 | static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req) | |
102 | { | |
103 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
104 | ||
105 | dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE); | |
7850c91b | 106 | mv_cesa_ahash_dma_free_cache(&creq->req.dma); |
53da740f | 107 | mv_cesa_dma_cleanup(&creq->base); |
db509a45 BB |
108 | } |
109 | ||
110 | static inline void mv_cesa_ahash_cleanup(struct ahash_request *req) | |
111 | { | |
112 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
113 | ||
53da740f | 114 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
db509a45 BB |
115 | mv_cesa_ahash_dma_cleanup(req); |
116 | } | |
117 | ||
f63601fd BB |
118 | static void mv_cesa_ahash_last_cleanup(struct ahash_request *req) |
119 | { | |
120 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
121 | ||
53da740f | 122 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
db509a45 | 123 | mv_cesa_ahash_dma_last_cleanup(req); |
f63601fd BB |
124 | } |
125 | ||
126 | static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq) | |
127 | { | |
128 | unsigned int index, padlen; | |
129 | ||
130 | index = creq->len & CESA_HASH_BLOCK_SIZE_MSK; | |
131 | padlen = (index < 56) ? (56 - index) : (64 + 56 - index); | |
132 | ||
133 | return padlen; | |
134 | } | |
135 | ||
136 | static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf) | |
137 | { | |
f63601fd BB |
138 | unsigned int index, padlen; |
139 | ||
140 | buf[0] = 0x80; | |
141 | /* Pad out to 56 mod 64 */ | |
142 | index = creq->len & CESA_HASH_BLOCK_SIZE_MSK; | |
143 | padlen = mv_cesa_ahash_pad_len(creq); | |
144 | memset(buf + 1, 0, padlen - 1); | |
51954a96 RK |
145 | |
146 | if (creq->algo_le) { | |
147 | __le64 bits = cpu_to_le64(creq->len << 3); | |
148 | memcpy(buf + padlen, &bits, sizeof(bits)); | |
149 | } else { | |
150 | __be64 bits = cpu_to_be64(creq->len << 3); | |
151 | memcpy(buf + padlen, &bits, sizeof(bits)); | |
152 | } | |
f63601fd BB |
153 | |
154 | return padlen + 8; | |
155 | } | |
156 | ||
157 | static void mv_cesa_ahash_std_step(struct ahash_request *req) | |
158 | { | |
159 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
160 | struct mv_cesa_ahash_std_req *sreq = &creq->req.std; | |
53da740f | 161 | struct mv_cesa_engine *engine = creq->base.engine; |
f63601fd BB |
162 | struct mv_cesa_op_ctx *op; |
163 | unsigned int new_cache_ptr = 0; | |
164 | u32 frag_mode; | |
165 | size_t len; | |
2786cee8 RP |
166 | unsigned int digsize; |
167 | int i; | |
168 | ||
169 | mv_cesa_adjust_op(engine, &creq->op_tmpl); | |
170 | memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl)); | |
171 | ||
9e5f7a14 RP |
172 | if (!sreq->offset) { |
173 | digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req)); | |
174 | for (i = 0; i < digsize / 4; i++) | |
175 | writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i)); | |
176 | } | |
f63601fd BB |
177 | |
178 | if (creq->cache_ptr) | |
0f3304dc RK |
179 | memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET, |
180 | creq->cache, creq->cache_ptr); | |
f63601fd BB |
181 | |
182 | len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset, | |
183 | CESA_SA_SRAM_PAYLOAD_SIZE); | |
184 | ||
185 | if (!creq->last_req) { | |
186 | new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK; | |
187 | len &= ~CESA_HASH_BLOCK_SIZE_MSK; | |
188 | } | |
189 | ||
190 | if (len - creq->cache_ptr) | |
191 | sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents, | |
192 | engine->sram + | |
193 | CESA_SA_DATA_SRAM_OFFSET + | |
194 | creq->cache_ptr, | |
195 | len - creq->cache_ptr, | |
196 | sreq->offset); | |
197 | ||
198 | op = &creq->op_tmpl; | |
199 | ||
200 | frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK; | |
201 | ||
202 | if (creq->last_req && sreq->offset == req->nbytes && | |
203 | creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) { | |
204 | if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG) | |
205 | frag_mode = CESA_SA_DESC_CFG_NOT_FRAG; | |
206 | else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG) | |
207 | frag_mode = CESA_SA_DESC_CFG_LAST_FRAG; | |
208 | } | |
209 | ||
210 | if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG || | |
211 | frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) { | |
212 | if (len && | |
213 | creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) { | |
214 | mv_cesa_set_mac_op_total_len(op, creq->len); | |
215 | } else { | |
216 | int trailerlen = mv_cesa_ahash_pad_len(creq) + 8; | |
217 | ||
218 | if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) { | |
219 | len &= CESA_HASH_BLOCK_SIZE_MSK; | |
220 | new_cache_ptr = 64 - trailerlen; | |
0f3304dc RK |
221 | memcpy_fromio(creq->cache, |
222 | engine->sram + | |
223 | CESA_SA_DATA_SRAM_OFFSET + len, | |
224 | new_cache_ptr); | |
f63601fd BB |
225 | } else { |
226 | len += mv_cesa_ahash_pad_req(creq, | |
227 | engine->sram + len + | |
228 | CESA_SA_DATA_SRAM_OFFSET); | |
229 | } | |
230 | ||
231 | if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) | |
232 | frag_mode = CESA_SA_DESC_CFG_MID_FRAG; | |
233 | else | |
234 | frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG; | |
235 | } | |
236 | } | |
237 | ||
238 | mv_cesa_set_mac_op_frag_len(op, len); | |
239 | mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK); | |
240 | ||
241 | /* FIXME: only update enc_len field */ | |
0f3304dc | 242 | memcpy_toio(engine->sram, op, sizeof(*op)); |
f63601fd BB |
243 | |
244 | if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG) | |
245 | mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG, | |
246 | CESA_SA_DESC_CFG_FRAG_MSK); | |
247 | ||
248 | creq->cache_ptr = new_cache_ptr; | |
249 | ||
250 | mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE); | |
b1508561 | 251 | writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG); |
f6283088 RP |
252 | BUG_ON(readl(engine->regs + CESA_SA_CMD) & |
253 | CESA_SA_CMD_EN_CESA_SA_ACCL0); | |
f63601fd BB |
254 | writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD); |
255 | } | |
256 | ||
257 | static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status) | |
258 | { | |
259 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
260 | struct mv_cesa_ahash_std_req *sreq = &creq->req.std; | |
261 | ||
262 | if (sreq->offset < (req->nbytes - creq->cache_ptr)) | |
263 | return -EINPROGRESS; | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
db509a45 BB |
268 | static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req) |
269 | { | |
270 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
53da740f | 271 | struct mv_cesa_req *basereq = &creq->base; |
db509a45 | 272 | |
53da740f | 273 | mv_cesa_dma_prepare(basereq, basereq->engine); |
db509a45 BB |
274 | } |
275 | ||
f63601fd BB |
276 | static void mv_cesa_ahash_std_prepare(struct ahash_request *req) |
277 | { | |
278 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
279 | struct mv_cesa_ahash_std_req *sreq = &creq->req.std; | |
f63601fd BB |
280 | |
281 | sreq->offset = 0; | |
f63601fd BB |
282 | } |
283 | ||
8759fec4 RP |
284 | static void mv_cesa_ahash_dma_step(struct ahash_request *req) |
285 | { | |
286 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
287 | struct mv_cesa_req *base = &creq->base; | |
288 | ||
289 | /* We must explicitly set the digest state. */ | |
290 | if (base->chain.first->flags & CESA_TDMA_SET_STATE) { | |
291 | struct mv_cesa_engine *engine = base->engine; | |
292 | int i; | |
293 | ||
294 | /* Set the hash state in the IVDIG regs. */ | |
295 | for (i = 0; i < ARRAY_SIZE(creq->state); i++) | |
296 | writel_relaxed(creq->state[i], engine->regs + | |
297 | CESA_IVDIG(i)); | |
298 | } | |
299 | ||
300 | mv_cesa_dma_step(base); | |
301 | } | |
302 | ||
f63601fd BB |
303 | static void mv_cesa_ahash_step(struct crypto_async_request *req) |
304 | { | |
305 | struct ahash_request *ahashreq = ahash_request_cast(req); | |
db509a45 | 306 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); |
f63601fd | 307 | |
53da740f | 308 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
8759fec4 | 309 | mv_cesa_ahash_dma_step(ahashreq); |
db509a45 BB |
310 | else |
311 | mv_cesa_ahash_std_step(ahashreq); | |
f63601fd BB |
312 | } |
313 | ||
314 | static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status) | |
315 | { | |
316 | struct ahash_request *ahashreq = ahash_request_cast(req); | |
317 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); | |
f63601fd | 318 | |
53da740f | 319 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
1bf6682c | 320 | return mv_cesa_dma_process(&creq->base, status); |
db509a45 | 321 | |
1bf6682c RP |
322 | return mv_cesa_ahash_std_process(ahashreq, status); |
323 | } | |
324 | ||
325 | static void mv_cesa_ahash_complete(struct crypto_async_request *req) | |
326 | { | |
327 | struct ahash_request *ahashreq = ahash_request_cast(req); | |
328 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); | |
329 | struct mv_cesa_engine *engine = creq->base.engine; | |
330 | unsigned int digsize; | |
331 | int i; | |
f63601fd BB |
332 | |
333 | digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq)); | |
f63601fd | 334 | |
f34dad17 RP |
335 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ && |
336 | (creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_RESULT) { | |
337 | __le32 *data = NULL; | |
338 | ||
4c2b130c | 339 | /* |
f34dad17 RP |
340 | * Result is already in the correct endianess when the SA is |
341 | * used | |
4c2b130c | 342 | */ |
f34dad17 RP |
343 | data = creq->base.chain.last->op->ctx.hash.hash; |
344 | for (i = 0; i < digsize / 4; i++) | |
345 | creq->state[i] = cpu_to_le32(data[i]); | |
4c2b130c | 346 | |
f34dad17 RP |
347 | memcpy(ahashreq->result, data, digsize); |
348 | } else { | |
349 | for (i = 0; i < digsize / 4; i++) | |
350 | creq->state[i] = readl_relaxed(engine->regs + | |
351 | CESA_IVDIG(i)); | |
352 | if (creq->last_req) { | |
353 | /* | |
354 | * Hardware's MD5 digest is in little endian format, but | |
355 | * SHA in big endian format | |
356 | */ | |
357 | if (creq->algo_le) { | |
358 | __le32 *result = (void *)ahashreq->result; | |
359 | ||
360 | for (i = 0; i < digsize / 4; i++) | |
361 | result[i] = cpu_to_le32(creq->state[i]); | |
362 | } else { | |
363 | __be32 *result = (void *)ahashreq->result; | |
f63601fd | 364 | |
f34dad17 RP |
365 | for (i = 0; i < digsize / 4; i++) |
366 | result[i] = cpu_to_be32(creq->state[i]); | |
367 | } | |
4c2b130c | 368 | } |
f63601fd | 369 | } |
bf8f91e7 RP |
370 | |
371 | atomic_sub(ahashreq->nbytes, &engine->load); | |
f63601fd BB |
372 | } |
373 | ||
374 | static void mv_cesa_ahash_prepare(struct crypto_async_request *req, | |
375 | struct mv_cesa_engine *engine) | |
376 | { | |
377 | struct ahash_request *ahashreq = ahash_request_cast(req); | |
378 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); | |
f63601fd | 379 | |
53da740f | 380 | creq->base.engine = engine; |
f63601fd | 381 | |
53da740f | 382 | if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) |
db509a45 BB |
383 | mv_cesa_ahash_dma_prepare(ahashreq); |
384 | else | |
385 | mv_cesa_ahash_std_prepare(ahashreq); | |
f63601fd BB |
386 | } |
387 | ||
388 | static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req) | |
389 | { | |
390 | struct ahash_request *ahashreq = ahash_request_cast(req); | |
391 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq); | |
392 | ||
393 | if (creq->last_req) | |
394 | mv_cesa_ahash_last_cleanup(ahashreq); | |
db509a45 BB |
395 | |
396 | mv_cesa_ahash_cleanup(ahashreq); | |
64ec6ccb RP |
397 | |
398 | if (creq->cache_ptr) | |
399 | sg_pcopy_to_buffer(ahashreq->src, creq->src_nents, | |
400 | creq->cache, | |
401 | creq->cache_ptr, | |
402 | ahashreq->nbytes - creq->cache_ptr); | |
f63601fd BB |
403 | } |
404 | ||
405 | static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = { | |
406 | .step = mv_cesa_ahash_step, | |
407 | .process = mv_cesa_ahash_process, | |
f63601fd | 408 | .cleanup = mv_cesa_ahash_req_cleanup, |
1bf6682c | 409 | .complete = mv_cesa_ahash_complete, |
f63601fd BB |
410 | }; |
411 | ||
3e5c66c9 | 412 | static void mv_cesa_ahash_init(struct ahash_request *req, |
a9eb678f | 413 | struct mv_cesa_op_ctx *tmpl, bool algo_le) |
f63601fd BB |
414 | { |
415 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
416 | ||
417 | memset(creq, 0, sizeof(*creq)); | |
418 | mv_cesa_update_op_cfg(tmpl, | |
419 | CESA_SA_DESC_CFG_OP_MAC_ONLY | | |
420 | CESA_SA_DESC_CFG_FIRST_FRAG, | |
421 | CESA_SA_DESC_CFG_OP_MSK | | |
422 | CESA_SA_DESC_CFG_FRAG_MSK); | |
423 | mv_cesa_set_mac_op_total_len(tmpl, 0); | |
424 | mv_cesa_set_mac_op_frag_len(tmpl, 0); | |
425 | creq->op_tmpl = *tmpl; | |
426 | creq->len = 0; | |
a9eb678f | 427 | creq->algo_le = algo_le; |
f63601fd BB |
428 | } |
429 | ||
430 | static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm) | |
431 | { | |
432 | struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm); | |
433 | ||
434 | ctx->base.ops = &mv_cesa_ahash_req_ops; | |
435 | ||
436 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
437 | sizeof(struct mv_cesa_ahash_req)); | |
438 | return 0; | |
439 | } | |
440 | ||
6dc156f4 | 441 | static bool mv_cesa_ahash_cache_req(struct ahash_request *req) |
f63601fd BB |
442 | { |
443 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
6dc156f4 | 444 | bool cached = false; |
f63601fd | 445 | |
47856204 | 446 | if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE && !creq->last_req) { |
6dc156f4 | 447 | cached = true; |
f63601fd BB |
448 | |
449 | if (!req->nbytes) | |
6dc156f4 | 450 | return cached; |
f63601fd BB |
451 | |
452 | sg_pcopy_to_buffer(req->src, creq->src_nents, | |
453 | creq->cache + creq->cache_ptr, | |
454 | req->nbytes, 0); | |
455 | ||
456 | creq->cache_ptr += req->nbytes; | |
457 | } | |
458 | ||
6dc156f4 | 459 | return cached; |
f63601fd BB |
460 | } |
461 | ||
db509a45 | 462 | static struct mv_cesa_op_ctx * |
96212886 RK |
463 | mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain, |
464 | struct mv_cesa_op_ctx *tmpl, unsigned int frag_len, | |
465 | gfp_t flags) | |
db509a45 | 466 | { |
96212886 | 467 | struct mv_cesa_op_ctx *op; |
db509a45 BB |
468 | int ret; |
469 | ||
96212886 RK |
470 | op = mv_cesa_dma_add_op(chain, tmpl, false, flags); |
471 | if (IS_ERR(op)) | |
472 | return op; | |
db509a45 | 473 | |
96212886 RK |
474 | /* Set the operation block fragment length. */ |
475 | mv_cesa_set_mac_op_frag_len(op, frag_len); | |
476 | ||
477 | /* Append dummy desc to launch operation */ | |
478 | ret = mv_cesa_dma_add_dummy_launch(chain, flags); | |
db509a45 BB |
479 | if (ret) |
480 | return ERR_PTR(ret); | |
481 | ||
2f396a91 RK |
482 | if (mv_cesa_mac_op_is_first_frag(tmpl)) |
483 | mv_cesa_update_op_cfg(tmpl, | |
484 | CESA_SA_DESC_CFG_MID_FRAG, | |
485 | CESA_SA_DESC_CFG_FRAG_MSK); | |
db509a45 BB |
486 | |
487 | return op; | |
488 | } | |
489 | ||
0971d09a | 490 | static int |
db509a45 | 491 | mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain, |
db509a45 BB |
492 | struct mv_cesa_ahash_req *creq, |
493 | gfp_t flags) | |
db509a45 | 494 | { |
db509a45 | 495 | struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma; |
7850c91b | 496 | int ret; |
db509a45 | 497 | |
db509a45 | 498 | if (!creq->cache_ptr) |
0971d09a | 499 | return 0; |
db509a45 | 500 | |
7850c91b BB |
501 | ret = mv_cesa_ahash_dma_alloc_cache(ahashdreq, flags); |
502 | if (ret) | |
503 | return ret; | |
504 | ||
505 | memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr); | |
506 | ||
0971d09a RK |
507 | return mv_cesa_dma_add_data_transfer(chain, |
508 | CESA_SA_DATA_SRAM_OFFSET, | |
509 | ahashdreq->cache_dma, | |
510 | creq->cache_ptr, | |
511 | CESA_TDMA_DST_IN_SRAM, | |
512 | flags); | |
db509a45 BB |
513 | } |
514 | ||
515 | static struct mv_cesa_op_ctx * | |
516 | mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain, | |
517 | struct mv_cesa_ahash_dma_iter *dma_iter, | |
518 | struct mv_cesa_ahash_req *creq, | |
58953e15 | 519 | unsigned int frag_len, gfp_t flags) |
db509a45 BB |
520 | { |
521 | struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma; | |
522 | unsigned int len, trailerlen, padoff = 0; | |
58953e15 | 523 | struct mv_cesa_op_ctx *op; |
db509a45 BB |
524 | int ret; |
525 | ||
aee84a7e RK |
526 | /* |
527 | * If the transfer is smaller than our maximum length, and we have | |
528 | * some data outstanding, we can ask the engine to finish the hash. | |
529 | */ | |
530 | if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) { | |
58953e15 RK |
531 | op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len, |
532 | flags); | |
533 | if (IS_ERR(op)) | |
534 | return op; | |
db509a45 | 535 | |
aee84a7e RK |
536 | mv_cesa_set_mac_op_total_len(op, creq->len); |
537 | mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ? | |
538 | CESA_SA_DESC_CFG_NOT_FRAG : | |
539 | CESA_SA_DESC_CFG_LAST_FRAG, | |
540 | CESA_SA_DESC_CFG_FRAG_MSK); | |
db509a45 | 541 | |
f34dad17 RP |
542 | ret = mv_cesa_dma_add_result_op(chain, |
543 | CESA_SA_CFG_SRAM_OFFSET, | |
544 | CESA_SA_DATA_SRAM_OFFSET, | |
545 | CESA_TDMA_SRC_IN_SRAM, flags); | |
546 | if (ret) | |
547 | return ERR_PTR(-ENOMEM); | |
db509a45 BB |
548 | return op; |
549 | } | |
550 | ||
aee84a7e RK |
551 | /* |
552 | * The request is longer than the engine can handle, or we have | |
553 | * no data outstanding. Manually generate the padding, adding it | |
554 | * as a "mid" fragment. | |
555 | */ | |
db509a45 BB |
556 | ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags); |
557 | if (ret) | |
558 | return ERR_PTR(ret); | |
559 | ||
560 | trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding); | |
561 | ||
ab270e70 RK |
562 | len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen); |
563 | if (len) { | |
564 | ret = mv_cesa_dma_add_data_transfer(chain, | |
db509a45 | 565 | CESA_SA_DATA_SRAM_OFFSET + |
ab270e70 | 566 | frag_len, |
db509a45 BB |
567 | ahashdreq->padding_dma, |
568 | len, CESA_TDMA_DST_IN_SRAM, | |
569 | flags); | |
ab270e70 RK |
570 | if (ret) |
571 | return ERR_PTR(ret); | |
db509a45 | 572 | |
ab270e70 RK |
573 | op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len, |
574 | flags); | |
575 | if (IS_ERR(op)) | |
576 | return op; | |
db509a45 | 577 | |
ab270e70 RK |
578 | if (len == trailerlen) |
579 | return op; | |
db509a45 | 580 | |
ab270e70 RK |
581 | padoff += len; |
582 | } | |
db509a45 BB |
583 | |
584 | ret = mv_cesa_dma_add_data_transfer(chain, | |
585 | CESA_SA_DATA_SRAM_OFFSET, | |
586 | ahashdreq->padding_dma + | |
587 | padoff, | |
588 | trailerlen - padoff, | |
589 | CESA_TDMA_DST_IN_SRAM, | |
590 | flags); | |
591 | if (ret) | |
592 | return ERR_PTR(ret); | |
593 | ||
96212886 RK |
594 | return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff, |
595 | flags); | |
db509a45 BB |
596 | } |
597 | ||
598 | static int mv_cesa_ahash_dma_req_init(struct ahash_request *req) | |
599 | { | |
600 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
601 | gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? | |
602 | GFP_KERNEL : GFP_ATOMIC; | |
53da740f | 603 | struct mv_cesa_req *basereq = &creq->base; |
db509a45 BB |
604 | struct mv_cesa_ahash_dma_iter iter; |
605 | struct mv_cesa_op_ctx *op = NULL; | |
e41bbebd | 606 | unsigned int frag_len; |
8759fec4 | 607 | bool set_state = false; |
db509a45 | 608 | int ret; |
f34dad17 | 609 | u32 type; |
db509a45 | 610 | |
53da740f RP |
611 | basereq->chain.first = NULL; |
612 | basereq->chain.last = NULL; | |
db509a45 | 613 | |
8759fec4 RP |
614 | if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl)) |
615 | set_state = true; | |
616 | ||
db509a45 BB |
617 | if (creq->src_nents) { |
618 | ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents, | |
619 | DMA_TO_DEVICE); | |
620 | if (!ret) { | |
621 | ret = -ENOMEM; | |
622 | goto err; | |
623 | } | |
624 | } | |
625 | ||
53da740f | 626 | mv_cesa_tdma_desc_iter_init(&basereq->chain); |
db509a45 BB |
627 | mv_cesa_ahash_req_iter_init(&iter, req); |
628 | ||
0971d09a RK |
629 | /* |
630 | * Add the cache (left-over data from a previous block) first. | |
631 | * This will never overflow the SRAM size. | |
632 | */ | |
2a8a7857 | 633 | ret = mv_cesa_ahash_dma_add_cache(&basereq->chain, creq, flags); |
0971d09a | 634 | if (ret) |
db509a45 | 635 | goto err_free_tdma; |
db509a45 | 636 | |
d9bba4c3 RK |
637 | if (iter.src.sg) { |
638 | /* | |
639 | * Add all the new data, inserting an operation block and | |
640 | * launch command between each full SRAM block-worth of | |
e41bbebd | 641 | * data. We intentionally do not add the final op block. |
d9bba4c3 | 642 | */ |
e41bbebd | 643 | while (true) { |
53da740f | 644 | ret = mv_cesa_dma_add_op_transfers(&basereq->chain, |
8c07f3a8 | 645 | &iter.base, |
d9bba4c3 RK |
646 | &iter.src, flags); |
647 | if (ret) | |
648 | goto err_free_tdma; | |
649 | ||
e41bbebd | 650 | frag_len = iter.base.op_len; |
db509a45 | 651 | |
e41bbebd RK |
652 | if (!mv_cesa_ahash_req_iter_next_op(&iter)) |
653 | break; | |
654 | ||
53da740f | 655 | op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl, |
e41bbebd | 656 | frag_len, flags); |
d9bba4c3 RK |
657 | if (IS_ERR(op)) { |
658 | ret = PTR_ERR(op); | |
659 | goto err_free_tdma; | |
660 | } | |
db509a45 | 661 | } |
e41bbebd | 662 | } else { |
d9bba4c3 | 663 | /* Account for the data that was in the cache. */ |
e41bbebd RK |
664 | frag_len = iter.base.op_len; |
665 | } | |
666 | ||
58953e15 RK |
667 | /* |
668 | * At this point, frag_len indicates whether we have any data | |
669 | * outstanding which needs an operation. Queue up the final | |
670 | * operation, which depends whether this is the final request. | |
671 | */ | |
672 | if (creq->last_req) | |
53da740f | 673 | op = mv_cesa_ahash_dma_last_req(&basereq->chain, &iter, creq, |
8c07f3a8 | 674 | frag_len, flags); |
58953e15 | 675 | else if (frag_len) |
53da740f | 676 | op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl, |
8c07f3a8 | 677 | frag_len, flags); |
db509a45 | 678 | |
db509a45 BB |
679 | if (IS_ERR(op)) { |
680 | ret = PTR_ERR(op); | |
681 | goto err_free_tdma; | |
682 | } | |
683 | ||
f34dad17 RP |
684 | /* |
685 | * If results are copied via DMA, this means that this | |
686 | * request can be directly processed by the engine, | |
687 | * without partial updates. So we can chain it at the | |
688 | * DMA level with other requests. | |
689 | */ | |
690 | type = basereq->chain.last->flags & CESA_TDMA_TYPE_MSK; | |
691 | ||
692 | if (op && type != CESA_TDMA_RESULT) { | |
db509a45 | 693 | /* Add dummy desc to wait for crypto operation end */ |
53da740f | 694 | ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags); |
db509a45 BB |
695 | if (ret) |
696 | goto err_free_tdma; | |
697 | } | |
698 | ||
699 | if (!creq->last_req) | |
700 | creq->cache_ptr = req->nbytes + creq->cache_ptr - | |
701 | iter.base.len; | |
702 | else | |
703 | creq->cache_ptr = 0; | |
704 | ||
f34dad17 RP |
705 | basereq->chain.last->flags |= CESA_TDMA_END_OF_REQ; |
706 | ||
707 | if (type != CESA_TDMA_RESULT) | |
708 | basereq->chain.last->flags |= CESA_TDMA_BREAK_CHAIN; | |
85030c51 | 709 | |
8759fec4 RP |
710 | if (set_state) { |
711 | /* | |
712 | * Put the CESA_TDMA_SET_STATE flag on the first tdma desc to | |
713 | * let the step logic know that the IVDIG registers should be | |
714 | * explicitly set before launching a TDMA chain. | |
715 | */ | |
716 | basereq->chain.first->flags |= CESA_TDMA_SET_STATE; | |
717 | } | |
718 | ||
db509a45 BB |
719 | return 0; |
720 | ||
721 | err_free_tdma: | |
53da740f | 722 | mv_cesa_dma_cleanup(basereq); |
db509a45 BB |
723 | dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE); |
724 | ||
725 | err: | |
726 | mv_cesa_ahash_last_cleanup(req); | |
727 | ||
728 | return ret; | |
729 | } | |
730 | ||
f63601fd BB |
731 | static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached) |
732 | { | |
733 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
db509a45 | 734 | |
f63601fd | 735 | creq->src_nents = sg_nents_for_len(req->src, req->nbytes); |
c22dafb3 LC |
736 | if (creq->src_nents < 0) { |
737 | dev_err(cesa_dev->dev, "Invalid number of src SG"); | |
738 | return creq->src_nents; | |
739 | } | |
f63601fd | 740 | |
6dc156f4 | 741 | *cached = mv_cesa_ahash_cache_req(req); |
db509a45 BB |
742 | |
743 | if (*cached) | |
744 | return 0; | |
745 | ||
53da740f | 746 | if (cesa_dev->caps->has_tdma) |
6dc156f4 TP |
747 | return mv_cesa_ahash_dma_req_init(req); |
748 | else | |
749 | return 0; | |
f63601fd BB |
750 | } |
751 | ||
bf8f91e7 | 752 | static int mv_cesa_ahash_queue_req(struct ahash_request *req) |
f63601fd BB |
753 | { |
754 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
bf8f91e7 | 755 | struct mv_cesa_engine *engine; |
f63601fd BB |
756 | bool cached = false; |
757 | int ret; | |
758 | ||
f63601fd BB |
759 | ret = mv_cesa_ahash_req_init(req, &cached); |
760 | if (ret) | |
761 | return ret; | |
762 | ||
763 | if (cached) | |
764 | return 0; | |
765 | ||
bf8f91e7 RP |
766 | engine = mv_cesa_select_engine(req->nbytes); |
767 | mv_cesa_ahash_prepare(&req->base, engine); | |
768 | ||
53da740f | 769 | ret = mv_cesa_queue_req(&req->base, &creq->base); |
bf8f91e7 | 770 | |
cfcd2271 | 771 | if (mv_cesa_req_needs_cleanup(&req->base, ret)) |
db509a45 | 772 | mv_cesa_ahash_cleanup(req); |
db509a45 BB |
773 | |
774 | return ret; | |
f63601fd BB |
775 | } |
776 | ||
bf8f91e7 RP |
777 | static int mv_cesa_ahash_update(struct ahash_request *req) |
778 | { | |
779 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
780 | ||
781 | creq->len += req->nbytes; | |
782 | ||
783 | return mv_cesa_ahash_queue_req(req); | |
784 | } | |
785 | ||
f63601fd BB |
786 | static int mv_cesa_ahash_final(struct ahash_request *req) |
787 | { | |
788 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
789 | struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl; | |
f63601fd BB |
790 | |
791 | mv_cesa_set_mac_op_total_len(tmpl, creq->len); | |
792 | creq->last_req = true; | |
793 | req->nbytes = 0; | |
794 | ||
bf8f91e7 | 795 | return mv_cesa_ahash_queue_req(req); |
f63601fd BB |
796 | } |
797 | ||
798 | static int mv_cesa_ahash_finup(struct ahash_request *req) | |
799 | { | |
800 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
801 | struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl; | |
f63601fd BB |
802 | |
803 | creq->len += req->nbytes; | |
804 | mv_cesa_set_mac_op_total_len(tmpl, creq->len); | |
805 | creq->last_req = true; | |
806 | ||
bf8f91e7 | 807 | return mv_cesa_ahash_queue_req(req); |
f63601fd BB |
808 | } |
809 | ||
a6479ea4 RK |
810 | static int mv_cesa_ahash_export(struct ahash_request *req, void *hash, |
811 | u64 *len, void *cache) | |
7aeef693 | 812 | { |
7aeef693 AE |
813 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); |
814 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
815 | unsigned int digsize = crypto_ahash_digestsize(ahash); | |
a6479ea4 | 816 | unsigned int blocksize; |
7aeef693 | 817 | |
80754539 | 818 | blocksize = crypto_ahash_blocksize(ahash); |
7aeef693 | 819 | |
a6479ea4 RK |
820 | *len = creq->len; |
821 | memcpy(hash, creq->state, digsize); | |
822 | memset(cache, 0, blocksize); | |
063327f5 | 823 | memcpy(cache, creq->cache, creq->cache_ptr); |
7aeef693 AE |
824 | |
825 | return 0; | |
826 | } | |
827 | ||
a6479ea4 RK |
828 | static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash, |
829 | u64 len, const void *cache) | |
7aeef693 | 830 | { |
7aeef693 AE |
831 | struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); |
832 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); | |
833 | unsigned int digsize = crypto_ahash_digestsize(ahash); | |
a6479ea4 | 834 | unsigned int blocksize; |
7aeef693 AE |
835 | unsigned int cache_ptr; |
836 | int ret; | |
837 | ||
e72f407e RK |
838 | ret = crypto_ahash_init(req); |
839 | if (ret) | |
840 | return ret; | |
841 | ||
80754539 | 842 | blocksize = crypto_ahash_blocksize(ahash); |
a6479ea4 | 843 | if (len >= blocksize) |
c3bf02a2 RK |
844 | mv_cesa_update_op_cfg(&creq->op_tmpl, |
845 | CESA_SA_DESC_CFG_MID_FRAG, | |
846 | CESA_SA_DESC_CFG_FRAG_MSK); | |
847 | ||
a6479ea4 RK |
848 | creq->len = len; |
849 | memcpy(creq->state, hash, digsize); | |
7aeef693 AE |
850 | creq->cache_ptr = 0; |
851 | ||
a6479ea4 | 852 | cache_ptr = do_div(len, blocksize); |
7aeef693 AE |
853 | if (!cache_ptr) |
854 | return 0; | |
855 | ||
a6479ea4 | 856 | memcpy(creq->cache, cache, cache_ptr); |
7aeef693 AE |
857 | creq->cache_ptr = cache_ptr; |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
a6479ea4 RK |
862 | static int mv_cesa_md5_init(struct ahash_request *req) |
863 | { | |
b0ef5106 | 864 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
d30cb2fa | 865 | struct mv_cesa_op_ctx tmpl = { }; |
a6479ea4 RK |
866 | |
867 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5); | |
57cfda1a RP |
868 | |
869 | mv_cesa_ahash_init(req, &tmpl, true); | |
870 | ||
b0ef5106 BB |
871 | creq->state[0] = MD5_H0; |
872 | creq->state[1] = MD5_H1; | |
873 | creq->state[2] = MD5_H2; | |
874 | creq->state[3] = MD5_H3; | |
a6479ea4 | 875 | |
a6479ea4 RK |
876 | return 0; |
877 | } | |
878 | ||
879 | static int mv_cesa_md5_export(struct ahash_request *req, void *out) | |
880 | { | |
881 | struct md5_state *out_state = out; | |
882 | ||
883 | return mv_cesa_ahash_export(req, out_state->hash, | |
884 | &out_state->byte_count, out_state->block); | |
885 | } | |
886 | ||
887 | static int mv_cesa_md5_import(struct ahash_request *req, const void *in) | |
888 | { | |
889 | const struct md5_state *in_state = in; | |
890 | ||
891 | return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count, | |
892 | in_state->block); | |
893 | } | |
894 | ||
7aeef693 AE |
895 | static int mv_cesa_md5_digest(struct ahash_request *req) |
896 | { | |
897 | int ret; | |
898 | ||
899 | ret = mv_cesa_md5_init(req); | |
900 | if (ret) | |
901 | return ret; | |
902 | ||
903 | return mv_cesa_ahash_finup(req); | |
904 | } | |
905 | ||
906 | struct ahash_alg mv_md5_alg = { | |
907 | .init = mv_cesa_md5_init, | |
908 | .update = mv_cesa_ahash_update, | |
909 | .final = mv_cesa_ahash_final, | |
910 | .finup = mv_cesa_ahash_finup, | |
911 | .digest = mv_cesa_md5_digest, | |
912 | .export = mv_cesa_md5_export, | |
913 | .import = mv_cesa_md5_import, | |
914 | .halg = { | |
915 | .digestsize = MD5_DIGEST_SIZE, | |
9f5594c9 | 916 | .statesize = sizeof(struct md5_state), |
7aeef693 AE |
917 | .base = { |
918 | .cra_name = "md5", | |
919 | .cra_driver_name = "mv-md5", | |
920 | .cra_priority = 300, | |
921 | .cra_flags = CRYPTO_ALG_ASYNC | | |
922 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
923 | .cra_blocksize = MD5_HMAC_BLOCK_SIZE, | |
924 | .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx), | |
925 | .cra_init = mv_cesa_ahash_cra_init, | |
926 | .cra_module = THIS_MODULE, | |
927 | } | |
928 | } | |
929 | }; | |
930 | ||
f63601fd BB |
931 | static int mv_cesa_sha1_init(struct ahash_request *req) |
932 | { | |
b0ef5106 | 933 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
d30cb2fa | 934 | struct mv_cesa_op_ctx tmpl = { }; |
f63601fd BB |
935 | |
936 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1); | |
57cfda1a RP |
937 | |
938 | mv_cesa_ahash_init(req, &tmpl, false); | |
939 | ||
b0ef5106 BB |
940 | creq->state[0] = SHA1_H0; |
941 | creq->state[1] = SHA1_H1; | |
942 | creq->state[2] = SHA1_H2; | |
943 | creq->state[3] = SHA1_H3; | |
944 | creq->state[4] = SHA1_H4; | |
f63601fd | 945 | |
f63601fd BB |
946 | return 0; |
947 | } | |
948 | ||
949 | static int mv_cesa_sha1_export(struct ahash_request *req, void *out) | |
950 | { | |
951 | struct sha1_state *out_state = out; | |
f63601fd | 952 | |
a6479ea4 RK |
953 | return mv_cesa_ahash_export(req, out_state->state, &out_state->count, |
954 | out_state->buffer); | |
f63601fd BB |
955 | } |
956 | ||
957 | static int mv_cesa_sha1_import(struct ahash_request *req, const void *in) | |
958 | { | |
959 | const struct sha1_state *in_state = in; | |
f63601fd | 960 | |
a6479ea4 RK |
961 | return mv_cesa_ahash_import(req, in_state->state, in_state->count, |
962 | in_state->buffer); | |
f63601fd BB |
963 | } |
964 | ||
965 | static int mv_cesa_sha1_digest(struct ahash_request *req) | |
966 | { | |
967 | int ret; | |
968 | ||
969 | ret = mv_cesa_sha1_init(req); | |
970 | if (ret) | |
971 | return ret; | |
972 | ||
973 | return mv_cesa_ahash_finup(req); | |
974 | } | |
975 | ||
976 | struct ahash_alg mv_sha1_alg = { | |
977 | .init = mv_cesa_sha1_init, | |
978 | .update = mv_cesa_ahash_update, | |
979 | .final = mv_cesa_ahash_final, | |
980 | .finup = mv_cesa_ahash_finup, | |
981 | .digest = mv_cesa_sha1_digest, | |
982 | .export = mv_cesa_sha1_export, | |
983 | .import = mv_cesa_sha1_import, | |
984 | .halg = { | |
985 | .digestsize = SHA1_DIGEST_SIZE, | |
9f5594c9 | 986 | .statesize = sizeof(struct sha1_state), |
f63601fd BB |
987 | .base = { |
988 | .cra_name = "sha1", | |
989 | .cra_driver_name = "mv-sha1", | |
990 | .cra_priority = 300, | |
991 | .cra_flags = CRYPTO_ALG_ASYNC | | |
992 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
993 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
994 | .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx), | |
995 | .cra_init = mv_cesa_ahash_cra_init, | |
996 | .cra_module = THIS_MODULE, | |
997 | } | |
998 | } | |
999 | }; | |
1000 | ||
f85a762e AE |
1001 | static int mv_cesa_sha256_init(struct ahash_request *req) |
1002 | { | |
b0ef5106 | 1003 | struct mv_cesa_ahash_req *creq = ahash_request_ctx(req); |
d30cb2fa | 1004 | struct mv_cesa_op_ctx tmpl = { }; |
f85a762e AE |
1005 | |
1006 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256); | |
57cfda1a RP |
1007 | |
1008 | mv_cesa_ahash_init(req, &tmpl, false); | |
1009 | ||
b0ef5106 BB |
1010 | creq->state[0] = SHA256_H0; |
1011 | creq->state[1] = SHA256_H1; | |
1012 | creq->state[2] = SHA256_H2; | |
1013 | creq->state[3] = SHA256_H3; | |
1014 | creq->state[4] = SHA256_H4; | |
1015 | creq->state[5] = SHA256_H5; | |
1016 | creq->state[6] = SHA256_H6; | |
1017 | creq->state[7] = SHA256_H7; | |
f85a762e | 1018 | |
f85a762e AE |
1019 | return 0; |
1020 | } | |
1021 | ||
1022 | static int mv_cesa_sha256_digest(struct ahash_request *req) | |
1023 | { | |
1024 | int ret; | |
1025 | ||
1026 | ret = mv_cesa_sha256_init(req); | |
1027 | if (ret) | |
1028 | return ret; | |
1029 | ||
1030 | return mv_cesa_ahash_finup(req); | |
1031 | } | |
1032 | ||
1033 | static int mv_cesa_sha256_export(struct ahash_request *req, void *out) | |
1034 | { | |
1035 | struct sha256_state *out_state = out; | |
f85a762e | 1036 | |
a6479ea4 RK |
1037 | return mv_cesa_ahash_export(req, out_state->state, &out_state->count, |
1038 | out_state->buf); | |
f85a762e AE |
1039 | } |
1040 | ||
1041 | static int mv_cesa_sha256_import(struct ahash_request *req, const void *in) | |
1042 | { | |
1043 | const struct sha256_state *in_state = in; | |
f85a762e | 1044 | |
a6479ea4 RK |
1045 | return mv_cesa_ahash_import(req, in_state->state, in_state->count, |
1046 | in_state->buf); | |
f85a762e AE |
1047 | } |
1048 | ||
1049 | struct ahash_alg mv_sha256_alg = { | |
1050 | .init = mv_cesa_sha256_init, | |
1051 | .update = mv_cesa_ahash_update, | |
1052 | .final = mv_cesa_ahash_final, | |
1053 | .finup = mv_cesa_ahash_finup, | |
1054 | .digest = mv_cesa_sha256_digest, | |
1055 | .export = mv_cesa_sha256_export, | |
1056 | .import = mv_cesa_sha256_import, | |
1057 | .halg = { | |
1058 | .digestsize = SHA256_DIGEST_SIZE, | |
9f5594c9 | 1059 | .statesize = sizeof(struct sha256_state), |
f85a762e AE |
1060 | .base = { |
1061 | .cra_name = "sha256", | |
1062 | .cra_driver_name = "mv-sha256", | |
1063 | .cra_priority = 300, | |
1064 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1065 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1066 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1067 | .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx), | |
1068 | .cra_init = mv_cesa_ahash_cra_init, | |
1069 | .cra_module = THIS_MODULE, | |
1070 | } | |
1071 | } | |
1072 | }; | |
1073 | ||
f63601fd BB |
1074 | struct mv_cesa_ahash_result { |
1075 | struct completion completion; | |
1076 | int error; | |
1077 | }; | |
1078 | ||
1079 | static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req, | |
1080 | int error) | |
1081 | { | |
1082 | struct mv_cesa_ahash_result *result = req->data; | |
1083 | ||
1084 | if (error == -EINPROGRESS) | |
1085 | return; | |
1086 | ||
1087 | result->error = error; | |
1088 | complete(&result->completion); | |
1089 | } | |
1090 | ||
1091 | static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad, | |
1092 | void *state, unsigned int blocksize) | |
1093 | { | |
1094 | struct mv_cesa_ahash_result result; | |
1095 | struct scatterlist sg; | |
1096 | int ret; | |
1097 | ||
1098 | ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, | |
1099 | mv_cesa_hmac_ahash_complete, &result); | |
1100 | sg_init_one(&sg, pad, blocksize); | |
1101 | ahash_request_set_crypt(req, &sg, pad, blocksize); | |
1102 | init_completion(&result.completion); | |
1103 | ||
1104 | ret = crypto_ahash_init(req); | |
1105 | if (ret) | |
1106 | return ret; | |
1107 | ||
1108 | ret = crypto_ahash_update(req); | |
1109 | if (ret && ret != -EINPROGRESS) | |
1110 | return ret; | |
1111 | ||
1112 | wait_for_completion_interruptible(&result.completion); | |
1113 | if (result.error) | |
1114 | return result.error; | |
1115 | ||
1116 | ret = crypto_ahash_export(req, state); | |
1117 | if (ret) | |
1118 | return ret; | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static int mv_cesa_ahmac_pad_init(struct ahash_request *req, | |
1124 | const u8 *key, unsigned int keylen, | |
1125 | u8 *ipad, u8 *opad, | |
1126 | unsigned int blocksize) | |
1127 | { | |
1128 | struct mv_cesa_ahash_result result; | |
1129 | struct scatterlist sg; | |
1130 | int ret; | |
1131 | int i; | |
1132 | ||
1133 | if (keylen <= blocksize) { | |
1134 | memcpy(ipad, key, keylen); | |
1135 | } else { | |
1136 | u8 *keydup = kmemdup(key, keylen, GFP_KERNEL); | |
1137 | ||
1138 | if (!keydup) | |
1139 | return -ENOMEM; | |
1140 | ||
1141 | ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, | |
1142 | mv_cesa_hmac_ahash_complete, | |
1143 | &result); | |
1144 | sg_init_one(&sg, keydup, keylen); | |
1145 | ahash_request_set_crypt(req, &sg, ipad, keylen); | |
1146 | init_completion(&result.completion); | |
1147 | ||
1148 | ret = crypto_ahash_digest(req); | |
1149 | if (ret == -EINPROGRESS) { | |
1150 | wait_for_completion_interruptible(&result.completion); | |
1151 | ret = result.error; | |
1152 | } | |
1153 | ||
1154 | /* Set the memory region to 0 to avoid any leak. */ | |
1155 | memset(keydup, 0, keylen); | |
1156 | kfree(keydup); | |
1157 | ||
1158 | if (ret) | |
1159 | return ret; | |
1160 | ||
1161 | keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req)); | |
1162 | } | |
1163 | ||
1164 | memset(ipad + keylen, 0, blocksize - keylen); | |
1165 | memcpy(opad, ipad, blocksize); | |
1166 | ||
1167 | for (i = 0; i < blocksize; i++) { | |
d477d813 CL |
1168 | ipad[i] ^= HMAC_IPAD_VALUE; |
1169 | opad[i] ^= HMAC_OPAD_VALUE; | |
f63601fd BB |
1170 | } |
1171 | ||
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | static int mv_cesa_ahmac_setkey(const char *hash_alg_name, | |
1176 | const u8 *key, unsigned int keylen, | |
1177 | void *istate, void *ostate) | |
1178 | { | |
1179 | struct ahash_request *req; | |
1180 | struct crypto_ahash *tfm; | |
1181 | unsigned int blocksize; | |
1182 | u8 *ipad = NULL; | |
1183 | u8 *opad; | |
1184 | int ret; | |
1185 | ||
1186 | tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH, | |
1187 | CRYPTO_ALG_TYPE_AHASH_MASK); | |
1188 | if (IS_ERR(tfm)) | |
1189 | return PTR_ERR(tfm); | |
1190 | ||
1191 | req = ahash_request_alloc(tfm, GFP_KERNEL); | |
1192 | if (!req) { | |
1193 | ret = -ENOMEM; | |
1194 | goto free_ahash; | |
1195 | } | |
1196 | ||
1197 | crypto_ahash_clear_flags(tfm, ~0); | |
1198 | ||
1199 | blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); | |
1200 | ||
6396bb22 | 1201 | ipad = kcalloc(2, blocksize, GFP_KERNEL); |
f63601fd BB |
1202 | if (!ipad) { |
1203 | ret = -ENOMEM; | |
1204 | goto free_req; | |
1205 | } | |
1206 | ||
1207 | opad = ipad + blocksize; | |
1208 | ||
1209 | ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize); | |
1210 | if (ret) | |
1211 | goto free_ipad; | |
1212 | ||
1213 | ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize); | |
1214 | if (ret) | |
1215 | goto free_ipad; | |
1216 | ||
1217 | ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize); | |
1218 | ||
1219 | free_ipad: | |
1220 | kfree(ipad); | |
1221 | free_req: | |
1222 | ahash_request_free(req); | |
1223 | free_ahash: | |
1224 | crypto_free_ahash(tfm); | |
1225 | ||
1226 | return ret; | |
1227 | } | |
1228 | ||
1229 | static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm) | |
1230 | { | |
1231 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm); | |
1232 | ||
1233 | ctx->base.ops = &mv_cesa_ahash_req_ops; | |
1234 | ||
1235 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
1236 | sizeof(struct mv_cesa_ahash_req)); | |
1237 | return 0; | |
1238 | } | |
1239 | ||
7aeef693 AE |
1240 | static int mv_cesa_ahmac_md5_init(struct ahash_request *req) |
1241 | { | |
1242 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); | |
d30cb2fa | 1243 | struct mv_cesa_op_ctx tmpl = { }; |
7aeef693 AE |
1244 | |
1245 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5); | |
1246 | memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); | |
1247 | ||
a9eb678f | 1248 | mv_cesa_ahash_init(req, &tmpl, true); |
7aeef693 AE |
1249 | |
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1254 | unsigned int keylen) | |
1255 | { | |
1256 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); | |
1257 | struct md5_state istate, ostate; | |
1258 | int ret, i; | |
1259 | ||
1260 | ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate); | |
1261 | if (ret) | |
1262 | return ret; | |
1263 | ||
1264 | for (i = 0; i < ARRAY_SIZE(istate.hash); i++) | |
1265 | ctx->iv[i] = be32_to_cpu(istate.hash[i]); | |
1266 | ||
1267 | for (i = 0; i < ARRAY_SIZE(ostate.hash); i++) | |
1268 | ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]); | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | static int mv_cesa_ahmac_md5_digest(struct ahash_request *req) | |
1274 | { | |
1275 | int ret; | |
1276 | ||
1277 | ret = mv_cesa_ahmac_md5_init(req); | |
1278 | if (ret) | |
1279 | return ret; | |
1280 | ||
1281 | return mv_cesa_ahash_finup(req); | |
1282 | } | |
1283 | ||
1284 | struct ahash_alg mv_ahmac_md5_alg = { | |
1285 | .init = mv_cesa_ahmac_md5_init, | |
1286 | .update = mv_cesa_ahash_update, | |
1287 | .final = mv_cesa_ahash_final, | |
1288 | .finup = mv_cesa_ahash_finup, | |
1289 | .digest = mv_cesa_ahmac_md5_digest, | |
1290 | .setkey = mv_cesa_ahmac_md5_setkey, | |
1291 | .export = mv_cesa_md5_export, | |
1292 | .import = mv_cesa_md5_import, | |
1293 | .halg = { | |
1294 | .digestsize = MD5_DIGEST_SIZE, | |
1295 | .statesize = sizeof(struct md5_state), | |
1296 | .base = { | |
1297 | .cra_name = "hmac(md5)", | |
1298 | .cra_driver_name = "mv-hmac-md5", | |
1299 | .cra_priority = 300, | |
1300 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1301 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1302 | .cra_blocksize = MD5_HMAC_BLOCK_SIZE, | |
1303 | .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx), | |
1304 | .cra_init = mv_cesa_ahmac_cra_init, | |
1305 | .cra_module = THIS_MODULE, | |
1306 | } | |
1307 | } | |
1308 | }; | |
1309 | ||
f63601fd BB |
1310 | static int mv_cesa_ahmac_sha1_init(struct ahash_request *req) |
1311 | { | |
1312 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); | |
d30cb2fa | 1313 | struct mv_cesa_op_ctx tmpl = { }; |
f63601fd BB |
1314 | |
1315 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1); | |
1316 | memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); | |
1317 | ||
a9eb678f | 1318 | mv_cesa_ahash_init(req, &tmpl, false); |
f63601fd BB |
1319 | |
1320 | return 0; | |
1321 | } | |
1322 | ||
1323 | static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1324 | unsigned int keylen) | |
1325 | { | |
1326 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); | |
1327 | struct sha1_state istate, ostate; | |
1328 | int ret, i; | |
1329 | ||
1330 | ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate); | |
1331 | if (ret) | |
1332 | return ret; | |
1333 | ||
1334 | for (i = 0; i < ARRAY_SIZE(istate.state); i++) | |
1335 | ctx->iv[i] = be32_to_cpu(istate.state[i]); | |
1336 | ||
1337 | for (i = 0; i < ARRAY_SIZE(ostate.state); i++) | |
1338 | ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]); | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req) | |
1344 | { | |
1345 | int ret; | |
1346 | ||
1347 | ret = mv_cesa_ahmac_sha1_init(req); | |
1348 | if (ret) | |
1349 | return ret; | |
1350 | ||
1351 | return mv_cesa_ahash_finup(req); | |
1352 | } | |
1353 | ||
1354 | struct ahash_alg mv_ahmac_sha1_alg = { | |
1355 | .init = mv_cesa_ahmac_sha1_init, | |
1356 | .update = mv_cesa_ahash_update, | |
1357 | .final = mv_cesa_ahash_final, | |
1358 | .finup = mv_cesa_ahash_finup, | |
1359 | .digest = mv_cesa_ahmac_sha1_digest, | |
1360 | .setkey = mv_cesa_ahmac_sha1_setkey, | |
1361 | .export = mv_cesa_sha1_export, | |
1362 | .import = mv_cesa_sha1_import, | |
1363 | .halg = { | |
1364 | .digestsize = SHA1_DIGEST_SIZE, | |
1365 | .statesize = sizeof(struct sha1_state), | |
1366 | .base = { | |
1367 | .cra_name = "hmac(sha1)", | |
1368 | .cra_driver_name = "mv-hmac-sha1", | |
1369 | .cra_priority = 300, | |
1370 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1371 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1372 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1373 | .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx), | |
1374 | .cra_init = mv_cesa_ahmac_cra_init, | |
1375 | .cra_module = THIS_MODULE, | |
1376 | } | |
1377 | } | |
1378 | }; | |
f85a762e AE |
1379 | |
1380 | static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1381 | unsigned int keylen) | |
1382 | { | |
1383 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm)); | |
1384 | struct sha256_state istate, ostate; | |
1385 | int ret, i; | |
1386 | ||
1387 | ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate); | |
1388 | if (ret) | |
1389 | return ret; | |
1390 | ||
1391 | for (i = 0; i < ARRAY_SIZE(istate.state); i++) | |
1392 | ctx->iv[i] = be32_to_cpu(istate.state[i]); | |
1393 | ||
1394 | for (i = 0; i < ARRAY_SIZE(ostate.state); i++) | |
1395 | ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]); | |
1396 | ||
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | static int mv_cesa_ahmac_sha256_init(struct ahash_request *req) | |
1401 | { | |
1402 | struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); | |
d30cb2fa | 1403 | struct mv_cesa_op_ctx tmpl = { }; |
f85a762e AE |
1404 | |
1405 | mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256); | |
1406 | memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); | |
1407 | ||
a9eb678f | 1408 | mv_cesa_ahash_init(req, &tmpl, false); |
f85a762e AE |
1409 | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req) | |
1414 | { | |
1415 | int ret; | |
1416 | ||
1417 | ret = mv_cesa_ahmac_sha256_init(req); | |
1418 | if (ret) | |
1419 | return ret; | |
1420 | ||
1421 | return mv_cesa_ahash_finup(req); | |
1422 | } | |
1423 | ||
1424 | struct ahash_alg mv_ahmac_sha256_alg = { | |
1425 | .init = mv_cesa_ahmac_sha256_init, | |
1426 | .update = mv_cesa_ahash_update, | |
1427 | .final = mv_cesa_ahash_final, | |
1428 | .finup = mv_cesa_ahash_finup, | |
1429 | .digest = mv_cesa_ahmac_sha256_digest, | |
1430 | .setkey = mv_cesa_ahmac_sha256_setkey, | |
1431 | .export = mv_cesa_sha256_export, | |
1432 | .import = mv_cesa_sha256_import, | |
1433 | .halg = { | |
1434 | .digestsize = SHA256_DIGEST_SIZE, | |
1435 | .statesize = sizeof(struct sha256_state), | |
1436 | .base = { | |
1437 | .cra_name = "hmac(sha256)", | |
1438 | .cra_driver_name = "mv-hmac-sha256", | |
1439 | .cra_priority = 300, | |
1440 | .cra_flags = CRYPTO_ALG_ASYNC | | |
1441 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
1442 | .cra_blocksize = SHA256_BLOCK_SIZE, | |
1443 | .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx), | |
1444 | .cra_init = mv_cesa_ahmac_cra_init, | |
1445 | .cra_module = THIS_MODULE, | |
1446 | } | |
1447 | } | |
1448 | }; |