[linux-2.6-block.git] / drivers / crypto / hisilicon / qm.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2019 HiSilicon Limited. */
#ifndef HISI_ACC_QM_H
#define HISI_ACC_QM_H

#include <linux/bitfield.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/pci.h>

/* qm user domain */
#define QM_ARUSER_M_CFG_1		0x100088
#define AXUSER_SNOOP_ENABLE		BIT(30)
#define AXUSER_CMD_TYPE			GENMASK(14, 12)
#define AXUSER_CMD_SMMU_NORMAL		1
#define AXUSER_NS			BIT(6)
#define AXUSER_NO			BIT(5)
#define AXUSER_FP			BIT(4)
#define AXUSER_SSV			BIT(0)
#define AXUSER_BASE			(AXUSER_SNOOP_ENABLE |		\
					FIELD_PREP(AXUSER_CMD_TYPE,	\
					AXUSER_CMD_SMMU_NORMAL) |	\
					AXUSER_NS | AXUSER_NO | AXUSER_FP)
#define QM_ARUSER_M_CFG_ENABLE		0x100090
#define ARUSER_M_CFG_ENABLE		0xfffffffe
#define QM_AWUSER_M_CFG_1		0x100098
#define QM_AWUSER_M_CFG_ENABLE		0x1000a0
#define AWUSER_M_CFG_ENABLE		0xfffffffe
#define QM_WUSER_M_CFG_ENABLE		0x1000a8
#define WUSER_M_CFG_ENABLE		0xffffffff

/* qm cache */
#define QM_CACHE_CTL			0x100050
#define SQC_CACHE_ENABLE		BIT(0)
#define CQC_CACHE_ENABLE		BIT(1)
#define SQC_CACHE_WB_ENABLE		BIT(4)
#define SQC_CACHE_WB_THRD		GENMASK(10, 5)
#define CQC_CACHE_WB_ENABLE		BIT(11)
#define CQC_CACHE_WB_THRD		GENMASK(17, 12)
#define QM_AXI_M_CFG			0x1000ac
#define AXI_M_CFG			0xffff
#define QM_AXI_M_CFG_ENABLE		0x1000b0
#define AXI_M_CFG_ENABLE		0xffffffff
#define QM_PEH_AXUSER_CFG		0x1000cc
#define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
#define PEH_AXUSER_CFG			0x401001
#define PEH_AXUSER_CFG_ENABLE		0xffffffff


#define QM_AXI_RRESP			BIT(0)
#define QM_AXI_BRESP			BIT(1)
#define QM_ECC_MBIT			BIT(2)
#define QM_ECC_1BIT			BIT(3)
#define QM_ACC_GET_TASK_TIMEOUT		BIT(4)
#define QM_ACC_DO_TASK_TIMEOUT		BIT(5)
#define QM_ACC_WB_NOT_READY_TIMEOUT	BIT(6)
#define QM_SQ_CQ_VF_INVALID		BIT(7)
#define QM_CQ_VF_INVALID		BIT(8)
#define QM_SQ_VF_INVALID		BIT(9)
#define QM_DB_TIMEOUT			BIT(10)
#define QM_OF_FIFO_OF			BIT(11)
#define QM_DB_RANDOM_INVALID		BIT(12)

#define QM_BASE_NFE	(QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
			 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
			 QM_OF_FIFO_OF)
#define QM_BASE_CE			QM_ECC_1BIT

#define QM_Q_DEPTH			1024

enum qp_state {
	QP_STOP,
};

enum qm_hw_ver {
	QM_HW_UNKNOWN = -1,
	QM_HW_V1 = 0x20,
	QM_HW_V2 = 0x21,
};

enum qm_fun_type {
	QM_HW_PF,
};

struct qm_dma {
	void *va;
	dma_addr_t dma;
	size_t size;
};

struct hisi_qm_status {
	u32 eq_head;
	bool eqc_phase;
	u32 aeq_head;
	bool aeqc_phase;
	unsigned long flags;
};

struct hisi_qm {
	enum qm_hw_ver ver;
	const char *dev_name;
	struct pci_dev *pdev;
	void __iomem *io_base;
	u32 sqe_size;
	u32 qp_base;
	u32 qp_num;
	u32 ctrl_qp_num;

	struct qm_dma qdma;
	struct qm_sqc *sqc;
	struct qm_cqc *cqc;
	struct qm_eqe *eqe;
	struct qm_aeqe *aeqe;
	dma_addr_t sqc_dma;
	dma_addr_t cqc_dma;
	dma_addr_t eqe_dma;
	dma_addr_t aeqe_dma;

	struct hisi_qm_status status;

	rwlock_t qps_lock;
	unsigned long *qp_bitmap;
	struct hisi_qp **qp_array;

	struct mutex mailbox_lock;

	const struct hisi_qm_hw_ops *ops;

	u32 error_mask;
	u32 msi_mask;

	bool use_dma_api;
};

struct hisi_qp_status {
	atomic_t used;
	u16 sq_tail;
	u16 cq_head;
	bool cqc_phase;
	unsigned long flags;
};

struct hisi_qp_ops {
	int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
};

struct hisi_qp {
	u32 qp_id;
	u8 alg_type;
	u8 req_type;

	struct qm_dma qdma;
	void *sqe;
	struct qm_cqe *cqe;
	dma_addr_t sqe_dma;
	dma_addr_t cqe_dma;

	struct hisi_qp_status qp_status;
	struct hisi_qp_ops *hw_ops;
	void *qp_ctx;
	void (*req_cb)(struct hisi_qp *qp, void *data);
	struct work_struct work;
	struct workqueue_struct *wq;

	struct hisi_qm *qm;
};

int hisi_qm_init(struct hisi_qm *qm);
void hisi_qm_uninit(struct hisi_qm *qm);
int hisi_qm_start(struct hisi_qm *qm);
int hisi_qm_stop(struct hisi_qm *qm);
struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
int hisi_qm_stop_qp(struct hisi_qp *qp);
void hisi_qm_release_qp(struct hisi_qp *qp);
int hisi_qp_send(struct hisi_qp *qp, const void *msg);
int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
			   u32 msi);
int hisi_qm_hw_error_handle(struct hisi_qm *qm);
enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
#endif
Commit	Line	Data
263c9959 ZW	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (c) 2019 HiSilicon Limited. */
	3	#ifndef HISI_ACC_QM_H
	4	#define HISI_ACC_QM_H
	5
	6	#include <linux/bitfield.h>
	7	#include <linux/iopoll.h>
	8	#include <linux/module.h>
	9	#include <linux/pci.h>
	10
	11	/* qm user domain */
	12	#define QM_ARUSER_M_CFG_1 0x100088
	13	#define AXUSER_SNOOP_ENABLE BIT(30)
	14	#define AXUSER_CMD_TYPE GENMASK(14, 12)
	15	#define AXUSER_CMD_SMMU_NORMAL 1
	16	#define AXUSER_NS BIT(6)
	17	#define AXUSER_NO BIT(5)
	18	#define AXUSER_FP BIT(4)
	19	#define AXUSER_SSV BIT(0)
	20	#define AXUSER_BASE (AXUSER_SNOOP_ENABLE \| \
	21	FIELD_PREP(AXUSER_CMD_TYPE, \
	22	AXUSER_CMD_SMMU_NORMAL) \| \
	23	AXUSER_NS \| AXUSER_NO \| AXUSER_FP)
	24	#define QM_ARUSER_M_CFG_ENABLE 0x100090
	25	#define ARUSER_M_CFG_ENABLE 0xfffffffe
	26	#define QM_AWUSER_M_CFG_1 0x100098
	27	#define QM_AWUSER_M_CFG_ENABLE 0x1000a0
	28	#define AWUSER_M_CFG_ENABLE 0xfffffffe
	29	#define QM_WUSER_M_CFG_ENABLE 0x1000a8
	30	#define WUSER_M_CFG_ENABLE 0xffffffff
	31
	32	/* qm cache */
	33	#define QM_CACHE_CTL 0x100050
	34	#define SQC_CACHE_ENABLE BIT(0)
	35	#define CQC_CACHE_ENABLE BIT(1)
	36	#define SQC_CACHE_WB_ENABLE BIT(4)
	37	#define SQC_CACHE_WB_THRD GENMASK(10, 5)
	38	#define CQC_CACHE_WB_ENABLE BIT(11)
	39	#define CQC_CACHE_WB_THRD GENMASK(17, 12)
	40	#define QM_AXI_M_CFG 0x1000ac
	41	#define AXI_M_CFG 0xffff
	42	#define QM_AXI_M_CFG_ENABLE 0x1000b0
	43	#define AXI_M_CFG_ENABLE 0xffffffff
	44	#define QM_PEH_AXUSER_CFG 0x1000cc
	45	#define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
	46	#define PEH_AXUSER_CFG 0x401001
	47	#define PEH_AXUSER_CFG_ENABLE 0xffffffff
	48
	49
	50	#define QM_AXI_RRESP BIT(0)
	51	#define QM_AXI_BRESP BIT(1)
	52	#define QM_ECC_MBIT BIT(2)
	53	#define QM_ECC_1BIT BIT(3)
	54	#define QM_ACC_GET_TASK_TIMEOUT BIT(4)
	55	#define QM_ACC_DO_TASK_TIMEOUT BIT(5)
	56	#define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
	57	#define QM_SQ_CQ_VF_INVALID BIT(7)
	58	#define QM_CQ_VF_INVALID BIT(8)
	59	#define QM_SQ_VF_INVALID BIT(9)
	60	#define QM_DB_TIMEOUT BIT(10)
	61	#define QM_OF_FIFO_OF BIT(11)
	62	#define QM_DB_RANDOM_INVALID BIT(12)
	63
	64	#define QM_BASE_NFE (QM_AXI_RRESP \| QM_AXI_BRESP \| QM_ECC_MBIT \| \
65	QM_ACC_GET_TASK_TIMEOUT \| QM_DB_TIMEOUT \| \
66	QM_OF_FIFO_OF)
67	#define QM_BASE_CE QM_ECC_1BIT
68
69	#define QM_Q_DEPTH 1024
70
71	enum qp_state {
72	QP_STOP,
73	};
74
75	enum qm_hw_ver {
76	QM_HW_UNKNOWN = -1,
77	QM_HW_V1 = 0x20,
78	QM_HW_V2 = 0x21,
79	};
80
81	enum qm_fun_type {
82	QM_HW_PF,
83	};
84
85	struct qm_dma {
86	void *va;
87	dma_addr_t dma;
88	size_t size;
89	};
90
91	struct hisi_qm_status {
92	u32 eq_head;
93	bool eqc_phase;
94	u32 aeq_head;
95	bool aeqc_phase;
96	unsigned long flags;
97	};
98
99	struct hisi_qm {
100	enum qm_hw_ver ver;
101	const char *dev_name;
102	struct pci_dev *pdev;
103	void __iomem *io_base;
104	u32 sqe_size;
105	u32 qp_base;
106	u32 qp_num;
107	u32 ctrl_qp_num;
108
109	struct qm_dma qdma;
110	struct qm_sqc *sqc;
111	struct qm_cqc *cqc;
112	struct qm_eqe *eqe;
113	struct qm_aeqe *aeqe;
114	dma_addr_t sqc_dma;
115	dma_addr_t cqc_dma;
116	dma_addr_t eqe_dma;
117	dma_addr_t aeqe_dma;
118
119	struct hisi_qm_status status;
120
121	rwlock_t qps_lock;
122	unsigned long *qp_bitmap;
123	struct hisi_qp **qp_array;
124
125	struct mutex mailbox_lock;
126
127	const struct hisi_qm_hw_ops *ops;
128
129	u32 error_mask;
130	u32 msi_mask;
131
132	bool use_dma_api;
133	};
134
135	struct hisi_qp_status {
136	atomic_t used;
137	u16 sq_tail;
138	u16 cq_head;
139	bool cqc_phase;
140	unsigned long flags;
141	};
142
143	struct hisi_qp_ops {
144	int (fill_sqe)(void sqe, void q_parm, void d_parm);
145	};
146
147	struct hisi_qp {
148	u32 qp_id;
149	u8 alg_type;
150	u8 req_type;
151
152	struct qm_dma qdma;
153	void *sqe;
154	struct qm_cqe *cqe;
155	dma_addr_t sqe_dma;
156	dma_addr_t cqe_dma;
157
158	struct hisi_qp_status qp_status;
159	struct hisi_qp_ops *hw_ops;
160	void *qp_ctx;
161	void (req_cb)(struct hisi_qp qp, void *data);
162	struct work_struct work;
163	struct workqueue_struct *wq;
164
165	struct hisi_qm *qm;
166	};
167
168	int hisi_qm_init(struct hisi_qm *qm);
169	void hisi_qm_uninit(struct hisi_qm *qm);
170	int hisi_qm_start(struct hisi_qm *qm);
171	int hisi_qm_stop(struct hisi_qm *qm);
172	struct hisi_qp hisi_qm_create_qp(struct hisi_qm qm, u8 alg_type);
173	int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
174	int hisi_qm_stop_qp(struct hisi_qp *qp);
175	void hisi_qm_release_qp(struct hisi_qp *qp);
176	int hisi_qp_send(struct hisi_qp qp, const void msg);
177	int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
178	void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
179	u32 msi);
180	int hisi_qm_hw_error_handle(struct hisi_qm *qm);
181	enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
182	#endif