[linux-2.6-block.git] / drivers / crypto / hisilicon / qm.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2019 HiSilicon Limited. */
#ifndef HISI_ACC_QM_H
#define HISI_ACC_QM_H

#include <linux/bitfield.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/pci.h>

#define QM_QNUM_V1			4096
#define QM_QNUM_V2			1024
#define QM_MAX_VFS_NUM_V2		63

/* qm user domain */
#define QM_ARUSER_M_CFG_1		0x100088
#define AXUSER_SNOOP_ENABLE		BIT(30)
#define AXUSER_CMD_TYPE			GENMASK(14, 12)
#define AXUSER_CMD_SMMU_NORMAL		1
#define AXUSER_NS			BIT(6)
#define AXUSER_NO			BIT(5)
#define AXUSER_FP			BIT(4)
#define AXUSER_SSV			BIT(0)
#define AXUSER_BASE			(AXUSER_SNOOP_ENABLE |		\
					FIELD_PREP(AXUSER_CMD_TYPE,	\
					AXUSER_CMD_SMMU_NORMAL) |	\
					AXUSER_NS | AXUSER_NO | AXUSER_FP)
#define QM_ARUSER_M_CFG_ENABLE		0x100090
#define ARUSER_M_CFG_ENABLE		0xfffffffe
#define QM_AWUSER_M_CFG_1		0x100098
#define QM_AWUSER_M_CFG_ENABLE		0x1000a0
#define AWUSER_M_CFG_ENABLE		0xfffffffe
#define QM_WUSER_M_CFG_ENABLE		0x1000a8
#define WUSER_M_CFG_ENABLE		0xffffffff

/* qm cache */
#define QM_CACHE_CTL			0x100050
#define SQC_CACHE_ENABLE		BIT(0)
#define CQC_CACHE_ENABLE		BIT(1)
#define SQC_CACHE_WB_ENABLE		BIT(4)
#define SQC_CACHE_WB_THRD		GENMASK(10, 5)
#define CQC_CACHE_WB_ENABLE		BIT(11)
#define CQC_CACHE_WB_THRD		GENMASK(17, 12)
#define QM_AXI_M_CFG			0x1000ac
#define AXI_M_CFG			0xffff
#define QM_AXI_M_CFG_ENABLE		0x1000b0
#define AM_CFG_SINGLE_PORT_MAX_TRANS	0x300014
#define AXI_M_CFG_ENABLE		0xffffffff
#define QM_PEH_AXUSER_CFG		0x1000cc
#define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
#define PEH_AXUSER_CFG			0x401001
#define PEH_AXUSER_CFG_ENABLE		0xffffffff

#define QM_DFX_MB_CNT_VF		0x104010
#define QM_DFX_DB_CNT_VF		0x104020
#define QM_DFX_SQE_CNT_VF_SQN		0x104030
#define QM_DFX_CQE_CNT_VF_CQN		0x104040
#define QM_DFX_QN_SHIFT			16
#define CURRENT_FUN_MASK		GENMASK(5, 0)
#define CURRENT_Q_MASK			GENMASK(31, 16)

#define QM_AXI_RRESP			BIT(0)
#define QM_AXI_BRESP			BIT(1)
#define QM_ECC_MBIT			BIT(2)
#define QM_ECC_1BIT			BIT(3)
#define QM_ACC_GET_TASK_TIMEOUT		BIT(4)
#define QM_ACC_DO_TASK_TIMEOUT		BIT(5)
#define QM_ACC_WB_NOT_READY_TIMEOUT	BIT(6)
#define QM_SQ_CQ_VF_INVALID		BIT(7)
#define QM_CQ_VF_INVALID		BIT(8)
#define QM_SQ_VF_INVALID		BIT(9)
#define QM_DB_TIMEOUT			BIT(10)
#define QM_OF_FIFO_OF			BIT(11)
#define QM_DB_RANDOM_INVALID		BIT(12)

#define QM_BASE_NFE	(QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
			 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
			 QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID)
#define QM_BASE_CE			QM_ECC_1BIT

#define QM_Q_DEPTH			1024

#define HISI_ACC_SGL_SGE_NR_MAX		255

/* page number for queue file region */
#define QM_DOORBELL_PAGE_NR		1

enum qm_stop_reason {
	QM_NORMAL,
	QM_SOFT_RESET,
	QM_FLR,
};

enum qm_state {
	QM_INIT = 0,
	QM_START,
	QM_CLOSE,
	QM_STOP,
};

enum qp_state {
	QP_INIT = 1,
	QP_START,
	QP_STOP,
	QP_CLOSE,
};

enum qm_hw_ver {
	QM_HW_UNKNOWN = -1,
	QM_HW_V1 = 0x20,
	QM_HW_V2 = 0x21,
	QM_HW_V3 = 0x30,
};

enum qm_fun_type {
	QM_HW_PF,
	QM_HW_VF,
};

enum qm_debug_file {
	CURRENT_Q,
	CLEAR_ENABLE,
	DEBUG_FILE_NUM,
};

struct qm_dfx {
	atomic64_t err_irq_cnt;
	atomic64_t aeq_irq_cnt;
	atomic64_t abnormal_irq_cnt;
	atomic64_t create_qp_err_cnt;
	atomic64_t mb_err_cnt;
};

struct debugfs_file {
	enum qm_debug_file index;
	struct mutex lock;
	struct qm_debug *debug;
};

struct qm_debug {
	u32 curr_qm_qp_num;
	u32 sqe_mask_offset;
	u32 sqe_mask_len;
	struct qm_dfx dfx;
	struct dentry *debug_root;
	struct dentry *qm_d;
	struct debugfs_file files[DEBUG_FILE_NUM];
};

struct qm_dma {
	void *va;
	dma_addr_t dma;
	size_t size;
};

struct hisi_qm_status {
	u32 eq_head;
	bool eqc_phase;
	u32 aeq_head;
	bool aeqc_phase;
	atomic_t flags;
	int stop_reason;
};

struct hisi_qm;

struct hisi_qm_err_info {
	char *acpi_rst;
	u32 msi_wr_port;
	u32 ecc_2bits_mask;
	u32 ce;
	u32 nfe;
	u32 fe;
};

struct hisi_qm_err_status {
	u32 is_qm_ecc_mbit;
	u32 is_dev_ecc_mbit;
};

struct hisi_qm_err_ini {
	int (*hw_init)(struct hisi_qm *qm);
	void (*hw_err_enable)(struct hisi_qm *qm);
	void (*hw_err_disable)(struct hisi_qm *qm);
	u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
	void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
	void (*open_axi_master_ooo)(struct hisi_qm *qm);
	void (*close_axi_master_ooo)(struct hisi_qm *qm);
	void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
	struct hisi_qm_err_info err_info;
};

struct hisi_qm_list {
	struct mutex lock;
	struct list_head list;
	int (*register_to_crypto)(void);
	void (*unregister_from_crypto)(void);
};

struct hisi_qm {
	enum qm_hw_ver ver;
	enum qm_fun_type fun_type;
	const char *dev_name;
	struct pci_dev *pdev;
	void __iomem *io_base;
	u32 sqe_size;
	u32 qp_base;
	u32 qp_num;
	u32 qp_in_used;
	u32 ctrl_qp_num;
	u32 vfs_num;
	struct list_head list;
	struct hisi_qm_list *qm_list;

	struct qm_dma qdma;
	struct qm_sqc *sqc;
	struct qm_cqc *cqc;
	struct qm_eqe *eqe;
	struct qm_aeqe *aeqe;
	dma_addr_t sqc_dma;
	dma_addr_t cqc_dma;
	dma_addr_t eqe_dma;
	dma_addr_t aeqe_dma;

	struct hisi_qm_status status;
	const struct hisi_qm_err_ini *err_ini;
	struct hisi_qm_err_status err_status;
	unsigned long reset_flag;

	struct rw_semaphore qps_lock;
	struct idr qp_idr;
	struct hisi_qp *qp_array;

	struct mutex mailbox_lock;

	const struct hisi_qm_hw_ops *ops;

	struct qm_debug debug;

	u32 error_mask;

	struct workqueue_struct *wq;
	struct work_struct work;
	struct work_struct rst_work;

	const char *algs;
	bool use_sva;
	bool is_frozen;
	resource_size_t phys_base;
	resource_size_t phys_size;
	struct uacce_device *uacce;
};

struct hisi_qp_status {
	atomic_t used;
	u16 sq_tail;
	u16 cq_head;
	bool cqc_phase;
	atomic_t flags;
};

struct hisi_qp_ops {
	int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
};

struct hisi_qp {
	u32 qp_id;
	u8 alg_type;
	u8 req_type;

	struct qm_dma qdma;
	void *sqe;
	struct qm_cqe *cqe;
	dma_addr_t sqe_dma;
	dma_addr_t cqe_dma;

	struct hisi_qp_status qp_status;
	struct hisi_qp_ops *hw_ops;
	void *qp_ctx;
	void (*req_cb)(struct hisi_qp *qp, void *data);
	void (*event_cb)(struct hisi_qp *qp);

	struct hisi_qm *qm;
	bool is_resetting;
	u16 pasid;
	struct uacce_queue *uacce_q;
};

static inline int q_num_set(const char *val, const struct kernel_param *kp,
			    unsigned int device)
{
	struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
					      device, NULL);
	u32 n, q_num;
	int ret;

	if (!val)
		return -EINVAL;

	if (!pdev) {
		q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
		pr_info("No device found currently, suppose queue number is %d\n",
			q_num);
	} else {
		if (pdev->revision == QM_HW_V1)
			q_num = QM_QNUM_V1;
		else
			q_num = QM_QNUM_V2;
	}

	ret = kstrtou32(val, 10, &n);
	if (ret || !n || n > q_num)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret < 0)
		return ret;

	if (n > QM_MAX_VFS_NUM_V2)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
{
	INIT_LIST_HEAD(&qm_list->list);
	mutex_init(&qm_list->lock);
}

int hisi_qm_init(struct hisi_qm *qm);
void hisi_qm_uninit(struct hisi_qm *qm);
int hisi_qm_start(struct hisi_qm *qm);
int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
int hisi_qm_stop_qp(struct hisi_qp *qp);
void hisi_qm_release_qp(struct hisi_qp *qp);
int hisi_qp_send(struct hisi_qp *qp, const void *msg);
int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
int hisi_qm_debug_init(struct hisi_qm *qm);
enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
void hisi_qm_dev_err_init(struct hisi_qm *qm);
void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
					  pci_channel_state_t state);
pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
void hisi_qm_reset_prepare(struct pci_dev *pdev);
void hisi_qm_reset_done(struct pci_dev *pdev);

struct hisi_acc_sgl_pool;
struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
	struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
	u32 index, dma_addr_t *hw_sgl_dma);
void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
			   struct hisi_acc_hw_sgl *hw_sgl);
struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
						   u32 count, u32 sge_nr);
void hisi_acc_free_sgl_pool(struct device *dev,
			    struct hisi_acc_sgl_pool *pool);
int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
			   u8 alg_type, int node, struct hisi_qp **qps);
void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
void hisi_qm_dev_shutdown(struct pci_dev *pdev);
void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
#endif
Commit	Line	Data
263c9959 ZW	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (c) 2019 HiSilicon Limited. */
	3	#ifndef HISI_ACC_QM_H
	4	#define HISI_ACC_QM_H
	5
	6	#include <linux/bitfield.h>
	7	#include <linux/iopoll.h>
	8	#include <linux/module.h>
	9	#include <linux/pci.h>
	10
20b291f5 ST	11	#define QM_QNUM_V1 4096
20b291f5 ST	12	#define QM_QNUM_V2 1024
35ee280f HF	13	#define QM_MAX_VFS_NUM_V2 63
35ee280f HF	14
263c9959 ZW	15	/* qm user domain */
	16	#define QM_ARUSER_M_CFG_1 0x100088
	17	#define AXUSER_SNOOP_ENABLE BIT(30)
	18	#define AXUSER_CMD_TYPE GENMASK(14, 12)
	19	#define AXUSER_CMD_SMMU_NORMAL 1
	20	#define AXUSER_NS BIT(6)
	21	#define AXUSER_NO BIT(5)
	22	#define AXUSER_FP BIT(4)
	23	#define AXUSER_SSV BIT(0)
	24	#define AXUSER_BASE (AXUSER_SNOOP_ENABLE \| \
	25	FIELD_PREP(AXUSER_CMD_TYPE, \
	26	AXUSER_CMD_SMMU_NORMAL) \| \
	27	AXUSER_NS \| AXUSER_NO \| AXUSER_FP)
	28	#define QM_ARUSER_M_CFG_ENABLE 0x100090
	29	#define ARUSER_M_CFG_ENABLE 0xfffffffe
	30	#define QM_AWUSER_M_CFG_1 0x100098
	31	#define QM_AWUSER_M_CFG_ENABLE 0x1000a0
	32	#define AWUSER_M_CFG_ENABLE 0xfffffffe
	33	#define QM_WUSER_M_CFG_ENABLE 0x1000a8
	34	#define WUSER_M_CFG_ENABLE 0xffffffff
	35
	36	/* qm cache */
	37	#define QM_CACHE_CTL 0x100050
	38	#define SQC_CACHE_ENABLE BIT(0)
	39	#define CQC_CACHE_ENABLE BIT(1)
	40	#define SQC_CACHE_WB_ENABLE BIT(4)
	41	#define SQC_CACHE_WB_THRD GENMASK(10, 5)
	42	#define CQC_CACHE_WB_ENABLE BIT(11)
	43	#define CQC_CACHE_WB_THRD GENMASK(17, 12)
	44	#define QM_AXI_M_CFG 0x1000ac
	45	#define AXI_M_CFG 0xffff
	46	#define QM_AXI_M_CFG_ENABLE 0x1000b0
d0228aeb	47	#define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
263c9959 ZW	48	#define AXI_M_CFG_ENABLE 0xffffffff
	49	#define QM_PEH_AXUSER_CFG 0x1000cc
	50	#define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
	51	#define PEH_AXUSER_CFG 0x401001
	52	#define PEH_AXUSER_CFG_ENABLE 0xffffffff
	53
72c7a68d ZW	54	#define QM_DFX_MB_CNT_VF 0x104010
	55	#define QM_DFX_DB_CNT_VF 0x104020
	56	#define QM_DFX_SQE_CNT_VF_SQN 0x104030
	57	#define QM_DFX_CQE_CNT_VF_CQN 0x104040
	58	#define QM_DFX_QN_SHIFT 16
	59	#define CURRENT_FUN_MASK GENMASK(5, 0)
	60	#define CURRENT_Q_MASK GENMASK(31, 16)
263c9959 ZW	61
	62	#define QM_AXI_RRESP BIT(0)
	63	#define QM_AXI_BRESP BIT(1)
	64	#define QM_ECC_MBIT BIT(2)
	65	#define QM_ECC_1BIT BIT(3)
	66	#define QM_ACC_GET_TASK_TIMEOUT BIT(4)
	67	#define QM_ACC_DO_TASK_TIMEOUT BIT(5)
	68	#define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
	69	#define QM_SQ_CQ_VF_INVALID BIT(7)
	70	#define QM_CQ_VF_INVALID BIT(8)
	71	#define QM_SQ_VF_INVALID BIT(9)
	72	#define QM_DB_TIMEOUT BIT(10)
	73	#define QM_OF_FIFO_OF BIT(11)
	74	#define QM_DB_RANDOM_INVALID BIT(12)
	75
	76	#define QM_BASE_NFE (QM_AXI_RRESP \| QM_AXI_BRESP \| QM_ECC_MBIT \| \
	77	QM_ACC_GET_TASK_TIMEOUT \| QM_DB_TIMEOUT \| \
3176637a	78	QM_OF_FIFO_OF \| QM_DB_RANDOM_INVALID)
263c9959 ZW	79	#define QM_BASE_CE QM_ECC_1BIT
	80
	81	#define QM_Q_DEPTH 1024
	82
f081fda2 ST	83	#define HISI_ACC_SGL_SGE_NR_MAX 255
f081fda2 ST	84
9e00df71 ZG	85	/* page number for queue file region */
	86	#define QM_DOORBELL_PAGE_NR 1
	87
b67202e8 ZW	88	enum qm_stop_reason {
	89	QM_NORMAL,
	90	QM_SOFT_RESET,
	91	QM_FLR,
	92	};
	93
	94	enum qm_state {
	95	QM_INIT = 0,
	96	QM_START,
	97	QM_CLOSE,
	98	QM_STOP,
	99	};
	100
263c9959	101	enum qp_state {
b67202e8 ZW	102	QP_INIT = 1,
b67202e8 ZW	103	QP_START,
263c9959	104	QP_STOP,
b67202e8	105	QP_CLOSE,
263c9959 ZW	106	};
	107
	108	enum qm_hw_ver {
	109	QM_HW_UNKNOWN = -1,
	110	QM_HW_V1 = 0x20,
	111	QM_HW_V2 = 0x21,
58ca0060	112	QM_HW_V3 = 0x30,
263c9959 ZW	113	};
	114
	115	enum qm_fun_type {
	116	QM_HW_PF,
79e09f30	117	QM_HW_VF,
263c9959 ZW	118	};
263c9959 ZW	119
72c7a68d ZW	120	enum qm_debug_file {
	121	CURRENT_Q,
	122	CLEAR_ENABLE,
	123	DEBUG_FILE_NUM,
	124	};
	125
85026525 LL	126	struct qm_dfx {
	127	atomic64_t err_irq_cnt;
	128	atomic64_t aeq_irq_cnt;
	129	atomic64_t abnormal_irq_cnt;
	130	atomic64_t create_qp_err_cnt;
	131	atomic64_t mb_err_cnt;
	132	};
	133
72c7a68d ZW	134	struct debugfs_file {
	135	enum qm_debug_file index;
	136	struct mutex lock;
	137	struct qm_debug *debug;
	138	};
	139
	140	struct qm_debug {
	141	u32 curr_qm_qp_num;
c31dc9fe ST	142	u32 sqe_mask_offset;
c31dc9fe ST	143	u32 sqe_mask_len;
85026525	144	struct qm_dfx dfx;
72c7a68d ZW	145	struct dentry *debug_root;
	146	struct dentry *qm_d;
	147	struct debugfs_file files[DEBUG_FILE_NUM];
	148	};
	149
263c9959 ZW	150	struct qm_dma {
	151	void *va;
	152	dma_addr_t dma;
	153	size_t size;
	154	};
	155
	156	struct hisi_qm_status {
	157	u32 eq_head;
	158	bool eqc_phase;
	159	u32 aeq_head;
	160	bool aeqc_phase;
b67202e8 ZW	161	atomic_t flags;
b67202e8 ZW	162	int stop_reason;
263c9959 ZW	163	};
263c9959 ZW	164
eaebf4c3 ST	165	struct hisi_qm;
	166
	167	struct hisi_qm_err_info {
6c6dd580 ST	168	char *acpi_rst;
	169	u32 msi_wr_port;
	170	u32 ecc_2bits_mask;
eaebf4c3 ST	171	u32 ce;
	172	u32 nfe;
	173	u32 fe;
eaebf4c3 ST	174	};
eaebf4c3 ST	175
6c6dd580 ST	176	struct hisi_qm_err_status {
	177	u32 is_qm_ecc_mbit;
	178	u32 is_dev_ecc_mbit;
	179	};
	180
eaebf4c3	181	struct hisi_qm_err_ini {
6c6dd580	182	int (hw_init)(struct hisi_qm qm);
eaebf4c3 ST	183	void (hw_err_enable)(struct hisi_qm qm);
eaebf4c3 ST	184	void (hw_err_disable)(struct hisi_qm qm);
f826e6ef	185	u32 (get_dev_hw_err_status)(struct hisi_qm qm);
6c6dd580 ST	186	void (clear_dev_hw_err_status)(struct hisi_qm qm, u32 err_sts);
	187	void (open_axi_master_ooo)(struct hisi_qm qm);
	188	void (close_axi_master_ooo)(struct hisi_qm qm);
f826e6ef	189	void (log_dev_hw_err)(struct hisi_qm qm, u32 err_sts);
eaebf4c3 ST	190	struct hisi_qm_err_info err_info;
	191	};
	192
3f1ec97a WQ	193	struct hisi_qm_list {
	194	struct mutex lock;
	195	struct list_head list;
3d29e98d YS	196	int (*register_to_crypto)(void);
3d29e98d YS	197	void (*unregister_from_crypto)(void);
3f1ec97a WQ	198	};
3f1ec97a WQ	199
263c9959 ZW	200	struct hisi_qm {
263c9959 ZW	201	enum qm_hw_ver ver;
79e09f30	202	enum qm_fun_type fun_type;
263c9959 ZW	203	const char *dev_name;
	204	struct pci_dev *pdev;
	205	void __iomem *io_base;
	206	u32 sqe_size;
	207	u32 qp_base;
	208	u32 qp_num;
700f7d0d	209	u32 qp_in_used;
263c9959	210	u32 ctrl_qp_num;
619e464a	211	u32 vfs_num;
3f1ec97a	212	struct list_head list;
6c6dd580	213	struct hisi_qm_list *qm_list;
263c9959 ZW	214
	215	struct qm_dma qdma;
	216	struct qm_sqc *sqc;
	217	struct qm_cqc *cqc;
	218	struct qm_eqe *eqe;
	219	struct qm_aeqe *aeqe;
	220	dma_addr_t sqc_dma;
	221	dma_addr_t cqc_dma;
	222	dma_addr_t eqe_dma;
	223	dma_addr_t aeqe_dma;
	224
	225	struct hisi_qm_status status;
eaebf4c3	226	const struct hisi_qm_err_ini *err_ini;
6c6dd580 ST	227	struct hisi_qm_err_status err_status;
6c6dd580 ST	228	unsigned long reset_flag;
263c9959	229
b67202e8	230	struct rw_semaphore qps_lock;
5308f660 WQ	231	struct idr qp_idr;
5308f660 WQ	232	struct hisi_qp *qp_array;
263c9959 ZW	233
	234	struct mutex mailbox_lock;
	235
	236	const struct hisi_qm_hw_ops *ops;
	237
72c7a68d ZW	238	struct qm_debug debug;
72c7a68d ZW	239
263c9959	240	u32 error_mask;
263c9959	241
57ca8124 ST	242	struct workqueue_struct *wq;
57ca8124 ST	243	struct work_struct work;
dbdc1ec3	244	struct work_struct rst_work;
57ca8124	245
9e00df71	246	const char *algs;
9e00df71	247	bool use_sva;
daa31783	248	bool is_frozen;
9e00df71 ZG	249	resource_size_t phys_base;
	250	resource_size_t phys_size;
	251	struct uacce_device *uacce;
263c9959 ZW	252	};
	253
	254	struct hisi_qp_status {
	255	atomic_t used;
	256	u16 sq_tail;
	257	u16 cq_head;
	258	bool cqc_phase;
b67202e8	259	atomic_t flags;
263c9959 ZW	260	};
	261
	262	struct hisi_qp_ops {
	263	int (fill_sqe)(void sqe, void q_parm, void d_parm);
	264	};
	265
	266	struct hisi_qp {
	267	u32 qp_id;
	268	u8 alg_type;
	269	u8 req_type;
	270
	271	struct qm_dma qdma;
	272	void *sqe;
	273	struct qm_cqe *cqe;
	274	dma_addr_t sqe_dma;
	275	dma_addr_t cqe_dma;
	276
	277	struct hisi_qp_status qp_status;
	278	struct hisi_qp_ops *hw_ops;
	279	void *qp_ctx;
	280	void (req_cb)(struct hisi_qp qp, void *data);
9e00df71	281	void (event_cb)(struct hisi_qp qp);
263c9959 ZW	282
263c9959 ZW	283	struct hisi_qm *qm;
b67202e8	284	bool is_resetting;
9e00df71 ZG	285	u16 pasid;
9e00df71 ZG	286	struct uacce_queue *uacce_q;
263c9959 ZW	287	};
263c9959 ZW	288
20b291f5 ST	289	static inline int q_num_set(const char val, const struct kernel_param kp,
	290	unsigned int device)
	291	{
	292	struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
	293	device, NULL);
	294	u32 n, q_num;
20b291f5 ST	295	int ret;
	296
	297	if (!val)
	298	return -EINVAL;
	299
	300	if (!pdev) {
	301	q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
	302	pr_info("No device found currently, suppose queue number is %d\n",
	303	q_num);
	304	} else {
58ca0060	305	if (pdev->revision == QM_HW_V1)
20b291f5	306	q_num = QM_QNUM_V1;
58ca0060	307	else
20b291f5	308	q_num = QM_QNUM_V2;
20b291f5 ST	309	}
	310
	311	ret = kstrtou32(val, 10, &n);
	312	if (ret \|\| !n \|\| n > q_num)
	313	return -EINVAL;
	314
	315	return param_set_int(val, kp);
	316	}
	317
35ee280f HF	318	static inline int vfs_num_set(const char val, const struct kernel_param kp)
	319	{
	320	u32 n;
	321	int ret;
	322
	323	if (!val)
	324	return -EINVAL;
	325
	326	ret = kstrtou32(val, 10, &n);
	327	if (ret < 0)
	328	return ret;
	329
	330	if (n > QM_MAX_VFS_NUM_V2)
	331	return -EINVAL;
	332
	333	return param_set_int(val, kp);
	334	}
	335
3f1ec97a WQ	336	static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
	337	{
	338	INIT_LIST_HEAD(&qm_list->list);
	339	mutex_init(&qm_list->lock);
	340	}
	341
263c9959 ZW	342	int hisi_qm_init(struct hisi_qm *qm);
	343	void hisi_qm_uninit(struct hisi_qm *qm);
	344	int hisi_qm_start(struct hisi_qm *qm);
e88dd6e1	345	int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
263c9959 ZW	346	struct hisi_qp hisi_qm_create_qp(struct hisi_qm qm, u8 alg_type);
	347	int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
	348	int hisi_qm_stop_qp(struct hisi_qp *qp);
	349	void hisi_qm_release_qp(struct hisi_qp *qp);
	350	int hisi_qp_send(struct hisi_qp qp, const void msg);
700f7d0d	351	int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
79e09f30	352	int hisi_qm_get_vft(struct hisi_qm qm, u32 base, u32 *number);
79e09f30	353	int hisi_qm_debug_init(struct hisi_qm *qm);
263c9959	354	enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
72c7a68d	355	void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
cd1b7ae3	356	int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
daa31783	357	int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
cd1b7ae3	358	int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
eaebf4c3 ST	359	void hisi_qm_dev_err_init(struct hisi_qm *qm);
eaebf4c3 ST	360	void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
f826e6ef ST	361	pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
f826e6ef ST	362	pci_channel_state_t state);
6c6dd580	363	pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
7ce396fa ST	364	void hisi_qm_reset_prepare(struct pci_dev *pdev);
7ce396fa ST	365	void hisi_qm_reset_done(struct pci_dev *pdev);
48c1cd40 ZW	366
	367	struct hisi_acc_sgl_pool;
	368	struct hisi_acc_hw_sgl hisi_acc_sg_buf_map_to_hw_sgl(struct device dev,
	369	struct scatterlist sgl, struct hisi_acc_sgl_pool pool,
	370	u32 index, dma_addr_t *hw_sgl_dma);
	371	void hisi_acc_sg_buf_unmap(struct device dev, struct scatterlist sgl,
	372	struct hisi_acc_hw_sgl *hw_sgl);
	373	struct hisi_acc_sgl_pool hisi_acc_create_sgl_pool(struct device dev,
	374	u32 count, u32 sge_nr);
	375	void hisi_acc_free_sgl_pool(struct device *dev,
	376	struct hisi_acc_sgl_pool *pool);
3f1ec97a WQ	377	int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
	378	u8 alg_type, int node, struct hisi_qp **qps);
	379	void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
64dfe495	380	void hisi_qm_dev_shutdown(struct pci_dev *pdev);
daa31783	381	void hisi_qm_wait_task_finish(struct hisi_qm qm, struct hisi_qm_list qm_list);
3d29e98d YS	382	int hisi_qm_alg_register(struct hisi_qm qm, struct hisi_qm_list qm_list);
3d29e98d YS	383	void hisi_qm_alg_unregister(struct hisi_qm qm, struct hisi_qm_list qm_list);
263c9959	384	#endif