[linux-2.6-block.git] / drivers / crypto / hisilicon / qm.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2019 HiSilicon Limited. */
#ifndef HISI_ACC_QM_H
#define HISI_ACC_QM_H

#include <linux/bitfield.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/pci.h>

/* qm user domain */
#define QM_ARUSER_M_CFG_1		0x100088
#define AXUSER_SNOOP_ENABLE		BIT(30)
#define AXUSER_CMD_TYPE			GENMASK(14, 12)
#define AXUSER_CMD_SMMU_NORMAL		1
#define AXUSER_NS			BIT(6)
#define AXUSER_NO			BIT(5)
#define AXUSER_FP			BIT(4)
#define AXUSER_SSV			BIT(0)
#define AXUSER_BASE			(AXUSER_SNOOP_ENABLE |		\
					FIELD_PREP(AXUSER_CMD_TYPE,	\
					AXUSER_CMD_SMMU_NORMAL) |	\
					AXUSER_NS | AXUSER_NO | AXUSER_FP)
#define QM_ARUSER_M_CFG_ENABLE		0x100090
#define ARUSER_M_CFG_ENABLE		0xfffffffe
#define QM_AWUSER_M_CFG_1		0x100098
#define QM_AWUSER_M_CFG_ENABLE		0x1000a0
#define AWUSER_M_CFG_ENABLE		0xfffffffe
#define QM_WUSER_M_CFG_ENABLE		0x1000a8
#define WUSER_M_CFG_ENABLE		0xffffffff

/* qm cache */
#define QM_CACHE_CTL			0x100050
#define SQC_CACHE_ENABLE		BIT(0)
#define CQC_CACHE_ENABLE		BIT(1)
#define SQC_CACHE_WB_ENABLE		BIT(4)
#define SQC_CACHE_WB_THRD		GENMASK(10, 5)
#define CQC_CACHE_WB_ENABLE		BIT(11)
#define CQC_CACHE_WB_THRD		GENMASK(17, 12)
#define QM_AXI_M_CFG			0x1000ac
#define AXI_M_CFG			0xffff
#define QM_AXI_M_CFG_ENABLE		0x1000b0
#define AXI_M_CFG_ENABLE		0xffffffff
#define QM_PEH_AXUSER_CFG		0x1000cc
#define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
#define PEH_AXUSER_CFG			0x401001
#define PEH_AXUSER_CFG_ENABLE		0xffffffff

#define QM_DFX_MB_CNT_VF		0x104010
#define QM_DFX_DB_CNT_VF		0x104020
#define QM_DFX_SQE_CNT_VF_SQN		0x104030
#define QM_DFX_CQE_CNT_VF_CQN		0x104040
#define QM_DFX_QN_SHIFT			16
#define CURRENT_FUN_MASK		GENMASK(5, 0)
#define CURRENT_Q_MASK			GENMASK(31, 16)

#define QM_AXI_RRESP			BIT(0)
#define QM_AXI_BRESP			BIT(1)
#define QM_ECC_MBIT			BIT(2)
#define QM_ECC_1BIT			BIT(3)
#define QM_ACC_GET_TASK_TIMEOUT		BIT(4)
#define QM_ACC_DO_TASK_TIMEOUT		BIT(5)
#define QM_ACC_WB_NOT_READY_TIMEOUT	BIT(6)
#define QM_SQ_CQ_VF_INVALID		BIT(7)
#define QM_CQ_VF_INVALID		BIT(8)
#define QM_SQ_VF_INVALID		BIT(9)
#define QM_DB_TIMEOUT			BIT(10)
#define QM_OF_FIFO_OF			BIT(11)
#define QM_DB_RANDOM_INVALID		BIT(12)

#define QM_BASE_NFE	(QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
			 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
			 QM_OF_FIFO_OF)
#define QM_BASE_CE			QM_ECC_1BIT

#define QM_Q_DEPTH			1024

#define HISI_ACC_SGL_SGE_NR_MAX		255

enum qp_state {
	QP_STOP,
};

enum qm_hw_ver {
	QM_HW_UNKNOWN = -1,
	QM_HW_V1 = 0x20,
	QM_HW_V2 = 0x21,
};

enum qm_fun_type {
	QM_HW_PF,
	QM_HW_VF,
};

enum qm_debug_file {
	CURRENT_Q,
	CLEAR_ENABLE,
	DEBUG_FILE_NUM,
};

struct debugfs_file {
	enum qm_debug_file index;
	struct mutex lock;
	struct qm_debug *debug;
};

struct qm_debug {
	u32 curr_qm_qp_num;
	struct dentry *debug_root;
	struct dentry *qm_d;
	struct debugfs_file files[DEBUG_FILE_NUM];
};

struct qm_dma {
	void *va;
	dma_addr_t dma;
	size_t size;
};

struct hisi_qm_status {
	u32 eq_head;
	bool eqc_phase;
	u32 aeq_head;
	bool aeqc_phase;
	unsigned long flags;
};

struct hisi_qm;

struct hisi_qm_err_info {
	u32 ce;
	u32 nfe;
	u32 fe;
	u32 msi;
};

struct hisi_qm_err_ini {
	void (*hw_err_enable)(struct hisi_qm *qm);
	void (*hw_err_disable)(struct hisi_qm *qm);
	u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
	void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
	struct hisi_qm_err_info err_info;
};

struct hisi_qm {
	enum qm_hw_ver ver;
	enum qm_fun_type fun_type;
	const char *dev_name;
	struct pci_dev *pdev;
	void __iomem *io_base;
	u32 sqe_size;
	u32 qp_base;
	u32 qp_num;
	u32 qp_in_used;
	u32 ctrl_qp_num;

	struct qm_dma qdma;
	struct qm_sqc *sqc;
	struct qm_cqc *cqc;
	struct qm_eqe *eqe;
	struct qm_aeqe *aeqe;
	dma_addr_t sqc_dma;
	dma_addr_t cqc_dma;
	dma_addr_t eqe_dma;
	dma_addr_t aeqe_dma;

	struct hisi_qm_status status;
	const struct hisi_qm_err_ini *err_ini;

	rwlock_t qps_lock;
	unsigned long *qp_bitmap;
	struct hisi_qp **qp_array;

	struct mutex mailbox_lock;

	const struct hisi_qm_hw_ops *ops;

	struct qm_debug debug;

	u32 error_mask;
	u32 msi_mask;

	bool use_dma_api;
};

struct hisi_qp_status {
	atomic_t used;
	u16 sq_tail;
	u16 cq_head;
	bool cqc_phase;
	unsigned long flags;
};

struct hisi_qp_ops {
	int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
};

struct hisi_qp {
	u32 qp_id;
	u8 alg_type;
	u8 req_type;

	struct qm_dma qdma;
	void *sqe;
	struct qm_cqe *cqe;
	dma_addr_t sqe_dma;
	dma_addr_t cqe_dma;

	struct hisi_qp_status qp_status;
	struct hisi_qp_ops *hw_ops;
	void *qp_ctx;
	void (*req_cb)(struct hisi_qp *qp, void *data);
	struct work_struct work;
	struct workqueue_struct *wq;

	struct hisi_qm *qm;
};

int hisi_qm_init(struct hisi_qm *qm);
void hisi_qm_uninit(struct hisi_qm *qm);
int hisi_qm_start(struct hisi_qm *qm);
int hisi_qm_stop(struct hisi_qm *qm);
struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
int hisi_qm_stop_qp(struct hisi_qp *qp);
void hisi_qm_release_qp(struct hisi_qp *qp);
int hisi_qp_send(struct hisi_qp *qp, const void *msg);
int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
int hisi_qm_debug_init(struct hisi_qm *qm);
enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
void hisi_qm_dev_err_init(struct hisi_qm *qm);
void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
					  pci_channel_state_t state);

struct hisi_acc_sgl_pool;
struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
	struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
	u32 index, dma_addr_t *hw_sgl_dma);
void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
			   struct hisi_acc_hw_sgl *hw_sgl);
struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
						   u32 count, u32 sge_nr);
void hisi_acc_free_sgl_pool(struct device *dev,
			    struct hisi_acc_sgl_pool *pool);
#endif
Commit	Line	Data
263c9959 ZW	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (c) 2019 HiSilicon Limited. */
	3	#ifndef HISI_ACC_QM_H
	4	#define HISI_ACC_QM_H
	5
	6	#include <linux/bitfield.h>
	7	#include <linux/iopoll.h>
	8	#include <linux/module.h>
	9	#include <linux/pci.h>
	10
	11	/* qm user domain */
	12	#define QM_ARUSER_M_CFG_1 0x100088
	13	#define AXUSER_SNOOP_ENABLE BIT(30)
	14	#define AXUSER_CMD_TYPE GENMASK(14, 12)
	15	#define AXUSER_CMD_SMMU_NORMAL 1
	16	#define AXUSER_NS BIT(6)
	17	#define AXUSER_NO BIT(5)
	18	#define AXUSER_FP BIT(4)
	19	#define AXUSER_SSV BIT(0)
	20	#define AXUSER_BASE (AXUSER_SNOOP_ENABLE \| \
	21	FIELD_PREP(AXUSER_CMD_TYPE, \
	22	AXUSER_CMD_SMMU_NORMAL) \| \
	23	AXUSER_NS \| AXUSER_NO \| AXUSER_FP)
	24	#define QM_ARUSER_M_CFG_ENABLE 0x100090
	25	#define ARUSER_M_CFG_ENABLE 0xfffffffe
	26	#define QM_AWUSER_M_CFG_1 0x100098
	27	#define QM_AWUSER_M_CFG_ENABLE 0x1000a0
	28	#define AWUSER_M_CFG_ENABLE 0xfffffffe
	29	#define QM_WUSER_M_CFG_ENABLE 0x1000a8
	30	#define WUSER_M_CFG_ENABLE 0xffffffff
	31
	32	/* qm cache */
	33	#define QM_CACHE_CTL 0x100050
	34	#define SQC_CACHE_ENABLE BIT(0)
	35	#define CQC_CACHE_ENABLE BIT(1)
	36	#define SQC_CACHE_WB_ENABLE BIT(4)
	37	#define SQC_CACHE_WB_THRD GENMASK(10, 5)
	38	#define CQC_CACHE_WB_ENABLE BIT(11)
	39	#define CQC_CACHE_WB_THRD GENMASK(17, 12)
	40	#define QM_AXI_M_CFG 0x1000ac
	41	#define AXI_M_CFG 0xffff
	42	#define QM_AXI_M_CFG_ENABLE 0x1000b0
	43	#define AXI_M_CFG_ENABLE 0xffffffff
	44	#define QM_PEH_AXUSER_CFG 0x1000cc
	45	#define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
	46	#define PEH_AXUSER_CFG 0x401001
	47	#define PEH_AXUSER_CFG_ENABLE 0xffffffff
	48
72c7a68d ZW	49	#define QM_DFX_MB_CNT_VF 0x104010
	50	#define QM_DFX_DB_CNT_VF 0x104020
	51	#define QM_DFX_SQE_CNT_VF_SQN 0x104030
	52	#define QM_DFX_CQE_CNT_VF_CQN 0x104040
	53	#define QM_DFX_QN_SHIFT 16
	54	#define CURRENT_FUN_MASK GENMASK(5, 0)
	55	#define CURRENT_Q_MASK GENMASK(31, 16)
263c9959 ZW	56
	57	#define QM_AXI_RRESP BIT(0)
	58	#define QM_AXI_BRESP BIT(1)
	59	#define QM_ECC_MBIT BIT(2)
	60	#define QM_ECC_1BIT BIT(3)
	61	#define QM_ACC_GET_TASK_TIMEOUT BIT(4)
	62	#define QM_ACC_DO_TASK_TIMEOUT BIT(5)
	63	#define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
	64	#define QM_SQ_CQ_VF_INVALID BIT(7)
	65	#define QM_CQ_VF_INVALID BIT(8)
	66	#define QM_SQ_VF_INVALID BIT(9)
	67	#define QM_DB_TIMEOUT BIT(10)
	68	#define QM_OF_FIFO_OF BIT(11)
	69	#define QM_DB_RANDOM_INVALID BIT(12)
	70
	71	#define QM_BASE_NFE (QM_AXI_RRESP \| QM_AXI_BRESP \| QM_ECC_MBIT \| \
	72	QM_ACC_GET_TASK_TIMEOUT \| QM_DB_TIMEOUT \| \
	73	QM_OF_FIFO_OF)
	74	#define QM_BASE_CE QM_ECC_1BIT
	75
	76	#define QM_Q_DEPTH 1024
	77
f081fda2 ST	78	#define HISI_ACC_SGL_SGE_NR_MAX 255
f081fda2 ST	79
263c9959 ZW	80	enum qp_state {
	81	QP_STOP,
	82	};
	83
	84	enum qm_hw_ver {
	85	QM_HW_UNKNOWN = -1,
	86	QM_HW_V1 = 0x20,
	87	QM_HW_V2 = 0x21,
	88	};
	89
	90	enum qm_fun_type {
	91	QM_HW_PF,
79e09f30	92	QM_HW_VF,
263c9959 ZW	93	};
263c9959 ZW	94
72c7a68d ZW	95	enum qm_debug_file {
	96	CURRENT_Q,
	97	CLEAR_ENABLE,
	98	DEBUG_FILE_NUM,
	99	};
	100
	101	struct debugfs_file {
	102	enum qm_debug_file index;
	103	struct mutex lock;
	104	struct qm_debug *debug;
	105	};
	106
	107	struct qm_debug {
	108	u32 curr_qm_qp_num;
	109	struct dentry *debug_root;
	110	struct dentry *qm_d;
	111	struct debugfs_file files[DEBUG_FILE_NUM];
	112	};
	113
263c9959 ZW	114	struct qm_dma {
	115	void *va;
	116	dma_addr_t dma;
	117	size_t size;
	118	};
	119
	120	struct hisi_qm_status {
	121	u32 eq_head;
	122	bool eqc_phase;
	123	u32 aeq_head;
	124	bool aeqc_phase;
	125	unsigned long flags;
	126	};
	127
eaebf4c3 ST	128	struct hisi_qm;
	129
	130	struct hisi_qm_err_info {
	131	u32 ce;
	132	u32 nfe;
	133	u32 fe;
	134	u32 msi;
	135	};
	136
	137	struct hisi_qm_err_ini {
	138	void (hw_err_enable)(struct hisi_qm qm);
	139	void (hw_err_disable)(struct hisi_qm qm);
f826e6ef ST	140	u32 (get_dev_hw_err_status)(struct hisi_qm qm);
f826e6ef ST	141	void (log_dev_hw_err)(struct hisi_qm qm, u32 err_sts);
eaebf4c3 ST	142	struct hisi_qm_err_info err_info;
	143	};
	144
263c9959 ZW	145	struct hisi_qm {
263c9959 ZW	146	enum qm_hw_ver ver;
79e09f30	147	enum qm_fun_type fun_type;
263c9959 ZW	148	const char *dev_name;
	149	struct pci_dev *pdev;
	150	void __iomem *io_base;
	151	u32 sqe_size;
	152	u32 qp_base;
	153	u32 qp_num;
700f7d0d	154	u32 qp_in_used;
263c9959 ZW	155	u32 ctrl_qp_num;
	156
	157	struct qm_dma qdma;
	158	struct qm_sqc *sqc;
	159	struct qm_cqc *cqc;
	160	struct qm_eqe *eqe;
	161	struct qm_aeqe *aeqe;
	162	dma_addr_t sqc_dma;
	163	dma_addr_t cqc_dma;
	164	dma_addr_t eqe_dma;
	165	dma_addr_t aeqe_dma;
	166
	167	struct hisi_qm_status status;
eaebf4c3	168	const struct hisi_qm_err_ini *err_ini;
263c9959 ZW	169
	170	rwlock_t qps_lock;
	171	unsigned long *qp_bitmap;
	172	struct hisi_qp **qp_array;
	173
	174	struct mutex mailbox_lock;
	175
	176	const struct hisi_qm_hw_ops *ops;
	177
72c7a68d ZW	178	struct qm_debug debug;
72c7a68d ZW	179
263c9959 ZW	180	u32 error_mask;
	181	u32 msi_mask;
	182
	183	bool use_dma_api;
	184	};
	185
	186	struct hisi_qp_status {
	187	atomic_t used;
	188	u16 sq_tail;
	189	u16 cq_head;
	190	bool cqc_phase;
	191	unsigned long flags;
	192	};
	193
	194	struct hisi_qp_ops {
	195	int (fill_sqe)(void sqe, void q_parm, void d_parm);
	196	};
	197
	198	struct hisi_qp {
	199	u32 qp_id;
	200	u8 alg_type;
	201	u8 req_type;
	202
	203	struct qm_dma qdma;
	204	void *sqe;
	205	struct qm_cqe *cqe;
	206	dma_addr_t sqe_dma;
	207	dma_addr_t cqe_dma;
	208
	209	struct hisi_qp_status qp_status;
	210	struct hisi_qp_ops *hw_ops;
	211	void *qp_ctx;
	212	void (req_cb)(struct hisi_qp qp, void *data);
	213	struct work_struct work;
	214	struct workqueue_struct *wq;
	215
	216	struct hisi_qm *qm;
	217	};
	218
	219	int hisi_qm_init(struct hisi_qm *qm);
	220	void hisi_qm_uninit(struct hisi_qm *qm);
	221	int hisi_qm_start(struct hisi_qm *qm);
	222	int hisi_qm_stop(struct hisi_qm *qm);
	223	struct hisi_qp hisi_qm_create_qp(struct hisi_qm qm, u8 alg_type);
	224	int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
	225	int hisi_qm_stop_qp(struct hisi_qp *qp);
	226	void hisi_qm_release_qp(struct hisi_qp *qp);
	227	int hisi_qp_send(struct hisi_qp qp, const void msg);
700f7d0d	228	int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
79e09f30	229	int hisi_qm_get_vft(struct hisi_qm qm, u32 base, u32 *number);
263c9959	230	int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
79e09f30	231	int hisi_qm_debug_init(struct hisi_qm *qm);
263c9959	232	enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
72c7a68d	233	void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
eaebf4c3 ST	234	void hisi_qm_dev_err_init(struct hisi_qm *qm);
eaebf4c3 ST	235	void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
f826e6ef ST	236	pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
f826e6ef ST	237	pci_channel_state_t state);
48c1cd40 ZW	238
	239	struct hisi_acc_sgl_pool;
	240	struct hisi_acc_hw_sgl hisi_acc_sg_buf_map_to_hw_sgl(struct device dev,
	241	struct scatterlist sgl, struct hisi_acc_sgl_pool pool,
	242	u32 index, dma_addr_t *hw_sgl_dma);
	243	void hisi_acc_sg_buf_unmap(struct device dev, struct scatterlist sgl,
	244	struct hisi_acc_hw_sgl *hw_sgl);
	245	struct hisi_acc_sgl_pool hisi_acc_create_sgl_pool(struct device dev,
	246	u32 count, u32 sge_nr);
	247	void hisi_acc_free_sgl_pool(struct device *dev,
	248	struct hisi_acc_sgl_pool *pool);
263c9959	249	#endif