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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
f7d0561e EP |
2 | /* |
3 | * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru> | |
4 | * All rights reserved. | |
f7d0561e EP |
5 | */ |
6 | ||
7 | #include <linux/kernel.h> | |
8 | #include <linux/module.h> | |
37a8023c | 9 | #include <linux/moduleparam.h> |
f7d0561e EP |
10 | #include <linux/mod_devicetable.h> |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/mm.h> | |
102d49d3 AM |
16 | #include <linux/dma-mapping.h> |
17 | #include <linux/scatterlist.h> | |
f7d0561e EP |
18 | #include <linux/highmem.h> |
19 | #include <linux/crypto.h> | |
fcd06755 PM |
20 | #include <linux/hw_random.h> |
21 | #include <linux/ktime.h> | |
f7d0561e EP |
22 | |
23 | #include <crypto/algapi.h> | |
c3041f9c | 24 | #include <crypto/des.h> |
f7d0561e | 25 | |
37a8023c PM |
26 | static char hifn_pll_ref[sizeof("extNNN")] = "ext"; |
27 | module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444); | |
28 | MODULE_PARM_DESC(hifn_pll_ref, | |
29 | "PLL reference clock (pci[freq] or ext[freq], default ext)"); | |
30 | ||
f7d0561e EP |
31 | static atomic_t hifn_dev_number; |
32 | ||
33 | #define ACRYPTO_OP_DECRYPT 0 | |
34 | #define ACRYPTO_OP_ENCRYPT 1 | |
35 | #define ACRYPTO_OP_HMAC 2 | |
36 | #define ACRYPTO_OP_RNG 3 | |
37 | ||
38 | #define ACRYPTO_MODE_ECB 0 | |
39 | #define ACRYPTO_MODE_CBC 1 | |
40 | #define ACRYPTO_MODE_CFB 2 | |
41 | #define ACRYPTO_MODE_OFB 3 | |
42 | ||
43 | #define ACRYPTO_TYPE_AES_128 0 | |
44 | #define ACRYPTO_TYPE_AES_192 1 | |
45 | #define ACRYPTO_TYPE_AES_256 2 | |
46 | #define ACRYPTO_TYPE_3DES 3 | |
47 | #define ACRYPTO_TYPE_DES 4 | |
48 | ||
49 | #define PCI_VENDOR_ID_HIFN 0x13A3 | |
50 | #define PCI_DEVICE_ID_HIFN_7955 0x0020 | |
51 | #define PCI_DEVICE_ID_HIFN_7956 0x001d | |
52 | ||
53 | /* I/O region sizes */ | |
54 | ||
55 | #define HIFN_BAR0_SIZE 0x1000 | |
56 | #define HIFN_BAR1_SIZE 0x2000 | |
57 | #define HIFN_BAR2_SIZE 0x8000 | |
58 | ||
59 | /* DMA registres */ | |
60 | ||
16f56e8b LC |
61 | #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */ |
62 | #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */ | |
f7d0561e EP |
63 | #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */ |
64 | #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */ | |
65 | #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */ | |
16f56e8b | 66 | #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */ |
f7d0561e EP |
67 | #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */ |
68 | #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */ | |
69 | #define HIFN_CHIP_ID 0x98 /* Chip ID */ | |
70 | ||
71 | /* | |
72 | * Processing Unit Registers (offset from BASEREG0) | |
73 | */ | |
74 | #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ | |
75 | #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ | |
76 | #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ | |
77 | #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ | |
78 | #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ | |
79 | #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ | |
80 | #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ | |
81 | #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ | |
82 | #define HIFN_0_SPACESIZE 0x20 /* Register space size */ | |
83 | ||
84 | /* Processing Unit Control Register (HIFN_0_PUCTRL) */ | |
85 | #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ | |
86 | #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ | |
87 | #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ | |
88 | #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ | |
89 | #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ | |
90 | ||
91 | /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ | |
92 | #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ | |
93 | #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ | |
94 | #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ | |
95 | #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ | |
96 | #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ | |
97 | #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ | |
98 | #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ | |
99 | #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ | |
100 | #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ | |
101 | #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ | |
102 | ||
103 | /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ | |
104 | #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ | |
105 | #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ | |
106 | #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ | |
107 | #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ | |
108 | #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ | |
109 | #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ | |
110 | #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ | |
111 | #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ | |
112 | #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ | |
113 | #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ | |
114 | #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ | |
115 | #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ | |
116 | #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ | |
117 | #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ | |
118 | #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ | |
119 | #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ | |
120 | #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ | |
121 | #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ | |
122 | #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ | |
123 | #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ | |
124 | #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ | |
125 | #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ | |
126 | #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ | |
127 | ||
128 | /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ | |
129 | #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ | |
130 | #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ | |
131 | #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ | |
132 | #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ | |
133 | #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ | |
134 | #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ | |
135 | #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ | |
136 | #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ | |
137 | #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ | |
138 | #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ | |
139 | ||
140 | /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ | |
141 | #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ | |
142 | #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ | |
143 | #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ | |
144 | #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ | |
145 | #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ | |
146 | #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ | |
147 | #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ | |
148 | #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ | |
149 | #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ | |
150 | #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ | |
151 | #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ | |
152 | #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ | |
153 | #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ | |
154 | #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ | |
155 | #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ | |
156 | #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ | |
157 | #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ | |
158 | ||
159 | /* FIFO Status Register (HIFN_0_FIFOSTAT) */ | |
160 | #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ | |
161 | #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ | |
162 | ||
163 | /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ | |
164 | #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */ | |
165 | ||
166 | /* | |
167 | * DMA Interface Registers (offset from BASEREG1) | |
168 | */ | |
169 | #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ | |
170 | #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ | |
171 | #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ | |
172 | #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ | |
173 | #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ | |
174 | #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ | |
175 | #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ | |
176 | #define HIFN_1_PLL 0x4c /* 795x: PLL config */ | |
177 | #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ | |
178 | #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ | |
179 | #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ | |
180 | #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ | |
181 | #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ | |
182 | #define HIFN_1_REVID 0x98 /* Revision ID */ | |
183 | #define HIFN_1_UNLOCK_SECRET1 0xf4 | |
184 | #define HIFN_1_UNLOCK_SECRET2 0xfc | |
185 | #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ | |
186 | #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ | |
187 | #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */ | |
188 | #define HIFN_1_PUB_OP 0x308 /* Public Operand */ | |
189 | #define HIFN_1_PUB_STATUS 0x30c /* Public Status */ | |
190 | #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ | |
191 | #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ | |
192 | #define HIFN_1_RNG_DATA 0x318 /* RNG data */ | |
193 | #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ | |
194 | #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ | |
195 | ||
196 | /* DMA Status and Control Register (HIFN_1_DMA_CSR) */ | |
197 | #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ | |
198 | #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ | |
199 | #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ | |
200 | #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ | |
201 | #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ | |
202 | #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ | |
203 | #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ | |
204 | #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ | |
205 | #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ | |
206 | #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ | |
207 | #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ | |
208 | #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ | |
209 | #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ | |
210 | #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ | |
211 | #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ | |
212 | #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ | |
213 | #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ | |
214 | #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ | |
215 | #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ | |
216 | #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ | |
217 | #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ | |
218 | #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ | |
219 | #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ | |
220 | #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ | |
221 | #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ | |
222 | #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ | |
223 | #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ | |
224 | #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ | |
225 | #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ | |
226 | #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ | |
227 | #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ | |
228 | #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ | |
229 | #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ | |
230 | #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ | |
231 | #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ | |
232 | #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ | |
233 | #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ | |
234 | #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ | |
235 | ||
236 | /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ | |
237 | #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ | |
238 | #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ | |
239 | #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ | |
240 | #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ | |
241 | #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ | |
242 | #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ | |
243 | #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ | |
244 | #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ | |
245 | #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ | |
246 | #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ | |
247 | #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ | |
248 | #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ | |
249 | #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ | |
250 | #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ | |
251 | #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ | |
252 | #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ | |
253 | #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ | |
254 | #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ | |
255 | #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ | |
256 | #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ | |
257 | #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ | |
258 | #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ | |
259 | ||
260 | /* DMA Configuration Register (HIFN_1_DMA_CNFG) */ | |
261 | #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ | |
262 | #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ | |
263 | #define HIFN_DMACNFG_UNLOCK 0x00000800 | |
264 | #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ | |
265 | #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ | |
266 | #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ | |
267 | #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ | |
268 | #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ | |
269 | ||
37a8023c PM |
270 | /* PLL configuration register */ |
271 | #define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */ | |
272 | #define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */ | |
273 | #define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */ | |
274 | #define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */ | |
275 | #define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */ | |
276 | #define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */ | |
277 | #define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */ | |
278 | #define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */ | |
279 | #define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */ | |
280 | #define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */ | |
281 | #define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */ | |
282 | #define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */ | |
283 | #define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */ | |
284 | #define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */ | |
285 | #define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */ | |
286 | #define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */ | |
287 | #define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */ | |
288 | ||
289 | #define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */ | |
f7d0561e EP |
290 | |
291 | /* Public key reset register (HIFN_1_PUB_RESET) */ | |
292 | #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ | |
293 | ||
294 | /* Public base address register (HIFN_1_PUB_BASE) */ | |
295 | #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */ | |
296 | ||
297 | /* Public operand length register (HIFN_1_PUB_OPLEN) */ | |
298 | #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */ | |
299 | #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */ | |
300 | #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */ | |
1537a363 | 301 | #define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */ |
f7d0561e EP |
302 | #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */ |
303 | #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */ | |
304 | ||
305 | /* Public operation register (HIFN_1_PUB_OP) */ | |
306 | #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */ | |
307 | #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */ | |
308 | #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */ | |
309 | #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */ | |
310 | #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */ | |
311 | #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */ | |
312 | #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ | |
313 | #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ | |
314 | #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ | |
315 | #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ | |
316 | #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ | |
317 | #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ | |
318 | #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ | |
319 | #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ | |
320 | #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ | |
321 | #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ | |
322 | #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ | |
323 | #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ | |
324 | #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */ | |
325 | #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */ | |
326 | ||
327 | /* Public status register (HIFN_1_PUB_STATUS) */ | |
328 | #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ | |
329 | #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ | |
330 | ||
331 | /* Public interrupt enable register (HIFN_1_PUB_IEN) */ | |
332 | #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ | |
333 | ||
334 | /* Random number generator config register (HIFN_1_RNG_CONFIG) */ | |
335 | #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ | |
336 | ||
337 | #define HIFN_NAMESIZE 32 | |
338 | #define HIFN_MAX_RESULT_ORDER 5 | |
339 | ||
16f56e8b LC |
340 | #define HIFN_D_CMD_RSIZE (24 * 1) |
341 | #define HIFN_D_SRC_RSIZE (80 * 1) | |
342 | #define HIFN_D_DST_RSIZE (80 * 1) | |
343 | #define HIFN_D_RES_RSIZE (24 * 1) | |
f7d0561e | 344 | |
d069033b PM |
345 | #define HIFN_D_DST_DALIGN 4 |
346 | ||
d6a10c84 | 347 | #define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1) |
f7d0561e EP |
348 | |
349 | #define AES_MIN_KEY_SIZE 16 | |
350 | #define AES_MAX_KEY_SIZE 32 | |
351 | ||
352 | #define HIFN_DES_KEY_LENGTH 8 | |
353 | #define HIFN_3DES_KEY_LENGTH 24 | |
354 | #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE | |
355 | #define HIFN_IV_LENGTH 8 | |
356 | #define HIFN_AES_IV_LENGTH 16 | |
357 | #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH | |
358 | ||
359 | #define HIFN_MAC_KEY_LENGTH 64 | |
360 | #define HIFN_MD5_LENGTH 16 | |
361 | #define HIFN_SHA1_LENGTH 20 | |
362 | #define HIFN_MAC_TRUNC_LENGTH 12 | |
363 | ||
364 | #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) | |
365 | #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4) | |
366 | #define HIFN_USED_RESULT 12 | |
367 | ||
16f56e8b | 368 | struct hifn_desc { |
e68970cd AV |
369 | volatile __le32 l; |
370 | volatile __le32 p; | |
f7d0561e EP |
371 | }; |
372 | ||
373 | struct hifn_dma { | |
16f56e8b LC |
374 | struct hifn_desc cmdr[HIFN_D_CMD_RSIZE + 1]; |
375 | struct hifn_desc srcr[HIFN_D_SRC_RSIZE + 1]; | |
376 | struct hifn_desc dstr[HIFN_D_DST_RSIZE + 1]; | |
377 | struct hifn_desc resr[HIFN_D_RES_RSIZE + 1]; | |
f7d0561e EP |
378 | |
379 | u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; | |
380 | u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; | |
381 | ||
f7d0561e EP |
382 | /* |
383 | * Our current positions for insertion and removal from the descriptor | |
384 | * rings. | |
385 | */ | |
386 | volatile int cmdi, srci, dsti, resi; | |
387 | volatile int cmdu, srcu, dstu, resu; | |
388 | int cmdk, srck, dstk, resk; | |
389 | }; | |
390 | ||
16f56e8b LC |
391 | #define HIFN_FLAG_CMD_BUSY (1 << 0) |
392 | #define HIFN_FLAG_SRC_BUSY (1 << 1) | |
393 | #define HIFN_FLAG_DST_BUSY (1 << 2) | |
394 | #define HIFN_FLAG_RES_BUSY (1 << 3) | |
395 | #define HIFN_FLAG_OLD_KEY (1 << 4) | |
f7d0561e EP |
396 | |
397 | #define HIFN_DEFAULT_ACTIVE_NUM 5 | |
398 | ||
16f56e8b | 399 | struct hifn_device { |
f7d0561e EP |
400 | char name[HIFN_NAMESIZE]; |
401 | ||
402 | int irq; | |
403 | ||
404 | struct pci_dev *pdev; | |
405 | void __iomem *bar[3]; | |
406 | ||
f7d0561e EP |
407 | void *desc_virt; |
408 | dma_addr_t desc_dma; | |
409 | ||
410 | u32 dmareg; | |
411 | ||
16f56e8b | 412 | void *sa[HIFN_D_RES_RSIZE]; |
f7d0561e EP |
413 | |
414 | spinlock_t lock; | |
415 | ||
f7d0561e EP |
416 | u32 flags; |
417 | int active, started; | |
418 | struct delayed_work work; | |
419 | unsigned long reset; | |
420 | unsigned long success; | |
421 | unsigned long prev_success; | |
422 | ||
423 | u8 snum; | |
424 | ||
a1e6ef2f EP |
425 | struct tasklet_struct tasklet; |
426 | ||
16f56e8b | 427 | struct crypto_queue queue; |
f7d0561e | 428 | struct list_head alg_list; |
fcd06755 PM |
429 | |
430 | unsigned int pk_clk_freq; | |
431 | ||
f881d829 | 432 | #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd06755 PM |
433 | unsigned int rng_wait_time; |
434 | ktime_t rngtime; | |
435 | struct hwrng rng; | |
436 | #endif | |
f7d0561e EP |
437 | }; |
438 | ||
439 | #define HIFN_D_LENGTH 0x0000ffff | |
440 | #define HIFN_D_NOINVALID 0x01000000 | |
441 | #define HIFN_D_MASKDONEIRQ 0x02000000 | |
442 | #define HIFN_D_DESTOVER 0x04000000 | |
443 | #define HIFN_D_OVER 0x08000000 | |
444 | #define HIFN_D_LAST 0x20000000 | |
445 | #define HIFN_D_JUMP 0x40000000 | |
446 | #define HIFN_D_VALID 0x80000000 | |
447 | ||
16f56e8b | 448 | struct hifn_base_command { |
e68970cd AV |
449 | volatile __le16 masks; |
450 | volatile __le16 session_num; | |
451 | volatile __le16 total_source_count; | |
452 | volatile __le16 total_dest_count; | |
f7d0561e EP |
453 | }; |
454 | ||
455 | #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */ | |
456 | #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */ | |
457 | #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */ | |
458 | #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */ | |
459 | #define HIFN_BASE_CMD_DECODE 0x2000 | |
460 | #define HIFN_BASE_CMD_SRCLEN_M 0xc000 | |
461 | #define HIFN_BASE_CMD_SRCLEN_S 14 | |
462 | #define HIFN_BASE_CMD_DSTLEN_M 0x3000 | |
463 | #define HIFN_BASE_CMD_DSTLEN_S 12 | |
464 | #define HIFN_BASE_CMD_LENMASK_HI 0x30000 | |
465 | #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff | |
466 | ||
467 | /* | |
468 | * Structure to help build up the command data structure. | |
469 | */ | |
16f56e8b LC |
470 | struct hifn_crypt_command { |
471 | volatile __le16 masks; | |
472 | volatile __le16 header_skip; | |
473 | volatile __le16 source_count; | |
474 | volatile __le16 reserved; | |
f7d0561e EP |
475 | }; |
476 | ||
477 | #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ | |
478 | #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ | |
479 | #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ | |
480 | #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ | |
481 | #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ | |
482 | #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ | |
483 | #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ | |
484 | #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ | |
485 | #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ | |
486 | #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ | |
487 | #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ | |
488 | #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ | |
489 | #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ | |
490 | #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ | |
491 | #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ | |
492 | #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ | |
493 | #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ | |
494 | #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 | |
495 | #define HIFN_CRYPT_CMD_SRCLEN_S 14 | |
496 | ||
497 | /* | |
498 | * Structure to help build up the command data structure. | |
499 | */ | |
16f56e8b LC |
500 | struct hifn_mac_command { |
501 | volatile __le16 masks; | |
502 | volatile __le16 header_skip; | |
503 | volatile __le16 source_count; | |
504 | volatile __le16 reserved; | |
f7d0561e EP |
505 | }; |
506 | ||
507 | #define HIFN_MAC_CMD_ALG_MASK 0x0001 | |
508 | #define HIFN_MAC_CMD_ALG_SHA1 0x0000 | |
509 | #define HIFN_MAC_CMD_ALG_MD5 0x0001 | |
510 | #define HIFN_MAC_CMD_MODE_MASK 0x000c | |
511 | #define HIFN_MAC_CMD_MODE_HMAC 0x0000 | |
512 | #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 | |
513 | #define HIFN_MAC_CMD_MODE_HASH 0x0008 | |
514 | #define HIFN_MAC_CMD_MODE_FULL 0x0004 | |
515 | #define HIFN_MAC_CMD_TRUNC 0x0010 | |
516 | #define HIFN_MAC_CMD_RESULT 0x0020 | |
517 | #define HIFN_MAC_CMD_APPEND 0x0040 | |
518 | #define HIFN_MAC_CMD_SRCLEN_M 0xc000 | |
519 | #define HIFN_MAC_CMD_SRCLEN_S 14 | |
520 | ||
521 | /* | |
522 | * MAC POS IPsec initiates authentication after encryption on encodes | |
523 | * and before decryption on decodes. | |
524 | */ | |
525 | #define HIFN_MAC_CMD_POS_IPSEC 0x0200 | |
526 | #define HIFN_MAC_CMD_NEW_KEY 0x0800 | |
527 | ||
16f56e8b LC |
528 | struct hifn_comp_command { |
529 | volatile __le16 masks; | |
530 | volatile __le16 header_skip; | |
531 | volatile __le16 source_count; | |
532 | volatile __le16 reserved; | |
f7d0561e EP |
533 | }; |
534 | ||
535 | #define HIFN_COMP_CMD_SRCLEN_M 0xc000 | |
536 | #define HIFN_COMP_CMD_SRCLEN_S 14 | |
537 | #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */ | |
538 | #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */ | |
539 | #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */ | |
540 | #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */ | |
541 | #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */ | |
542 | #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */ | |
543 | #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */ | |
544 | #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */ | |
545 | ||
16f56e8b LC |
546 | struct hifn_base_result { |
547 | volatile __le16 flags; | |
548 | volatile __le16 session; | |
549 | volatile __le16 src_cnt; /* 15:0 of source count */ | |
550 | volatile __le16 dst_cnt; /* 15:0 of dest count */ | |
f7d0561e EP |
551 | }; |
552 | ||
553 | #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */ | |
554 | #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */ | |
555 | #define HIFN_BASE_RES_SRCLEN_S 14 | |
556 | #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */ | |
557 | #define HIFN_BASE_RES_DSTLEN_S 12 | |
558 | ||
16f56e8b | 559 | struct hifn_comp_result { |
3c42cbc2 PM |
560 | volatile __le16 flags; |
561 | volatile __le16 crc; | |
f7d0561e EP |
562 | }; |
563 | ||
564 | #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */ | |
565 | #define HIFN_COMP_RES_LCB_S 8 | |
566 | #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */ | |
567 | #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */ | |
568 | #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */ | |
569 | ||
16f56e8b LC |
570 | struct hifn_mac_result { |
571 | volatile __le16 flags; | |
572 | volatile __le16 reserved; | |
f7d0561e EP |
573 | /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */ |
574 | }; | |
575 | ||
576 | #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */ | |
577 | #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */ | |
578 | ||
16f56e8b | 579 | struct hifn_crypt_result { |
3c42cbc2 PM |
580 | volatile __le16 flags; |
581 | volatile __le16 reserved; | |
f7d0561e EP |
582 | }; |
583 | ||
584 | #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */ | |
585 | ||
586 | #ifndef HIFN_POLL_FREQUENCY | |
587 | #define HIFN_POLL_FREQUENCY 0x1 | |
588 | #endif | |
589 | ||
590 | #ifndef HIFN_POLL_SCALAR | |
591 | #define HIFN_POLL_SCALAR 0x0 | |
592 | #endif | |
593 | ||
16f56e8b | 594 | #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ |
f7d0561e EP |
595 | #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ |
596 | ||
16f56e8b | 597 | struct hifn_crypto_alg { |
f7d0561e EP |
598 | struct list_head entry; |
599 | struct crypto_alg alg; | |
600 | struct hifn_device *dev; | |
601 | }; | |
602 | ||
603 | #define ASYNC_SCATTERLIST_CACHE 16 | |
604 | ||
16f56e8b | 605 | #define ASYNC_FLAGS_MISALIGNED (1 << 0) |
f7d0561e | 606 | |
16f56e8b | 607 | struct hifn_cipher_walk { |
f7d0561e EP |
608 | struct scatterlist cache[ASYNC_SCATTERLIST_CACHE]; |
609 | u32 flags; | |
610 | int num; | |
611 | }; | |
612 | ||
16f56e8b | 613 | struct hifn_context { |
5df4c0c6 | 614 | u8 key[HIFN_MAX_CRYPT_KEY_LENGTH]; |
f7d0561e | 615 | struct hifn_device *dev; |
5df4c0c6 PM |
616 | unsigned int keysize; |
617 | }; | |
618 | ||
16f56e8b | 619 | struct hifn_request_context { |
5df4c0c6 PM |
620 | u8 *iv; |
621 | unsigned int ivsize; | |
f7d0561e | 622 | u8 op, type, mode, unused; |
3385329a | 623 | struct hifn_cipher_walk walk; |
f7d0561e EP |
624 | }; |
625 | ||
b966b546 | 626 | #define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg) |
f7d0561e EP |
627 | |
628 | static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg) | |
629 | { | |
36e09e1f | 630 | return readl(dev->bar[0] + reg); |
f7d0561e EP |
631 | } |
632 | ||
633 | static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg) | |
634 | { | |
36e09e1f | 635 | return readl(dev->bar[1] + reg); |
f7d0561e EP |
636 | } |
637 | ||
638 | static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) | |
639 | { | |
3c42cbc2 | 640 | writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); |
f7d0561e EP |
641 | } |
642 | ||
643 | static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) | |
644 | { | |
3c42cbc2 | 645 | writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); |
f7d0561e EP |
646 | } |
647 | ||
648 | static void hifn_wait_puc(struct hifn_device *dev) | |
649 | { | |
650 | int i; | |
651 | u32 ret; | |
652 | ||
16f56e8b | 653 | for (i = 10000; i > 0; --i) { |
f7d0561e EP |
654 | ret = hifn_read_0(dev, HIFN_0_PUCTRL); |
655 | if (!(ret & HIFN_PUCTRL_RESET)) | |
656 | break; | |
657 | ||
658 | udelay(1); | |
659 | } | |
660 | ||
661 | if (!i) | |
cfeecab4 | 662 | dev_err(&dev->pdev->dev, "Failed to reset PUC unit.\n"); |
f7d0561e EP |
663 | } |
664 | ||
665 | static void hifn_reset_puc(struct hifn_device *dev) | |
666 | { | |
667 | hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); | |
668 | hifn_wait_puc(dev); | |
669 | } | |
670 | ||
671 | static void hifn_stop_device(struct hifn_device *dev) | |
672 | { | |
673 | hifn_write_1(dev, HIFN_1_DMA_CSR, | |
674 | HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | | |
675 | HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS); | |
676 | hifn_write_0(dev, HIFN_0_PUIER, 0); | |
677 | hifn_write_1(dev, HIFN_1_DMA_IER, 0); | |
678 | } | |
679 | ||
680 | static void hifn_reset_dma(struct hifn_device *dev, int full) | |
681 | { | |
682 | hifn_stop_device(dev); | |
683 | ||
684 | /* | |
685 | * Setting poll frequency and others to 0. | |
686 | */ | |
687 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | | |
688 | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); | |
689 | mdelay(1); | |
690 | ||
691 | /* | |
692 | * Reset DMA. | |
693 | */ | |
694 | if (full) { | |
695 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); | |
696 | mdelay(1); | |
697 | } else { | |
698 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE | | |
699 | HIFN_DMACNFG_MSTRESET); | |
700 | hifn_reset_puc(dev); | |
701 | } | |
702 | ||
703 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | | |
704 | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); | |
705 | ||
706 | hifn_reset_puc(dev); | |
707 | } | |
708 | ||
16f56e8b | 709 | static u32 hifn_next_signature(u32 a, u_int cnt) |
f7d0561e EP |
710 | { |
711 | int i; | |
712 | u32 v; | |
713 | ||
714 | for (i = 0; i < cnt; i++) { | |
f7d0561e EP |
715 | /* get the parity */ |
716 | v = a & 0x80080125; | |
717 | v ^= v >> 16; | |
718 | v ^= v >> 8; | |
719 | v ^= v >> 4; | |
720 | v ^= v >> 2; | |
721 | v ^= v >> 1; | |
722 | ||
723 | a = (v & 1) ^ (a << 1); | |
724 | } | |
725 | ||
726 | return a; | |
727 | } | |
728 | ||
729 | static struct pci2id { | |
730 | u_short pci_vendor; | |
731 | u_short pci_prod; | |
732 | char card_id[13]; | |
733 | } pci2id[] = { | |
734 | { | |
735 | PCI_VENDOR_ID_HIFN, | |
736 | PCI_DEVICE_ID_HIFN_7955, | |
737 | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
738 | 0x00, 0x00, 0x00, 0x00, 0x00 } | |
739 | }, | |
740 | { | |
741 | PCI_VENDOR_ID_HIFN, | |
742 | PCI_DEVICE_ID_HIFN_7956, | |
743 | { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
744 | 0x00, 0x00, 0x00, 0x00, 0x00 } | |
745 | } | |
746 | }; | |
747 | ||
f881d829 | 748 | #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd06755 PM |
749 | static int hifn_rng_data_present(struct hwrng *rng, int wait) |
750 | { | |
751 | struct hifn_device *dev = (struct hifn_device *)rng->priv; | |
752 | s64 nsec; | |
753 | ||
754 | nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime)); | |
755 | nsec -= dev->rng_wait_time; | |
756 | if (nsec <= 0) | |
757 | return 1; | |
758 | if (!wait) | |
759 | return 0; | |
760 | ndelay(nsec); | |
761 | return 1; | |
762 | } | |
763 | ||
764 | static int hifn_rng_data_read(struct hwrng *rng, u32 *data) | |
765 | { | |
766 | struct hifn_device *dev = (struct hifn_device *)rng->priv; | |
767 | ||
768 | *data = hifn_read_1(dev, HIFN_1_RNG_DATA); | |
769 | dev->rngtime = ktime_get(); | |
770 | return 4; | |
771 | } | |
772 | ||
773 | static int hifn_register_rng(struct hifn_device *dev) | |
774 | { | |
775 | /* | |
776 | * We must wait at least 256 Pk_clk cycles between two reads of the rng. | |
777 | */ | |
76f16f83 JK |
778 | dev->rng_wait_time = DIV_ROUND_UP_ULL(NSEC_PER_SEC, |
779 | dev->pk_clk_freq) * 256; | |
fcd06755 PM |
780 | |
781 | dev->rng.name = dev->name; | |
782 | dev->rng.data_present = hifn_rng_data_present, | |
783 | dev->rng.data_read = hifn_rng_data_read, | |
784 | dev->rng.priv = (unsigned long)dev; | |
785 | ||
786 | return hwrng_register(&dev->rng); | |
787 | } | |
788 | ||
789 | static void hifn_unregister_rng(struct hifn_device *dev) | |
790 | { | |
791 | hwrng_unregister(&dev->rng); | |
792 | } | |
793 | #else | |
794 | #define hifn_register_rng(dev) 0 | |
795 | #define hifn_unregister_rng(dev) | |
796 | #endif | |
797 | ||
f7d0561e EP |
798 | static int hifn_init_pubrng(struct hifn_device *dev) |
799 | { | |
800 | int i; | |
801 | ||
802 | hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) | | |
803 | HIFN_PUBRST_RESET); | |
804 | ||
16f56e8b | 805 | for (i = 100; i > 0; --i) { |
f7d0561e EP |
806 | mdelay(1); |
807 | ||
808 | if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0) | |
809 | break; | |
810 | } | |
811 | ||
16f56e8b | 812 | if (!i) { |
cfeecab4 | 813 | dev_err(&dev->pdev->dev, "Failed to initialise public key engine.\n"); |
16f56e8b | 814 | } else { |
f7d0561e EP |
815 | hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); |
816 | dev->dmareg |= HIFN_DMAIER_PUBDONE; | |
817 | hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); | |
818 | ||
cfeecab4 | 819 | dev_dbg(&dev->pdev->dev, "Public key engine has been successfully initialised.\n"); |
f7d0561e EP |
820 | } |
821 | ||
16f56e8b | 822 | /* Enable RNG engine. */ |
f7d0561e EP |
823 | |
824 | hifn_write_1(dev, HIFN_1_RNG_CONFIG, | |
825 | hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA); | |
cfeecab4 | 826 | dev_dbg(&dev->pdev->dev, "RNG engine has been successfully initialised.\n"); |
f7d0561e | 827 | |
f881d829 | 828 | #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG |
fcd06755 PM |
829 | /* First value must be discarded */ |
830 | hifn_read_1(dev, HIFN_1_RNG_DATA); | |
831 | dev->rngtime = ktime_get(); | |
832 | #endif | |
f7d0561e EP |
833 | return 0; |
834 | } | |
835 | ||
836 | static int hifn_enable_crypto(struct hifn_device *dev) | |
837 | { | |
838 | u32 dmacfg, addr; | |
839 | char *offtbl = NULL; | |
840 | int i; | |
841 | ||
0936a944 | 842 | for (i = 0; i < ARRAY_SIZE(pci2id); i++) { |
f7d0561e EP |
843 | if (pci2id[i].pci_vendor == dev->pdev->vendor && |
844 | pci2id[i].pci_prod == dev->pdev->device) { | |
845 | offtbl = pci2id[i].card_id; | |
846 | break; | |
847 | } | |
848 | } | |
849 | ||
16f56e8b | 850 | if (!offtbl) { |
cfeecab4 | 851 | dev_err(&dev->pdev->dev, "Unknown card!\n"); |
f7d0561e EP |
852 | return -ENODEV; |
853 | } | |
854 | ||
855 | dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG); | |
856 | ||
857 | hifn_write_1(dev, HIFN_1_DMA_CNFG, | |
858 | HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET | | |
859 | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); | |
860 | mdelay(1); | |
861 | addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1); | |
862 | mdelay(1); | |
863 | hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0); | |
864 | mdelay(1); | |
865 | ||
16f56e8b | 866 | for (i = 0; i < 12; ++i) { |
f7d0561e EP |
867 | addr = hifn_next_signature(addr, offtbl[i] + 0x101); |
868 | hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr); | |
869 | ||
870 | mdelay(1); | |
871 | } | |
872 | hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg); | |
873 | ||
cfeecab4 | 874 | dev_dbg(&dev->pdev->dev, "%s %s.\n", dev->name, pci_name(dev->pdev)); |
f7d0561e EP |
875 | |
876 | return 0; | |
877 | } | |
878 | ||
879 | static void hifn_init_dma(struct hifn_device *dev) | |
880 | { | |
881 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
882 | u32 dptr = dev->desc_dma; | |
883 | int i; | |
884 | ||
16f56e8b | 885 | for (i = 0; i < HIFN_D_CMD_RSIZE; ++i) |
f7d0561e EP |
886 | dma->cmdr[i].p = __cpu_to_le32(dptr + |
887 | offsetof(struct hifn_dma, command_bufs[i][0])); | |
16f56e8b | 888 | for (i = 0; i < HIFN_D_RES_RSIZE; ++i) |
f7d0561e EP |
889 | dma->resr[i].p = __cpu_to_le32(dptr + |
890 | offsetof(struct hifn_dma, result_bufs[i][0])); | |
891 | ||
16f56e8b | 892 | /* Setup LAST descriptors. */ |
f7d0561e EP |
893 | dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr + |
894 | offsetof(struct hifn_dma, cmdr[0])); | |
895 | dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr + | |
896 | offsetof(struct hifn_dma, srcr[0])); | |
897 | dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr + | |
898 | offsetof(struct hifn_dma, dstr[0])); | |
899 | dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr + | |
900 | offsetof(struct hifn_dma, resr[0])); | |
901 | ||
902 | dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; | |
903 | dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; | |
904 | dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; | |
905 | } | |
906 | ||
37a8023c PM |
907 | /* |
908 | * Initialize the PLL. We need to know the frequency of the reference clock | |
909 | * to calculate the optimal multiplier. For PCI we assume 66MHz, since that | |
910 | * allows us to operate without the risk of overclocking the chip. If it | |
911 | * actually uses 33MHz, the chip will operate at half the speed, this can be | |
16f56e8b | 912 | * overridden by specifying the frequency as module parameter (pci33). |
37a8023c PM |
913 | * |
914 | * Unfortunately the PCI clock is not very suitable since the HIFN needs a | |
915 | * stable clock and the PCI clock frequency may vary, so the default is the | |
916 | * external clock. There is no way to find out its frequency, we default to | |
917 | * 66MHz since according to Mike Ham of HiFn, almost every board in existence | |
918 | * has an external crystal populated at 66MHz. | |
919 | */ | |
920 | static void hifn_init_pll(struct hifn_device *dev) | |
921 | { | |
922 | unsigned int freq, m; | |
923 | u32 pllcfg; | |
924 | ||
925 | pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1; | |
926 | ||
927 | if (strncmp(hifn_pll_ref, "ext", 3) == 0) | |
928 | pllcfg |= HIFN_PLL_REF_CLK_PLL; | |
929 | else | |
930 | pllcfg |= HIFN_PLL_REF_CLK_HBI; | |
931 | ||
932 | if (hifn_pll_ref[3] != '\0') | |
933 | freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10); | |
934 | else { | |
935 | freq = 66; | |
cfeecab4 LC |
936 | dev_info(&dev->pdev->dev, "assuming %uMHz clock speed, override with hifn_pll_ref=%.3s<frequency>\n", |
937 | freq, hifn_pll_ref); | |
37a8023c PM |
938 | } |
939 | ||
940 | m = HIFN_PLL_FCK_MAX / freq; | |
941 | ||
942 | pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT; | |
943 | if (m <= 8) | |
944 | pllcfg |= HIFN_PLL_IS_1_8; | |
945 | else | |
946 | pllcfg |= HIFN_PLL_IS_9_12; | |
947 | ||
948 | /* Select clock source and enable clock bypass */ | |
949 | hifn_write_1(dev, HIFN_1_PLL, pllcfg | | |
950 | HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP); | |
951 | ||
952 | /* Let the chip lock to the input clock */ | |
953 | mdelay(10); | |
954 | ||
955 | /* Disable clock bypass */ | |
956 | hifn_write_1(dev, HIFN_1_PLL, pllcfg | | |
957 | HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI); | |
958 | ||
959 | /* Switch the engines to the PLL */ | |
960 | hifn_write_1(dev, HIFN_1_PLL, pllcfg | | |
961 | HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL); | |
fcd06755 PM |
962 | |
963 | /* | |
964 | * The Fpk_clk runs at half the total speed. Its frequency is needed to | |
965 | * calculate the minimum time between two reads of the rng. Since 33MHz | |
966 | * is actually 33.333... we overestimate the frequency here, resulting | |
967 | * in slightly larger intervals. | |
968 | */ | |
969 | dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2; | |
37a8023c PM |
970 | } |
971 | ||
f7d0561e EP |
972 | static void hifn_init_registers(struct hifn_device *dev) |
973 | { | |
974 | u32 dptr = dev->desc_dma; | |
975 | ||
976 | /* Initialization magic... */ | |
977 | hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); | |
978 | hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); | |
979 | hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); | |
980 | ||
981 | /* write all 4 ring address registers */ | |
3c42cbc2 PM |
982 | hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr + |
983 | offsetof(struct hifn_dma, cmdr[0])); | |
984 | hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr + | |
985 | offsetof(struct hifn_dma, srcr[0])); | |
986 | hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr + | |
987 | offsetof(struct hifn_dma, dstr[0])); | |
988 | hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr + | |
989 | offsetof(struct hifn_dma, resr[0])); | |
f7d0561e EP |
990 | |
991 | mdelay(2); | |
992 | #if 0 | |
993 | hifn_write_1(dev, HIFN_1_DMA_CSR, | |
994 | HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | | |
995 | HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | | |
996 | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | | |
997 | HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | | |
998 | HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | | |
999 | HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | | |
1000 | HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | | |
1001 | HIFN_DMACSR_S_WAIT | | |
1002 | HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | | |
1003 | HIFN_DMACSR_C_WAIT | | |
1004 | HIFN_DMACSR_ENGINE | | |
1005 | HIFN_DMACSR_PUBDONE); | |
1006 | #else | |
1007 | hifn_write_1(dev, HIFN_1_DMA_CSR, | |
1008 | HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | | |
1009 | HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA | | |
1010 | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | | |
1011 | HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | | |
1012 | HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | | |
1013 | HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | | |
1014 | HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | | |
1015 | HIFN_DMACSR_S_WAIT | | |
1016 | HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | | |
1017 | HIFN_DMACSR_C_WAIT | | |
1018 | HIFN_DMACSR_ENGINE | | |
1019 | HIFN_DMACSR_PUBDONE); | |
1020 | #endif | |
1021 | hifn_read_1(dev, HIFN_1_DMA_CSR); | |
1022 | ||
1023 | dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | | |
1024 | HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | | |
1025 | HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | | |
1026 | HIFN_DMAIER_ENGINE; | |
1027 | dev->dmareg &= ~HIFN_DMAIER_C_WAIT; | |
1028 | ||
1029 | hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); | |
1030 | hifn_read_1(dev, HIFN_1_DMA_IER); | |
1031 | #if 0 | |
1032 | hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG | | |
1033 | HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | | |
1034 | HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | | |
1035 | HIFN_PUCNFG_DRAM); | |
1036 | #else | |
1037 | hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342); | |
1038 | #endif | |
37a8023c | 1039 | hifn_init_pll(dev); |
f7d0561e EP |
1040 | |
1041 | hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); | |
1042 | hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | | |
1043 | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | | |
1044 | ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | | |
1045 | ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); | |
1046 | } | |
1047 | ||
1048 | static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf, | |
1049 | unsigned dlen, unsigned slen, u16 mask, u8 snum) | |
1050 | { | |
1051 | struct hifn_base_command *base_cmd; | |
1052 | u8 *buf_pos = buf; | |
1053 | ||
1054 | base_cmd = (struct hifn_base_command *)buf_pos; | |
1055 | base_cmd->masks = __cpu_to_le16(mask); | |
1056 | base_cmd->total_source_count = | |
1057 | __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO); | |
1058 | base_cmd->total_dest_count = | |
1059 | __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO); | |
1060 | ||
1061 | dlen >>= 16; | |
1062 | slen >>= 16; | |
1063 | base_cmd->session_num = __cpu_to_le16(snum | | |
1064 | ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | | |
1065 | ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); | |
1066 | ||
1067 | return sizeof(struct hifn_base_command); | |
1068 | } | |
1069 | ||
1070 | static int hifn_setup_crypto_command(struct hifn_device *dev, | |
1071 | u8 *buf, unsigned dlen, unsigned slen, | |
1072 | u8 *key, int keylen, u8 *iv, int ivsize, u16 mode) | |
1073 | { | |
1074 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1075 | struct hifn_crypt_command *cry_cmd; | |
1076 | u8 *buf_pos = buf; | |
1077 | u16 cmd_len; | |
1078 | ||
1079 | cry_cmd = (struct hifn_crypt_command *)buf_pos; | |
1080 | ||
1081 | cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff); | |
1082 | dlen >>= 16; | |
1083 | cry_cmd->masks = __cpu_to_le16(mode | | |
1084 | ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & | |
1085 | HIFN_CRYPT_CMD_SRCLEN_M)); | |
1086 | cry_cmd->header_skip = 0; | |
1087 | cry_cmd->reserved = 0; | |
1088 | ||
1089 | buf_pos += sizeof(struct hifn_crypt_command); | |
1090 | ||
1091 | dma->cmdu++; | |
1092 | if (dma->cmdu > 1) { | |
1093 | dev->dmareg |= HIFN_DMAIER_C_WAIT; | |
1094 | hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); | |
1095 | } | |
1096 | ||
1097 | if (keylen) { | |
1098 | memcpy(buf_pos, key, keylen); | |
1099 | buf_pos += keylen; | |
1100 | } | |
1101 | if (ivsize) { | |
1102 | memcpy(buf_pos, iv, ivsize); | |
1103 | buf_pos += ivsize; | |
1104 | } | |
1105 | ||
1106 | cmd_len = buf_pos - buf; | |
1107 | ||
1108 | return cmd_len; | |
1109 | } | |
1110 | ||
85e7e60b | 1111 | static int hifn_setup_cmd_desc(struct hifn_device *dev, |
5df4c0c6 PM |
1112 | struct hifn_context *ctx, struct hifn_request_context *rctx, |
1113 | void *priv, unsigned int nbytes) | |
f7d0561e EP |
1114 | { |
1115 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1116 | int cmd_len, sa_idx; | |
1117 | u8 *buf, *buf_pos; | |
1118 | u16 mask; | |
1119 | ||
85e7e60b | 1120 | sa_idx = dma->cmdi; |
f7d0561e EP |
1121 | buf_pos = buf = dma->command_bufs[dma->cmdi]; |
1122 | ||
1123 | mask = 0; | |
5df4c0c6 | 1124 | switch (rctx->op) { |
16f56e8b LC |
1125 | case ACRYPTO_OP_DECRYPT: |
1126 | mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE; | |
1127 | break; | |
1128 | case ACRYPTO_OP_ENCRYPT: | |
1129 | mask = HIFN_BASE_CMD_CRYPT; | |
1130 | break; | |
1131 | case ACRYPTO_OP_HMAC: | |
1132 | mask = HIFN_BASE_CMD_MAC; | |
1133 | break; | |
1134 | default: | |
1135 | goto err_out; | |
f7d0561e EP |
1136 | } |
1137 | ||
1138 | buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes, | |
1139 | nbytes, mask, dev->snum); | |
1140 | ||
5df4c0c6 | 1141 | if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) { |
f7d0561e EP |
1142 | u16 md = 0; |
1143 | ||
1144 | if (ctx->keysize) | |
1145 | md |= HIFN_CRYPT_CMD_NEW_KEY; | |
5df4c0c6 | 1146 | if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB) |
f7d0561e EP |
1147 | md |= HIFN_CRYPT_CMD_NEW_IV; |
1148 | ||
5df4c0c6 | 1149 | switch (rctx->mode) { |
16f56e8b LC |
1150 | case ACRYPTO_MODE_ECB: |
1151 | md |= HIFN_CRYPT_CMD_MODE_ECB; | |
1152 | break; | |
1153 | case ACRYPTO_MODE_CBC: | |
1154 | md |= HIFN_CRYPT_CMD_MODE_CBC; | |
1155 | break; | |
1156 | case ACRYPTO_MODE_CFB: | |
1157 | md |= HIFN_CRYPT_CMD_MODE_CFB; | |
1158 | break; | |
1159 | case ACRYPTO_MODE_OFB: | |
1160 | md |= HIFN_CRYPT_CMD_MODE_OFB; | |
1161 | break; | |
1162 | default: | |
1163 | goto err_out; | |
f7d0561e EP |
1164 | } |
1165 | ||
5df4c0c6 | 1166 | switch (rctx->type) { |
16f56e8b LC |
1167 | case ACRYPTO_TYPE_AES_128: |
1168 | if (ctx->keysize != 16) | |
f7d0561e | 1169 | goto err_out; |
16f56e8b LC |
1170 | md |= HIFN_CRYPT_CMD_KSZ_128 | |
1171 | HIFN_CRYPT_CMD_ALG_AES; | |
1172 | break; | |
1173 | case ACRYPTO_TYPE_AES_192: | |
1174 | if (ctx->keysize != 24) | |
1175 | goto err_out; | |
1176 | md |= HIFN_CRYPT_CMD_KSZ_192 | | |
1177 | HIFN_CRYPT_CMD_ALG_AES; | |
1178 | break; | |
1179 | case ACRYPTO_TYPE_AES_256: | |
1180 | if (ctx->keysize != 32) | |
1181 | goto err_out; | |
1182 | md |= HIFN_CRYPT_CMD_KSZ_256 | | |
1183 | HIFN_CRYPT_CMD_ALG_AES; | |
1184 | break; | |
1185 | case ACRYPTO_TYPE_3DES: | |
1186 | if (ctx->keysize != 24) | |
1187 | goto err_out; | |
1188 | md |= HIFN_CRYPT_CMD_ALG_3DES; | |
1189 | break; | |
1190 | case ACRYPTO_TYPE_DES: | |
1191 | if (ctx->keysize != 8) | |
1192 | goto err_out; | |
1193 | md |= HIFN_CRYPT_CMD_ALG_DES; | |
1194 | break; | |
1195 | default: | |
1196 | goto err_out; | |
f7d0561e EP |
1197 | } |
1198 | ||
1199 | buf_pos += hifn_setup_crypto_command(dev, buf_pos, | |
1200 | nbytes, nbytes, ctx->key, ctx->keysize, | |
5df4c0c6 | 1201 | rctx->iv, rctx->ivsize, md); |
f7d0561e EP |
1202 | } |
1203 | ||
1204 | dev->sa[sa_idx] = priv; | |
d6a10c84 | 1205 | dev->started++; |
f7d0561e EP |
1206 | |
1207 | cmd_len = buf_pos - buf; | |
1208 | dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID | | |
1209 | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); | |
1210 | ||
1211 | if (++dma->cmdi == HIFN_D_CMD_RSIZE) { | |
5df4c0c6 | 1212 | dma->cmdr[dma->cmdi].l = __cpu_to_le32( |
f7d0561e EP |
1213 | HIFN_D_VALID | HIFN_D_LAST | |
1214 | HIFN_D_MASKDONEIRQ | HIFN_D_JUMP); | |
1215 | dma->cmdi = 0; | |
16f56e8b LC |
1216 | } else { |
1217 | dma->cmdr[dma->cmdi - 1].l |= __cpu_to_le32(HIFN_D_VALID); | |
1218 | } | |
f7d0561e EP |
1219 | |
1220 | if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) { | |
1221 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); | |
1222 | dev->flags |= HIFN_FLAG_CMD_BUSY; | |
1223 | } | |
f7d0561e EP |
1224 | return 0; |
1225 | ||
1226 | err_out: | |
1227 | return -EINVAL; | |
1228 | } | |
1229 | ||
85e7e60b | 1230 | static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page, |
75741a03 | 1231 | unsigned int offset, unsigned int size, int last) |
85e7e60b PM |
1232 | { |
1233 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1234 | int idx; | |
1235 | dma_addr_t addr; | |
1236 | ||
1237 | addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE); | |
1238 | ||
1239 | idx = dma->srci; | |
1240 | ||
1241 | dma->srcr[idx].p = __cpu_to_le32(addr); | |
1242 | dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | | |
75741a03 | 1243 | HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); |
85e7e60b PM |
1244 | |
1245 | if (++idx == HIFN_D_SRC_RSIZE) { | |
1246 | dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID | | |
75741a03 PM |
1247 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | |
1248 | (last ? HIFN_D_LAST : 0)); | |
85e7e60b PM |
1249 | idx = 0; |
1250 | } | |
1251 | ||
1252 | dma->srci = idx; | |
1253 | dma->srcu++; | |
1254 | ||
1255 | if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) { | |
1256 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); | |
1257 | dev->flags |= HIFN_FLAG_SRC_BUSY; | |
1258 | } | |
1259 | ||
1260 | return size; | |
1261 | } | |
1262 | ||
1263 | static void hifn_setup_res_desc(struct hifn_device *dev) | |
1264 | { | |
1265 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1266 | ||
1267 | dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT | | |
1268 | HIFN_D_VALID | HIFN_D_LAST); | |
1269 | /* | |
1270 | * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID | | |
692af5da | 1271 | * HIFN_D_LAST); |
85e7e60b PM |
1272 | */ |
1273 | ||
1274 | if (++dma->resi == HIFN_D_RES_RSIZE) { | |
1275 | dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID | | |
1276 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST); | |
1277 | dma->resi = 0; | |
1278 | } | |
1279 | ||
1280 | dma->resu++; | |
1281 | ||
1282 | if (!(dev->flags & HIFN_FLAG_RES_BUSY)) { | |
1283 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); | |
1284 | dev->flags |= HIFN_FLAG_RES_BUSY; | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page, | |
75741a03 | 1289 | unsigned offset, unsigned size, int last) |
85e7e60b PM |
1290 | { |
1291 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1292 | int idx; | |
1293 | dma_addr_t addr; | |
1294 | ||
1295 | addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE); | |
1296 | ||
1297 | idx = dma->dsti; | |
1298 | dma->dstr[idx].p = __cpu_to_le32(addr); | |
1299 | dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | | |
75741a03 | 1300 | HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); |
85e7e60b PM |
1301 | |
1302 | if (++idx == HIFN_D_DST_RSIZE) { | |
1303 | dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID | | |
1304 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | | |
75741a03 | 1305 | (last ? HIFN_D_LAST : 0)); |
85e7e60b PM |
1306 | idx = 0; |
1307 | } | |
1308 | dma->dsti = idx; | |
1309 | dma->dstu++; | |
1310 | ||
1311 | if (!(dev->flags & HIFN_FLAG_DST_BUSY)) { | |
1312 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); | |
1313 | dev->flags |= HIFN_FLAG_DST_BUSY; | |
1314 | } | |
1315 | } | |
1316 | ||
5df4c0c6 PM |
1317 | static int hifn_setup_dma(struct hifn_device *dev, |
1318 | struct hifn_context *ctx, struct hifn_request_context *rctx, | |
75741a03 PM |
1319 | struct scatterlist *src, struct scatterlist *dst, |
1320 | unsigned int nbytes, void *priv) | |
85e7e60b | 1321 | { |
75741a03 PM |
1322 | struct scatterlist *t; |
1323 | struct page *spage, *dpage; | |
1324 | unsigned int soff, doff; | |
1325 | unsigned int n, len; | |
1326 | ||
34161586 PM |
1327 | n = nbytes; |
1328 | while (n) { | |
1329 | spage = sg_page(src); | |
1330 | soff = src->offset; | |
1331 | len = min(src->length, n); | |
1332 | ||
34161586 PM |
1333 | hifn_setup_src_desc(dev, spage, soff, len, n - len == 0); |
1334 | ||
1335 | src++; | |
1336 | n -= len; | |
1337 | } | |
1338 | ||
5df4c0c6 | 1339 | t = &rctx->walk.cache[0]; |
75741a03 PM |
1340 | n = nbytes; |
1341 | while (n) { | |
5df4c0c6 | 1342 | if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { |
5f459f0a | 1343 | BUG_ON(!sg_page(t)); |
34161586 PM |
1344 | dpage = sg_page(t); |
1345 | doff = 0; | |
75741a03 PM |
1346 | len = t->length; |
1347 | } else { | |
5f459f0a | 1348 | BUG_ON(!sg_page(dst)); |
75741a03 PM |
1349 | dpage = sg_page(dst); |
1350 | doff = dst->offset; | |
75741a03 PM |
1351 | len = dst->length; |
1352 | } | |
1353 | len = min(len, n); | |
1354 | ||
75741a03 PM |
1355 | hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0); |
1356 | ||
75741a03 PM |
1357 | dst++; |
1358 | t++; | |
1359 | n -= len; | |
1360 | } | |
1361 | ||
5df4c0c6 | 1362 | hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes); |
85e7e60b PM |
1363 | hifn_setup_res_desc(dev); |
1364 | return 0; | |
1365 | } | |
1366 | ||
3385329a | 1367 | static int hifn_cipher_walk_init(struct hifn_cipher_walk *w, |
f7d0561e EP |
1368 | int num, gfp_t gfp_flags) |
1369 | { | |
1370 | int i; | |
1371 | ||
1372 | num = min(ASYNC_SCATTERLIST_CACHE, num); | |
1373 | sg_init_table(w->cache, num); | |
1374 | ||
1375 | w->num = 0; | |
16f56e8b | 1376 | for (i = 0; i < num; ++i) { |
f7d0561e EP |
1377 | struct page *page = alloc_page(gfp_flags); |
1378 | struct scatterlist *s; | |
1379 | ||
1380 | if (!page) | |
1381 | break; | |
1382 | ||
1383 | s = &w->cache[i]; | |
1384 | ||
1385 | sg_set_page(s, page, PAGE_SIZE, 0); | |
1386 | w->num++; | |
1387 | } | |
1388 | ||
1389 | return i; | |
1390 | } | |
1391 | ||
3385329a | 1392 | static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w) |
f7d0561e EP |
1393 | { |
1394 | int i; | |
1395 | ||
16f56e8b | 1396 | for (i = 0; i < w->num; ++i) { |
f7d0561e EP |
1397 | struct scatterlist *s = &w->cache[i]; |
1398 | ||
1399 | __free_page(sg_page(s)); | |
1400 | ||
1401 | s->length = 0; | |
1402 | } | |
1403 | ||
1404 | w->num = 0; | |
1405 | } | |
1406 | ||
34161586 | 1407 | static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst, |
f7d0561e EP |
1408 | unsigned int size, unsigned int *nbytesp) |
1409 | { | |
1410 | unsigned int copy, drest = *drestp, nbytes = *nbytesp; | |
1411 | int idx = 0; | |
f7d0561e EP |
1412 | |
1413 | if (drest < size || size > nbytes) | |
1414 | return -EINVAL; | |
1415 | ||
1416 | while (size) { | |
732eacc0 | 1417 | copy = min3(drest, size, dst->length); |
f7d0561e EP |
1418 | |
1419 | size -= copy; | |
1420 | drest -= copy; | |
1421 | nbytes -= copy; | |
f7d0561e | 1422 | |
cfeecab4 LC |
1423 | pr_debug("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n", |
1424 | __func__, copy, size, drest, nbytes); | |
f7d0561e | 1425 | |
34161586 | 1426 | dst++; |
f7d0561e EP |
1427 | idx++; |
1428 | } | |
1429 | ||
1430 | *nbytesp = nbytes; | |
1431 | *drestp = drest; | |
1432 | ||
1433 | return idx; | |
1434 | } | |
1435 | ||
3385329a DM |
1436 | static int hifn_cipher_walk(struct ablkcipher_request *req, |
1437 | struct hifn_cipher_walk *w) | |
f7d0561e | 1438 | { |
34161586 | 1439 | struct scatterlist *dst, *t; |
f7d0561e EP |
1440 | unsigned int nbytes = req->nbytes, offset, copy, diff; |
1441 | int idx, tidx, err; | |
1442 | ||
1443 | tidx = idx = 0; | |
1444 | offset = 0; | |
1445 | while (nbytes) { | |
1446 | if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED)) | |
1447 | return -EINVAL; | |
1448 | ||
f7d0561e EP |
1449 | dst = &req->dst[idx]; |
1450 | ||
cfeecab4 LC |
1451 | pr_debug("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n", |
1452 | __func__, dst->length, dst->offset, offset, nbytes); | |
f7d0561e | 1453 | |
d069033b PM |
1454 | if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) || |
1455 | !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) || | |
1456 | offset) { | |
34161586 | 1457 | unsigned slen = min(dst->length - offset, nbytes); |
f7d0561e EP |
1458 | unsigned dlen = PAGE_SIZE; |
1459 | ||
1460 | t = &w->cache[idx]; | |
1461 | ||
34161586 | 1462 | err = ablkcipher_add(&dlen, dst, slen, &nbytes); |
f7d0561e | 1463 | if (err < 0) |
34161586 | 1464 | return err; |
f7d0561e EP |
1465 | |
1466 | idx += err; | |
1467 | ||
d069033b PM |
1468 | copy = slen & ~(HIFN_D_DST_DALIGN - 1); |
1469 | diff = slen & (HIFN_D_DST_DALIGN - 1); | |
f7d0561e EP |
1470 | |
1471 | if (dlen < nbytes) { | |
1472 | /* | |
1473 | * Destination page does not have enough space | |
1474 | * to put there additional blocksized chunk, | |
1475 | * so we mark that page as containing only | |
1476 | * blocksize aligned chunks: | |
16f56e8b | 1477 | * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1)); |
f7d0561e EP |
1478 | * and increase number of bytes to be processed |
1479 | * in next chunk: | |
16f56e8b | 1480 | * nbytes += diff; |
f7d0561e EP |
1481 | */ |
1482 | nbytes += diff; | |
1483 | ||
1484 | /* | |
1485 | * Temporary of course... | |
1486 | * Kick author if you will catch this one. | |
1487 | */ | |
cfeecab4 LC |
1488 | pr_err("%s: dlen: %u, nbytes: %u, slen: %u, offset: %u.\n", |
1489 | __func__, dlen, nbytes, slen, offset); | |
1490 | pr_err("%s: please contact author to fix this " | |
1491 | "issue, generally you should not catch " | |
1492 | "this path under any condition but who " | |
1493 | "knows how did you use crypto code.\n" | |
1494 | "Thank you.\n", __func__); | |
f7d0561e EP |
1495 | BUG(); |
1496 | } else { | |
1497 | copy += diff + nbytes; | |
1498 | ||
34161586 | 1499 | dst = &req->dst[idx]; |
f7d0561e | 1500 | |
34161586 | 1501 | err = ablkcipher_add(&dlen, dst, nbytes, &nbytes); |
f7d0561e | 1502 | if (err < 0) |
34161586 | 1503 | return err; |
f7d0561e EP |
1504 | |
1505 | idx += err; | |
1506 | } | |
1507 | ||
1508 | t->length = copy; | |
1509 | t->offset = offset; | |
f7d0561e | 1510 | } else { |
34161586 | 1511 | nbytes -= min(dst->length, nbytes); |
f7d0561e EP |
1512 | idx++; |
1513 | } | |
1514 | ||
1515 | tidx++; | |
1516 | } | |
1517 | ||
1518 | return tidx; | |
f7d0561e EP |
1519 | } |
1520 | ||
1521 | static int hifn_setup_session(struct ablkcipher_request *req) | |
1522 | { | |
1523 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
5df4c0c6 | 1524 | struct hifn_request_context *rctx = ablkcipher_request_ctx(req); |
f7d0561e | 1525 | struct hifn_device *dev = ctx->dev; |
75741a03 PM |
1526 | unsigned long dlen, flags; |
1527 | unsigned int nbytes = req->nbytes, idx = 0; | |
f7d0561e | 1528 | int err = -EINVAL, sg_num; |
75741a03 | 1529 | struct scatterlist *dst; |
f7d0561e | 1530 | |
5df4c0c6 | 1531 | if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB) |
f7d0561e EP |
1532 | goto err_out_exit; |
1533 | ||
5df4c0c6 | 1534 | rctx->walk.flags = 0; |
f7d0561e EP |
1535 | |
1536 | while (nbytes) { | |
f7d0561e | 1537 | dst = &req->dst[idx]; |
136f702f | 1538 | dlen = min(dst->length, nbytes); |
f7d0561e | 1539 | |
d069033b | 1540 | if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) || |
136f702f | 1541 | !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN)) |
5df4c0c6 | 1542 | rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED; |
f7d0561e | 1543 | |
136f702f | 1544 | nbytes -= dlen; |
f7d0561e EP |
1545 | idx++; |
1546 | } | |
1547 | ||
5df4c0c6 | 1548 | if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { |
3385329a | 1549 | err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC); |
f7d0561e EP |
1550 | if (err < 0) |
1551 | return err; | |
1552 | } | |
1553 | ||
3385329a | 1554 | sg_num = hifn_cipher_walk(req, &rctx->walk); |
94eaa1bd PM |
1555 | if (sg_num < 0) { |
1556 | err = sg_num; | |
1557 | goto err_out_exit; | |
1558 | } | |
f7d0561e EP |
1559 | |
1560 | spin_lock_irqsave(&dev->lock, flags); | |
1561 | if (dev->started + sg_num > HIFN_QUEUE_LENGTH) { | |
1562 | err = -EAGAIN; | |
1563 | goto err_out; | |
1564 | } | |
1565 | ||
5df4c0c6 | 1566 | err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->nbytes, req); |
75741a03 PM |
1567 | if (err) |
1568 | goto err_out; | |
f7d0561e | 1569 | |
d6a10c84 EP |
1570 | dev->snum++; |
1571 | ||
f7d0561e EP |
1572 | dev->active = HIFN_DEFAULT_ACTIVE_NUM; |
1573 | spin_unlock_irqrestore(&dev->lock, flags); | |
1574 | ||
1575 | return 0; | |
1576 | ||
1577 | err_out: | |
1578 | spin_unlock_irqrestore(&dev->lock, flags); | |
1579 | err_out_exit: | |
d6a10c84 | 1580 | if (err) { |
cfeecab4 LC |
1581 | dev_info(&dev->pdev->dev, "iv: %p [%d], key: %p [%d], mode: %u, op: %u, " |
1582 | "type: %u, err: %d.\n", | |
1583 | rctx->iv, rctx->ivsize, | |
1584 | ctx->key, ctx->keysize, | |
1585 | rctx->mode, rctx->op, rctx->type, err); | |
d6a10c84 | 1586 | } |
f7d0561e EP |
1587 | |
1588 | return err; | |
1589 | } | |
1590 | ||
f7d0561e EP |
1591 | static int hifn_start_device(struct hifn_device *dev) |
1592 | { | |
1593 | int err; | |
1594 | ||
d6a10c84 | 1595 | dev->started = dev->active = 0; |
f7d0561e EP |
1596 | hifn_reset_dma(dev, 1); |
1597 | ||
1598 | err = hifn_enable_crypto(dev); | |
1599 | if (err) | |
1600 | return err; | |
1601 | ||
1602 | hifn_reset_puc(dev); | |
1603 | ||
1604 | hifn_init_dma(dev); | |
1605 | ||
1606 | hifn_init_registers(dev); | |
1607 | ||
1608 | hifn_init_pubrng(dev); | |
1609 | ||
1610 | return 0; | |
1611 | } | |
1612 | ||
1613 | static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset, | |
1614 | struct scatterlist *dst, unsigned int size, unsigned int *nbytesp) | |
1615 | { | |
1616 | unsigned int srest = *srestp, nbytes = *nbytesp, copy; | |
1617 | void *daddr; | |
1618 | int idx = 0; | |
1619 | ||
1620 | if (srest < size || size > nbytes) | |
1621 | return -EINVAL; | |
1622 | ||
1623 | while (size) { | |
732eacc0 | 1624 | copy = min3(srest, dst->length, size); |
f7d0561e | 1625 | |
237f259c | 1626 | daddr = kmap_atomic(sg_page(dst)); |
f7d0561e | 1627 | memcpy(daddr + dst->offset + offset, saddr, copy); |
237f259c | 1628 | kunmap_atomic(daddr); |
f7d0561e EP |
1629 | |
1630 | nbytes -= copy; | |
1631 | size -= copy; | |
1632 | srest -= copy; | |
1633 | saddr += copy; | |
1634 | offset = 0; | |
1635 | ||
cfeecab4 LC |
1636 | pr_debug("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n", |
1637 | __func__, copy, size, srest, nbytes); | |
f7d0561e EP |
1638 | |
1639 | dst++; | |
1640 | idx++; | |
1641 | } | |
1642 | ||
1643 | *nbytesp = nbytes; | |
1644 | *srestp = srest; | |
1645 | ||
1646 | return idx; | |
1647 | } | |
1648 | ||
d6a10c84 | 1649 | static inline void hifn_complete_sa(struct hifn_device *dev, int i) |
f7d0561e | 1650 | { |
d6a10c84 | 1651 | unsigned long flags; |
f7d0561e | 1652 | |
d6a10c84 EP |
1653 | spin_lock_irqsave(&dev->lock, flags); |
1654 | dev->sa[i] = NULL; | |
1655 | dev->started--; | |
1656 | if (dev->started < 0) | |
cfeecab4 LC |
1657 | dev_info(&dev->pdev->dev, "%s: started: %d.\n", __func__, |
1658 | dev->started); | |
d6a10c84 EP |
1659 | spin_unlock_irqrestore(&dev->lock, flags); |
1660 | BUG_ON(dev->started < 0); | |
1661 | } | |
f7d0561e | 1662 | |
d6a10c84 EP |
1663 | static void hifn_process_ready(struct ablkcipher_request *req, int error) |
1664 | { | |
1665 | struct hifn_request_context *rctx = ablkcipher_request_ctx(req); | |
f7d0561e | 1666 | |
5df4c0c6 | 1667 | if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { |
f7d0561e EP |
1668 | unsigned int nbytes = req->nbytes; |
1669 | int idx = 0, err; | |
1670 | struct scatterlist *dst, *t; | |
1671 | void *saddr; | |
1672 | ||
75741a03 | 1673 | while (nbytes) { |
5df4c0c6 | 1674 | t = &rctx->walk.cache[idx]; |
75741a03 | 1675 | dst = &req->dst[idx]; |
f7d0561e | 1676 | |
cfeecab4 | 1677 | pr_debug("\n%s: sg_page(t): %p, t->length: %u, " |
75741a03 PM |
1678 | "sg_page(dst): %p, dst->length: %u, " |
1679 | "nbytes: %u.\n", | |
1680 | __func__, sg_page(t), t->length, | |
1681 | sg_page(dst), dst->length, nbytes); | |
f7d0561e | 1682 | |
75741a03 PM |
1683 | if (!t->length) { |
1684 | nbytes -= min(dst->length, nbytes); | |
1685 | idx++; | |
1686 | continue; | |
1687 | } | |
f7d0561e | 1688 | |
237f259c | 1689 | saddr = kmap_atomic(sg_page(t)); |
f7d0561e | 1690 | |
75741a03 PM |
1691 | err = ablkcipher_get(saddr, &t->length, t->offset, |
1692 | dst, nbytes, &nbytes); | |
1693 | if (err < 0) { | |
237f259c | 1694 | kunmap_atomic(saddr); |
75741a03 | 1695 | break; |
f7d0561e EP |
1696 | } |
1697 | ||
75741a03 | 1698 | idx += err; |
237f259c | 1699 | kunmap_atomic(saddr); |
f7d0561e EP |
1700 | } |
1701 | ||
3385329a | 1702 | hifn_cipher_walk_exit(&rctx->walk); |
f7d0561e | 1703 | } |
75741a03 PM |
1704 | |
1705 | req->base.complete(&req->base, error); | |
f7d0561e EP |
1706 | } |
1707 | ||
d6a10c84 | 1708 | static void hifn_clear_rings(struct hifn_device *dev, int error) |
f7d0561e EP |
1709 | { |
1710 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1711 | int i, u; | |
1712 | ||
cfeecab4 | 1713 | dev_dbg(&dev->pdev->dev, "ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, " |
f7d0561e | 1714 | "k: %d.%d.%d.%d.\n", |
f7d0561e EP |
1715 | dma->cmdi, dma->srci, dma->dsti, dma->resi, |
1716 | dma->cmdu, dma->srcu, dma->dstu, dma->resu, | |
1717 | dma->cmdk, dma->srck, dma->dstk, dma->resk); | |
1718 | ||
1719 | i = dma->resk; u = dma->resu; | |
1720 | while (u != 0) { | |
1721 | if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID)) | |
1722 | break; | |
1723 | ||
d6a10c84 EP |
1724 | if (dev->sa[i]) { |
1725 | dev->success++; | |
1726 | dev->reset = 0; | |
1727 | hifn_process_ready(dev->sa[i], error); | |
1728 | hifn_complete_sa(dev, i); | |
1729 | } | |
f7d0561e | 1730 | |
d6a10c84 | 1731 | if (++i == HIFN_D_RES_RSIZE) |
f7d0561e | 1732 | i = 0; |
d6a10c84 | 1733 | u--; |
f7d0561e EP |
1734 | } |
1735 | dma->resk = i; dma->resu = u; | |
1736 | ||
1737 | i = dma->srck; u = dma->srcu; | |
1738 | while (u != 0) { | |
f7d0561e EP |
1739 | if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID)) |
1740 | break; | |
d6a10c84 EP |
1741 | if (++i == HIFN_D_SRC_RSIZE) |
1742 | i = 0; | |
1743 | u--; | |
f7d0561e EP |
1744 | } |
1745 | dma->srck = i; dma->srcu = u; | |
1746 | ||
1747 | i = dma->cmdk; u = dma->cmdu; | |
1748 | while (u != 0) { | |
1749 | if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID)) | |
1750 | break; | |
d6a10c84 | 1751 | if (++i == HIFN_D_CMD_RSIZE) |
f7d0561e | 1752 | i = 0; |
d6a10c84 | 1753 | u--; |
f7d0561e EP |
1754 | } |
1755 | dma->cmdk = i; dma->cmdu = u; | |
1756 | ||
1757 | i = dma->dstk; u = dma->dstu; | |
1758 | while (u != 0) { | |
f7d0561e EP |
1759 | if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID)) |
1760 | break; | |
d6a10c84 EP |
1761 | if (++i == HIFN_D_DST_RSIZE) |
1762 | i = 0; | |
1763 | u--; | |
f7d0561e EP |
1764 | } |
1765 | dma->dstk = i; dma->dstu = u; | |
1766 | ||
cfeecab4 | 1767 | dev_dbg(&dev->pdev->dev, "ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, " |
f7d0561e | 1768 | "k: %d.%d.%d.%d.\n", |
f7d0561e EP |
1769 | dma->cmdi, dma->srci, dma->dsti, dma->resi, |
1770 | dma->cmdu, dma->srcu, dma->dstu, dma->resu, | |
1771 | dma->cmdk, dma->srck, dma->dstk, dma->resk); | |
1772 | } | |
1773 | ||
1774 | static void hifn_work(struct work_struct *work) | |
1775 | { | |
bf6aede7 | 1776 | struct delayed_work *dw = to_delayed_work(work); |
f7d0561e EP |
1777 | struct hifn_device *dev = container_of(dw, struct hifn_device, work); |
1778 | unsigned long flags; | |
1779 | int reset = 0; | |
1780 | u32 r = 0; | |
1781 | ||
1782 | spin_lock_irqsave(&dev->lock, flags); | |
1783 | if (dev->active == 0) { | |
1784 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1785 | ||
1786 | if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) { | |
1787 | dev->flags &= ~HIFN_FLAG_CMD_BUSY; | |
1788 | r |= HIFN_DMACSR_C_CTRL_DIS; | |
1789 | } | |
1790 | if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) { | |
1791 | dev->flags &= ~HIFN_FLAG_SRC_BUSY; | |
1792 | r |= HIFN_DMACSR_S_CTRL_DIS; | |
1793 | } | |
1794 | if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) { | |
1795 | dev->flags &= ~HIFN_FLAG_DST_BUSY; | |
1796 | r |= HIFN_DMACSR_D_CTRL_DIS; | |
1797 | } | |
1798 | if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) { | |
1799 | dev->flags &= ~HIFN_FLAG_RES_BUSY; | |
1800 | r |= HIFN_DMACSR_R_CTRL_DIS; | |
1801 | } | |
1802 | if (r) | |
1803 | hifn_write_1(dev, HIFN_1_DMA_CSR, r); | |
1804 | } else | |
1805 | dev->active--; | |
1806 | ||
d6a10c84 | 1807 | if ((dev->prev_success == dev->success) && dev->started) |
f7d0561e EP |
1808 | reset = 1; |
1809 | dev->prev_success = dev->success; | |
1810 | spin_unlock_irqrestore(&dev->lock, flags); | |
1811 | ||
1812 | if (reset) { | |
f7d0561e | 1813 | if (++dev->reset >= 5) { |
d6a10c84 EP |
1814 | int i; |
1815 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1816 | ||
cfeecab4 LC |
1817 | dev_info(&dev->pdev->dev, |
1818 | "r: %08x, active: %d, started: %d, " | |
1819 | "success: %lu: qlen: %u/%u, reset: %d.\n", | |
1820 | r, dev->active, dev->started, | |
1821 | dev->success, dev->queue.qlen, dev->queue.max_qlen, | |
1822 | reset); | |
d6a10c84 | 1823 | |
cfeecab4 | 1824 | dev_info(&dev->pdev->dev, "%s: res: ", __func__); |
16f56e8b | 1825 | for (i = 0; i < HIFN_D_RES_RSIZE; ++i) { |
cfeecab4 | 1826 | pr_info("%x.%p ", dma->resr[i].l, dev->sa[i]); |
d6a10c84 EP |
1827 | if (dev->sa[i]) { |
1828 | hifn_process_ready(dev->sa[i], -ENODEV); | |
1829 | hifn_complete_sa(dev, i); | |
1830 | } | |
1831 | } | |
cfeecab4 | 1832 | pr_info("\n"); |
d6a10c84 | 1833 | |
f7d0561e EP |
1834 | hifn_reset_dma(dev, 1); |
1835 | hifn_stop_device(dev); | |
1836 | hifn_start_device(dev); | |
1837 | dev->reset = 0; | |
1838 | } | |
1839 | ||
d6a10c84 | 1840 | tasklet_schedule(&dev->tasklet); |
f7d0561e EP |
1841 | } |
1842 | ||
1843 | schedule_delayed_work(&dev->work, HZ); | |
1844 | } | |
1845 | ||
1846 | static irqreturn_t hifn_interrupt(int irq, void *data) | |
1847 | { | |
1848 | struct hifn_device *dev = (struct hifn_device *)data; | |
1849 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1850 | u32 dmacsr, restart; | |
1851 | ||
1852 | dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); | |
1853 | ||
cfeecab4 | 1854 | dev_dbg(&dev->pdev->dev, "1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], " |
f7d0561e | 1855 | "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n", |
cfeecab4 | 1856 | dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi, |
d6a10c84 EP |
1857 | dma->cmdi, dma->srci, dma->dsti, dma->resi, |
1858 | dma->cmdu, dma->srcu, dma->dstu, dma->resu); | |
f7d0561e EP |
1859 | |
1860 | if ((dmacsr & dev->dmareg) == 0) | |
1861 | return IRQ_NONE; | |
1862 | ||
1863 | hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); | |
1864 | ||
1865 | if (dmacsr & HIFN_DMACSR_ENGINE) | |
1866 | hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR)); | |
1867 | if (dmacsr & HIFN_DMACSR_PUBDONE) | |
1868 | hifn_write_1(dev, HIFN_1_PUB_STATUS, | |
1869 | hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); | |
1870 | ||
1871 | restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER); | |
1872 | if (restart) { | |
1873 | u32 puisr = hifn_read_0(dev, HIFN_0_PUISR); | |
1874 | ||
cfeecab4 LC |
1875 | dev_warn(&dev->pdev->dev, "overflow: r: %d, d: %d, puisr: %08x, d: %u.\n", |
1876 | !!(dmacsr & HIFN_DMACSR_R_OVER), | |
1877 | !!(dmacsr & HIFN_DMACSR_D_OVER), | |
d6a10c84 | 1878 | puisr, !!(puisr & HIFN_PUISR_DSTOVER)); |
f7d0561e EP |
1879 | if (!!(puisr & HIFN_PUISR_DSTOVER)) |
1880 | hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); | |
1881 | hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | | |
1882 | HIFN_DMACSR_D_OVER)); | |
1883 | } | |
1884 | ||
1885 | restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | | |
1886 | HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); | |
1887 | if (restart) { | |
cfeecab4 LC |
1888 | dev_warn(&dev->pdev->dev, "abort: c: %d, s: %d, d: %d, r: %d.\n", |
1889 | !!(dmacsr & HIFN_DMACSR_C_ABORT), | |
1890 | !!(dmacsr & HIFN_DMACSR_S_ABORT), | |
1891 | !!(dmacsr & HIFN_DMACSR_D_ABORT), | |
1892 | !!(dmacsr & HIFN_DMACSR_R_ABORT)); | |
f7d0561e EP |
1893 | hifn_reset_dma(dev, 1); |
1894 | hifn_init_dma(dev); | |
1895 | hifn_init_registers(dev); | |
1896 | } | |
1897 | ||
1898 | if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { | |
cfeecab4 | 1899 | dev_dbg(&dev->pdev->dev, "wait on command.\n"); |
f7d0561e EP |
1900 | dev->dmareg &= ~(HIFN_DMAIER_C_WAIT); |
1901 | hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); | |
1902 | } | |
1903 | ||
a1e6ef2f | 1904 | tasklet_schedule(&dev->tasklet); |
f7d0561e EP |
1905 | |
1906 | return IRQ_HANDLED; | |
1907 | } | |
1908 | ||
1909 | static void hifn_flush(struct hifn_device *dev) | |
1910 | { | |
1911 | unsigned long flags; | |
1912 | struct crypto_async_request *async_req; | |
f7d0561e EP |
1913 | struct ablkcipher_request *req; |
1914 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | |
1915 | int i; | |
1916 | ||
16f56e8b | 1917 | for (i = 0; i < HIFN_D_RES_RSIZE; ++i) { |
f7d0561e EP |
1918 | struct hifn_desc *d = &dma->resr[i]; |
1919 | ||
1920 | if (dev->sa[i]) { | |
1921 | hifn_process_ready(dev->sa[i], | |
16f56e8b | 1922 | (d->l & __cpu_to_le32(HIFN_D_VALID)) ? -ENODEV : 0); |
d6a10c84 | 1923 | hifn_complete_sa(dev, i); |
f7d0561e EP |
1924 | } |
1925 | } | |
1926 | ||
d6a10c84 | 1927 | spin_lock_irqsave(&dev->lock, flags); |
f7d0561e | 1928 | while ((async_req = crypto_dequeue_request(&dev->queue))) { |
48d62764 | 1929 | req = ablkcipher_request_cast(async_req); |
d6a10c84 | 1930 | spin_unlock_irqrestore(&dev->lock, flags); |
f7d0561e EP |
1931 | |
1932 | hifn_process_ready(req, -ENODEV); | |
d6a10c84 EP |
1933 | |
1934 | spin_lock_irqsave(&dev->lock, flags); | |
f7d0561e EP |
1935 | } |
1936 | spin_unlock_irqrestore(&dev->lock, flags); | |
1937 | } | |
1938 | ||
1939 | static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key, | |
1940 | unsigned int len) | |
1941 | { | |
1942 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
1943 | struct hifn_context *ctx = crypto_tfm_ctx(tfm); | |
1944 | struct hifn_device *dev = ctx->dev; | |
1945 | ||
1946 | if (len > HIFN_MAX_CRYPT_KEY_LENGTH) { | |
1947 | crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
1948 | return -1; | |
1949 | } | |
1950 | ||
c3041f9c EP |
1951 | if (len == HIFN_DES_KEY_LENGTH) { |
1952 | u32 tmp[DES_EXPKEY_WORDS]; | |
1953 | int ret = des_ekey(tmp, key); | |
16f56e8b | 1954 | |
231baecd EB |
1955 | if (unlikely(ret == 0) && |
1956 | (tfm->crt_flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS)) { | |
c3041f9c EP |
1957 | tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; |
1958 | return -EINVAL; | |
1959 | } | |
1960 | } | |
1961 | ||
f7d0561e EP |
1962 | dev->flags &= ~HIFN_FLAG_OLD_KEY; |
1963 | ||
1964 | memcpy(ctx->key, key, len); | |
1965 | ctx->keysize = len; | |
1966 | ||
1967 | return 0; | |
1968 | } | |
1969 | ||
270e21da HX |
1970 | static int hifn_des3_setkey(struct crypto_ablkcipher *cipher, const u8 *key, |
1971 | unsigned int len) | |
1972 | { | |
1973 | struct hifn_context *ctx = crypto_ablkcipher_ctx(cipher); | |
1974 | struct hifn_device *dev = ctx->dev; | |
1975 | u32 flags; | |
1976 | int err; | |
1977 | ||
1978 | flags = crypto_ablkcipher_get_flags(cipher); | |
1979 | err = __des3_verify_key(&flags, key); | |
1980 | if (unlikely(err)) { | |
1981 | crypto_ablkcipher_set_flags(cipher, flags); | |
1982 | return err; | |
1983 | } | |
1984 | ||
1985 | dev->flags &= ~HIFN_FLAG_OLD_KEY; | |
1986 | ||
1987 | memcpy(ctx->key, key, len); | |
1988 | ctx->keysize = len; | |
1989 | ||
1990 | return 0; | |
1991 | } | |
1992 | ||
f7d0561e EP |
1993 | static int hifn_handle_req(struct ablkcipher_request *req) |
1994 | { | |
1995 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
1996 | struct hifn_device *dev = ctx->dev; | |
1997 | int err = -EAGAIN; | |
1998 | ||
1999 | if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH) | |
2000 | err = hifn_setup_session(req); | |
2001 | ||
2002 | if (err == -EAGAIN) { | |
2003 | unsigned long flags; | |
2004 | ||
2005 | spin_lock_irqsave(&dev->lock, flags); | |
2006 | err = ablkcipher_enqueue_request(&dev->queue, req); | |
2007 | spin_unlock_irqrestore(&dev->lock, flags); | |
2008 | } | |
2009 | ||
2010 | return err; | |
2011 | } | |
2012 | ||
2013 | static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op, | |
2014 | u8 type, u8 mode) | |
2015 | { | |
2016 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
5df4c0c6 | 2017 | struct hifn_request_context *rctx = ablkcipher_request_ctx(req); |
f7d0561e EP |
2018 | unsigned ivsize; |
2019 | ||
2020 | ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req)); | |
2021 | ||
2022 | if (req->info && mode != ACRYPTO_MODE_ECB) { | |
2023 | if (type == ACRYPTO_TYPE_AES_128) | |
2024 | ivsize = HIFN_AES_IV_LENGTH; | |
2025 | else if (type == ACRYPTO_TYPE_DES) | |
2026 | ivsize = HIFN_DES_KEY_LENGTH; | |
2027 | else if (type == ACRYPTO_TYPE_3DES) | |
2028 | ivsize = HIFN_3DES_KEY_LENGTH; | |
2029 | } | |
2030 | ||
2031 | if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) { | |
2032 | if (ctx->keysize == 24) | |
2033 | type = ACRYPTO_TYPE_AES_192; | |
2034 | else if (ctx->keysize == 32) | |
2035 | type = ACRYPTO_TYPE_AES_256; | |
2036 | } | |
2037 | ||
5df4c0c6 PM |
2038 | rctx->op = op; |
2039 | rctx->mode = mode; | |
2040 | rctx->type = type; | |
2041 | rctx->iv = req->info; | |
2042 | rctx->ivsize = ivsize; | |
f7d0561e EP |
2043 | |
2044 | /* | |
2045 | * HEAVY TODO: needs to kick Herbert XU to write documentation. | |
2046 | * HEAVY TODO: needs to kick Herbert XU to write documentation. | |
2047 | * HEAVY TODO: needs to kick Herbert XU to write documentation. | |
2048 | */ | |
2049 | ||
2050 | return hifn_handle_req(req); | |
2051 | } | |
2052 | ||
2053 | static int hifn_process_queue(struct hifn_device *dev) | |
2054 | { | |
ed4f92e3 | 2055 | struct crypto_async_request *async_req, *backlog; |
f7d0561e EP |
2056 | struct ablkcipher_request *req; |
2057 | unsigned long flags; | |
2058 | int err = 0; | |
2059 | ||
2060 | while (dev->started < HIFN_QUEUE_LENGTH) { | |
2061 | spin_lock_irqsave(&dev->lock, flags); | |
ed4f92e3 | 2062 | backlog = crypto_get_backlog(&dev->queue); |
f7d0561e EP |
2063 | async_req = crypto_dequeue_request(&dev->queue); |
2064 | spin_unlock_irqrestore(&dev->lock, flags); | |
2065 | ||
2066 | if (!async_req) | |
2067 | break; | |
2068 | ||
ed4f92e3 PM |
2069 | if (backlog) |
2070 | backlog->complete(backlog, -EINPROGRESS); | |
2071 | ||
48d62764 | 2072 | req = ablkcipher_request_cast(async_req); |
f7d0561e EP |
2073 | |
2074 | err = hifn_handle_req(req); | |
2075 | if (err) | |
2076 | break; | |
2077 | } | |
2078 | ||
2079 | return err; | |
2080 | } | |
2081 | ||
2082 | static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op, | |
2083 | u8 type, u8 mode) | |
2084 | { | |
2085 | int err; | |
2086 | struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); | |
2087 | struct hifn_device *dev = ctx->dev; | |
2088 | ||
2089 | err = hifn_setup_crypto_req(req, op, type, mode); | |
2090 | if (err) | |
2091 | return err; | |
2092 | ||
2093 | if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen) | |
9e70a408 | 2094 | hifn_process_queue(dev); |
f7d0561e | 2095 | |
9e70a408 | 2096 | return -EINPROGRESS; |
f7d0561e EP |
2097 | } |
2098 | ||
2099 | /* | |
2100 | * AES ecryption functions. | |
2101 | */ | |
2102 | static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req) | |
2103 | { | |
2104 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2105 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB); | |
2106 | } | |
2107 | static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req) | |
2108 | { | |
2109 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2110 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC); | |
2111 | } | |
2112 | static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req) | |
2113 | { | |
2114 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2115 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB); | |
2116 | } | |
2117 | static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req) | |
2118 | { | |
2119 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2120 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB); | |
2121 | } | |
2122 | ||
2123 | /* | |
2124 | * AES decryption functions. | |
2125 | */ | |
2126 | static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req) | |
2127 | { | |
2128 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2129 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB); | |
2130 | } | |
2131 | static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req) | |
2132 | { | |
2133 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2134 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC); | |
2135 | } | |
2136 | static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req) | |
2137 | { | |
2138 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2139 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB); | |
2140 | } | |
2141 | static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req) | |
2142 | { | |
2143 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2144 | ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB); | |
2145 | } | |
2146 | ||
2147 | /* | |
2148 | * DES ecryption functions. | |
2149 | */ | |
2150 | static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req) | |
2151 | { | |
2152 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2153 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB); | |
2154 | } | |
2155 | static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req) | |
2156 | { | |
2157 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2158 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC); | |
2159 | } | |
2160 | static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req) | |
2161 | { | |
2162 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2163 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB); | |
2164 | } | |
2165 | static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req) | |
2166 | { | |
2167 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2168 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB); | |
2169 | } | |
2170 | ||
2171 | /* | |
2172 | * DES decryption functions. | |
2173 | */ | |
2174 | static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req) | |
2175 | { | |
2176 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2177 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB); | |
2178 | } | |
2179 | static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req) | |
2180 | { | |
2181 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2182 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC); | |
2183 | } | |
2184 | static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req) | |
2185 | { | |
2186 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2187 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB); | |
2188 | } | |
2189 | static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req) | |
2190 | { | |
2191 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2192 | ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB); | |
2193 | } | |
2194 | ||
2195 | /* | |
2196 | * 3DES ecryption functions. | |
2197 | */ | |
2198 | static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req) | |
2199 | { | |
2200 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2201 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB); | |
2202 | } | |
2203 | static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req) | |
2204 | { | |
2205 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2206 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC); | |
2207 | } | |
2208 | static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req) | |
2209 | { | |
2210 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2211 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB); | |
2212 | } | |
2213 | static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req) | |
2214 | { | |
2215 | return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, | |
2216 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB); | |
2217 | } | |
2218 | ||
16f56e8b | 2219 | /* 3DES decryption functions. */ |
f7d0561e EP |
2220 | static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req) |
2221 | { | |
2222 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2223 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB); | |
2224 | } | |
2225 | static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req) | |
2226 | { | |
2227 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2228 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC); | |
2229 | } | |
2230 | static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req) | |
2231 | { | |
2232 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2233 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB); | |
2234 | } | |
2235 | static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req) | |
2236 | { | |
2237 | return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, | |
2238 | ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB); | |
2239 | } | |
2240 | ||
16f56e8b | 2241 | struct hifn_alg_template { |
f7d0561e EP |
2242 | char name[CRYPTO_MAX_ALG_NAME]; |
2243 | char drv_name[CRYPTO_MAX_ALG_NAME]; | |
2244 | unsigned int bsize; | |
2245 | struct ablkcipher_alg ablkcipher; | |
2246 | }; | |
2247 | ||
2248 | static struct hifn_alg_template hifn_alg_templates[] = { | |
2249 | /* | |
2250 | * 3DES ECB, CBC, CFB and OFB modes. | |
2251 | */ | |
2252 | { | |
281d6bd4 | 2253 | .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8, |
f7d0561e EP |
2254 | .ablkcipher = { |
2255 | .min_keysize = HIFN_3DES_KEY_LENGTH, | |
2256 | .max_keysize = HIFN_3DES_KEY_LENGTH, | |
270e21da | 2257 | .setkey = hifn_des3_setkey, |
f7d0561e EP |
2258 | .encrypt = hifn_encrypt_3des_cfb, |
2259 | .decrypt = hifn_decrypt_3des_cfb, | |
2260 | }, | |
2261 | }, | |
2262 | { | |
281d6bd4 | 2263 | .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8, |
f7d0561e EP |
2264 | .ablkcipher = { |
2265 | .min_keysize = HIFN_3DES_KEY_LENGTH, | |
2266 | .max_keysize = HIFN_3DES_KEY_LENGTH, | |
270e21da | 2267 | .setkey = hifn_des3_setkey, |
f7d0561e EP |
2268 | .encrypt = hifn_encrypt_3des_ofb, |
2269 | .decrypt = hifn_decrypt_3des_ofb, | |
2270 | }, | |
2271 | }, | |
2272 | { | |
281d6bd4 | 2273 | .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8, |
f7d0561e | 2274 | .ablkcipher = { |
4b804b53 | 2275 | .ivsize = HIFN_IV_LENGTH, |
f7d0561e EP |
2276 | .min_keysize = HIFN_3DES_KEY_LENGTH, |
2277 | .max_keysize = HIFN_3DES_KEY_LENGTH, | |
270e21da | 2278 | .setkey = hifn_des3_setkey, |
f7d0561e EP |
2279 | .encrypt = hifn_encrypt_3des_cbc, |
2280 | .decrypt = hifn_decrypt_3des_cbc, | |
2281 | }, | |
2282 | }, | |
2283 | { | |
281d6bd4 | 2284 | .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8, |
f7d0561e EP |
2285 | .ablkcipher = { |
2286 | .min_keysize = HIFN_3DES_KEY_LENGTH, | |
2287 | .max_keysize = HIFN_3DES_KEY_LENGTH, | |
270e21da | 2288 | .setkey = hifn_des3_setkey, |
f7d0561e EP |
2289 | .encrypt = hifn_encrypt_3des_ecb, |
2290 | .decrypt = hifn_decrypt_3des_ecb, | |
2291 | }, | |
2292 | }, | |
2293 | ||
2294 | /* | |
2295 | * DES ECB, CBC, CFB and OFB modes. | |
2296 | */ | |
2297 | { | |
281d6bd4 | 2298 | .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8, |
f7d0561e EP |
2299 | .ablkcipher = { |
2300 | .min_keysize = HIFN_DES_KEY_LENGTH, | |
2301 | .max_keysize = HIFN_DES_KEY_LENGTH, | |
2302 | .setkey = hifn_setkey, | |
2303 | .encrypt = hifn_encrypt_des_cfb, | |
2304 | .decrypt = hifn_decrypt_des_cfb, | |
2305 | }, | |
2306 | }, | |
2307 | { | |
281d6bd4 | 2308 | .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8, |
f7d0561e EP |
2309 | .ablkcipher = { |
2310 | .min_keysize = HIFN_DES_KEY_LENGTH, | |
2311 | .max_keysize = HIFN_DES_KEY_LENGTH, | |
2312 | .setkey = hifn_setkey, | |
2313 | .encrypt = hifn_encrypt_des_ofb, | |
2314 | .decrypt = hifn_decrypt_des_ofb, | |
2315 | }, | |
2316 | }, | |
2317 | { | |
281d6bd4 | 2318 | .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8, |
f7d0561e | 2319 | .ablkcipher = { |
4b804b53 | 2320 | .ivsize = HIFN_IV_LENGTH, |
f7d0561e EP |
2321 | .min_keysize = HIFN_DES_KEY_LENGTH, |
2322 | .max_keysize = HIFN_DES_KEY_LENGTH, | |
2323 | .setkey = hifn_setkey, | |
2324 | .encrypt = hifn_encrypt_des_cbc, | |
2325 | .decrypt = hifn_decrypt_des_cbc, | |
2326 | }, | |
2327 | }, | |
2328 | { | |
281d6bd4 | 2329 | .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8, |
f7d0561e EP |
2330 | .ablkcipher = { |
2331 | .min_keysize = HIFN_DES_KEY_LENGTH, | |
2332 | .max_keysize = HIFN_DES_KEY_LENGTH, | |
2333 | .setkey = hifn_setkey, | |
2334 | .encrypt = hifn_encrypt_des_ecb, | |
2335 | .decrypt = hifn_decrypt_des_ecb, | |
2336 | }, | |
2337 | }, | |
2338 | ||
2339 | /* | |
2340 | * AES ECB, CBC, CFB and OFB modes. | |
2341 | */ | |
2342 | { | |
281d6bd4 | 2343 | .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16, |
f7d0561e EP |
2344 | .ablkcipher = { |
2345 | .min_keysize = AES_MIN_KEY_SIZE, | |
2346 | .max_keysize = AES_MAX_KEY_SIZE, | |
2347 | .setkey = hifn_setkey, | |
2348 | .encrypt = hifn_encrypt_aes_ecb, | |
2349 | .decrypt = hifn_decrypt_aes_ecb, | |
2350 | }, | |
2351 | }, | |
2352 | { | |
281d6bd4 | 2353 | .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16, |
f7d0561e | 2354 | .ablkcipher = { |
4b804b53 | 2355 | .ivsize = HIFN_AES_IV_LENGTH, |
f7d0561e EP |
2356 | .min_keysize = AES_MIN_KEY_SIZE, |
2357 | .max_keysize = AES_MAX_KEY_SIZE, | |
2358 | .setkey = hifn_setkey, | |
2359 | .encrypt = hifn_encrypt_aes_cbc, | |
2360 | .decrypt = hifn_decrypt_aes_cbc, | |
2361 | }, | |
2362 | }, | |
2363 | { | |
281d6bd4 | 2364 | .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16, |
f7d0561e EP |
2365 | .ablkcipher = { |
2366 | .min_keysize = AES_MIN_KEY_SIZE, | |
2367 | .max_keysize = AES_MAX_KEY_SIZE, | |
2368 | .setkey = hifn_setkey, | |
2369 | .encrypt = hifn_encrypt_aes_cfb, | |
2370 | .decrypt = hifn_decrypt_aes_cfb, | |
2371 | }, | |
2372 | }, | |
2373 | { | |
281d6bd4 | 2374 | .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16, |
f7d0561e EP |
2375 | .ablkcipher = { |
2376 | .min_keysize = AES_MIN_KEY_SIZE, | |
2377 | .max_keysize = AES_MAX_KEY_SIZE, | |
2378 | .setkey = hifn_setkey, | |
2379 | .encrypt = hifn_encrypt_aes_ofb, | |
2380 | .decrypt = hifn_decrypt_aes_ofb, | |
2381 | }, | |
2382 | }, | |
2383 | }; | |
2384 | ||
2385 | static int hifn_cra_init(struct crypto_tfm *tfm) | |
2386 | { | |
2387 | struct crypto_alg *alg = tfm->__crt_alg; | |
2388 | struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg); | |
2389 | struct hifn_context *ctx = crypto_tfm_ctx(tfm); | |
2390 | ||
2391 | ctx->dev = ha->dev; | |
5df4c0c6 | 2392 | tfm->crt_ablkcipher.reqsize = sizeof(struct hifn_request_context); |
f7d0561e EP |
2393 | return 0; |
2394 | } | |
2395 | ||
2396 | static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t) | |
2397 | { | |
2398 | struct hifn_crypto_alg *alg; | |
2399 | int err; | |
2400 | ||
16f56e8b | 2401 | alg = kzalloc(sizeof(*alg), GFP_KERNEL); |
f7d0561e EP |
2402 | if (!alg) |
2403 | return -ENOMEM; | |
2404 | ||
2405 | snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name); | |
281d6bd4 PM |
2406 | snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s", |
2407 | t->drv_name, dev->name); | |
f7d0561e EP |
2408 | |
2409 | alg->alg.cra_priority = 300; | |
d912bb76 NM |
2410 | alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
2411 | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC; | |
f7d0561e EP |
2412 | alg->alg.cra_blocksize = t->bsize; |
2413 | alg->alg.cra_ctxsize = sizeof(struct hifn_context); | |
d069033b | 2414 | alg->alg.cra_alignmask = 0; |
f7d0561e EP |
2415 | alg->alg.cra_type = &crypto_ablkcipher_type; |
2416 | alg->alg.cra_module = THIS_MODULE; | |
2417 | alg->alg.cra_u.ablkcipher = t->ablkcipher; | |
2418 | alg->alg.cra_init = hifn_cra_init; | |
2419 | ||
2420 | alg->dev = dev; | |
2421 | ||
2422 | list_add_tail(&alg->entry, &dev->alg_list); | |
2423 | ||
2424 | err = crypto_register_alg(&alg->alg); | |
2425 | if (err) { | |
2426 | list_del(&alg->entry); | |
2427 | kfree(alg); | |
2428 | } | |
2429 | ||
2430 | return err; | |
2431 | } | |
2432 | ||
2433 | static void hifn_unregister_alg(struct hifn_device *dev) | |
2434 | { | |
2435 | struct hifn_crypto_alg *a, *n; | |
2436 | ||
2437 | list_for_each_entry_safe(a, n, &dev->alg_list, entry) { | |
2438 | list_del(&a->entry); | |
2439 | crypto_unregister_alg(&a->alg); | |
2440 | kfree(a); | |
2441 | } | |
2442 | } | |
2443 | ||
2444 | static int hifn_register_alg(struct hifn_device *dev) | |
2445 | { | |
2446 | int i, err; | |
2447 | ||
16f56e8b | 2448 | for (i = 0; i < ARRAY_SIZE(hifn_alg_templates); ++i) { |
f7d0561e EP |
2449 | err = hifn_alg_alloc(dev, &hifn_alg_templates[i]); |
2450 | if (err) | |
2451 | goto err_out_exit; | |
2452 | } | |
2453 | ||
2454 | return 0; | |
2455 | ||
2456 | err_out_exit: | |
2457 | hifn_unregister_alg(dev); | |
2458 | return err; | |
2459 | } | |
2460 | ||
a1e6ef2f EP |
2461 | static void hifn_tasklet_callback(unsigned long data) |
2462 | { | |
2463 | struct hifn_device *dev = (struct hifn_device *)data; | |
2464 | ||
2465 | /* | |
2466 | * This is ok to call this without lock being held, | |
2467 | * althogh it modifies some parameters used in parallel, | |
2468 | * (like dev->success), but they are used in process | |
2469 | * context or update is atomic (like setting dev->sa[i] to NULL). | |
2470 | */ | |
d6a10c84 | 2471 | hifn_clear_rings(dev, 0); |
ed4f92e3 PM |
2472 | |
2473 | if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen) | |
2474 | hifn_process_queue(dev); | |
a1e6ef2f EP |
2475 | } |
2476 | ||
49cfe4db | 2477 | static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
f7d0561e EP |
2478 | { |
2479 | int err, i; | |
2480 | struct hifn_device *dev; | |
2481 | char name[8]; | |
2482 | ||
2483 | err = pci_enable_device(pdev); | |
2484 | if (err) | |
2485 | return err; | |
2486 | pci_set_master(pdev); | |
2487 | ||
284901a9 | 2488 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
f7d0561e EP |
2489 | if (err) |
2490 | goto err_out_disable_pci_device; | |
2491 | ||
2492 | snprintf(name, sizeof(name), "hifn%d", | |
16f56e8b | 2493 | atomic_inc_return(&hifn_dev_number) - 1); |
f7d0561e EP |
2494 | |
2495 | err = pci_request_regions(pdev, name); | |
2496 | if (err) | |
2497 | goto err_out_disable_pci_device; | |
2498 | ||
2499 | if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE || | |
2500 | pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE || | |
2501 | pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) { | |
cfeecab4 | 2502 | dev_err(&pdev->dev, "Broken hardware - I/O regions are too small.\n"); |
f7d0561e EP |
2503 | err = -ENODEV; |
2504 | goto err_out_free_regions; | |
2505 | } | |
2506 | ||
2507 | dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg), | |
2508 | GFP_KERNEL); | |
2509 | if (!dev) { | |
2510 | err = -ENOMEM; | |
2511 | goto err_out_free_regions; | |
2512 | } | |
2513 | ||
2514 | INIT_LIST_HEAD(&dev->alg_list); | |
2515 | ||
2516 | snprintf(dev->name, sizeof(dev->name), "%s", name); | |
2517 | spin_lock_init(&dev->lock); | |
2518 | ||
16f56e8b | 2519 | for (i = 0; i < 3; ++i) { |
f7d0561e EP |
2520 | unsigned long addr, size; |
2521 | ||
2522 | addr = pci_resource_start(pdev, i); | |
2523 | size = pci_resource_len(pdev, i); | |
2524 | ||
2525 | dev->bar[i] = ioremap_nocache(addr, size); | |
c2ff861d PST |
2526 | if (!dev->bar[i]) { |
2527 | err = -ENOMEM; | |
f7d0561e | 2528 | goto err_out_unmap_bars; |
c2ff861d | 2529 | } |
f7d0561e EP |
2530 | } |
2531 | ||
7e835084 JP |
2532 | dev->desc_virt = pci_zalloc_consistent(pdev, sizeof(struct hifn_dma), |
2533 | &dev->desc_dma); | |
f7d0561e | 2534 | if (!dev->desc_virt) { |
cfeecab4 | 2535 | dev_err(&pdev->dev, "Failed to allocate descriptor rings.\n"); |
c2ff861d | 2536 | err = -ENOMEM; |
3ec858de | 2537 | goto err_out_unmap_bars; |
f7d0561e | 2538 | } |
f7d0561e EP |
2539 | |
2540 | dev->pdev = pdev; | |
2541 | dev->irq = pdev->irq; | |
2542 | ||
16f56e8b | 2543 | for (i = 0; i < HIFN_D_RES_RSIZE; ++i) |
f7d0561e EP |
2544 | dev->sa[i] = NULL; |
2545 | ||
2546 | pci_set_drvdata(pdev, dev); | |
2547 | ||
a1e6ef2f EP |
2548 | tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev); |
2549 | ||
f7d0561e EP |
2550 | crypto_init_queue(&dev->queue, 1); |
2551 | ||
2552 | err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev); | |
2553 | if (err) { | |
cfeecab4 LC |
2554 | dev_err(&pdev->dev, "Failed to request IRQ%d: err: %d.\n", |
2555 | dev->irq, err); | |
f7d0561e EP |
2556 | dev->irq = 0; |
2557 | goto err_out_free_desc; | |
2558 | } | |
2559 | ||
2560 | err = hifn_start_device(dev); | |
2561 | if (err) | |
2562 | goto err_out_free_irq; | |
2563 | ||
fcd06755 | 2564 | err = hifn_register_rng(dev); |
f7d0561e EP |
2565 | if (err) |
2566 | goto err_out_stop_device; | |
2567 | ||
fcd06755 PM |
2568 | err = hifn_register_alg(dev); |
2569 | if (err) | |
2570 | goto err_out_unregister_rng; | |
2571 | ||
f7d0561e EP |
2572 | INIT_DELAYED_WORK(&dev->work, hifn_work); |
2573 | schedule_delayed_work(&dev->work, HZ); | |
2574 | ||
cfeecab4 LC |
2575 | dev_dbg(&pdev->dev, "HIFN crypto accelerator card at %s has been " |
2576 | "successfully registered as %s.\n", | |
2577 | pci_name(pdev), dev->name); | |
f7d0561e EP |
2578 | |
2579 | return 0; | |
2580 | ||
fcd06755 PM |
2581 | err_out_unregister_rng: |
2582 | hifn_unregister_rng(dev); | |
f7d0561e EP |
2583 | err_out_stop_device: |
2584 | hifn_reset_dma(dev, 1); | |
2585 | hifn_stop_device(dev); | |
2586 | err_out_free_irq: | |
b0226653 | 2587 | free_irq(dev->irq, dev); |
a1e6ef2f | 2588 | tasklet_kill(&dev->tasklet); |
f7d0561e EP |
2589 | err_out_free_desc: |
2590 | pci_free_consistent(pdev, sizeof(struct hifn_dma), | |
2591 | dev->desc_virt, dev->desc_dma); | |
2592 | ||
f7d0561e | 2593 | err_out_unmap_bars: |
16f56e8b | 2594 | for (i = 0; i < 3; ++i) |
f7d0561e EP |
2595 | if (dev->bar[i]) |
2596 | iounmap(dev->bar[i]); | |
1964e333 | 2597 | kfree(dev); |
f7d0561e EP |
2598 | |
2599 | err_out_free_regions: | |
2600 | pci_release_regions(pdev); | |
2601 | ||
2602 | err_out_disable_pci_device: | |
2603 | pci_disable_device(pdev); | |
2604 | ||
2605 | return err; | |
2606 | } | |
2607 | ||
49cfe4db | 2608 | static void hifn_remove(struct pci_dev *pdev) |
f7d0561e EP |
2609 | { |
2610 | int i; | |
2611 | struct hifn_device *dev; | |
2612 | ||
2613 | dev = pci_get_drvdata(pdev); | |
2614 | ||
2615 | if (dev) { | |
f4e523f2 | 2616 | cancel_delayed_work_sync(&dev->work); |
f7d0561e | 2617 | |
fcd06755 | 2618 | hifn_unregister_rng(dev); |
f7d0561e EP |
2619 | hifn_unregister_alg(dev); |
2620 | hifn_reset_dma(dev, 1); | |
2621 | hifn_stop_device(dev); | |
2622 | ||
b0226653 | 2623 | free_irq(dev->irq, dev); |
a1e6ef2f | 2624 | tasklet_kill(&dev->tasklet); |
f7d0561e EP |
2625 | |
2626 | hifn_flush(dev); | |
2627 | ||
2628 | pci_free_consistent(pdev, sizeof(struct hifn_dma), | |
2629 | dev->desc_virt, dev->desc_dma); | |
16f56e8b | 2630 | for (i = 0; i < 3; ++i) |
f7d0561e EP |
2631 | if (dev->bar[i]) |
2632 | iounmap(dev->bar[i]); | |
2633 | ||
2634 | kfree(dev); | |
2635 | } | |
2636 | ||
2637 | pci_release_regions(pdev); | |
2638 | pci_disable_device(pdev); | |
2639 | } | |
2640 | ||
2641 | static struct pci_device_id hifn_pci_tbl[] = { | |
2642 | { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) }, | |
2643 | { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) }, | |
2644 | { 0 } | |
2645 | }; | |
2646 | MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); | |
2647 | ||
2648 | static struct pci_driver hifn_pci_driver = { | |
2649 | .name = "hifn795x", | |
2650 | .id_table = hifn_pci_tbl, | |
2651 | .probe = hifn_probe, | |
49cfe4db | 2652 | .remove = hifn_remove, |
f7d0561e EP |
2653 | }; |
2654 | ||
f3d8fe40 | 2655 | static int __init hifn_init(void) |
f7d0561e | 2656 | { |
37a8023c | 2657 | unsigned int freq; |
f7d0561e EP |
2658 | int err; |
2659 | ||
75b76625 RW |
2660 | /* HIFN supports only 32-bit addresses */ |
2661 | BUILD_BUG_ON(sizeof(dma_addr_t) != 4); | |
a44b56cc | 2662 | |
37a8023c PM |
2663 | if (strncmp(hifn_pll_ref, "ext", 3) && |
2664 | strncmp(hifn_pll_ref, "pci", 3)) { | |
cfeecab4 | 2665 | pr_err("hifn795x: invalid hifn_pll_ref clock, must be pci or ext"); |
37a8023c PM |
2666 | return -EINVAL; |
2667 | } | |
2668 | ||
2669 | /* | |
2670 | * For the 7955/7956 the reference clock frequency must be in the | |
2671 | * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz, | |
2672 | * but this chip is currently not supported. | |
2673 | */ | |
2674 | if (hifn_pll_ref[3] != '\0') { | |
2675 | freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10); | |
2676 | if (freq < 20 || freq > 100) { | |
cfeecab4 LC |
2677 | pr_err("hifn795x: invalid hifn_pll_ref frequency, must" |
2678 | "be in the range of 20-100"); | |
37a8023c PM |
2679 | return -EINVAL; |
2680 | } | |
2681 | } | |
2682 | ||
f7d0561e EP |
2683 | err = pci_register_driver(&hifn_pci_driver); |
2684 | if (err < 0) { | |
cfeecab4 LC |
2685 | pr_err("Failed to register PCI driver for %s device.\n", |
2686 | hifn_pci_driver.name); | |
f7d0561e EP |
2687 | return -ENODEV; |
2688 | } | |
2689 | ||
cfeecab4 LC |
2690 | pr_info("Driver for HIFN 795x crypto accelerator chip " |
2691 | "has been successfully registered.\n"); | |
f7d0561e EP |
2692 | |
2693 | return 0; | |
2694 | } | |
2695 | ||
f3d8fe40 | 2696 | static void __exit hifn_fini(void) |
f7d0561e EP |
2697 | { |
2698 | pci_unregister_driver(&hifn_pci_driver); | |
2699 | ||
cfeecab4 LC |
2700 | pr_info("Driver for HIFN 795x crypto accelerator chip " |
2701 | "has been successfully unregistered.\n"); | |
f7d0561e EP |
2702 | } |
2703 | ||
2704 | module_init(hifn_init); | |
2705 | module_exit(hifn_fini); | |
2706 | ||
2707 | MODULE_LICENSE("GPL"); | |
2708 | MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>"); | |
2709 | MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip."); |