[linux-2.6-block.git] / drivers / crypto / chelsio / chcr_crypto.h

/*
 * This file is part of the Chelsio T6 Crypto driver for Linux.
 *
 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef __CHCR_CRYPTO_H__
#define __CHCR_CRYPTO_H__

#define GHASH_BLOCK_SIZE    16
#define GHASH_DIGEST_SIZE   16

#define CCM_B0_SIZE             16
#define CCM_AAD_FIELD_SIZE      2
// 511 - 16(For IV)
#define T6_MAX_AAD_SIZE 495


/* Define following if h/w is not dropping the AAD and IV data before
 * giving the processed data
 */

#define CHCR_CRA_PRIORITY 500
#define CHCR_AEAD_PRIORITY 6000
#define CHCR_AES_MAX_KEY_LEN  (2 * (AES_MAX_KEY_SIZE)) /* consider xts */
#define CHCR_MAX_CRYPTO_IV_LEN 16 /* AES IV len */

#define CHCR_MAX_AUTHENC_AES_KEY_LEN 32 /* max aes key length*/
#define CHCR_MAX_AUTHENC_SHA_KEY_LEN 128 /* max sha key length*/

#define CHCR_GIVENCRYPT_OP 2
/* CPL/SCMD parameters */

#define CHCR_ENCRYPT_OP 0
#define CHCR_DECRYPT_OP 1

#define CHCR_SCMD_SEQ_NO_CTRL_32BIT     1
#define CHCR_SCMD_SEQ_NO_CTRL_48BIT     2
#define CHCR_SCMD_SEQ_NO_CTRL_64BIT     3

#define CHCR_SCMD_PROTO_VERSION_GENERIC 4

#define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
#define CHCR_SCMD_AUTH_CTRL_CIPHER_AUTH 1

#define CHCR_SCMD_CIPHER_MODE_NOP               0
#define CHCR_SCMD_CIPHER_MODE_AES_CBC           1
#define CHCR_SCMD_CIPHER_MODE_AES_GCM           2
#define CHCR_SCMD_CIPHER_MODE_AES_CTR           3
#define CHCR_SCMD_CIPHER_MODE_GENERIC_AES       4
#define CHCR_SCMD_CIPHER_MODE_AES_XTS           6
#define CHCR_SCMD_CIPHER_MODE_AES_CCM           7

#define CHCR_SCMD_AUTH_MODE_NOP             0
#define CHCR_SCMD_AUTH_MODE_SHA1            1
#define CHCR_SCMD_AUTH_MODE_SHA224          2
#define CHCR_SCMD_AUTH_MODE_SHA256          3
#define CHCR_SCMD_AUTH_MODE_GHASH           4
#define CHCR_SCMD_AUTH_MODE_SHA512_224      5
#define CHCR_SCMD_AUTH_MODE_SHA512_256      6
#define CHCR_SCMD_AUTH_MODE_SHA512_384      7
#define CHCR_SCMD_AUTH_MODE_SHA512_512      8
#define CHCR_SCMD_AUTH_MODE_CBCMAC          9
#define CHCR_SCMD_AUTH_MODE_CMAC            10

#define CHCR_SCMD_HMAC_CTRL_NOP             0
#define CHCR_SCMD_HMAC_CTRL_NO_TRUNC        1
#define CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366   2
#define CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT     3
#define CHCR_SCMD_HMAC_CTRL_PL1		    4
#define CHCR_SCMD_HMAC_CTRL_PL2		    5
#define CHCR_SCMD_HMAC_CTRL_PL3		    6
#define CHCR_SCMD_HMAC_CTRL_DIV2	    7
#define VERIFY_HW 0
#define VERIFY_SW 1

#define CHCR_SCMD_IVGEN_CTRL_HW             0
#define CHCR_SCMD_IVGEN_CTRL_SW             1
/* This are not really mac key size. They are intermediate values
 * of sha engine and its size
 */
#define CHCR_KEYCTX_MAC_KEY_SIZE_128        0
#define CHCR_KEYCTX_MAC_KEY_SIZE_160        1
#define CHCR_KEYCTX_MAC_KEY_SIZE_192        2
#define CHCR_KEYCTX_MAC_KEY_SIZE_256        3
#define CHCR_KEYCTX_MAC_KEY_SIZE_512        4
#define CHCR_KEYCTX_CIPHER_KEY_SIZE_128     0
#define CHCR_KEYCTX_CIPHER_KEY_SIZE_192     1
#define CHCR_KEYCTX_CIPHER_KEY_SIZE_256     2
#define CHCR_KEYCTX_NO_KEY                  15

#define CHCR_CPL_FW4_PLD_IV_OFFSET          (5 * 64) /* bytes. flt #5 and #6 */
#define CHCR_CPL_FW4_PLD_HASH_RESULT_OFFSET (7 * 64) /* bytes. flt #7 */
#define CHCR_CPL_FW4_PLD_DATA_SIZE          (4 * 64) /* bytes. flt #4 to #7 */

#define KEY_CONTEXT_HDR_SALT_AND_PAD	    16
#define flits_to_bytes(x)  (x * 8)

#define IV_NOP                  0
#define IV_IMMEDIATE            1
#define IV_DSGL			2

#define AEAD_H_SIZE             16

#define CRYPTO_ALG_SUB_TYPE_MASK            0x0f000000
#define CRYPTO_ALG_SUB_TYPE_HASH_HMAC       0x01000000
#define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106    0x02000000
#define CRYPTO_ALG_SUB_TYPE_AEAD_GCM	    0x03000000
#define CRYPTO_ALG_SUB_TYPE_CBC_SHA	    0x04000000
#define CRYPTO_ALG_SUB_TYPE_AEAD_CCM        0x05000000
#define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309    0x06000000
#define CRYPTO_ALG_SUB_TYPE_CBC_NULL	    0x07000000
#define CRYPTO_ALG_SUB_TYPE_CTR             0x08000000
#define CRYPTO_ALG_SUB_TYPE_CTR_RFC3686     0x09000000
#define CRYPTO_ALG_SUB_TYPE_XTS		    0x0a000000
#define CRYPTO_ALG_SUB_TYPE_CBC		    0x0b000000
#define CRYPTO_ALG_SUB_TYPE_CTR_SHA	    0x0c000000
#define CRYPTO_ALG_SUB_TYPE_CTR_NULL   0x0d000000
#define CRYPTO_ALG_TYPE_HMAC (CRYPTO_ALG_TYPE_AHASH |\
			      CRYPTO_ALG_SUB_TYPE_HASH_HMAC)

#define MAX_SCRATCH_PAD_SIZE    32

#define CHCR_HASH_MAX_BLOCK_SIZE_64  64
#define CHCR_HASH_MAX_BLOCK_SIZE_128 128
#define CHCR_SRC_SG_SIZE (0x10000 - sizeof(int))
#define CHCR_DST_SG_SIZE 2048

static inline struct chcr_context *a_ctx(struct crypto_aead *tfm)
{
	return crypto_aead_ctx(tfm);
}

static inline struct chcr_context *c_ctx(struct crypto_ablkcipher *tfm)
{
	return crypto_ablkcipher_ctx(tfm);
}

static inline struct chcr_context *h_ctx(struct crypto_ahash *tfm)
{
	return crypto_tfm_ctx(crypto_ahash_tfm(tfm));
}

struct ablk_ctx {
	struct crypto_sync_skcipher *sw_cipher;
	struct crypto_cipher *aes_generic;
	__be32 key_ctx_hdr;
	unsigned int enckey_len;
	unsigned char ciph_mode;
	u8 key[CHCR_AES_MAX_KEY_LEN];
	u8 nonce[4];
	u8 rrkey[AES_MAX_KEY_SIZE];
};
struct chcr_aead_reqctx {
	struct	sk_buff	*skb;
	dma_addr_t iv_dma;
	dma_addr_t b0_dma;
	unsigned int b0_len;
	unsigned int op;
	u16 imm;
	u16 verify;
	u8 iv[CHCR_MAX_CRYPTO_IV_LEN + MAX_SCRATCH_PAD_SIZE];
	u8 *scratch_pad;
};

struct ulptx_walk {
	struct ulptx_sgl *sgl;
	unsigned int nents;
	unsigned int pair_idx;
	unsigned int last_sg_len;
	struct scatterlist *last_sg;
	struct ulptx_sge_pair *pair;

};

struct dsgl_walk {
	unsigned int nents;
	unsigned int last_sg_len;
	struct scatterlist *last_sg;
	struct cpl_rx_phys_dsgl *dsgl;
	struct phys_sge_pairs *to;
};

struct chcr_gcm_ctx {
	u8 ghash_h[AEAD_H_SIZE];
};

struct chcr_authenc_ctx {
	u8 dec_rrkey[AES_MAX_KEY_SIZE];
	u8 h_iopad[2 * CHCR_HASH_MAX_DIGEST_SIZE];
	unsigned char auth_mode;
};

struct __aead_ctx {
	struct chcr_gcm_ctx gcm[0];
	struct chcr_authenc_ctx authenc[0];
};

struct chcr_aead_ctx {
	__be32 key_ctx_hdr;
	unsigned int enckey_len;
	struct crypto_aead *sw_cipher;
	u8 salt[MAX_SALT];
	u8 key[CHCR_AES_MAX_KEY_LEN];
	u8 nonce[4];
	u16 hmac_ctrl;
	u16 mayverify;
	struct	__aead_ctx ctx[0];
};

struct hmac_ctx {
	struct crypto_shash *base_hash;
	u8 ipad[CHCR_HASH_MAX_BLOCK_SIZE_128];
	u8 opad[CHCR_HASH_MAX_BLOCK_SIZE_128];
};

struct __crypto_ctx {
	struct hmac_ctx hmacctx[0];
	struct ablk_ctx ablkctx[0];
	struct chcr_aead_ctx aeadctx[0];
};

struct chcr_context {
	struct chcr_dev *dev;
	unsigned char tx_qidx;
	unsigned char rx_qidx;
	unsigned char tx_chan_id;
	unsigned char pci_chan_id;
	struct __crypto_ctx crypto_ctx[0];
};

struct chcr_hctx_per_wr {
	struct scatterlist *srcsg;
	struct sk_buff *skb;
	dma_addr_t dma_addr;
	u32 dma_len;
	unsigned int src_ofst;
	unsigned int processed;
	u32 result;
	u8 is_sg_map;
	u8 imm;
	/*Final callback called. Driver cannot rely on nbytes to decide
	 * final call
	 */
	u8 isfinal;
};

struct chcr_ahash_req_ctx {
	struct chcr_hctx_per_wr hctx_wr;
	u8 *reqbfr;
	u8 *skbfr;
	/* SKB which is being sent to the hardware for processing */
	u64 data_len;  /* Data len till time */
	u8 reqlen;
	u8 partial_hash[CHCR_HASH_MAX_DIGEST_SIZE];
	u8 bfr1[CHCR_HASH_MAX_BLOCK_SIZE_128];
	u8 bfr2[CHCR_HASH_MAX_BLOCK_SIZE_128];
};

struct chcr_blkcipher_req_ctx {
	struct sk_buff *skb;
	struct scatterlist *dstsg;
	unsigned int processed;
	unsigned int last_req_len;
	struct scatterlist *srcsg;
	unsigned int src_ofst;
	unsigned int dst_ofst;
	unsigned int op;
	u16 imm;
	u8 iv[CHCR_MAX_CRYPTO_IV_LEN];
};

struct chcr_alg_template {
	u32 type;
	u32 is_registered;
	union {
		struct crypto_alg crypto;
		struct ahash_alg hash;
		struct aead_alg aead;
	} alg;
};

typedef struct sk_buff *(*create_wr_t)(struct aead_request *req,
				       unsigned short qid,
				       int size);

void chcr_verify_tag(struct aead_request *req, u8 *input, int *err);
int chcr_aead_dma_map(struct device *dev, struct aead_request *req,
		      unsigned short op_type);
void chcr_aead_dma_unmap(struct device *dev, struct aead_request *req,
			 unsigned short op_type);
void chcr_add_aead_dst_ent(struct aead_request *req,
			   struct cpl_rx_phys_dsgl *phys_cpl,
			   unsigned short qid);
void chcr_add_aead_src_ent(struct aead_request *req, struct ulptx_sgl *ulptx);
void chcr_add_cipher_src_ent(struct ablkcipher_request *req,
			     void *ulptx,
			     struct  cipher_wr_param *wrparam);
int chcr_cipher_dma_map(struct device *dev, struct ablkcipher_request *req);
void chcr_cipher_dma_unmap(struct device *dev, struct ablkcipher_request *req);
void chcr_add_cipher_dst_ent(struct ablkcipher_request *req,
			     struct cpl_rx_phys_dsgl *phys_cpl,
			     struct  cipher_wr_param *wrparam,
			     unsigned short qid);
int sg_nents_len_skip(struct scatterlist *sg, u64 len, u64 skip);
void chcr_add_hash_src_ent(struct ahash_request *req, struct ulptx_sgl *ulptx,
			   struct hash_wr_param *param);
int chcr_hash_dma_map(struct device *dev, struct ahash_request *req);
void chcr_hash_dma_unmap(struct device *dev, struct ahash_request *req);
void chcr_aead_common_exit(struct aead_request *req);
#endif /* __CHCR_CRYPTO_H__ */
Commit	Line	Data
324429d7 HS	1	/*
	2	* This file is part of the Chelsio T6 Crypto driver for Linux.
	3	*
	4	* Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* COPYING in the main directory of this source tree, or the
	10	* OpenIB.org BSD license below:
	11	*
	12	* Redistribution and use in source and binary forms, with or
	13	* without modification, are permitted provided that the following
	14	* conditions are met:
	15	*
	16	* - Redistributions of source code must retain the above
	17	* copyright notice, this list of conditions and the following
	18	* disclaimer.
	19	*
	20	* - Redistributions in binary form must reproduce the above
	21	* copyright notice, this list of conditions and the following
	22	* disclaimer in the documentation and/or other materials
	23	* provided with the distribution.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	26	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	27	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	28	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	29	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	30	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	31	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	32	* SOFTWARE.
	33	*
	34	*/
	35
	36	#ifndef __CHCR_CRYPTO_H__
	37	#define __CHCR_CRYPTO_H__
	38
2debd332 HJ	39	#define GHASH_BLOCK_SIZE 16
	40	#define GHASH_DIGEST_SIZE 16
	41
	42	#define CCM_B0_SIZE 16
	43	#define CCM_AAD_FIELD_SIZE 2
1f479e4c HJ	44	// 511 - 16(For IV)
1f479e4c HJ	45	#define T6_MAX_AAD_SIZE 495
2debd332 HJ	46
2debd332 HJ	47
324429d7 HS	48	/* Define following if h/w is not dropping the AAD and IV data before
	49	* giving the processed data
	50	*/
	51
e29abda5 HJ	52	#define CHCR_CRA_PRIORITY 500
e29abda5 HJ	53	#define CHCR_AEAD_PRIORITY 6000
324429d7 HS	54	#define CHCR_AES_MAX_KEY_LEN (2 * (AES_MAX_KEY_SIZE)) /* consider xts */
	55	#define CHCR_MAX_CRYPTO_IV_LEN 16 /* AES IV len */
	56
	57	#define CHCR_MAX_AUTHENC_AES_KEY_LEN 32 /* max aes key length*/
	58	#define CHCR_MAX_AUTHENC_SHA_KEY_LEN 128 /* max sha key length*/
	59
	60	#define CHCR_GIVENCRYPT_OP 2
	61	/* CPL/SCMD parameters */
	62
	63	#define CHCR_ENCRYPT_OP 0
	64	#define CHCR_DECRYPT_OP 1
	65
	66	#define CHCR_SCMD_SEQ_NO_CTRL_32BIT 1
	67	#define CHCR_SCMD_SEQ_NO_CTRL_48BIT 2
	68	#define CHCR_SCMD_SEQ_NO_CTRL_64BIT 3
	69
	70	#define CHCR_SCMD_PROTO_VERSION_GENERIC 4
	71
	72	#define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
	73	#define CHCR_SCMD_AUTH_CTRL_CIPHER_AUTH 1
	74
2debd332 HJ	75	#define CHCR_SCMD_CIPHER_MODE_NOP 0
	76	#define CHCR_SCMD_CIPHER_MODE_AES_CBC 1
	77	#define CHCR_SCMD_CIPHER_MODE_AES_GCM 2
	78	#define CHCR_SCMD_CIPHER_MODE_AES_CTR 3
	79	#define CHCR_SCMD_CIPHER_MODE_GENERIC_AES 4
	80	#define CHCR_SCMD_CIPHER_MODE_AES_XTS 6
	81	#define CHCR_SCMD_CIPHER_MODE_AES_CCM 7
324429d7 HS	82
	83	#define CHCR_SCMD_AUTH_MODE_NOP 0
	84	#define CHCR_SCMD_AUTH_MODE_SHA1 1
	85	#define CHCR_SCMD_AUTH_MODE_SHA224 2
	86	#define CHCR_SCMD_AUTH_MODE_SHA256 3
2debd332	87	#define CHCR_SCMD_AUTH_MODE_GHASH 4
324429d7 HS	88	#define CHCR_SCMD_AUTH_MODE_SHA512_224 5
	89	#define CHCR_SCMD_AUTH_MODE_SHA512_256 6
	90	#define CHCR_SCMD_AUTH_MODE_SHA512_384 7
	91	#define CHCR_SCMD_AUTH_MODE_SHA512_512 8
2debd332 HJ	92	#define CHCR_SCMD_AUTH_MODE_CBCMAC 9
2debd332 HJ	93	#define CHCR_SCMD_AUTH_MODE_CMAC 10
324429d7 HS	94
	95	#define CHCR_SCMD_HMAC_CTRL_NOP 0
	96	#define CHCR_SCMD_HMAC_CTRL_NO_TRUNC 1
2debd332 HJ	97	#define CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366 2
	98	#define CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT 3
	99	#define CHCR_SCMD_HMAC_CTRL_PL1 4
	100	#define CHCR_SCMD_HMAC_CTRL_PL2 5
	101	#define CHCR_SCMD_HMAC_CTRL_PL3 6
	102	#define CHCR_SCMD_HMAC_CTRL_DIV2 7
	103	#define VERIFY_HW 0
	104	#define VERIFY_SW 1
324429d7 HS	105
	106	#define CHCR_SCMD_IVGEN_CTRL_HW 0
	107	#define CHCR_SCMD_IVGEN_CTRL_SW 1
	108	/* This are not really mac key size. They are intermediate values
	109	* of sha engine and its size
	110	*/
	111	#define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
	112	#define CHCR_KEYCTX_MAC_KEY_SIZE_160 1
	113	#define CHCR_KEYCTX_MAC_KEY_SIZE_192 2
	114	#define CHCR_KEYCTX_MAC_KEY_SIZE_256 3
	115	#define CHCR_KEYCTX_MAC_KEY_SIZE_512 4
	116	#define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
	117	#define CHCR_KEYCTX_CIPHER_KEY_SIZE_192 1
	118	#define CHCR_KEYCTX_CIPHER_KEY_SIZE_256 2
	119	#define CHCR_KEYCTX_NO_KEY 15
	120
	121	#define CHCR_CPL_FW4_PLD_IV_OFFSET (5 * 64) /* bytes. flt #5 and #6 */
	122	#define CHCR_CPL_FW4_PLD_HASH_RESULT_OFFSET (7 * 64) /* bytes. flt #7 */
	123	#define CHCR_CPL_FW4_PLD_DATA_SIZE (4 * 64) /* bytes. flt #4 to #7 */
	124
	125	#define KEY_CONTEXT_HDR_SALT_AND_PAD 16
	126	#define flits_to_bytes(x) (x * 8)
	127
	128	#define IV_NOP 0
	129	#define IV_IMMEDIATE 1
	130	#define IV_DSGL 2
	131
2debd332 HJ	132	#define AEAD_H_SIZE 16
2debd332 HJ	133
324429d7 HS	134	#define CRYPTO_ALG_SUB_TYPE_MASK 0x0f000000
324429d7 HS	135	#define CRYPTO_ALG_SUB_TYPE_HASH_HMAC 0x01000000
2debd332 HJ	136	#define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106 0x02000000
2debd332 HJ	137	#define CRYPTO_ALG_SUB_TYPE_AEAD_GCM 0x03000000
3d64bd67	138	#define CRYPTO_ALG_SUB_TYPE_CBC_SHA 0x04000000
2debd332 HJ	139	#define CRYPTO_ALG_SUB_TYPE_AEAD_CCM 0x05000000
2debd332 HJ	140	#define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309 0x06000000
3d64bd67	141	#define CRYPTO_ALG_SUB_TYPE_CBC_NULL 0x07000000
2debd332	142	#define CRYPTO_ALG_SUB_TYPE_CTR 0x08000000
b8fd1f41 HJ	143	#define CRYPTO_ALG_SUB_TYPE_CTR_RFC3686 0x09000000
	144	#define CRYPTO_ALG_SUB_TYPE_XTS 0x0a000000
	145	#define CRYPTO_ALG_SUB_TYPE_CBC 0x0b000000
3d64bd67 HJ	146	#define CRYPTO_ALG_SUB_TYPE_CTR_SHA 0x0c000000
3d64bd67 HJ	147	#define CRYPTO_ALG_SUB_TYPE_CTR_NULL 0x0d000000
324429d7 HS	148	#define CRYPTO_ALG_TYPE_HMAC (CRYPTO_ALG_TYPE_AHASH \|\
	149	CRYPTO_ALG_SUB_TYPE_HASH_HMAC)
	150
324429d7 HS	151	#define MAX_SCRATCH_PAD_SIZE 32
	152
	153	#define CHCR_HASH_MAX_BLOCK_SIZE_64 64
	154	#define CHCR_HASH_MAX_BLOCK_SIZE_128 128
2f47d580 HJ	155	#define CHCR_SRC_SG_SIZE (0x10000 - sizeof(int))
2f47d580 HJ	156	#define CHCR_DST_SG_SIZE 2048
324429d7	157
2f47d580 HJ	158	static inline struct chcr_context a_ctx(struct crypto_aead tfm)
	159	{
	160	return crypto_aead_ctx(tfm);
	161	}
	162
	163	static inline struct chcr_context c_ctx(struct crypto_ablkcipher tfm)
	164	{
	165	return crypto_ablkcipher_ctx(tfm);
	166	}
	167
	168	static inline struct chcr_context h_ctx(struct crypto_ahash tfm)
	169	{
	170	return crypto_tfm_ctx(crypto_ahash_tfm(tfm));
	171	}
324429d7 HS	172
324429d7 HS	173	struct ablk_ctx {
28874f26	174	struct crypto_sync_skcipher *sw_cipher;
d3f1d2f7	175	struct crypto_cipher *aes_generic;
324429d7 HS	176	__be32 key_ctx_hdr;
324429d7 HS	177	unsigned int enckey_len;
324429d7	178	unsigned char ciph_mode;
b8fd1f41 HJ	179	u8 key[CHCR_AES_MAX_KEY_LEN];
b8fd1f41 HJ	180	u8 nonce[4];
5c86a8ff	181	u8 rrkey[AES_MAX_KEY_SIZE];
324429d7	182	};
2debd332 HJ	183	struct chcr_aead_reqctx {
2debd332 HJ	184	struct sk_buff *skb;
2f47d580 HJ	185	dma_addr_t iv_dma;
	186	dma_addr_t b0_dma;
	187	unsigned int b0_len;
	188	unsigned int op;
2f47d580	189	u16 imm;
2debd332	190	u16 verify;
4262c98a HJ	191	u8 iv[CHCR_MAX_CRYPTO_IV_LEN + MAX_SCRATCH_PAD_SIZE];
4262c98a HJ	192	u8 *scratch_pad;
2debd332 HJ	193	};
2debd332 HJ	194
2f47d580 HJ	195	struct ulptx_walk {
	196	struct ulptx_sgl *sgl;
	197	unsigned int nents;
	198	unsigned int pair_idx;
	199	unsigned int last_sg_len;
	200	struct scatterlist *last_sg;
	201	struct ulptx_sge_pair *pair;
	202
	203	};
	204
	205	struct dsgl_walk {
	206	unsigned int nents;
	207	unsigned int last_sg_len;
	208	struct scatterlist *last_sg;
	209	struct cpl_rx_phys_dsgl *dsgl;
	210	struct phys_sge_pairs *to;
	211	};
	212
2debd332 HJ	213	struct chcr_gcm_ctx {
	214	u8 ghash_h[AEAD_H_SIZE];
	215	};
	216
	217	struct chcr_authenc_ctx {
	218	u8 dec_rrkey[AES_MAX_KEY_SIZE];
	219	u8 h_iopad[2 * CHCR_HASH_MAX_DIGEST_SIZE];
	220	unsigned char auth_mode;
	221	};
	222
	223	struct __aead_ctx {
	224	struct chcr_gcm_ctx gcm[0];
	225	struct chcr_authenc_ctx authenc[0];
	226	};
	227
2debd332 HJ	228	struct chcr_aead_ctx {
	229	__be32 key_ctx_hdr;
	230	unsigned int enckey_len;
0e93708d	231	struct crypto_aead *sw_cipher;
2debd332 HJ	232	u8 salt[MAX_SALT];
2debd332 HJ	233	u8 key[CHCR_AES_MAX_KEY_LEN];
3d64bd67	234	u8 nonce[4];
2debd332 HJ	235	u16 hmac_ctrl;
	236	u16 mayverify;
	237	struct __aead_ctx ctx[0];
	238	};
	239
324429d7	240	struct hmac_ctx {
e7922729	241	struct crypto_shash *base_hash;
324429d7 HS	242	u8 ipad[CHCR_HASH_MAX_BLOCK_SIZE_128];
	243	u8 opad[CHCR_HASH_MAX_BLOCK_SIZE_128];
	244	};
	245
	246	struct __crypto_ctx {
	247	struct hmac_ctx hmacctx[0];
	248	struct ablk_ctx ablkctx[0];
2debd332	249	struct chcr_aead_ctx aeadctx[0];
324429d7 HS	250	};
	251
	252	struct chcr_context {
	253	struct chcr_dev *dev;
72a56ca9 HJ	254	unsigned char tx_qidx;
72a56ca9 HJ	255	unsigned char rx_qidx;
add92a81 HJ	256	unsigned char tx_chan_id;
add92a81 HJ	257	unsigned char pci_chan_id;
324429d7 HS	258	struct __crypto_ctx crypto_ctx[0];
	259	};
	260
5110e655 HJ	261	struct chcr_hctx_per_wr {
	262	struct scatterlist *srcsg;
	263	struct sk_buff *skb;
	264	dma_addr_t dma_addr;
	265	u32 dma_len;
	266	unsigned int src_ofst;
	267	unsigned int processed;
324429d7	268	u32 result;
5110e655 HJ	269	u8 is_sg_map;
	270	u8 imm;
	271	/*Final callback called. Driver cannot rely on nbytes to decide
	272	* final call
	273	*/
	274	u8 isfinal;
	275	};
	276
	277	struct chcr_ahash_req_ctx {
	278	struct chcr_hctx_per_wr hctx_wr;
44fce12a HJ	279	u8 *reqbfr;
44fce12a HJ	280	u8 *skbfr;
5110e655 HJ	281	/* SKB which is being sent to the hardware for processing */
5110e655 HJ	282	u64 data_len; /* Data len till time */
44fce12a	283	u8 reqlen;
324429d7	284	u8 partial_hash[CHCR_HASH_MAX_DIGEST_SIZE];
5110e655 HJ	285	u8 bfr1[CHCR_HASH_MAX_BLOCK_SIZE_128];
5110e655 HJ	286	u8 bfr2[CHCR_HASH_MAX_BLOCK_SIZE_128];
324429d7 HS	287	};
	288
	289	struct chcr_blkcipher_req_ctx {
	290	struct sk_buff *skb;
b8fd1f41	291	struct scatterlist *dstsg;
b8fd1f41	292	unsigned int processed;
de1a00ac	293	unsigned int last_req_len;
2f47d580 HJ	294	struct scatterlist *srcsg;
	295	unsigned int src_ofst;
	296	unsigned int dst_ofst;
b8fd1f41	297	unsigned int op;
2f47d580	298	u16 imm;
5c86a8ff	299	u8 iv[CHCR_MAX_CRYPTO_IV_LEN];
324429d7 HS	300	};
	301
	302	struct chcr_alg_template {
	303	u32 type;
	304	u32 is_registered;
	305	union {
	306	struct crypto_alg crypto;
	307	struct ahash_alg hash;
2debd332	308	struct aead_alg aead;
324429d7 HS	309	} alg;
	310	};
	311
2debd332	312	typedef struct sk_buff (create_wr_t)(struct aead_request *req,
324429d7	313	unsigned short qid,
4262c98a	314	int size);
324429d7	315
6dad4e8a AG	316	void chcr_verify_tag(struct aead_request req, u8 input, int *err);
	317	int chcr_aead_dma_map(struct device dev, struct aead_request req,
	318	unsigned short op_type);
	319	void chcr_aead_dma_unmap(struct device dev, struct aead_request req,
	320	unsigned short op_type);
	321	void chcr_add_aead_dst_ent(struct aead_request *req,
	322	struct cpl_rx_phys_dsgl *phys_cpl,
6dad4e8a	323	unsigned short qid);
1f479e4c	324	void chcr_add_aead_src_ent(struct aead_request req, struct ulptx_sgl ulptx);
6dad4e8a	325	void chcr_add_cipher_src_ent(struct ablkcipher_request *req,
335bcc4a	326	void *ulptx,
6dad4e8a AG	327	struct cipher_wr_param *wrparam);
	328	int chcr_cipher_dma_map(struct device dev, struct ablkcipher_request req);
	329	void chcr_cipher_dma_unmap(struct device dev, struct ablkcipher_request req);
	330	void chcr_add_cipher_dst_ent(struct ablkcipher_request *req,
	331	struct cpl_rx_phys_dsgl *phys_cpl,
	332	struct cipher_wr_param *wrparam,
	333	unsigned short qid);
2f47d580	334	int sg_nents_len_skip(struct scatterlist *sg, u64 len, u64 skip);
6dad4e8a AG	335	void chcr_add_hash_src_ent(struct ahash_request req, struct ulptx_sgl ulptx,
	336	struct hash_wr_param *param);
	337	int chcr_hash_dma_map(struct device dev, struct ahash_request req);
	338	void chcr_hash_dma_unmap(struct device dev, struct ahash_request req);
4262c98a	339	void chcr_aead_common_exit(struct aead_request *req);
324429d7	340	#endif /* __CHCR_CRYPTO_H__ */