[linux-2.6-block.git] / drivers / crypto / ccree / cc_hash.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */

/* \file cc_hash.h
 * ARM CryptoCell Hash Crypto API
 */

#ifndef __CC_HASH_H__
#define __CC_HASH_H__

#include "cc_buffer_mgr.h"

#define HMAC_IPAD_CONST	0x36363636
#define HMAC_OPAD_CONST	0x5C5C5C5C
#define HASH_LEN_SIZE_712 16
#define HASH_LEN_SIZE_630 8
#define HASH_MAX_LEN_SIZE HASH_LEN_SIZE_712
#define CC_MAX_HASH_DIGEST_SIZE	SHA512_DIGEST_SIZE
#define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE

#define XCBC_MAC_K1_OFFSET 0
#define XCBC_MAC_K2_OFFSET 16
#define XCBC_MAC_K3_OFFSET 32

#define CC_EXPORT_MAGIC 0xC2EE1070U

/* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used
 * for xcbc/cmac statesize
 */
struct aeshash_state {
	u8 state[AES_BLOCK_SIZE];
	unsigned int count;
	u8 buffer[AES_BLOCK_SIZE];
};

/* ahash state */
struct ahash_req_ctx {
	u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
	u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
	u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
	u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
	u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;
	struct async_gen_req_ctx gen_ctx ____cacheline_aligned;
	enum cc_req_dma_buf_type data_dma_buf_type;
	dma_addr_t opad_digest_dma_addr;
	dma_addr_t digest_buff_dma_addr;
	dma_addr_t digest_bytes_len_dma_addr;
	dma_addr_t digest_result_dma_addr;
	u32 buf_cnt[2];
	u32 buff_index;
	u32 xcbc_count; /* count xcbc update operatations */
	struct scatterlist buff_sg[2];
	struct scatterlist *curr_sg;
	u32 in_nents;
	u32 mlli_nents;
	struct mlli_params mlli_params;
};

static inline u32 *cc_hash_buf_cnt(struct ahash_req_ctx *state)
{
	return &state->buf_cnt[state->buff_index];
}

static inline u8 *cc_hash_buf(struct ahash_req_ctx *state)
{
	return state->buffers[state->buff_index];
}

static inline u32 *cc_next_buf_cnt(struct ahash_req_ctx *state)
{
	return &state->buf_cnt[state->buff_index ^ 1];
}

static inline u8 *cc_next_buf(struct ahash_req_ctx *state)
{
	return state->buffers[state->buff_index ^ 1];
}

int cc_hash_alloc(struct cc_drvdata *drvdata);
int cc_init_hash_sram(struct cc_drvdata *drvdata);
int cc_hash_free(struct cc_drvdata *drvdata);

/*!
 * Gets the initial digest length
 *
 * \param drvdata
 * \param mode The Hash mode. Supported modes:
 *             MD5/SHA1/SHA224/SHA256/SHA384/SHA512
 *
 * \return u32 returns the address of the initial digest length in SRAM
 */
cc_sram_addr_t
cc_digest_len_addr(void *drvdata, u32 mode);

/*!
 * Gets the address of the initial digest in SRAM
 * according to the given hash mode
 *
 * \param drvdata
 * \param mode The Hash mode. Supported modes:
 *             MD5/SHA1/SHA224/SHA256/SHA384/SHA512
 *
 * \return u32 The address of the initial digest in SRAM
 */
cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode);

void cc_hash_global_init(void);

#endif /*__CC_HASH_H__*/
Commit	Line	Data
63893811 GBY	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
	3
	4	/* \file cc_hash.h
	5	* ARM CryptoCell Hash Crypto API
	6	*/
	7
	8	#ifndef __CC_HASH_H__
	9	#define __CC_HASH_H__
	10
	11	#include "cc_buffer_mgr.h"
	12
	13	#define HMAC_IPAD_CONST 0x36363636
	14	#define HMAC_OPAD_CONST 0x5C5C5C5C
27b3b22d GBY	15	#define HASH_LEN_SIZE_712 16
	16	#define HASH_LEN_SIZE_630 8
	17	#define HASH_MAX_LEN_SIZE HASH_LEN_SIZE_712
63893811 GBY	18	#define CC_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE
63893811 GBY	19	#define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE
63893811 GBY	20
	21	#define XCBC_MAC_K1_OFFSET 0
	22	#define XCBC_MAC_K2_OFFSET 16
	23	#define XCBC_MAC_K3_OFFSET 32
	24
	25	#define CC_EXPORT_MAGIC 0xC2EE1070U
	26
	27	/* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used
	28	* for xcbc/cmac statesize
	29	*/
	30	struct aeshash_state {
	31	u8 state[AES_BLOCK_SIZE];
	32	unsigned int count;
	33	u8 buffer[AES_BLOCK_SIZE];
	34	};
	35
	36	/* ahash state */
	37	struct ahash_req_ctx {
	38	u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
	39	u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
	40	u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
	41	u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
27b3b22d	42	u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;
63893811 GBY	43	struct async_gen_req_ctx gen_ctx ____cacheline_aligned;
	44	enum cc_req_dma_buf_type data_dma_buf_type;
	45	dma_addr_t opad_digest_dma_addr;
	46	dma_addr_t digest_buff_dma_addr;
	47	dma_addr_t digest_bytes_len_dma_addr;
	48	dma_addr_t digest_result_dma_addr;
	49	u32 buf_cnt[2];
	50	u32 buff_index;
	51	u32 xcbc_count; /* count xcbc update operatations */
	52	struct scatterlist buff_sg[2];
	53	struct scatterlist *curr_sg;
	54	u32 in_nents;
	55	u32 mlli_nents;
	56	struct mlli_params mlli_params;
	57	};
	58
	59	static inline u32 cc_hash_buf_cnt(struct ahash_req_ctx state)
	60	{
	61	return &state->buf_cnt[state->buff_index];
	62	}
	63
	64	static inline u8 cc_hash_buf(struct ahash_req_ctx state)
	65	{
	66	return state->buffers[state->buff_index];
	67	}
	68
	69	static inline u32 cc_next_buf_cnt(struct ahash_req_ctx state)
	70	{
	71	return &state->buf_cnt[state->buff_index ^ 1];
	72	}
	73
	74	static inline u8 cc_next_buf(struct ahash_req_ctx state)
	75	{
	76	return state->buffers[state->buff_index ^ 1];
	77	}
	78
	79	int cc_hash_alloc(struct cc_drvdata *drvdata);
	80	int cc_init_hash_sram(struct cc_drvdata *drvdata);
	81	int cc_hash_free(struct cc_drvdata *drvdata);
	82
	83	/*!
	84	* Gets the initial digest length
	85	*
	86	* \param drvdata
	87	* \param mode The Hash mode. Supported modes:
	88	* MD5/SHA1/SHA224/SHA256/SHA384/SHA512
	89	*
	90	* \return u32 returns the address of the initial digest length in SRAM
	91	*/
	92	cc_sram_addr_t
	93	cc_digest_len_addr(void *drvdata, u32 mode);
	94
	95	/*!
	96	* Gets the address of the initial digest in SRAM
	97	* according to the given hash mode
	98	*
	99	* \param drvdata
	100	* \param mode The Hash mode. Supported modes:
	101	* MD5/SHA1/SHA224/SHA256/SHA384/SHA512
	102	*
	103	* \return u32 The address of the initial digest in SRAM
	104	*/
	105	cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode);
	106
107	void cc_hash_global_init(void);
108
109	#endif /__CC_HASH_H__/