[linux-block.git] / drivers / crypto / ccree / cc_driver.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */

/* \file cc_driver.h
 * ARM CryptoCell Linux Crypto Driver
 */

#ifndef __CC_DRIVER_H__
#define __CC_DRIVER_H__

#ifdef COMP_IN_WQ
#include <linux/workqueue.h>
#else
#include <linux/interrupt.h>
#endif
#include <linux/dma-mapping.h>
#include <crypto/algapi.h>
#include <crypto/internal/skcipher.h>
#include <crypto/aes.h>
#include <crypto/sha1.h>
#include <crypto/sha2.h>
#include <crypto/aead.h>
#include <crypto/authenc.h>
#include <crypto/hash.h>
#include <crypto/skcipher.h>
#include <linux/version.h>
#include <linux/clk.h>
#include <linux/platform_device.h>

#include "cc_host_regs.h"
#include "cc_crypto_ctx.h"
#include "cc_hw_queue_defs.h"
#include "cc_sram_mgr.h"

extern bool cc_dump_desc;
extern bool cc_dump_bytes;

#define DRV_MODULE_VERSION "5.0"

enum cc_hw_rev {
	CC_HW_REV_630 = 630,
	CC_HW_REV_710 = 710,
	CC_HW_REV_712 = 712,
	CC_HW_REV_713 = 713
};

enum cc_std_body {
	CC_STD_NIST = 0x1,
	CC_STD_OSCCA = 0x2,
	CC_STD_ALL = 0x3
};

#define CC_COHERENT_CACHE_PARAMS 0xEEE

#define CC_PINS_FULL	0x0
#define CC_PINS_SLIM	0x9F

/* Maximum DMA mask supported by IP */
#define DMA_BIT_MASK_LEN 48

#define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
			  (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
			  (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
			  (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))

#define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)

#define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)

#define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT)

#define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)

#define AXIM_MON_COMP_VALUE CC_GENMASK(CC_AXIM_MON_COMP_VALUE)

#define CC_CPP_AES_ABORT_MASK ( \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT))

#define CC_CPP_SM4_ABORT_MASK ( \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \
	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT))

/* Register name mangling macro */
#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET

/* TEE FIPS status interrupt */
#define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)

#define CC_CRA_PRIO 400

#define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */

#define MAX_REQUEST_QUEUE_SIZE 4096
#define MAX_MLLI_BUFF_SIZE 2080

/* Definitions for HW descriptors DIN/DOUT fields */
#define NS_BIT 1
#define AXI_ID 0
/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
 * field in the HW descriptor. The DMA engine +8 that value.
 */

struct cc_cpp_req {
	bool is_cpp;
	enum cc_cpp_alg alg;
	u8 slot;
};

#define CC_MAX_IVGEN_DMA_ADDRESSES	3
struct cc_crypto_req {
	void (*user_cb)(struct device *dev, void *req, int err);
	void *user_arg;
	struct completion seq_compl; /* request completion */
	struct cc_cpp_req cpp;
};

/**
 * struct cc_drvdata - driver private data context
 * @cc_base:	virt address of the CC registers
 * @irq:	bitmap indicating source of last interrupt
 */
struct cc_drvdata {
	void __iomem *cc_base;
	int irq;
	struct completion hw_queue_avail; /* wait for HW queue availability */
	struct platform_device *plat_dev;
	u32 mlli_sram_addr;
	struct dma_pool *mlli_buffs_pool;
	struct list_head alg_list;
	void *hash_handle;
	void *aead_handle;
	void *request_mgr_handle;
	void *fips_handle;
	u32 sram_free_offset;	/* offset to non-allocated area in SRAM */
	struct dentry *dir;	/* for debugfs */
	struct clk *clk;
	bool coherent;
	char *hw_rev_name;
	enum cc_hw_rev hw_rev;
	u32 axim_mon_offset;
	u32 sig_offset;
	u32 ver_offset;
	int std_bodies;
	bool sec_disabled;
	u32 comp_mask;
};

struct cc_crypto_alg {
	struct list_head entry;
	int cipher_mode;
	int flow_mode; /* Note: currently, refers to the cipher mode only. */
	int auth_mode;
	struct cc_drvdata *drvdata;
	struct skcipher_alg skcipher_alg;
	struct aead_alg aead_alg;
};

struct cc_alg_template {
	char name[CRYPTO_MAX_ALG_NAME];
	char driver_name[CRYPTO_MAX_ALG_NAME];
	unsigned int blocksize;
	union {
		struct skcipher_alg skcipher;
		struct aead_alg aead;
	} template_u;
	int cipher_mode;
	int flow_mode; /* Note: currently, refers to the cipher mode only. */
	int auth_mode;
	u32 min_hw_rev;
	enum cc_std_body std_body;
	bool sec_func;
	unsigned int data_unit;
	struct cc_drvdata *drvdata;
};

struct async_gen_req_ctx {
	dma_addr_t iv_dma_addr;
	u8 *iv;
	enum drv_crypto_direction op_type;
};

static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata)
{
	return &drvdata->plat_dev->dev;
}

void __dump_byte_array(const char *name, const u8 *buf, size_t len);
static inline void dump_byte_array(const char *name, const u8 *the_array,
				   size_t size)
{
	if (cc_dump_bytes)
		__dump_byte_array(name, the_array, size);
}

bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
void fini_cc_regs(struct cc_drvdata *drvdata);
unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);

static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
{
	iowrite32(val, (drvdata->cc_base + reg));
}

static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
{
	return ioread32(drvdata->cc_base + reg);
}

static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
{
	return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
			GFP_KERNEL : GFP_ATOMIC;
}

static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
				      struct cc_hw_desc *pdesc)
{
	if (drvdata->hw_rev >= CC_HW_REV_712)
		set_queue_last_ind_bit(pdesc);
}

#endif /*__CC_DRIVER_H__*/
Commit	Line	Data
4c3f9727	1	/* SPDX-License-Identifier: GPL-2.0 */
03963cae	2	/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
4c3f9727 GBY	3
	4	/* \file cc_driver.h
	5	* ARM CryptoCell Linux Crypto Driver
	6	*/
	7
	8	#ifndef __CC_DRIVER_H__
	9	#define __CC_DRIVER_H__
	10
	11	#ifdef COMP_IN_WQ
	12	#include <linux/workqueue.h>
	13	#else
	14	#include <linux/interrupt.h>
	15	#endif
	16	#include <linux/dma-mapping.h>
	17	#include <crypto/algapi.h>
63ee04c8	18	#include <crypto/internal/skcipher.h>
4c3f9727	19	#include <crypto/aes.h>
a24d22b2 EB	20	#include <crypto/sha1.h>
a24d22b2 EB	21	#include <crypto/sha2.h>
4c3f9727 GBY	22	#include <crypto/aead.h>
	23	#include <crypto/authenc.h>
	24	#include <crypto/hash.h>
	25	#include <crypto/skcipher.h>
	26	#include <linux/version.h>
	27	#include <linux/clk.h>
	28	#include <linux/platform_device.h>
	29
4c3f9727	30	#include "cc_host_regs.h"
4c3f9727 GBY	31	#include "cc_crypto_ctx.h"
	32	#include "cc_hw_queue_defs.h"
	33	#include "cc_sram_mgr.h"
	34
	35	extern bool cc_dump_desc;
	36	extern bool cc_dump_bytes;
	37
e40fdb50	38	#define DRV_MODULE_VERSION "5.0"
27b3b22d GBY	39
	40	enum cc_hw_rev {
	41	CC_HW_REV_630 = 630,
	42	CC_HW_REV_710 = 710,
e40fdb50 GBY	43	CC_HW_REV_712 = 712,
e40fdb50 GBY	44	CC_HW_REV_713 = 713
27b3b22d	45	};
4c3f9727	46
1c876a90 GBY	47	enum cc_std_body {
	48	CC_STD_NIST = 0x1,
	49	CC_STD_OSCCA = 0x2,
	50	CC_STD_ALL = 0x3
	51	};
	52
4c3f9727 GBY	53	#define CC_COHERENT_CACHE_PARAMS 0xEEE
4c3f9727 GBY	54
303f99ac GBY	55	#define CC_PINS_FULL 0x0
	56	#define CC_PINS_SLIM 0x9F
	57
4c3f9727 GBY	58	/* Maximum DMA mask supported by IP */
	59	#define DMA_BIT_MASK_LEN 48
	60
4c3f9727 GBY	61	#define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) \| \
	62	(1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) \| \
	63	(1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) \| \
	64	(1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))
	65
	66	#define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
	67
	68	#define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
	69
f98f6e21 GBY	70	#define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT)
f98f6e21 GBY	71
d84f6269 OD	72	#define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)
d84f6269 OD	73
d8215ff1	74	#define AXIM_MON_COMP_VALUE CC_GENMASK(CC_AXIM_MON_COMP_VALUE)
4c3f9727	75
cadfd898 GBY	76	#define CC_CPP_AES_ABORT_MASK ( \
	77	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) \| \
	78	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) \| \
	79	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) \| \
	80	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) \| \
	81	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) \| \
	82	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) \| \
	83	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) \| \
	84	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT))
	85
	86	#define CC_CPP_SM4_ABORT_MASK ( \
	87	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) \| \
	88	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) \| \
	89	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) \| \
	90	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) \| \
	91	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) \| \
	92	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) \| \
	93	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) \| \
	94	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT))
	95
4c3f9727 GBY	96	/* Register name mangling macro */
	97	#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
	98
	99	/* TEE FIPS status interrupt */
	100	#define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)
	101
	102	#define CC_CRA_PRIO 400
	103
	104	#define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
	105
	106	#define MAX_REQUEST_QUEUE_SIZE 4096
	107	#define MAX_MLLI_BUFF_SIZE 2080
4c3f9727 GBY	108
	109	/* Definitions for HW descriptors DIN/DOUT fields */
	110	#define NS_BIT 1
	111	#define AXI_ID 0
	112	/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
	113	* field in the HW descriptor. The DMA engine +8 that value.
	114	*/
	115
cadfd898 GBY	116	struct cc_cpp_req {
	117	bool is_cpp;
	118	enum cc_cpp_alg alg;
	119	u8 slot;
	120	};
	121
4c3f9727 GBY	122	#define CC_MAX_IVGEN_DMA_ADDRESSES 3
	123	struct cc_crypto_req {
	124	void (user_cb)(struct device dev, void *req, int err);
	125	void *user_arg;
4c3f9727	126	struct completion seq_compl; /* request completion */
cadfd898	127	struct cc_cpp_req cpp;
4c3f9727 GBY	128	};
	129
	130	/**
	131	* struct cc_drvdata - driver private data context
	132	* @cc_base: virt address of the CC registers
33c4b310	133	* @irq: bitmap indicating source of last interrupt
4c3f9727 GBY	134	*/
	135	struct cc_drvdata {
	136	void __iomem *cc_base;
	137	int irq;
4c3f9727 GBY	138	struct completion hw_queue_avail; /* wait for HW queue availability */
4c3f9727 GBY	139	struct platform_device *plat_dev;
1a895f1d	140	u32 mlli_sram_addr;
040187a0	141	struct dma_pool *mlli_buffs_pool;
c23d7997	142	struct list_head alg_list;
63893811	143	void *hash_handle;
ff27e85a	144	void *aead_handle;
4c3f9727	145	void *request_mgr_handle;
ab8ec965	146	void *fips_handle;
f1b19dff	147	u32 sram_free_offset; /* offset to non-allocated area in SRAM */
ec8f3a55	148	struct dentry dir; / for debugfs */
4c3f9727 GBY	149	struct clk *clk;
4c3f9727 GBY	150	bool coherent;
27b3b22d GBY	151	char *hw_rev_name;
27b3b22d GBY	152	enum cc_hw_rev hw_rev;
27b3b22d	153	u32 axim_mon_offset;
281a58c8 GBY	154	u32 sig_offset;
281a58c8 GBY	155	u32 ver_offset;
1c876a90	156	int std_bodies;
f98f6e21	157	bool sec_disabled;
cadfd898	158	u32 comp_mask;
4c3f9727 GBY	159	};
	160
	161	struct cc_crypto_alg {
	162	struct list_head entry;
	163	int cipher_mode;
	164	int flow_mode; /* Note: currently, refers to the cipher mode only. */
	165	int auth_mode;
	166	struct cc_drvdata *drvdata;
63ee04c8	167	struct skcipher_alg skcipher_alg;
ff27e85a	168	struct aead_alg aead_alg;
4c3f9727 GBY	169	};
	170
	171	struct cc_alg_template {
	172	char name[CRYPTO_MAX_ALG_NAME];
	173	char driver_name[CRYPTO_MAX_ALG_NAME];
	174	unsigned int blocksize;
4c3f9727 GBY	175	union {
	176	struct skcipher_alg skcipher;
	177	struct aead_alg aead;
	178	} template_u;
	179	int cipher_mode;
	180	int flow_mode; /* Note: currently, refers to the cipher mode only. */
	181	int auth_mode;
27b3b22d	182	u32 min_hw_rev;
1c876a90	183	enum cc_std_body std_body;
f98f6e21	184	bool sec_func;
63ee04c8	185	unsigned int data_unit;
4c3f9727 GBY	186	struct cc_drvdata *drvdata;
	187	};
	188
	189	struct async_gen_req_ctx {
	190	dma_addr_t iv_dma_addr;
e8662a6a	191	u8 *iv;
4c3f9727 GBY	192	enum drv_crypto_direction op_type;
	193	};
	194
	195	static inline struct device drvdata_to_dev(struct cc_drvdata drvdata)
	196	{
	197	return &drvdata->plat_dev->dev;
	198	}
	199
	200	void __dump_byte_array(const char name, const u8 buf, size_t len);
	201	static inline void dump_byte_array(const char name, const u8 the_array,
	202	size_t size)
	203	{
	204	if (cc_dump_bytes)
	205	__dump_byte_array(name, the_array, size);
	206	}
	207
d84f6269	208	bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
4c3f9727 GBY	209	int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
4c3f9727 GBY	210	void fini_cc_regs(struct cc_drvdata *drvdata);
f1e52fd0	211	unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
4c3f9727 GBY	212
	213	static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
	214	{
	215	iowrite32(val, (drvdata->cc_base + reg));
	216	}
	217
	218	static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
	219	{
	220	return ioread32(drvdata->cc_base + reg);
	221	}
	222
	223	static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
	224	{
	225	return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
	226	GFP_KERNEL : GFP_ATOMIC;
	227	}
	228
27b3b22d GBY	229	static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
	230	struct cc_hw_desc *pdesc)
	231	{
	232	if (drvdata->hw_rev >= CC_HW_REV_712)
	233	set_queue_last_ind_bit(pdesc);
	234	}
	235
4c3f9727	236	#endif /__CC_DRIVER_H__/