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4c3f9727 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
03963cae | 2 | /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ |
4c3f9727 GBY |
3 | |
4 | #ifndef _CC_CRYPTO_CTX_H_ | |
5 | #define _CC_CRYPTO_CTX_H_ | |
6 | ||
7 | #include <linux/types.h> | |
8 | ||
4c3f9727 GBY |
9 | #define CC_DRV_DES_IV_SIZE 8 |
10 | #define CC_DRV_DES_BLOCK_SIZE 8 | |
11 | ||
12 | #define CC_DRV_DES_ONE_KEY_SIZE 8 | |
13 | #define CC_DRV_DES_DOUBLE_KEY_SIZE 16 | |
14 | #define CC_DRV_DES_TRIPLE_KEY_SIZE 24 | |
15 | #define CC_DRV_DES_KEY_SIZE_MAX CC_DRV_DES_TRIPLE_KEY_SIZE | |
16 | ||
17 | #define CC_AES_IV_SIZE 16 | |
18 | #define CC_AES_IV_SIZE_WORDS (CC_AES_IV_SIZE >> 2) | |
19 | ||
20 | #define CC_AES_BLOCK_SIZE 16 | |
21 | #define CC_AES_BLOCK_SIZE_WORDS 4 | |
22 | ||
23 | #define CC_AES_128_BIT_KEY_SIZE 16 | |
24 | #define CC_AES_128_BIT_KEY_SIZE_WORDS (CC_AES_128_BIT_KEY_SIZE >> 2) | |
25 | #define CC_AES_192_BIT_KEY_SIZE 24 | |
26 | #define CC_AES_192_BIT_KEY_SIZE_WORDS (CC_AES_192_BIT_KEY_SIZE >> 2) | |
27 | #define CC_AES_256_BIT_KEY_SIZE 32 | |
28 | #define CC_AES_256_BIT_KEY_SIZE_WORDS (CC_AES_256_BIT_KEY_SIZE >> 2) | |
29 | #define CC_AES_KEY_SIZE_MAX CC_AES_256_BIT_KEY_SIZE | |
30 | #define CC_AES_KEY_SIZE_WORDS_MAX (CC_AES_KEY_SIZE_MAX >> 2) | |
31 | ||
32 | #define CC_MD5_DIGEST_SIZE 16 | |
33 | #define CC_SHA1_DIGEST_SIZE 20 | |
34 | #define CC_SHA224_DIGEST_SIZE 28 | |
35 | #define CC_SHA256_DIGEST_SIZE 32 | |
36 | #define CC_SHA256_DIGEST_SIZE_IN_WORDS 8 | |
37 | #define CC_SHA384_DIGEST_SIZE 48 | |
38 | #define CC_SHA512_DIGEST_SIZE 64 | |
39 | ||
40 | #define CC_SHA1_BLOCK_SIZE 64 | |
41 | #define CC_SHA1_BLOCK_SIZE_IN_WORDS 16 | |
42 | #define CC_MD5_BLOCK_SIZE 64 | |
43 | #define CC_MD5_BLOCK_SIZE_IN_WORDS 16 | |
44 | #define CC_SHA224_BLOCK_SIZE 64 | |
45 | #define CC_SHA256_BLOCK_SIZE 64 | |
46 | #define CC_SHA256_BLOCK_SIZE_IN_WORDS 16 | |
47 | #define CC_SHA1_224_256_BLOCK_SIZE 64 | |
48 | #define CC_SHA384_BLOCK_SIZE 128 | |
49 | #define CC_SHA512_BLOCK_SIZE 128 | |
50 | ||
4c3f9727 GBY |
51 | #define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE |
52 | #define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/ | |
4c3f9727 GBY |
53 | |
54 | #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX | |
55 | ||
56 | #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX | |
57 | ||
cadfd898 GBY |
58 | #define CC_CPP_NUM_SLOTS 8 |
59 | #define CC_CPP_NUM_ALGS 2 | |
60 | ||
61 | enum cc_cpp_alg { | |
62 | CC_CPP_SM4 = 1, | |
63 | CC_CPP_AES = 0 | |
64 | }; | |
65 | ||
4c3f9727 GBY |
66 | enum drv_engine_type { |
67 | DRV_ENGINE_NULL = 0, | |
68 | DRV_ENGINE_AES = 1, | |
69 | DRV_ENGINE_DES = 2, | |
70 | DRV_ENGINE_HASH = 3, | |
71 | DRV_ENGINE_RC4 = 4, | |
72 | DRV_ENGINE_DOUT = 5, | |
73 | DRV_ENGINE_RESERVE32B = S32_MAX, | |
74 | }; | |
75 | ||
76 | enum drv_crypto_alg { | |
77 | DRV_CRYPTO_ALG_NULL = -1, | |
78 | DRV_CRYPTO_ALG_AES = 0, | |
79 | DRV_CRYPTO_ALG_DES = 1, | |
80 | DRV_CRYPTO_ALG_HASH = 2, | |
81 | DRV_CRYPTO_ALG_C2 = 3, | |
82 | DRV_CRYPTO_ALG_HMAC = 4, | |
83 | DRV_CRYPTO_ALG_AEAD = 5, | |
84 | DRV_CRYPTO_ALG_BYPASS = 6, | |
85 | DRV_CRYPTO_ALG_NUM = 7, | |
86 | DRV_CRYPTO_ALG_RESERVE32B = S32_MAX | |
87 | }; | |
88 | ||
89 | enum drv_crypto_direction { | |
90 | DRV_CRYPTO_DIRECTION_NULL = -1, | |
91 | DRV_CRYPTO_DIRECTION_ENCRYPT = 0, | |
92 | DRV_CRYPTO_DIRECTION_DECRYPT = 1, | |
93 | DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3, | |
94 | DRV_CRYPTO_DIRECTION_RESERVE32B = S32_MAX | |
95 | }; | |
96 | ||
97 | enum drv_cipher_mode { | |
98 | DRV_CIPHER_NULL_MODE = -1, | |
99 | DRV_CIPHER_ECB = 0, | |
100 | DRV_CIPHER_CBC = 1, | |
101 | DRV_CIPHER_CTR = 2, | |
102 | DRV_CIPHER_CBC_MAC = 3, | |
103 | DRV_CIPHER_XTS = 4, | |
104 | DRV_CIPHER_XCBC_MAC = 5, | |
105 | DRV_CIPHER_OFB = 6, | |
106 | DRV_CIPHER_CMAC = 7, | |
107 | DRV_CIPHER_CCM = 8, | |
108 | DRV_CIPHER_CBC_CTS = 11, | |
109 | DRV_CIPHER_GCTR = 12, | |
110 | DRV_CIPHER_ESSIV = 13, | |
4c3f9727 GBY |
111 | DRV_CIPHER_RESERVE32B = S32_MAX |
112 | }; | |
113 | ||
114 | enum drv_hash_mode { | |
115 | DRV_HASH_NULL = -1, | |
116 | DRV_HASH_SHA1 = 0, | |
117 | DRV_HASH_SHA256 = 1, | |
118 | DRV_HASH_SHA224 = 2, | |
119 | DRV_HASH_SHA512 = 3, | |
120 | DRV_HASH_SHA384 = 4, | |
121 | DRV_HASH_MD5 = 5, | |
122 | DRV_HASH_CBC_MAC = 6, | |
123 | DRV_HASH_XCBC_MAC = 7, | |
124 | DRV_HASH_CMAC = 8, | |
927574e0 YC |
125 | DRV_HASH_SM3 = 9, |
126 | DRV_HASH_MODE_NUM = 10, | |
4c3f9727 GBY |
127 | DRV_HASH_RESERVE32B = S32_MAX |
128 | }; | |
129 | ||
130 | enum drv_hash_hw_mode { | |
131 | DRV_HASH_HW_MD5 = 0, | |
132 | DRV_HASH_HW_SHA1 = 1, | |
133 | DRV_HASH_HW_SHA256 = 2, | |
134 | DRV_HASH_HW_SHA224 = 10, | |
135 | DRV_HASH_HW_SHA512 = 4, | |
136 | DRV_HASH_HW_SHA384 = 12, | |
137 | DRV_HASH_HW_GHASH = 6, | |
927574e0 | 138 | DRV_HASH_HW_SM3 = 14, |
4c3f9727 GBY |
139 | DRV_HASH_HW_RESERVE32B = S32_MAX |
140 | }; | |
141 | ||
4c3f9727 | 142 | #endif /* _CC_CRYPTO_CTX_H_ */ |