projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
crypto: caam - enable raw data instead of von Neumann data
[linux-2.6-block.git] / drivers / crypto / caam / regs.h
CommitLineData
8e8ec596
KP		 1/*
2 * CAAM hardware register-level view
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 */
6
7#ifndef REGS_H
8#define REGS_H
9
10#include <linux/types.h>
11#include <linux/io.h>
12
13/*
14 * Architecture-specific register access methods
15 *
16 * CAAM's bus-addressable registers are 64 bits internally.
17 * They have been wired to be safely accessible on 32-bit
18 * architectures, however. Registers were organized such
19 * that (a) they can be contained in 32 bits, (b) if not, then they
20 * can be treated as two 32-bit entities, or finally (c) if they
21 * must be treated as a single 64-bit value, then this can safely
22 * be done with two 32-bit cycles.
23 *
24 * For 32-bit operations on 64-bit values, CAAM follows the same
25 * 64-bit register access conventions as it's predecessors, in that
26 * writes are "triggered" by a write to the register at the numerically
27 * higher address, thus, a full 64-bit write cycle requires a write
28 * to the lower address, followed by a write to the higher address,
29 * which will latch/execute the write cycle.
30 *
31 * For example, let's assume a SW reset of CAAM through the master
32 * configuration register.
33 * - SWRST is in bit 31 of MCFG.
34 * - MCFG begins at base+0x0000.
35 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
36 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
37 *
38 * (and on Power, the convention is 0-31, 32-63, I know...)
39 *
40 * Assuming a 64-bit write to this MCFG to perform a software reset
41 * would then require a write of 0 to base+0x0000, followed by a
42 * write of 0x80000000 to base+0x0004, which would "execute" the
43 * reset.
44 *
45 * Of course, since MCFG 63-32 is all zero, we could cheat and simply
46 * write 0x8000000 to base+0x0004, and the reset would work fine.
47 * However, since CAAM does contain some write-and-read-intended
48 * 64-bit registers, this code defines 64-bit access methods for
49 * the sake of internal consistency and simplicity, and so that a
50 * clean transition to 64-bit is possible when it becomes necessary.
51 *
52 * There are limitations to this that the developer must recognize.
53 * 32-bit architectures cannot enforce an atomic-64 operation,
54 * Therefore:
55 *
56 * - On writes, since the HW is assumed to latch the cycle on the
57 * write of the higher-numeric-address word, then ordered
58 * writes work OK.
59 *
60 * - For reads, where a register contains a relevant value of more
61 * that 32 bits, the hardware employs logic to latch the other
62 * "half" of the data until read, ensuring an accurate value.
63 * This is of particular relevance when dealing with CAAM's
64 * performance counters.
65 *
66 */
67
68#ifdef __BIG_ENDIAN
69#define wr_reg32(reg, data) out_be32(reg, data)
70#define rd_reg32(reg) in_be32(reg)
71#ifdef CONFIG_64BIT
72#define wr_reg64(reg, data) out_be64(reg, data)
73#define rd_reg64(reg) in_be64(reg)
74#endif
75#else
76#ifdef __LITTLE_ENDIAN
f829e7a3 77#define wr_reg32(reg, data) __raw_writel(data, reg)
8e8ec596
KP		 78#define rd_reg32(reg) __raw_readl(reg)
79#ifdef CONFIG_64BIT
f829e7a3 80#define wr_reg64(reg, data) __raw_writeq(data, reg)
8e8ec596
KP		 81#define rd_reg64(reg) __raw_readq(reg)
82#endif
83#endif
84#endif
85
86#ifndef CONFIG_64BIT
ef94b1d8 87#ifdef __BIG_ENDIAN
8e8ec596
KP		 88static inline void wr_reg64(u64 __iomem *reg, u64 data)
89{
90 wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
91 wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull);
92}
93
94static inline u64 rd_reg64(u64 __iomem *reg)
95{
96 return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
97 ((u64)rd_reg32((u32 __iomem *)reg + 1));
98}
ef94b1d8
RG		 99#else
100#ifdef __LITTLE_ENDIAN
101static inline void wr_reg64(u64 __iomem *reg, u64 data)
102{
103 wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32);
104 wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull);
105}
106
107static inline u64 rd_reg64(u64 __iomem *reg)
108{
109 return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) |
110 ((u64)rd_reg32((u32 __iomem *)reg));
111}
112#endif
113#endif
8e8ec596
KP		 114#endif
115
116/*
117 * jr_outentry
118 * Represents each entry in a JobR output ring
119 */
120struct jr_outentry {
121 dma_addr_t desc;/* Pointer to completed descriptor */
122 u32 jrstatus; /* Status for completed descriptor */
123} __packed;
124
125/*
126 * caam_perfmon - Performance Monitor/Secure Memory Status/
127 * CAAM Global Status/Component Version IDs
128 *
129 * Spans f00-fff wherever instantiated
130 */
131
132/* Number of DECOs */
eb1139cd
RG		 133#define CHA_NUM_MS_DECONUM_SHIFT 24
134#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
8e8ec596 135
986dfbcf 136/* CHA Version IDs */
eb1139cd
RG		 137#define CHA_ID_LS_AES_SHIFT 0
138#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
986dfbcf 139
eb1139cd
RG		 140#define CHA_ID_LS_DES_SHIFT 4
141#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
986dfbcf 142
eb1139cd
RG		 143#define CHA_ID_LS_ARC4_SHIFT 8
144#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT)
986dfbcf 145
eb1139cd
RG		 146#define CHA_ID_LS_MD_SHIFT 12
147#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
986dfbcf 148
eb1139cd
RG		 149#define CHA_ID_LS_RNG_SHIFT 16
150#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
986dfbcf 151
eb1139cd
RG		 152#define CHA_ID_LS_SNW8_SHIFT 20
153#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT)
986dfbcf 154
eb1139cd
RG		 155#define CHA_ID_LS_KAS_SHIFT 24
156#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT)
986dfbcf 157
eb1139cd
RG		 158#define CHA_ID_LS_PK_SHIFT 28
159#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT)
986dfbcf 160
eb1139cd
RG		 161#define CHA_ID_MS_CRC_SHIFT 0
162#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT)
986dfbcf 163
eb1139cd
RG		 164#define CHA_ID_MS_SNW9_SHIFT 4
165#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT)
986dfbcf 166
eb1139cd
RG		 167#define CHA_ID_MS_DECO_SHIFT 24
168#define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT)
986dfbcf 169
eb1139cd
RG		 170#define CHA_ID_MS_JR_SHIFT 28
171#define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT)
986dfbcf 172
82c2f960
AP		 173struct sec_vid {
174 u16 ip_id;
175 u8 maj_rev;
176 u8 min_rev;
177};
178
8e8ec596
KP		 179struct caam_perfmon {
180 /* Performance Monitor Registers f00-f9f */
181 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
182 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
183 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
184 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
185 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
186 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
187 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */
188 u64 rsvd[13];
189
190 /* CAAM Hardware Instantiation Parameters fa0-fbf */
eb1139cd
RG		 191 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
192 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
193#define CTPR_MS_QI_SHIFT 25
194#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
17157c90
RG		 195#define CTPR_MS_VIRT_EN_INCL 0x00000001
196#define CTPR_MS_VIRT_EN_POR 0x00000002
eb1139cd
RG		 197 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
198 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
8e8ec596
KP		 199 u64 rsvd1[2];
200
201 /* CAAM Global Status fc0-fdf */
202 u64 faultaddr; /* FAR - Fault Address */
203 u32 faultliodn; /* FALR - Fault Address LIODN */
204 u32 faultdetail; /* FADR - Fault Addr Detail */
205 u32 rsvd2;
206 u32 status; /* CSTA - CAAM Status */
207 u64 rsvd3;
208
209 /* Component Instantiation Parameters fe0-fff */
210 u32 rtic_id; /* RVID - RTIC Version ID */
211 u32 ccb_id; /* CCBVID - CCB Version ID */
eb1139cd
RG		 212 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
213 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
214 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
215 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
216 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
217 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
8e8ec596
KP		 218};
219
220/* LIODN programming for DMA configuration */
221#define MSTRID_LOCK_LIODN 0x80000000
222#define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
223
224#define MSTRID_LIODN_MASK 0x0fff
225struct masterid {
226 u32 liodn_ms; /* lock and make-trusted control bits */
227 u32 liodn_ls; /* LIODN for non-sequence and seq access */
228};
229
230/* Partition ID for DMA configuration */
231struct partid {
232 u32 rsvd1;
233 u32 pidr; /* partition ID, DECO */
234};
235
281922a1 236/* RNGB test mode (replicated twice in some configurations) */
8e8ec596
KP		 237/* Padded out to 0x100 */
238struct rngtst {
239 u32 mode; /* RTSTMODEx - Test mode */
240 u32 rsvd1[3];
241 u32 reset; /* RTSTRESETx - Test reset control */
242 u32 rsvd2[3];
243 u32 status; /* RTSTSSTATUSx - Test status */
244 u32 rsvd3;
245 u32 errstat; /* RTSTERRSTATx - Test error status */
246 u32 rsvd4;
247 u32 errctl; /* RTSTERRCTLx - Test error control */
248 u32 rsvd5;
249 u32 entropy; /* RTSTENTROPYx - Test entropy */
250 u32 rsvd6[15];
251 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
252 u32 rsvd7;
253 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
254 u32 rsvd8;
255 u32 verifdata; /* RTSTVERIFDx - Test verification data */
256 u32 rsvd9;
257 u32 xkey; /* RTSTXKEYx - Test XKEY */
258 u32 rsvd10;
259 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
260 u32 rsvd11;
261 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
262 u32 rsvd12;
263 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
264 u32 rsvd13[2];
265 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
266 u32 rsvd14[15];
267};
268
281922a1
KP		 269/* RNG4 TRNG test registers */
270struct rng4tst {
1005bccd 271#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
e5ffbfc1
AP		 272#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
273 both entropy shifter and
274 statistical checker */
275#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
276 entropy shifter and
277 statistical checker */
278#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
279 entropy shifter, raw data
280 in statistical checker */
281#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
281922a1
KP		 282 u32 rtmctl; /* misc. control register */
283 u32 rtscmisc; /* statistical check misc. register */
284 u32 rtpkrrng; /* poker range register */
285 union {
286 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
287 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
288 };
289#define RTSDCTL_ENT_DLY_SHIFT 16
290#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
eeaa1724 291#define RTSDCTL_ENT_DLY_MIN 3200
84cf4827 292#define RTSDCTL_ENT_DLY_MAX 12800
281922a1
KP		 293 u32 rtsdctl; /* seed control register */
294 union {
295 u32 rtsblim; /* PRGM=1: sparse bit limit register */
296 u32 rttotsam; /* PRGM=0: total samples register */
297 };
298 u32 rtfrqmin; /* frequency count min. limit register */
b061f3fe 299#define RTFRQMAX_DISABLE (1 << 20)
281922a1
KP		 300 union {
301 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
302 u32 rtfrqcnt; /* PRGM=0: freq. count register */
303 };
986dfbcf 304 u32 rsvd1[40];
1005bccd
AP		 305#define RDSTA_SKVT 0x80000000
306#define RDSTA_SKVN 0x40000000
986dfbcf 307#define RDSTA_IF0 0x00000001
1005bccd
AP		 308#define RDSTA_IF1 0x00000002
309#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
986dfbcf
RG		 310 u32 rdsta;
311 u32 rsvd2[15];
281922a1
KP		 312};
313
8e8ec596
KP		 314/*
315 * caam_ctrl - basic core configuration
316 * starts base + 0x0000 padded out to 0x1000
317 */
318
319#define KEK_KEY_SIZE 8
320#define TKEK_KEY_SIZE 8
321#define TDSK_KEY_SIZE 8
322
323#define DECO_RESET 1 /* Use with DECO reset/availability regs */
324#define DECO_RESET_0 (DECO_RESET << 0)
325#define DECO_RESET_1 (DECO_RESET << 1)
326#define DECO_RESET_2 (DECO_RESET << 2)
327#define DECO_RESET_3 (DECO_RESET << 3)
328#define DECO_RESET_4 (DECO_RESET << 4)
329
330struct caam_ctrl {
331 /* Basic Configuration Section 000-01f */
332 /* Read/Writable */
333 u32 rsvd1;
334 u32 mcr; /* MCFG Master Config Register */
575c1bd5
VG		 335 u32 rsvd2;
336 u32 scfgr; /* SCFGR, Security Config Register */
8e8ec596
KP		 337
338 /* Bus Access Configuration Section 010-11f */
339 /* Read/Writable */
340 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
17157c90
RG		 341 u32 rsvd3[11];
342 u32 jrstart; /* JRSTART - Job Ring Start Register */
8e8ec596 343 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
17157c90
RG		 344 u32 rsvd4[5];
345 u32 deco_rsr; /* DECORSR - Deco Request Source */
346 u32 rsvd11;
8e8ec596
KP		 347 u32 deco_rq; /* DECORR - DECO Request */
348 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
349 u32 rsvd5[22];
350
351 /* DECO Availability/Reset Section 120-3ff */
352 u32 deco_avail; /* DAR - DECO availability */
353 u32 deco_reset; /* DRR - DECO reset */
354 u32 rsvd6[182];
355
356 /* Key Encryption/Decryption Configuration 400-5ff */
357 /* Read/Writable only while in Non-secure mode */
358 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
359 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
360 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
361 u32 rsvd7[32];
362 u64 sknonce; /* SKNR - Secure Key Nonce */
363 u32 rsvd8[70];
364
365 /* RNG Test/Verification/Debug Access 600-7ff */
366 /* (Useful in Test/Debug modes only...) */
281922a1
KP		 367 union {
368 struct rngtst rtst[2];
369 struct rng4tst r4tst[2];
370 };
8e8ec596
KP		 371
372 u32 rsvd9[448];
373
374 /* Performance Monitor f00-fff */
375 struct caam_perfmon perfmon;
376};
377
378/*
379 * Controller master config register defs
380 */
381#define MCFGR_SWRESET 0x80000000 /* software reset */
382#define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */
383#define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
384#define MCFGR_DMA_RESET 0x10000000
385#define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
575c1bd5 386#define SCFGR_RDBENABLE 0x00000400
17157c90 387#define SCFGR_VIRT_EN 0x00008000
997ad290 388#define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */
17157c90
RG		 389#define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */
390#define DECORSR_VALID 0x80000000
997ad290 391#define DECORR_DEN0 0x00010000 /* DECO0 available for access*/
8e8ec596
KP		 392
393/* AXI read cache control */
394#define MCFGR_ARCACHE_SHIFT 12
395#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
396
397/* AXI write cache control */
398#define MCFGR_AWCACHE_SHIFT 8
399#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
400
401/* AXI pipeline depth */
402#define MCFGR_AXIPIPE_SHIFT 4
403#define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
404
405#define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
406#define MCFGR_BURST_64 0x00000001 /* Max burst size */
407
17157c90
RG		 408/* JRSTART register offsets */
409#define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */
410#define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */
411#define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */
412#define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */
413
8e8ec596
KP		 414/*
415 * caam_job_ring - direct job ring setup
416 * 1-4 possible per instantiation, base + 1000/2000/3000/4000
417 * Padded out to 0x1000
418 */
419struct caam_job_ring {
420 /* Input ring */
421 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
422 u32 rsvd1;
423 u32 inpring_size; /* IRSx - Input ring size */
424 u32 rsvd2;
425 u32 inpring_avail; /* IRSAx - Input ring room remaining */
426 u32 rsvd3;
427 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
428
429 /* Output Ring */
430 u64 outring_base; /* ORBAx - Output status ring base addr */
431 u32 rsvd4;
432 u32 outring_size; /* ORSx - Output ring size */
433 u32 rsvd5;
434 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
435 u32 rsvd6;
436 u32 outring_used; /* ORSFx - Output ring slots full */
437
438 /* Status/Configuration */
439 u32 rsvd7;
440 u32 jroutstatus; /* JRSTAx - JobR output status */
441 u32 rsvd8;
442 u32 jrintstatus; /* JRINTx - JobR interrupt status */
443 u32 rconfig_hi; /* JRxCFG - Ring configuration */
444 u32 rconfig_lo;
445
446 /* Indices. CAAM maintains as "heads" of each queue */
447 u32 rsvd9;
448 u32 inp_rdidx; /* IRRIx - Input ring read index */
449 u32 rsvd10;
450 u32 out_wtidx; /* ORWIx - Output ring write index */
451
452 /* Command/control */
453 u32 rsvd11;
454 u32 jrcommand; /* JRCRx - JobR command */
455
456 u32 rsvd12[932];
457
458 /* Performance Monitor f00-fff */
459 struct caam_perfmon perfmon;
460};
461
462#define JR_RINGSIZE_MASK 0x03ff
463/*
464 * jrstatus - Job Ring Output Status
465 * All values in lo word
466 * Also note, same values written out as status through QI
467 * in the command/status field of a frame descriptor
468 */
469#define JRSTA_SSRC_SHIFT 28
470#define JRSTA_SSRC_MASK 0xf0000000
471
472#define JRSTA_SSRC_NONE 0x00000000
473#define JRSTA_SSRC_CCB_ERROR 0x20000000
474#define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
475#define JRSTA_SSRC_DECO 0x40000000
476#define JRSTA_SSRC_JRERROR 0x60000000
477#define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
478
479#define JRSTA_DECOERR_JUMP 0x08000000
480#define JRSTA_DECOERR_INDEX_SHIFT 8
481#define JRSTA_DECOERR_INDEX_MASK 0xff00
482#define JRSTA_DECOERR_ERROR_MASK 0x00ff
483
484#define JRSTA_DECOERR_NONE 0x00
485#define JRSTA_DECOERR_LINKLEN 0x01
486#define JRSTA_DECOERR_LINKPTR 0x02
487#define JRSTA_DECOERR_JRCTRL 0x03
488#define JRSTA_DECOERR_DESCCMD 0x04
489#define JRSTA_DECOERR_ORDER 0x05
490#define JRSTA_DECOERR_KEYCMD 0x06
491#define JRSTA_DECOERR_LOADCMD 0x07
492#define JRSTA_DECOERR_STORECMD 0x08
493#define JRSTA_DECOERR_OPCMD 0x09
494#define JRSTA_DECOERR_FIFOLDCMD 0x0a
495#define JRSTA_DECOERR_FIFOSTCMD 0x0b
496#define JRSTA_DECOERR_MOVECMD 0x0c
497#define JRSTA_DECOERR_JUMPCMD 0x0d
498#define JRSTA_DECOERR_MATHCMD 0x0e
499#define JRSTA_DECOERR_SHASHCMD 0x0f
500#define JRSTA_DECOERR_SEQCMD 0x10
501#define JRSTA_DECOERR_DECOINTERNAL 0x11
502#define JRSTA_DECOERR_SHDESCHDR 0x12
503#define JRSTA_DECOERR_HDRLEN 0x13
504#define JRSTA_DECOERR_BURSTER 0x14
505#define JRSTA_DECOERR_DESCSIGNATURE 0x15
506#define JRSTA_DECOERR_DMA 0x16
507#define JRSTA_DECOERR_BURSTFIFO 0x17
508#define JRSTA_DECOERR_JRRESET 0x1a
509#define JRSTA_DECOERR_JOBFAIL 0x1b
510#define JRSTA_DECOERR_DNRERR 0x80
511#define JRSTA_DECOERR_UNDEFPCL 0x81
512#define JRSTA_DECOERR_PDBERR 0x82
513#define JRSTA_DECOERR_ANRPLY_LATE 0x83
514#define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
515#define JRSTA_DECOERR_SEQOVF 0x85
516#define JRSTA_DECOERR_INVSIGN 0x86
517#define JRSTA_DECOERR_DSASIGN 0x87
518
519#define JRSTA_CCBERR_JUMP 0x08000000
520#define JRSTA_CCBERR_INDEX_MASK 0xff00
521#define JRSTA_CCBERR_INDEX_SHIFT 8
522#define JRSTA_CCBERR_CHAID_MASK 0x00f0
523#define JRSTA_CCBERR_CHAID_SHIFT 4
524#define JRSTA_CCBERR_ERRID_MASK 0x000f
525
526#define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
527#define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
528#define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
529#define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
530#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
531#define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
532#define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
533#define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
534#define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
535
536#define JRSTA_CCBERR_ERRID_NONE 0x00
537#define JRSTA_CCBERR_ERRID_MODE 0x01
538#define JRSTA_CCBERR_ERRID_DATASIZ 0x02
539#define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
540#define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
541#define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
542#define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
543#define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
544#define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
545#define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
546#define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
547#define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
548#define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
549#define JRSTA_CCBERR_ERRID_INVCHA 0x0f
550
551#define JRINT_ERR_INDEX_MASK 0x3fff0000
552#define JRINT_ERR_INDEX_SHIFT 16
553#define JRINT_ERR_TYPE_MASK 0xf00
554#define JRINT_ERR_TYPE_SHIFT 8
555#define JRINT_ERR_HALT_MASK 0xc
556#define JRINT_ERR_HALT_SHIFT 2
557#define JRINT_ERR_HALT_INPROGRESS 0x4
558#define JRINT_ERR_HALT_COMPLETE 0x8
559#define JRINT_JR_ERROR 0x02
560#define JRINT_JR_INT 0x01
561
562#define JRINT_ERR_TYPE_WRITE 1
563#define JRINT_ERR_TYPE_BAD_INPADDR 3
564#define JRINT_ERR_TYPE_BAD_OUTADDR 4
565#define JRINT_ERR_TYPE_INV_INPWRT 5
566#define JRINT_ERR_TYPE_INV_OUTWRT 6
567#define JRINT_ERR_TYPE_RESET 7
568#define JRINT_ERR_TYPE_REMOVE_OFL 8
569#define JRINT_ERR_TYPE_ADD_OFL 9
570
571#define JRCFG_SOE 0x04
572#define JRCFG_ICEN 0x02
573#define JRCFG_IMSK 0x01
574#define JRCFG_ICDCT_SHIFT 8
575#define JRCFG_ICTT_SHIFT 16
576
577#define JRCR_RESET 0x01
578
579/*
580 * caam_assurance - Assurance Controller View
581 * base + 0x6000 padded out to 0x1000
582 */
583
584struct rtic_element {
585 u64 address;
586 u32 rsvd;
587 u32 length;
588};
589
590struct rtic_block {
591 struct rtic_element element[2];
592};
593
594struct rtic_memhash {
595 u32 memhash_be[32];
596 u32 memhash_le[32];
597};
598
599struct caam_assurance {
600 /* Status/Command/Watchdog */
601 u32 rsvd1;
602 u32 status; /* RSTA - Status */
603 u32 rsvd2;
604 u32 cmd; /* RCMD - Command */
605 u32 rsvd3;
606 u32 ctrl; /* RCTL - Control */
607 u32 rsvd4;
608 u32 throttle; /* RTHR - Throttle */
609 u32 rsvd5[2];
610 u64 watchdog; /* RWDOG - Watchdog Timer */
611 u32 rsvd6;
612 u32 rend; /* REND - Endian corrections */
613 u32 rsvd7[50];
614
615 /* Block access/configuration @ 100/110/120/130 */
616 struct rtic_block memblk[4]; /* Memory Blocks A-D */
617 u32 rsvd8[32];
618
619 /* Block hashes @ 200/300/400/500 */
620 struct rtic_memhash hash[4]; /* Block hash values A-D */
621 u32 rsvd_3[640];
622};
623
624/*
625 * caam_queue_if - QI configuration and control
626 * starts base + 0x7000, padded out to 0x1000 long
627 */
628
629struct caam_queue_if {
630 u32 qi_control_hi; /* QICTL - QI Control */
631 u32 qi_control_lo;
632 u32 rsvd1;
633 u32 qi_status; /* QISTA - QI Status */
634 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
635 u32 qi_deq_cfg_lo;
636 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
637 u32 qi_enq_cfg_lo;
638 u32 rsvd2[1016];
639};
640
641/* QI control bits - low word */
642#define QICTL_DQEN 0x01 /* Enable frame pop */
643#define QICTL_STOP 0x02 /* Stop dequeue/enqueue */
644#define QICTL_SOE 0x04 /* Stop on error */
645
646/* QI control bits - high word */
647#define QICTL_MBSI 0x01
648#define QICTL_MHWSI 0x02
649#define QICTL_MWSI 0x04
650#define QICTL_MDWSI 0x08
651#define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */
652#define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */
653#define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */
654#define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */
655#define QICTL_MBSO 0x0100
656#define QICTL_MHWSO 0x0200
657#define QICTL_MWSO 0x0400
658#define QICTL_MDWSO 0x0800
659#define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */
660#define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */
661#define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */
662#define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */
663#define QICTL_DMBS 0x010000
664#define QICTL_EPO 0x020000
665
666/* QI status bits */
667#define QISTA_PHRDERR 0x01 /* PreHeader Read Error */
668#define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */
669#define QISTA_OFWRERR 0x04 /* Output Frame Read Error */
670#define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */
671#define QISTA_BTSERR 0x10 /* Buffer Undersize */
672#define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */
673#define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */
674
675/* deco_sg_table - DECO view of scatter/gather table */
676struct deco_sg_table {
677 u64 addr; /* Segment Address */
678 u32 elen; /* E, F bits + 30-bit length */
679 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
680};
681
682/*
683 * caam_deco - descriptor controller - CHA cluster block
684 *
685 * Only accessible when direct DECO access is turned on
686 * (done in DECORR, via MID programmed in DECOxMID
687 *
688 * 5 typical, base + 0x8000/9000/a000/b000
689 * Padded out to 0x1000 long
690 */
691struct caam_deco {
692 u32 rsvd1;
693 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
694 u32 rsvd2;
695 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
696 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
697 u32 cls1_datasize_lo;
698 u32 rsvd3;
699 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
700 u32 rsvd4[5];
701 u32 cha_ctrl; /* CCTLR - CHA control */
702 u32 rsvd5;
703 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
704 u32 rsvd6;
705 u32 clr_written; /* CxCWR - Clear-Written */
706 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
707 u32 ccb_status_lo;
708 u32 rsvd7[3];
709 u32 aad_size; /* CxAADSZR - Current AAD Size */
710 u32 rsvd8;
711 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
712 u32 rsvd9[7];
713 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
714 u32 rsvd10;
715 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
716 u32 rsvd11;
717 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
718 u32 rsvd12;
719 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
720 u32 rsvd13[24];
721 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
722 u32 rsvd14[48];
723 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
724 u32 rsvd15[121];
725 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
726 u32 rsvd16;
727 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
728 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
729 u32 cls2_datasize_lo;
730 u32 rsvd17;
731 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
732 u32 rsvd18[56];
733 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
734 u32 rsvd19[46];
735 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
736 u32 rsvd20[84];
737 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
738 u32 inp_infofifo_lo;
739 u32 rsvd21[2];
740 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
741 u32 rsvd22[2];
742 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
743 u32 rsvd23[2];
744 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
745 u32 jr_ctl_lo;
746 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
1005bccd 747#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
8e8ec596
KP		 748 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
749 u32 op_status_lo;
750 u32 rsvd24[2];
751 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
752 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
753 u32 rsvd26[6];
754 u64 math[4]; /* DxMTH - Math register */
755 u32 rsvd27[8];
756 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
757 u32 rsvd28[16];
758 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
759 u32 rsvd29[48];
760 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
997ad290 761 u32 rscvd30[193];
84cf4827
AP		 762#define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000
763#define DESC_DBG_DECO_STAT_VALID 0x80000000
764#define DESC_DBG_DECO_STAT_MASK 0x00F00000
997ad290
RG		 765 u32 desc_dbg; /* DxDDR - DECO Debug Register */
766 u32 rsvd31[126];
8e8ec596
KP		 767};
768
997ad290
RG		 769#define DECO_JQCR_WHL 0x20000000
770#define DECO_JQCR_FOUR 0x10000000
771
8e8ec596
KP		 772/*
773 * Current top-level view of memory map is:
774 *
775 * 0x0000 - 0x0fff - CAAM Top-Level Control
776 * 0x1000 - 0x1fff - Job Ring 0
777 * 0x2000 - 0x2fff - Job Ring 1
778 * 0x3000 - 0x3fff - Job Ring 2
779 * 0x4000 - 0x4fff - Job Ring 3
780 * 0x5000 - 0x5fff - (unused)
781 * 0x6000 - 0x6fff - Assurance Controller
782 * 0x7000 - 0x7fff - Queue Interface
783 * 0x8000 - 0x8fff - DECO-CCB 0
784 * 0x9000 - 0x9fff - DECO-CCB 1
785 * 0xa000 - 0xafff - DECO-CCB 2
786 * 0xb000 - 0xbfff - DECO-CCB 3
787 * 0xc000 - 0xcfff - DECO-CCB 4
788 *
789 * caam_full describes the full register view of CAAM if useful,
790 * although many configurations may choose to implement parts of
791 * the register map separately, in differing privilege regions
792 */
793struct caam_full {
794 struct caam_ctrl __iomem ctrl;
795 struct caam_job_ring jr[4];
796 u64 rsvd[512];
797 struct caam_assurance assure;
798 struct caam_queue_if qi;
997ad290 799 struct caam_deco deco;
8e8ec596
KP		 800};
801
802#endif /* REGS_H */
Linux 6.x block layer and io_uring tree(s)