Commit | Line | Data |
---|---|---|
8e8ec596 KP |
1 | /* |
2 | * CAAM control-plane driver backend | |
3 | * Controller-level driver, kernel property detection, initialization | |
4 | * | |
281922a1 | 5 | * Copyright 2008-2012 Freescale Semiconductor, Inc. |
8e8ec596 KP |
6 | */ |
7 | ||
4776d381 | 8 | #include <linux/device.h> |
5af50730 RH |
9 | #include <linux/of_address.h> |
10 | #include <linux/of_irq.h> | |
11 | ||
8e8ec596 KP |
12 | #include "compat.h" |
13 | #include "regs.h" | |
14 | #include "intern.h" | |
15 | #include "jr.h" | |
281922a1 KP |
16 | #include "desc_constr.h" |
17 | #include "error.h" | |
8e8ec596 | 18 | |
281922a1 KP |
19 | /* |
20 | * Descriptor to instantiate RNG State Handle 0 in normal mode and | |
21 | * load the JDKEK, TDKEK and TDSK registers | |
22 | */ | |
1005bccd | 23 | static void build_instantiation_desc(u32 *desc, int handle, int do_sk) |
281922a1 | 24 | { |
1005bccd | 25 | u32 *jump_cmd, op_flags; |
281922a1 KP |
26 | |
27 | init_job_desc(desc, 0); | |
28 | ||
1005bccd AP |
29 | op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | |
30 | (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; | |
31 | ||
281922a1 | 32 | /* INIT RNG in non-test mode */ |
1005bccd | 33 | append_operation(desc, op_flags); |
281922a1 | 34 | |
1005bccd AP |
35 | if (!handle && do_sk) { |
36 | /* | |
37 | * For SH0, Secure Keys must be generated as well | |
38 | */ | |
281922a1 | 39 | |
1005bccd AP |
40 | /* wait for done */ |
41 | jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); | |
42 | set_jump_tgt_here(desc, jump_cmd); | |
281922a1 | 43 | |
1005bccd AP |
44 | /* |
45 | * load 1 to clear written reg: | |
46 | * resets the done interrrupt and returns the RNG to idle. | |
47 | */ | |
48 | append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); | |
49 | ||
50 | /* Initialize State Handle */ | |
51 | append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | | |
52 | OP_ALG_AAI_RNG4_SK); | |
53 | } | |
281922a1 | 54 | |
d5e4e999 | 55 | append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); |
281922a1 | 56 | } |
281922a1 | 57 | |
b1f996e0 | 58 | /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ |
1005bccd | 59 | static void build_deinstantiation_desc(u32 *desc, int handle) |
b1f996e0 AP |
60 | { |
61 | init_job_desc(desc, 0); | |
281922a1 | 62 | |
b1f996e0 | 63 | /* Uninstantiate State Handle 0 */ |
281922a1 | 64 | append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | |
1005bccd | 65 | (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); |
b1f996e0 AP |
66 | |
67 | append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); | |
281922a1 KP |
68 | } |
69 | ||
04cddbfe AP |
70 | /* |
71 | * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of | |
72 | * the software (no JR/QI used). | |
73 | * @ctrldev - pointer to device | |
1005bccd AP |
74 | * @status - descriptor status, after being run |
75 | * | |
04cddbfe AP |
76 | * Return: - 0 if no error occurred |
77 | * - -ENODEV if the DECO couldn't be acquired | |
78 | * - -EAGAIN if an error occurred while executing the descriptor | |
79 | */ | |
1005bccd AP |
80 | static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, |
81 | u32 *status) | |
281922a1 | 82 | { |
997ad290 RG |
83 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); |
84 | struct caam_full __iomem *topregs; | |
85 | unsigned int timeout = 100000; | |
04cddbfe | 86 | u32 deco_dbg_reg, flags; |
b1f996e0 | 87 | int i; |
997ad290 RG |
88 | |
89 | /* Set the bit to request direct access to DECO0 */ | |
90 | topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; | |
17157c90 | 91 | |
8f1da7b9 | 92 | if (ctrlpriv->virt_en == 1) { |
17157c90 RG |
93 | setbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0); |
94 | ||
8f1da7b9 HG |
95 | while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) && |
96 | --timeout) | |
97 | cpu_relax(); | |
98 | ||
99 | timeout = 100000; | |
100 | } | |
17157c90 | 101 | |
997ad290 RG |
102 | setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE); |
103 | ||
104 | while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) && | |
105 | --timeout) | |
106 | cpu_relax(); | |
107 | ||
108 | if (!timeout) { | |
109 | dev_err(ctrldev, "failed to acquire DECO 0\n"); | |
04cddbfe AP |
110 | clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE); |
111 | return -ENODEV; | |
281922a1 KP |
112 | } |
113 | ||
997ad290 | 114 | for (i = 0; i < desc_len(desc); i++) |
04cddbfe | 115 | wr_reg32(&topregs->deco.descbuf[i], *(desc + i)); |
281922a1 | 116 | |
04cddbfe AP |
117 | flags = DECO_JQCR_WHL; |
118 | /* | |
119 | * If the descriptor length is longer than 4 words, then the | |
120 | * FOUR bit in JRCTRL register must be set. | |
121 | */ | |
122 | if (desc_len(desc) >= 4) | |
123 | flags |= DECO_JQCR_FOUR; | |
124 | ||
125 | /* Instruct the DECO to execute it */ | |
126 | wr_reg32(&topregs->deco.jr_ctl_hi, flags); | |
997ad290 RG |
127 | |
128 | timeout = 10000000; | |
84cf4827 AP |
129 | do { |
130 | deco_dbg_reg = rd_reg32(&topregs->deco.desc_dbg); | |
131 | /* | |
132 | * If an error occured in the descriptor, then | |
133 | * the DECO status field will be set to 0x0D | |
134 | */ | |
135 | if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == | |
136 | DESC_DBG_DECO_STAT_HOST_ERR) | |
137 | break; | |
997ad290 | 138 | cpu_relax(); |
84cf4827 | 139 | } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); |
281922a1 | 140 | |
1005bccd AP |
141 | *status = rd_reg32(&topregs->deco.op_status_hi) & |
142 | DECO_OP_STATUS_HI_ERR_MASK; | |
997ad290 | 143 | |
17157c90 RG |
144 | if (ctrlpriv->virt_en == 1) |
145 | clrbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0); | |
146 | ||
04cddbfe | 147 | /* Mark the DECO as free */ |
997ad290 | 148 | clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE); |
04cddbfe AP |
149 | |
150 | if (!timeout) | |
151 | return -EAGAIN; | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | /* | |
157 | * instantiate_rng - builds and executes a descriptor on DECO0, | |
158 | * which initializes the RNG block. | |
159 | * @ctrldev - pointer to device | |
1005bccd AP |
160 | * @state_handle_mask - bitmask containing the instantiation status |
161 | * for the RNG4 state handles which exist in | |
162 | * the RNG4 block: 1 if it's been instantiated | |
163 | * by an external entry, 0 otherwise. | |
164 | * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; | |
165 | * Caution: this can be done only once; if the keys need to be | |
166 | * regenerated, a POR is required | |
167 | * | |
04cddbfe AP |
168 | * Return: - 0 if no error occurred |
169 | * - -ENOMEM if there isn't enough memory to allocate the descriptor | |
170 | * - -ENODEV if DECO0 couldn't be acquired | |
171 | * - -EAGAIN if an error occurred when executing the descriptor | |
172 | * f.i. there was a RNG hardware error due to not "good enough" | |
173 | * entropy being aquired. | |
174 | */ | |
1005bccd AP |
175 | static int instantiate_rng(struct device *ctrldev, int state_handle_mask, |
176 | int gen_sk) | |
04cddbfe | 177 | { |
1005bccd AP |
178 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); |
179 | struct caam_full __iomem *topregs; | |
180 | struct rng4tst __iomem *r4tst; | |
181 | u32 *desc, status, rdsta_val; | |
182 | int ret = 0, sh_idx; | |
183 | ||
184 | topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; | |
185 | r4tst = &topregs->ctrl.r4tst[0]; | |
04cddbfe AP |
186 | |
187 | desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); | |
188 | if (!desc) | |
189 | return -ENOMEM; | |
04cddbfe | 190 | |
1005bccd AP |
191 | for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { |
192 | /* | |
193 | * If the corresponding bit is set, this state handle | |
194 | * was initialized by somebody else, so it's left alone. | |
195 | */ | |
196 | if ((1 << sh_idx) & state_handle_mask) | |
197 | continue; | |
198 | ||
199 | /* Create the descriptor for instantiating RNG State Handle */ | |
200 | build_instantiation_desc(desc, sh_idx, gen_sk); | |
201 | ||
202 | /* Try to run it through DECO0 */ | |
203 | ret = run_descriptor_deco0(ctrldev, desc, &status); | |
204 | ||
205 | /* | |
206 | * If ret is not 0, or descriptor status is not 0, then | |
207 | * something went wrong. No need to try the next state | |
208 | * handle (if available), bail out here. | |
209 | * Also, if for some reason, the State Handle didn't get | |
210 | * instantiated although the descriptor has finished | |
211 | * without any error (HW optimizations for later | |
212 | * CAAM eras), then try again. | |
213 | */ | |
214 | rdsta_val = | |
215 | rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IFMASK; | |
216 | if (status || !(rdsta_val & (1 << sh_idx))) | |
217 | ret = -EAGAIN; | |
218 | if (ret) | |
219 | break; | |
220 | ||
221 | dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); | |
222 | /* Clear the contents before recreating the descriptor */ | |
223 | memset(desc, 0x00, CAAM_CMD_SZ * 7); | |
224 | } | |
04cddbfe | 225 | |
997ad290 | 226 | kfree(desc); |
04cddbfe | 227 | |
281922a1 KP |
228 | return ret; |
229 | } | |
230 | ||
231 | /* | |
b1f996e0 AP |
232 | * deinstantiate_rng - builds and executes a descriptor on DECO0, |
233 | * which deinitializes the RNG block. | |
234 | * @ctrldev - pointer to device | |
1005bccd AP |
235 | * @state_handle_mask - bitmask containing the instantiation status |
236 | * for the RNG4 state handles which exist in | |
237 | * the RNG4 block: 1 if it's been instantiated | |
b1f996e0 AP |
238 | * |
239 | * Return: - 0 if no error occurred | |
240 | * - -ENOMEM if there isn't enough memory to allocate the descriptor | |
241 | * - -ENODEV if DECO0 couldn't be acquired | |
242 | * - -EAGAIN if an error occurred when executing the descriptor | |
281922a1 | 243 | */ |
1005bccd | 244 | static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) |
b1f996e0 | 245 | { |
1005bccd AP |
246 | u32 *desc, status; |
247 | int sh_idx, ret = 0; | |
b1f996e0 AP |
248 | |
249 | desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); | |
250 | if (!desc) | |
251 | return -ENOMEM; | |
252 | ||
1005bccd AP |
253 | for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { |
254 | /* | |
255 | * If the corresponding bit is set, then it means the state | |
256 | * handle was initialized by us, and thus it needs to be | |
257 | * deintialized as well | |
258 | */ | |
259 | if ((1 << sh_idx) & state_handle_mask) { | |
260 | /* | |
261 | * Create the descriptor for deinstantating this state | |
262 | * handle | |
263 | */ | |
264 | build_deinstantiation_desc(desc, sh_idx); | |
265 | ||
266 | /* Try to run it through DECO0 */ | |
267 | ret = run_descriptor_deco0(ctrldev, desc, &status); | |
268 | ||
269 | if (ret || status) { | |
270 | dev_err(ctrldev, | |
271 | "Failed to deinstantiate RNG4 SH%d\n", | |
272 | sh_idx); | |
273 | break; | |
274 | } | |
275 | dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); | |
276 | } | |
277 | } | |
b1f996e0 AP |
278 | |
279 | kfree(desc); | |
280 | ||
281 | return ret; | |
282 | } | |
283 | ||
04cddbfe AP |
284 | static int caam_remove(struct platform_device *pdev) |
285 | { | |
286 | struct device *ctrldev; | |
287 | struct caam_drv_private *ctrlpriv; | |
04cddbfe AP |
288 | struct caam_full __iomem *topregs; |
289 | int ring, ret = 0; | |
290 | ||
291 | ctrldev = &pdev->dev; | |
292 | ctrlpriv = dev_get_drvdata(ctrldev); | |
293 | topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; | |
294 | ||
313ea293 | 295 | /* Remove platform devices for JobRs */ |
04cddbfe | 296 | for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) { |
313ea293 RG |
297 | if (ctrlpriv->jrpdev[ring]) |
298 | of_device_unregister(ctrlpriv->jrpdev[ring]); | |
04cddbfe AP |
299 | } |
300 | ||
1005bccd AP |
301 | /* De-initialize RNG state handles initialized by this driver. */ |
302 | if (ctrlpriv->rng4_sh_init) | |
303 | deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); | |
b1f996e0 | 304 | |
04cddbfe AP |
305 | /* Shut down debug views */ |
306 | #ifdef CONFIG_DEBUG_FS | |
307 | debugfs_remove_recursive(ctrlpriv->dfs_root); | |
308 | #endif | |
309 | ||
310 | /* Unmap controller region */ | |
311 | iounmap(&topregs->ctrl); | |
312 | ||
281922a1 KP |
313 | return ret; |
314 | } | |
315 | ||
316 | /* | |
84cf4827 AP |
317 | * kick_trng - sets the various parameters for enabling the initialization |
318 | * of the RNG4 block in CAAM | |
319 | * @pdev - pointer to the platform device | |
320 | * @ent_delay - Defines the length (in system clocks) of each entropy sample. | |
281922a1 | 321 | */ |
84cf4827 | 322 | static void kick_trng(struct platform_device *pdev, int ent_delay) |
281922a1 KP |
323 | { |
324 | struct device *ctrldev = &pdev->dev; | |
325 | struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); | |
326 | struct caam_full __iomem *topregs; | |
327 | struct rng4tst __iomem *r4tst; | |
328 | u32 val; | |
329 | ||
330 | topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; | |
331 | r4tst = &topregs->ctrl.r4tst[0]; | |
332 | ||
333 | /* put RNG4 into program mode */ | |
334 | setbits32(&r4tst->rtmctl, RTMCTL_PRGM); | |
84cf4827 AP |
335 | |
336 | /* | |
337 | * Performance-wise, it does not make sense to | |
338 | * set the delay to a value that is lower | |
339 | * than the last one that worked (i.e. the state handles | |
340 | * were instantiated properly. Thus, instead of wasting | |
341 | * time trying to set the values controlling the sample | |
342 | * frequency, the function simply returns. | |
343 | */ | |
344 | val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) | |
345 | >> RTSDCTL_ENT_DLY_SHIFT; | |
346 | if (ent_delay <= val) { | |
347 | /* put RNG4 into run mode */ | |
348 | clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); | |
349 | return; | |
350 | } | |
351 | ||
281922a1 | 352 | val = rd_reg32(&r4tst->rtsdctl); |
84cf4827 AP |
353 | val = (val & ~RTSDCTL_ENT_DLY_MASK) | |
354 | (ent_delay << RTSDCTL_ENT_DLY_SHIFT); | |
281922a1 | 355 | wr_reg32(&r4tst->rtsdctl, val); |
84cf4827 AP |
356 | /* min. freq. count, equal to 1/4 of the entropy sample length */ |
357 | wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); | |
358 | /* max. freq. count, equal to 8 times the entropy sample length */ | |
359 | wr_reg32(&r4tst->rtfrqmax, ent_delay << 3); | |
281922a1 KP |
360 | /* put RNG4 into run mode */ |
361 | clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); | |
362 | } | |
363 | ||
82c2f960 AP |
364 | /** |
365 | * caam_get_era() - Return the ERA of the SEC on SoC, based | |
883619a9 | 366 | * on "sec-era" propery in the DTS. This property is updated by u-boot. |
82c2f960 | 367 | **/ |
883619a9 | 368 | int caam_get_era(void) |
82c2f960 | 369 | { |
883619a9 AP |
370 | struct device_node *caam_node; |
371 | for_each_compatible_node(caam_node, NULL, "fsl,sec-v4.0") { | |
372 | const uint32_t *prop = (uint32_t *)of_get_property(caam_node, | |
373 | "fsl,sec-era", | |
374 | NULL); | |
375 | return prop ? *prop : -ENOTSUPP; | |
376 | } | |
82c2f960 AP |
377 | |
378 | return -ENOTSUPP; | |
379 | } | |
380 | EXPORT_SYMBOL(caam_get_era); | |
381 | ||
8e8ec596 | 382 | /* Probe routine for CAAM top (controller) level */ |
2930d497 | 383 | static int caam_probe(struct platform_device *pdev) |
8e8ec596 | 384 | { |
1005bccd | 385 | int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; |
82c2f960 | 386 | u64 caam_id; |
8e8ec596 KP |
387 | struct device *dev; |
388 | struct device_node *nprop, *np; | |
389 | struct caam_ctrl __iomem *ctrl; | |
390 | struct caam_full __iomem *topregs; | |
391 | struct caam_drv_private *ctrlpriv; | |
23457bc9 KP |
392 | #ifdef CONFIG_DEBUG_FS |
393 | struct caam_perfmon *perfmon; | |
394 | #endif | |
17157c90 | 395 | u32 scfgr, comp_params; |
eb1139cd | 396 | u32 cha_vid_ls; |
8e8ec596 | 397 | |
4776d381 HS |
398 | ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private), |
399 | GFP_KERNEL); | |
8e8ec596 KP |
400 | if (!ctrlpriv) |
401 | return -ENOMEM; | |
402 | ||
403 | dev = &pdev->dev; | |
404 | dev_set_drvdata(dev, ctrlpriv); | |
405 | ctrlpriv->pdev = pdev; | |
406 | nprop = pdev->dev.of_node; | |
407 | ||
408 | /* Get configuration properties from device tree */ | |
409 | /* First, get register page */ | |
410 | ctrl = of_iomap(nprop, 0); | |
411 | if (ctrl == NULL) { | |
412 | dev_err(dev, "caam: of_iomap() failed\n"); | |
413 | return -ENOMEM; | |
414 | } | |
415 | ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; | |
416 | ||
417 | /* topregs used to derive pointers to CAAM sub-blocks only */ | |
418 | topregs = (struct caam_full __iomem *)ctrl; | |
419 | ||
420 | /* Get the IRQ of the controller (for security violations only) */ | |
f7578496 | 421 | ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); |
8e8ec596 KP |
422 | |
423 | /* | |
424 | * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, | |
e13af18a | 425 | * long pointers in master configuration register |
8e8ec596 KP |
426 | */ |
427 | setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE | | |
428 | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); | |
429 | ||
17157c90 RG |
430 | /* |
431 | * Read the Compile Time paramters and SCFGR to determine | |
432 | * if Virtualization is enabled for this platform | |
433 | */ | |
434 | comp_params = rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms); | |
435 | scfgr = rd_reg32(&topregs->ctrl.scfgr); | |
436 | ||
437 | ctrlpriv->virt_en = 0; | |
438 | if (comp_params & CTPR_MS_VIRT_EN_INCL) { | |
439 | /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or | |
440 | * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 | |
441 | */ | |
442 | if ((comp_params & CTPR_MS_VIRT_EN_POR) || | |
443 | (!(comp_params & CTPR_MS_VIRT_EN_POR) && | |
444 | (scfgr & SCFGR_VIRT_EN))) | |
445 | ctrlpriv->virt_en = 1; | |
446 | } else { | |
447 | /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ | |
448 | if (comp_params & CTPR_MS_VIRT_EN_POR) | |
449 | ctrlpriv->virt_en = 1; | |
450 | } | |
451 | ||
452 | if (ctrlpriv->virt_en == 1) | |
453 | setbits32(&topregs->ctrl.jrstart, JRSTART_JR0_START | | |
454 | JRSTART_JR1_START | JRSTART_JR2_START | | |
455 | JRSTART_JR3_START); | |
456 | ||
8e8ec596 | 457 | if (sizeof(dma_addr_t) == sizeof(u64)) |
e13af18a | 458 | if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) |
a2ac287e | 459 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); |
e13af18a | 460 | else |
a2ac287e | 461 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); |
e13af18a | 462 | else |
a2ac287e | 463 | dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
8e8ec596 | 464 | |
8e8ec596 KP |
465 | /* |
466 | * Detect and enable JobRs | |
467 | * First, find out how many ring spec'ed, allocate references | |
468 | * for all, then go probe each one. | |
469 | */ | |
470 | rspec = 0; | |
0a63b09d NL |
471 | for_each_available_child_of_node(nprop, np) |
472 | if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || | |
473 | of_device_is_compatible(np, "fsl,sec4.0-job-ring")) | |
a0ea0f6d | 474 | rspec++; |
a0ea0f6d | 475 | |
4776d381 HS |
476 | ctrlpriv->jrpdev = devm_kzalloc(&pdev->dev, |
477 | sizeof(struct platform_device *) * rspec, | |
478 | GFP_KERNEL); | |
313ea293 | 479 | if (ctrlpriv->jrpdev == NULL) { |
8e8ec596 KP |
480 | iounmap(&topregs->ctrl); |
481 | return -ENOMEM; | |
482 | } | |
483 | ||
484 | ring = 0; | |
485 | ctrlpriv->total_jobrs = 0; | |
0a63b09d NL |
486 | for_each_available_child_of_node(nprop, np) |
487 | if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || | |
488 | of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { | |
313ea293 RG |
489 | ctrlpriv->jrpdev[ring] = |
490 | of_platform_device_create(np, NULL, dev); | |
491 | if (!ctrlpriv->jrpdev[ring]) { | |
492 | pr_warn("JR%d Platform device creation error\n", | |
493 | ring); | |
494 | continue; | |
495 | } | |
a0ea0f6d SL |
496 | ctrlpriv->total_jobrs++; |
497 | ring++; | |
498 | } | |
8e8ec596 KP |
499 | |
500 | /* Check to see if QI present. If so, enable */ | |
eb1139cd RG |
501 | ctrlpriv->qi_present = |
502 | !!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) & | |
503 | CTPR_MS_QI_MASK); | |
8e8ec596 KP |
504 | if (ctrlpriv->qi_present) { |
505 | ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi; | |
506 | /* This is all that's required to physically enable QI */ | |
507 | wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN); | |
508 | } | |
509 | ||
510 | /* If no QI and no rings specified, quit and go home */ | |
511 | if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { | |
512 | dev_err(dev, "no queues configured, terminating\n"); | |
513 | caam_remove(pdev); | |
514 | return -ENOMEM; | |
515 | } | |
516 | ||
eb1139cd | 517 | cha_vid_ls = rd_reg32(&topregs->ctrl.perfmon.cha_id_ls); |
986dfbcf | 518 | |
281922a1 | 519 | /* |
986dfbcf | 520 | * If SEC has RNG version >= 4 and RNG state handle has not been |
84cf4827 | 521 | * already instantiated, do RNG instantiation |
281922a1 | 522 | */ |
eb1139cd | 523 | if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { |
1005bccd AP |
524 | ctrlpriv->rng4_sh_init = |
525 | rd_reg32(&topregs->ctrl.r4tst[0].rdsta); | |
526 | /* | |
527 | * If the secure keys (TDKEK, JDKEK, TDSK), were already | |
528 | * generated, signal this to the function that is instantiating | |
529 | * the state handles. An error would occur if RNG4 attempts | |
530 | * to regenerate these keys before the next POR. | |
531 | */ | |
532 | gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; | |
533 | ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; | |
84cf4827 | 534 | do { |
1005bccd AP |
535 | int inst_handles = |
536 | rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & | |
537 | RDSTA_IFMASK; | |
538 | /* | |
539 | * If either SH were instantiated by somebody else | |
540 | * (e.g. u-boot) then it is assumed that the entropy | |
541 | * parameters are properly set and thus the function | |
542 | * setting these (kick_trng(...)) is skipped. | |
543 | * Also, if a handle was instantiated, do not change | |
544 | * the TRNG parameters. | |
545 | */ | |
546 | if (!(ctrlpriv->rng4_sh_init || inst_handles)) { | |
547 | kick_trng(pdev, ent_delay); | |
548 | ent_delay += 400; | |
549 | } | |
550 | /* | |
551 | * if instantiate_rng(...) fails, the loop will rerun | |
552 | * and the kick_trng(...) function will modfiy the | |
553 | * upper and lower limits of the entropy sampling | |
554 | * interval, leading to a sucessful initialization of | |
555 | * the RNG. | |
556 | */ | |
557 | ret = instantiate_rng(dev, inst_handles, | |
558 | gen_sk); | |
04cddbfe | 559 | } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); |
281922a1 | 560 | if (ret) { |
84cf4827 | 561 | dev_err(dev, "failed to instantiate RNG"); |
281922a1 KP |
562 | caam_remove(pdev); |
563 | return ret; | |
564 | } | |
1005bccd AP |
565 | /* |
566 | * Set handles init'ed by this module as the complement of the | |
567 | * already initialized ones | |
568 | */ | |
569 | ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; | |
575c1bd5 VG |
570 | |
571 | /* Enable RDB bit so that RNG works faster */ | |
572 | setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE); | |
281922a1 KP |
573 | } |
574 | ||
8e8ec596 KP |
575 | /* NOTE: RTIC detection ought to go here, around Si time */ |
576 | ||
eb1139cd RG |
577 | caam_id = (u64)rd_reg32(&topregs->ctrl.perfmon.caam_id_ms) << 32 | |
578 | (u64)rd_reg32(&topregs->ctrl.perfmon.caam_id_ls); | |
82c2f960 | 579 | |
8e8ec596 | 580 | /* Report "alive" for developer to see */ |
82c2f960 | 581 | dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, |
883619a9 | 582 | caam_get_era()); |
8e8ec596 KP |
583 | dev_info(dev, "job rings = %d, qi = %d\n", |
584 | ctrlpriv->total_jobrs, ctrlpriv->qi_present); | |
585 | ||
586 | #ifdef CONFIG_DEBUG_FS | |
587 | /* | |
588 | * FIXME: needs better naming distinction, as some amalgamation of | |
589 | * "caam" and nprop->full_name. The OF name isn't distinctive, | |
590 | * but does separate instances | |
591 | */ | |
592 | perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; | |
593 | ||
178f827a | 594 | ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); |
8e8ec596 KP |
595 | ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); |
596 | ||
597 | /* Controller-level - performance monitor counters */ | |
598 | ctrlpriv->ctl_rq_dequeued = | |
599 | debugfs_create_u64("rq_dequeued", | |
eda65cc6 | 600 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
601 | ctrlpriv->ctl, &perfmon->req_dequeued); |
602 | ctrlpriv->ctl_ob_enc_req = | |
603 | debugfs_create_u64("ob_rq_encrypted", | |
eda65cc6 | 604 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
605 | ctrlpriv->ctl, &perfmon->ob_enc_req); |
606 | ctrlpriv->ctl_ib_dec_req = | |
607 | debugfs_create_u64("ib_rq_decrypted", | |
eda65cc6 | 608 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
609 | ctrlpriv->ctl, &perfmon->ib_dec_req); |
610 | ctrlpriv->ctl_ob_enc_bytes = | |
611 | debugfs_create_u64("ob_bytes_encrypted", | |
eda65cc6 | 612 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
613 | ctrlpriv->ctl, &perfmon->ob_enc_bytes); |
614 | ctrlpriv->ctl_ob_prot_bytes = | |
615 | debugfs_create_u64("ob_bytes_protected", | |
eda65cc6 | 616 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
617 | ctrlpriv->ctl, &perfmon->ob_prot_bytes); |
618 | ctrlpriv->ctl_ib_dec_bytes = | |
619 | debugfs_create_u64("ib_bytes_decrypted", | |
eda65cc6 | 620 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
621 | ctrlpriv->ctl, &perfmon->ib_dec_bytes); |
622 | ctrlpriv->ctl_ib_valid_bytes = | |
623 | debugfs_create_u64("ib_bytes_validated", | |
eda65cc6 | 624 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
625 | ctrlpriv->ctl, &perfmon->ib_valid_bytes); |
626 | ||
627 | /* Controller level - global status values */ | |
628 | ctrlpriv->ctl_faultaddr = | |
629 | debugfs_create_u64("fault_addr", | |
eda65cc6 | 630 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
631 | ctrlpriv->ctl, &perfmon->faultaddr); |
632 | ctrlpriv->ctl_faultdetail = | |
633 | debugfs_create_u32("fault_detail", | |
eda65cc6 | 634 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
635 | ctrlpriv->ctl, &perfmon->faultdetail); |
636 | ctrlpriv->ctl_faultstatus = | |
637 | debugfs_create_u32("fault_status", | |
eda65cc6 | 638 | S_IRUSR | S_IRGRP | S_IROTH, |
8e8ec596 KP |
639 | ctrlpriv->ctl, &perfmon->status); |
640 | ||
641 | /* Internal covering keys (useful in non-secure mode only) */ | |
642 | ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0]; | |
643 | ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
644 | ctrlpriv->ctl_kek = debugfs_create_blob("kek", | |
eda65cc6 | 645 | S_IRUSR | |
8e8ec596 KP |
646 | S_IRGRP | S_IROTH, |
647 | ctrlpriv->ctl, | |
648 | &ctrlpriv->ctl_kek_wrap); | |
649 | ||
650 | ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0]; | |
651 | ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
652 | ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", | |
eda65cc6 | 653 | S_IRUSR | |
8e8ec596 KP |
654 | S_IRGRP | S_IROTH, |
655 | ctrlpriv->ctl, | |
656 | &ctrlpriv->ctl_tkek_wrap); | |
657 | ||
658 | ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0]; | |
659 | ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); | |
660 | ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", | |
eda65cc6 | 661 | S_IRUSR | |
8e8ec596 KP |
662 | S_IRGRP | S_IROTH, |
663 | ctrlpriv->ctl, | |
664 | &ctrlpriv->ctl_tdsk_wrap); | |
665 | #endif | |
666 | return 0; | |
667 | } | |
668 | ||
669 | static struct of_device_id caam_match[] = { | |
670 | { | |
54e198d4 | 671 | .compatible = "fsl,sec-v4.0", |
8e8ec596 | 672 | }, |
a0ea0f6d SL |
673 | { |
674 | .compatible = "fsl,sec4.0", | |
675 | }, | |
8e8ec596 KP |
676 | {}, |
677 | }; | |
678 | MODULE_DEVICE_TABLE(of, caam_match); | |
679 | ||
2930d497 | 680 | static struct platform_driver caam_driver = { |
8e8ec596 KP |
681 | .driver = { |
682 | .name = "caam", | |
683 | .owner = THIS_MODULE, | |
684 | .of_match_table = caam_match, | |
685 | }, | |
686 | .probe = caam_probe, | |
49cfe4db | 687 | .remove = caam_remove, |
8e8ec596 KP |
688 | }; |
689 | ||
741e8c2d | 690 | module_platform_driver(caam_driver); |
8e8ec596 KP |
691 | |
692 | MODULE_LICENSE("GPL"); | |
693 | MODULE_DESCRIPTION("FSL CAAM request backend"); | |
694 | MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); |